30th week of 2011 patent applcation highlights part 56 |
Patent application number | Title | Published |
20110185054 | TERMINAL DEVICE AND CONNECTION SWITCHING MANAGEMENT METHOD - Provided is a terminal device which can perform connection switching to a more appropriate communication network while normally executing a service from a server. The terminal device includes: an input unit ( | 2011-07-28 |
20110185055 | SYSTEM AND METHOD FOR CORRELATING NETWORK IDENTITIES AND ADDRESSES - The system and method for correlating network identities and addresses described herein may include a log correlation engine distributed on a network that identifies relationships between certain network identities and Internet Protocol (IP) and Ethernet addresses in the network. In particular, the log correlation engine may analyze various event logs that describe activity in a network to learn relationships between network identities and network addresses and generate alerts in response to discovering changes in the learned relationships. For example, the log correlation engine may identify authentication events described in the logs to map network identities to IP addresses, and may further analyze the logs to map the IP addresses to Ethernet addresses. Thus, the log correlation engine may discover new and changed relationships between the network identities, the IP addresses, and the Ethernet addresses. | 2011-07-28 |
20110185056 | INSIDER THREAT CORRELATION TOOL - Systems and methods for calculating threat scores for individuals within an organization or domain are provided. Aspects of the invention relate to computer-implemented methods that form a predictive threat rating for user accounts. In one implementation, a first threat score representing a first time period may be calculated. The first threat score may be compared with aspects of the same user accounts for a second time period. Weighting schemes may be applied to certain activities, controls, and/or user accounts. Further aspects relate to apparatuses configured to execute methods for ranking individual user accounts. Certain embodiments may not block transmissions that violate predefine rules, however, indications of such improper transmission may be considered when constructing a threat rating. Blocked transmissions enforced upon a user account may also be received. Certain activity, such as accessing the internet, may be monitored for the presence of a security threat and/or an ethics threat. | 2011-07-28 |
20110185057 | Apparatus And Method Of Administering Modular Online Environments - In a modular on-line virtual environment, in which each module of the on-line virtual environment has a plurality of parallel instances each able to host a limited number of users, a server arranged to administer the modular on-line virtual environment comprises a network communications arrangement operable to receive data representative of the actions of users within an instance of a first module of the modular on-line virtual environment, and to transmit to each user within that instance of that module data representative of the actions of each other user within that instance of that module, behaviour analysis means operable to analyse user behaviour within that instance of the first module, in which if the behaviour of two or more users satisfies a predetermined criterion then the two or more users are classified as belonging to a social group comprising the two or more users, module instance selection means operable to select an instance of a second module for a user when that user moves within the modular on-line virtual environment from the first module to a second module, in which the module instance selection means is operable to select an instance of the second module that has the capacity to accommodate the greatest number of the common social group once one member of that social group moves within the modular on-line virtual environment from the first module to the second module and the server is operable to place a subsequent respective member of the social group in that same selected instance of the second module if that member moves within the modular on-line virtual environment from the first module to the second module. | 2011-07-28 |
20110185058 | Method and Arrangement for Supporting Playout of Content - Methods and arrangements in a client node and a server node support a decision on decoding and playout of a certain content in the client node. The methods and arrangements relate to the determining, conveying and obtaining of information related to the characteristics (level) required for decoding and playing out the certain media content at a non-regular playout rate. The method and arrangement in the client node further relate to determining, based on the obtained information, which playout rate(s) is/are supported by the client node in regard of level. The methods and arrangements enable the client node to refrain from attempting to decode and play out of the content at a non-regular rate requiring a level which is not supported by the client node. | 2011-07-28 |
20110185059 | SYSTEM AND METHOD FOR DETECTING RF TRANSMISSIONS IN FREQUENCY BANDS OF INTEREST ACROSS A GEOGRAPHIC AREA - Wireless devices form a significant portion of equipment forming the source/destination of content transmitted over telecommunications infrastructure together with applications such as RF identification, smart tags, etc. As such the wireless spectrum supports these devices operating to multiple standards, both licensed and unlicensed. In many environments it would be beneficial for a network administrator to know whether the environment and network they are responsible for is compliant to policies established in dependence of the environment/network. The invention provides distributed wireless signal analyzers within the environment/network to provide signal/spectrum analysis and determine whether received signals by the wireless signal analyzer are compliant to the network administrator policy. Compliance may be based upon time or frequency domain measurements with different rules for different wireless spectrum regions. Non-compliance is communicated to remote servers and/or network administrator and allows local control of network equipment. | 2011-07-28 |
20110185060 | METHOD FOR ALLOWING AND BLOCKING A USER PC WHICH CAN USE INTERNET AT THE SAME TIME IN A PRIVATE NETWORK THEROF A METHOD FOR ANALYZING AND DETECTING A JUDGEMENT ABOUT WHETHER NAT(NETWORK ADDRESS TRANSLATION) CAN BE USED OR NOT USING A TRAFFIC DATA, AND THE NUMBER OF TERMINALS SHARING NAT - The present invention provides a method consisting of a step for analyzing a traffic receiving mirroring, a step for judging whether NAT (Network Address Translation) use of a client configuring and using a private network as well as a provided authorized IP (an Internet IP) is allowed or not, for analyzing and detecting the number of sharing terminals, a step for creating a database using data, and a step for formulating a policy by using information in database, so that when the users of a private network connect to Internet at the same time, permission or blocking of Internet use can be executed selectively. | 2011-07-28 |
20110185061 | System and method for Quarantining IP Service Devices - A system and method for quarantining IP service devices (ISDs). When an ISD is placed into a quarantined environment, any request from the ISD will be re-directed to a quarantine alert server in a quarantine sub-system. In response to the request, the quarantine alert server may provide the user with information about the quarantine and may redirect, or instruct the user to redirect, the request to a quarantine response server. The quarantine response server may provide additional information that is not in the quarantine video message as to how the user may end the quarantine. | 2011-07-28 |
20110185062 | Qualitative Assignment of Resources to a Logical Partition In a Multipartitioned Computer System - A qualitative resource assignment wizard receives qualitative information for a logical partition (LPAR) and calculates computer resource assignments for the LPAR based on the qualitative information and a set of conversion functions. For example, the qualitative resource assignment wizard may calculate a processing unit assignment, a memory assignment, and an I/O slot assignment for the LPAR. The qualitative information may be input by a user, for example, utilizing a graphical user interface (GUI). In one embodiment, the conversion functions are calculated during a training phase, in which a user periodically provides qualitative information while resource usage data is gathered. The wizard may reside in a hardware management console (HMC) or other administrative console and/or may be a component of a hypervisor or other partition management code. Software code associated with the wizard may be provided by a network server application to a client system for enabling a user to remotely input the qualitative information. | 2011-07-28 |
20110185063 | METHOD AND SYSTEM FOR ABSTRACTING NON-FUNCTIONAL REQUIREMENTS BASED DEPLOYMENT OF VIRTUAL MACHINES - A system and method for allocating resources in a cloud environment includes providing an abstraction layer between a cloud environment and one or more data centers by generating a virtual hypervisor as an application programming interface. Responsive to a workload request by the one or more data centers, resources are partitioned and virtual machines are instantiated in the one or more data centers using the virtual hypervisor such that non-functional requirements of the workload are addressed at the abstraction level using the virtual hypervisor. | 2011-07-28 |
20110185064 | SYSTEM AND METHOD FOR FAIR AND ECONOMICAL RESOURCE PARTITIONING USING VIRTUAL HYPERVISOR - A system and method for allocating resources in a cloud environment includes determining permitted usage of virtual machines and partitioning resources between network servers in accordance with a virtual hyperviser generated in accordance with an abstraction layer configured as an interface between a solution manager and an interface to a cloud network. Resource usage limits are determined for each virtual machine associated with the virtual hyperviser, and the servers are analyzed through the virtual hypervisers to determine if the virtual machines need to be migrated. If reallocation is needed, virtual machine migration requests are issued to migrate virtual machines into a new configuration at the virtual hypervisor abstraction level. The servers are reanalyzed to determine if migration of the new configuration is needed. Shares are computed to enforce balance requirements, and virtual machine shares and limits are adjusted for resources according to the computed shares. | 2011-07-28 |
20110185065 | STATELESS FORWARDING OF LOAD BALANCED PACKETS - A load balancer dynamically load balances packets for network connections between clients and servers. When receiving a packet from a client that requests a new connection, the load balancer checks the current load of all the servers and selects the server most suitable to handle the new connection. The load balancer then forwards that packet to the selected server. If the server accepts the request for the new connection, then the server responds with an acknowledgement packet. The acknowledgement packet also includes the server's blade identification that the client uses for all subsequent packets on the accepted connection. When the load balancer receives a packet containing the blade identification, the load balancer forwards the packet to the server corresponding to the blade identification. Backup load balancers can therefore continue packet forwarding services in a smooth and efficient manner. | 2011-07-28 |
20110185066 | Audio/Video Streaming in a Topology of Devices - Resources may be managed in a topology for audio/video streaming. The topology includes audio/video sources and sinks and intervening branch devices. Messages between these sources, sinks, and branch devices may be used for resource management. | 2011-07-28 |
20110185067 | Network-Network Interface - In one embodiment, a method includes receiving at a first portal of a first node data for communication from a first network to a second network that belong to a particular one of a first set of service classes of the first network; determining at the first portal a particular one of a second set of service classes of the second network for the data; and directing the data from the first portal to a second portal of a second node residing at least in part in the second network. | 2011-07-28 |
20110185068 | MULTI-LINK REMOTE PROTOCOL - In various embodiments, a remote client is allowed to access at least a part of a connection service located on alternate sources other than the primary remote presentation server. In some embodiments, the remote presentation virtual channels may be split into multiple connections with the purpose of allowing better flow control. Some embodiments may be implemented in a virtual machine environment for cases in which the data to be transferred through a data channel is located in the host virtual machine partition but the remote endpoint is located on the guest virtual machine partition. | 2011-07-28 |
20110185069 | Method For Establishing A Local Media Connection In A Communication System - The present invention relates to a method for deciding, in an IP-based communication system, whether a local media/media release is allowed between a first and at least a second terminal. The method is characterized in that the decision is based on information established by an application server in an multimedia core network. The present invention further also relates to a session border controller unit, a session border controller, an application server and a computer program product for performing said method. | 2011-07-28 |
20110185070 | METHOD AND DEVICE OF SESSION CONTROL - A method and device of session control are used to resolve the problem that when there is a failure in the session control function bound with the user, the UE can not re-login in time or the session can not be continued. In the flow of the user initial login, an address information of P-CSCF bound with the user in HSS is saved, so that when the user is called, an available S-CSCF can get the address information of P-CSCF bound with the called user from the HSS, and inform the user to do re-initial login according to the address information of P-CSCF or complete the session continuation; further, the address information of the user in D-HSS is saved, so that when the user is called, an available A-CSCF can get the address information of the called user from the D-HSS, and inform the user to do re-initial login according to the address information of the called user or complete the session continuation. | 2011-07-28 |
20110185071 | LOSS TOLERANT PROTOCOL FOR REMOTING DESKTOP GRAPHICS - In various embodiments, remote presentation encoding techniques may be modified in such a way that the data can be transmitted over transports without guaranteed packet delivery. In one embodiment, the desktop graphics data may be encoded in individual frames, each frame comprising self-contained graphics elements that fit in a small number of User Datagram Protocol (UDP) protocol data units (PDUs). The PDUs may then be sent to the client on a separate lossy link instead of the lossless link. On the client side, the client may detect which graphic elements within a frame were “lost” as a result of dropped UDP packets and request a refresh from the server through the lossless channel. | 2011-07-28 |
20110185072 | METHOD AND SYSTEM OF EMULATING DEVICES ACROSS SELECTED COMMUNICATION PATHWAYS THROUGH A TERMINAL SESSION - Emulating devices across selected communication pathways by way of a terminal session. At least some of the illustrative embodiments are methods including establishing a terminal session between a first computer system and a second computer system (the second computer system distinct from the first computer system, and the second computer system having a management processor with a plurality of communication pathways to a main processor of the second computer system), configuring the management processor to send data regarding emulation of a first mass storage device across a first selected pathway of the plurality of communication pathways to the main processor (the configuring by way of the terminal session), and emulating (by the management processor) the first mass storage device across the first selected pathway. | 2011-07-28 |
20110185073 | SYSTEMS AND METHODS FOR CLIENT IP ADDRESS INSERTION VIA TCP OPTIONS - The present disclosure presents systems and methods for maintaining identification of network devices sending or traversing a network packet en route to an intermediary device deployed between a source and a destination network device. An intermediary may receive an acknowledgement packet comprising an option field identified by an option number for a transport layer connection established via intermediary. The acknowledgement packet may comprise overlay network data that identifies IP addresses of the originating network device and host network devices intercepting and forwarding the network packet to the intermediary. The intermediary device may determine the option number for the option field from which to obtain the overlay network data identifying IP addresses. The intermediary device may receive a second request of the client to access the server via the transport layer connection and insert IP addresses from the overlay network data into an application layer protocol header of the second request forwarded to the server. | 2011-07-28 |
20110185074 | REAL-TIME PUBLISH-SUBSCRIBE SYSTEM - A real-time protocol for real-time network programming applications is disclosed. The protocol is executable on a computer network having a plurality of nodes that include applications, a network stack, an operating system, and middleware capable of executing real-time operations. The protocol can use group objects to model physical and logical devices connected to the network wherein each group object comprises at least one variable. Changes in these variables are encapsulated in variable change messages which are propagated in the network using communication objects. Also described is a real-time messaging format useful for implementing the protocol. | 2011-07-28 |
20110185075 | SYSTEM AND METHOD FOR PREVENTING COLLISIONS IN A HIERARCHICAL NETWORK - A system and method for reducing transmission collisions. In one embodiment, a transmitter for communicating of a smart grid power line network includes an arbiter. The arbiter is configured to select a transmission interval during which the transmitter can transmit. The interval is selected from a plurality of available transmission intervals reserved for contending transmissions, and selected based on a level of a hierarchical network at which the transmitter is located. The interval selected is different from any interval used by a different transmitter spaced two hierarchical levels away from the level of the hierarchical network at which the transmitter is located. | 2011-07-28 |
20110185076 | System and Method for Network Interfacing - Systems and methods for network interfacing may include a communication data center with a first tier, a second tier and a third tier. The first tier may include a first server with a first single integrated convergent network controller chip. The second server may include a second server with a second single integrated convergent network controller chip. The third tier may include a third server with a third single integrated convergent network controller chip. The second server may be coupled to the first server via a single fabric with a single connector. The third server may be coupled to the second server via the single fabric with the single connector. The respective first, second and third server, each processes a plurality of different traffic types concurrently via the respective first, second and third single integrated convergent network chip over the single fabric that is coupled to the single connector. | 2011-07-28 |
20110185077 | MULTI-PATTERN MATCHING IN COMPRESSED COMMUNICATION TRAFFIC - A method for processing data includes accepting a specification of a plurality of patterns, each pattern defining a respective uncompressed sequence of symbols. Multi-pattern matching is applied to an incoming stream of compressed communication traffic containing compression metadata so as to identify the patterns occurring in the stream while using the compression metadata to skip over parts of the stream. | 2011-07-28 |
20110185078 | MEDIA SCRUBBING USING A MEDIA PROCESSOR - A system and method for a media processor separates the functions of topology creation and maintenance from the functions of processing data through a topology. The system includes a control layer including a topology generating element to generate a topology describing a set of input multimedia streams, one or more sources for the input multimedia streams, a sequence of operations to perform on the multimedia data, and a set of output multimedia streams, and a media processor to govern the passing of the multimedia data as described in the topology and govern the performance of the sequence of multimedia operations on the multimedia data to create the set of output multimedia streams. The core layer includes the input media streams, the sources for the input multimedia streams, one or more transforms to operate on the multimedia data, stream sinks, and media sinks to provide the set of output multimedia streams. | 2011-07-28 |
20110185079 | ACHIEVING DISTRIBUTED FLOW CONTROL VIA DATA CONFLATION - A distributed method that combines both flow control and smart volume reduction means in a communication network is provided herein. The stages of the method are applied by each node in the network in a distributed way, which adapts to the evolving state of the system. The operations performed by each node in the network are adapted dynamically in a way that adjusts itself to the changes that occur in various parameters of the network. Such parameters include both local node state and also the state of different nodes in the distributed infrastructure. The state of the nodes is characterized by parameters such as transmission rates, available buffer space and the state of data in buffer. The stages are carried out in parallel by the nodes and ordered such that the equality of the data flowing in the network, in terms of delay and specified attributes, is maximized. | 2011-07-28 |
20110185080 | STREAM GENERATING DEVICE, METHOD FOR CALCULATING INPUT BUFFER PADDING LEVEL INSIDE THE DEVICE AND STREAM CONTROL METHOD - The present invention concerns a method of calculating a filtered filling level of the input buffer of a gateway generating a data stream from a received data stream resisting the jitter of the stream received. It applies more particularly to a gateway receiving an MPEG (Moving Picture Experts Group) transport stream received according to the IP protocol (Internet Protocol) and retransmitted over an ASI interface (Asynchronous Serial Interface). | 2011-07-28 |
20110185081 | Process for communication between a device running Java ME.RTM. and a server over the air, as well as related system - Process of communication via HTTP or HTTPS between a device running Java ME® and a server over the air, said server receiving and transmitting SOAP (Simple Object Access Protocol) messages from/to an operator on a host over a network and being capable of exchanging SOAP messages under Application Protocol Data Unit (APDU) data form/with the device, characterized in that the SOAP messages are translated from/to binary messages according to a protocol in the server, said binary messages being exchanged with the device, the binary messages being binary request messages or binary response messages. | 2011-07-28 |
20110185082 | SYSTEMS AND METHODS FOR NETWORK VIRTUALIZATION - In a system for network virtualization in a publish and subscribe middleware architecture, a virtual application executes within an execution module on a computer system, where the virtual application has a virtual address and the computer system has a logical address. A network virtualization module manages message routing for the virtual application and a data forwarding plane performs message routing for the virtual application. A communication interface identifies a correspondence between the virtual address and the logical address during message routing with the data forwarding plane and the virtual application. | 2011-07-28 |
20110185083 | IDENTIFIER AND LOCATOR STRUCTURE, AND COMMUNICATION METHOD BASED ON THE STRUCTURE - In an identifier and locator structure and a communication method based on the structure, only an identifier to identify a communication object is allocated to a mobile host, and a locator to indicate the location of the communication object is allocated to a corresponding end router. Accordingly, the mobile host and the end router communicate with each other on the basis of the identifier, and a source-side end router and a designation-side end router communicate with each other on the basis of the locator. | 2011-07-28 |
20110185084 | INFORMATION COMMUNICATION SYSTEM, RELAY NODE DEVICE, INFORMATION COMMUNICATION METHOD, AND COMPUTER READABLE RECORDING MEDIUM - An information communication system including, among a plurality of node devices, a relay node device which is connected to a private network and which relays the messages between the private network and an external network differing from the private network, wherein the relay node device comprising relay unit configured to relay the message after causing the global address information acquired by the acquisition unit to be contained in the message in response to relaying the message from the private network to the external network, and to relay the message after causing the private address information acquired by the acquisition unit to be contained in the message in response to relaying the message from the external network to the private network which is connected to the external network. | 2011-07-28 |
20110185085 | Network Address Translation Based on Recorded Application State - A method and system for improved NAT operation enable efficient translation for packets destined for communication systems within a domain utilizing network addresses that are incompatible with source and destination addresses indicated in packets delivered from the global Internet. Since the addresses are not compatible with global Internet addresses, delivery cannot be accomplished except by some method of address translation. Traditional systems have not been constructed to enable such inbound translations, providing, instead, only communication outbound from the incompatibly addressed domain towards the global Internet. Embodiments may employ application-specific knowledge for peer-to-peer based applications, associated over time with specific destinations. Embodiments may further employ an application-specific state machine in the NAT function to trace the development of the application protocol so that the resource identifier can be observed. | 2011-07-28 |
20110185086 | APPARATUS AND METHOD FOR PRODUCING DEVICE IDENTIFIERS FOR SERIALLY INTERCONNECTED DEVICES OF MIXED TYPE - A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. In cases of different device types being separately provided to the interconnected devices, sequential IDs are generated in each of the different device types and also the total number of each device type are recognized. In a case of a “don't care” code is provided to the interconnected devices, sequential IDs are generated and also, the total number of the interconnected devices is recognized, regardless of the type differences. | 2011-07-28 |
20110185087 | Data Transfer Between Devices Maintaining State Data - Transferring data between devices utilizing state data. The devices may include a writer device and a reader device, each coupled to a common bus. A host device may create a transfer session between the devices. Each of the host device, the writer device, and the reader device may maintain state data of the transfer session. The host device may notify at least one of the reader device or the writer device of a state change from a disabled state to an enabled state. After enabling, data may be transferred directly between the writer device and the reader device without involving the host device. Finally, the host device may notify at least one of the reader device or the writer device of a state change from the enabled state to the disabled state. After disabling, the direct transfer of data between the writer device and the reader device may be stopped. | 2011-07-28 |
20110185088 | Asynchronous computer communication - A computer array ( | 2011-07-28 |
20110185089 | Method and System for Supporting Hardware Acceleration for iSCSI Read and Write Operations and iSCSI Chimney - Certain aspects of a method and system for supporting hardware acceleration for iSCSI read and write operations via a TCP offload engine may comprise pre-registering at least one buffer with hardware. An iSCSI command may be received from an initiator. An initiator test tag value, a data sequence value and/or a buffer offset value of an iSCSI buffer may be compared with the pre-registered buffer. Data may be fetched from the pre-registered buffer based on comparing the initiator test tag value, the data sequence value and/or the buffer offset value of the iSCSI buffer with the pre-registered buffer. The fetched data may be zero copied from the pre-registered buffer to the initiator. | 2011-07-28 |
20110185090 | Apparatus for Translating and Expanding Inputs for a Point Of Sale Device - An apparatus includes a PS2 input for receiving first input logic signals from a first device. A USB input receives second input logic signals from a second device. A RS232 input receives third input logic signals from a third device. A TTL input receives fourth input logic signals from a fourth device. A programmed logic circuit translates the first input logic signals, the second input logic signals, the third input logic signals and the fourth input logic signals to first output logic signals having a RS232 output. The programmed logic circuit further translates the first input logic signals, the second input logic signals, the third input logic signals and the fourth input logic signals to second output logic signals having a TTL output. A RS232 output transmits the first output logic signals to a POS device and a TTL output transmits the second output logic signals to a POS device. Input Ports for logic signals may be distinct in cases where a signal translation function is sought. Input Ports for logic signals may also be repeated for the same input logic where an expansion function is sought. | 2011-07-28 |
20110185091 | Wireless Bus for Intra-Chip and Inter-Chip Communication, Including Data Center/Server Embodiments - Embodiments of the present invention are directed to a wire-free data center/server. The data center/server is wire-free in the sense that communication within a data unit of the data center/server (i.e., intra-data unit), between data units of the data center/server (inter-data unit), and between the data units and the backplane of the data center/server is performed wirelessly. | 2011-07-28 |
20110185092 | Configurable System of Wireless-Enabled Components And Applications Thereof - Disclosed herein is a configurable system of wireless-enabled components (WECs) and applications thereof. The system includes a plurality of WECs and a controller. Each WEC comprises a functional resource and is adapted to wirelessly communicate with other WECs. The controller is adapted to dynamically configure the functional resource of each WEC and wireless communications among the plurality of WECs to form a field-programmable communications array. The controller may be one of the plurality of WECs. The plurality of WECs may be located on a single chip, on multiple chips of a single device, or on multiple chips of multiple devices. | 2011-07-28 |
20110185093 | COMMUNICATION SLAVE AND COMMUNICATION NETWORK SYSTEM - In a communication network system in which a master and a plurality of communication slaves are coupled through a high-potential side bus and a low-potential side bus in a daisy-chain manner, each of the communication slaves includes a control circuit, a resistance element, and a potential difference detecting portion. The control circuit controls communication with the master. The resistance element is inserted into the high-potential side bus at a portion located downstream of a point where the control circuit is coupled with the high-potential side bus. The potential difference detecting portion detects a potential difference between an upstream terminal of the resistance element and the low-potential side bus. The control circuit sets an ID value for communicating with the master in accordance with the potential difference detected by the potential difference detecting portion. | 2011-07-28 |
20110185094 | DATA TRANSFER CONTROL DEVICE AND DATA TRANSFER CONTROL METHOD - A data transfer control device that selects one of a plurality of DMA channels and transfers data to or from memory includes a request holding section configured to hold a certain number of data transfer requests of the plurality of DMA channels and a request rearranging section configured to select and rearrange the data transfer requests that are held in a basic transfer order so that the data transfer requests of each of the plurality of DMA channels are successively outputted for a number of successive transfers set in advance. | 2011-07-28 |
20110185095 | ARBITRATION SCHEME FOR ACCESSING A SHARED RESOURCE - A processing system includes a shared resource, an arbitration module, and a requesting device for issuing requests to the arbitration module to access the shared resource to perform transactions on the shared resource. The arbitration module grants access to the requesting device for a fixed time duration. The fixed time duration comprises one of a plurality of time durations including a first and a second time duration; the second longer than the first. The requesting device prioritizes performance of the transactions on the shared resource based upon the fixed time duration and types of transactions to be performed. Transaction type comprises one of a plurality of types including a first type that requires a time duration that can be performed within the first time duration and a second type that requires a time duration that exceeds the first time duration but can be performed within the second time duration. | 2011-07-28 |
20110185096 | SYSTEMS AND METHODS FOR EMBEDDING INTERRUPTS INTO A SERIAL DATA STREAM - Systems and methods for transmitting and processing interrupts by embedding interrupt information into a serial data stream are disclosed. An event is detected and converted into an interrupt signal. The interrupt signal is converted into a special interrupt character or symbol sequence. The special interrupt character or symbol sequence is embedded into a serial data stream at the next available character or symbol boundary and transmitted to a receiving controller. The receiving controller strips the special interrupt character or symbol sequence from the serial data stream and raises a corresponding interrupt. The receiving controller processes the interrupt by interrupting normal processing to run an interrupt subroutine. Once the receiver has detected and raised an interrupt, it can return an acknowledgement character or symbol sequence by the same mechanism. The transmitter can repeat the interrupt embedding and transmission if it fails to receive the acknowledgement within a predetermined period of time. | 2011-07-28 |
20110185097 | Method And System For A Connector With Integrated Shield Detection - A connector comprising one or more circuits and/or processors is operable to determine characteristics of an attached corresponding connector, an attached cable and/or a channel established via the corresponding connector and/or cable. The characteristics are stored in a register on the connector and/or communicated via a pin connection to a host and/or upstream device. Ganged connectors may communicate via a shared pin. Sensing pins in the connector detect presence of a shield on the cable. Cable diagnostics are run on the attached corresponding connector and cable by a PHY device that may be integrated within the connector. The connector may determine characteristics such as cable length, cable grade, presence of shielding, channel characteristics and/or crosstalk on the attached corresponding connector and/or cable. Based on the determined characteristics, a data rate is determined, transmission parameters are auto-negotiated and/or data may be communicated. | 2011-07-28 |
20110185098 | MEMORY CARD SUPPLEMENTED WITH WIRELESS COMMUNICATION MODULE, TERMINAL FOR USING SAME, MEMORY CARD INCLUDING WPAN COMMUNICATION MODULE, AND WPAN COMMUNICATION METHOD USING SAME - A memory card with a wireless communication module attached and its associated terminal for using the memory card are disclosed. A memory card that provides both of an external memory to an information communication terminal and a connectable memory card WPAN add-on to an information communication terminal lacking a built-in wireless communication module, and its associated information communication terminal are disclosed. According to the disclosure, the memory card with the extra wireless communication module adds the WPAN function to the information communication terminal lacking a built-in wireless communication module by inserting it into a card slot of the terminal, protecting the wireless communication module from external impacts and permitting the module to be left and secured inside the terminal at the card slot without a concern to lose such a module. | 2011-07-28 |
20110185099 | Modular and Redundant Data-Storage Controller And a Method for Providing a Hot-Swappable and Field-Serviceable Data-Storage Controller - A modular and redundant storage controller system includes management modules, controller modules and an interconnect module. The management modules provide direct-current power and signals to respective controller modules. The controller modules include respective signal interfaces, direct-current interfaces, and interconnect interfaces. The signal interfaces couple the controllers to a respective management module. The direct-current interfaces couple the controllers to a respective management module. The interconnect module includes a pair of connectors arranged to couple a pair of the controller modules via the respective interconnect module interfaces. | 2011-07-28 |
20110185100 | Virtual Heterogeneous Channel For Message Passing - A technique includes using a virtual channel between a first process and a second process to communicate messages between the processes. Each message contains protocol data and user data. All of the protocol data is communicated over a first channel associated with the virtual channel, and the user data is selectively communicated over at least one other channel associated with the virtual channel. | 2011-07-28 |
20110185101 | SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM - A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact. | 2011-07-28 |
20110185102 | BUS BRIDGE AND METHOD FOR INTERFACING OUT-OF-ORDER BUS AND MULTIPLE ORDERED BUSES - A method for interfacing an out-of-order bus and multiple ordered buses and a bus bridge. The bus bridge includes multiple ordered bus interfaces, where each ordered bus interface is coupled to an ordered bus. A flow control logic circuit is coupled to the out-of-order bus and to the multiple ordered bus interfaces. The flow control logic circuit controls a flow of transaction requests between the out-of-order bus and each of the ordered buses interfaces. The flow control logic circuit includes an updating circuit for updating dependency resolution attributes and data readiness attributes associated with transaction requests, and a shared memory unit for storing the dependency resolution attributes, the data readiness attributes and the transaction requests where the transaction requests are destined to the ordered buses. A managing circuit, coupled to the shared memory unit and to the multiple ordered bus interfaces, is used to determine a readiness of each transaction request based on a dependency resolution attribute and a data readiness attribute associated with the transaction request, and for managing a dequeueing of ready transaction requests to the ordered bus interfaces based on an availability of the ordered bus interfaces. | 2011-07-28 |
20110185103 | Serial communication device configurable to operate in root mode or endpoint mode - Systems and methods according to the present invention provide serial communication devices which are pin-configurable at power on to operate as either a root ( | 2011-07-28 |
20110185104 | Merging Subsequent Updates To A Memory Location - A method of merging subsequent updates to a memory location includes receiving, at a first stage in an update pipeline, a first request to update a status word at a first address of a cache memory and receiving the status word from the cache memory. The method continues with determining, at a stage subsequent to the first stage, that a second request to update the status word has been received. Further included is updating the status word according to the first and second requests to form an updated status word and writing the updated status word to the cache memory. | 2011-07-28 |
20110185105 | MEMORY SYSTEM - A memory system in which speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponds to the logical address, and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position. These forward and reverse lookup tables are linked. | 2011-07-28 |
20110185106 | MEMORY SYSTEM - A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past. | 2011-07-28 |
20110185107 | MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer. The first pointer is stored in a fixed area in the second storing unit and the second pointer is stored in an area excluding the fixed area in the second storing unit. | 2011-07-28 |
20110185108 | MEMORY SYSTEM - A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which a plurality of memory cells that can store multi-value data are arranged, the memory cells having a plurality of pages, and a controller that performs data transfer between a host apparatus and the second storing unit via the first storing unit. The controller includes a save processing unit that backs up, when, before data is written in the second storing unit in a write-once manner, data is written in a lower order page of a memory cell same as that of a page in which the data is written, the data of the lower order page and a broken-information-restoration processing unit that restores, when the data in the lower order page is broken, the broken data using the backed-up data. | 2011-07-28 |
20110185109 | High Performance Data Rate System for Flash Devices - A Flash memory system includes N flash devices, where N is an integer, each flash device having a flash device interface consisting of a control signal line, a R/B signal line, and a I/O signal line, and wherein each flash device has an operating speed of s. A logic block is connected to each flash device interface, and is further connected to a controller which whose interfaces also has a control signal line, a R/B signal line, and a I/O signal line, so that controller operates at an operating speed of N times s, and wherein the logic block controls each flash device simultaneously. | 2011-07-28 |
20110185110 | METHOD AND DEVICE FOR PROTECTING INFORMATION CONTAINED IN AN INTEGRATED CIRCUIT - An integrated circuit and a method of protection of an integrated circuit provides for a test controller state machine (TCSM) to be coupled to a control structure and/or an input and/or an output of at least one data storage device of the integrated circuit. The TCSM monitors the state of the data storage device and, upon a test request to the integrated circuit, causes the information in the data storage device to be changed or blocked until the data storage device is deemed safe for access. Such an integrated circuit and method protects information contained in data storage devices of the integrated circuit from being revealed during testing of circuitry of the integrated circuit. | 2011-07-28 |
20110185111 | Systems and Methods for Extended Life Multi-Bit Memory Cells - Various embodiments of the present invention provide for extended life operation of multi-bit memory cells. As an example, some embodiments of the present invention provide electronic systems that include a plurality of multi-bit memory cells, an encoding circuit and a decoding circuit. Each of the plurality of multi-bit memory cells is operable to hold at least two bits. The encoding circuit is operable to receive a data input including at least two data bits, and to encode the two data bits as an encoded output to the plurality of multi-bit memory cells. The encoded output may be selected to be either a single two bit output representing the two bits, or a series of two two bit outputs representing the two bits. The decoding circuit is operable to reverse the encoding applied by the encoding circuit. | 2011-07-28 |
20110185112 | Verifying Whether Metadata Identifies a Most Current Version of Stored Data in a Memory Space - Method and apparatus for verifying whether metadata identifies a most current version of data stored in a memory space. In accordance with various embodiments, a physical location within a first portion of a solid-state memory space is identified by metadata as storing a current version of user data having a selected logical address. A reverse search is performed upon a second portion of the memory space to determine whether the physical address identified by the metadata stores a stale version of the user data, or whether the physical address stores the current version. | 2011-07-28 |
20110185113 | Maintaining Data Integrity in a Data Storage Device - Method and apparatus for maintaining data integrity in a data storage device. In accordance with some embodiments, a memory space has a plurality of garbage collection units (GCUs) each arranged to store user data identified by logical addresses. Each GCU has a metadata region that stores metadata that correlates the logical addresses LBAs with physical addresses and a header region that stores descriptor data that identifies LBAs stored in the associated GCU. A control circuit identifies an error in the metadata from the descriptor data of a selected GCU and rebuilds the metadata to indicate a storage location of a most current version of data associated with a selected logical address. | 2011-07-28 |
20110185114 | SYSTEM AND METHOD FOR READ-WHILE-WRITE WITH NAND MEMORY DEVICE - System, method, and program to perform simultaneous read and write operations in a NAND-type memory device, including: assigning a first partition in a NAND-type memory device, wherein the first partition is configured to perform read operations on high priority read content; assigning a second partition in the NAND-type memory device, wherein the second partition is configured to perform read operations and write operations, wherein the read operations are performed on non-high priority read content; and controlling the first partition and second partition to operate in a simultaneous manner. | 2011-07-28 |
20110185115 | METHOD AND DEVICE FOR PERFORMING DIAGNOSTICS ON A MOTOR VEHICLE MANAGEMENT SYSTEM - A device for recording data emitted from a motor vehicle management system, including a volatile memory, a non-volatile memory, and a data recording module configured to receive a signal concerning activation status emitted by the management system and to record the data in a first zone of the volatile memory on a rising edge of the activation status signal and in a second zone of the volatile memory on a falling edge of the activation status signal, and including a record management module configured to receive the activation status signal and to activate a command to record on a falling edge with the activation status signal, the recording module being further configured to receive the record command and to record the content of the two zones of the volatile memory into a zone of the non-volatile memory when the record command is activated. | 2011-07-28 |
20110185116 | Memory device with vertically embedded non-flash non-volatile memory for emulation of NAND flash memory - A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example. | 2011-07-28 |
20110185117 | SYSTEMS AND METHODS FOR MANAGING A CACHE IN A MULTI-NODE VIRTUAL TAPE CONTROLLER - According to one embodiment, a system includes a virtual tape library having a cache, a virtual tape controller (VTC) coupled to the virtual tape library, and an interface for coupling at least one host to the VTC. The cache is shared by all the hosts, and a common view of a cache state, a virtual library state, and a number of write requests pending is provided to all the hosts by the VTC. In another embodiment, a method includes receiving data from at least one host using a VTC, storing data received from all the hosts to a cache using the VTC, sending an alert to all the hosts when free space is low and entering into a warning state, sending another alert to all the hosts when free space is critically low and entering into a critical state while allowing previously mounted virtual drives to continue normally. | 2011-07-28 |
20110185118 | STORAGE SYSTEM - The storage system includes a disk controller for receiving write commands from a computer, and a plurality of disk devices in which data is written in accordance with the control of the disk controller. The size of the first block which constitutes the data unit handled in the execution of the input/output processing of the data in accordance with the write command by the disk controller is different from the size of the second block which constitutes the data unit handled in the execution of the input/output processing of data by the plurality of disk devices. The disk controller issues an instruction for the writing of data to the disk devices using a third block unit of a size corresponding to a common multiple of the size of the first block and the size of the second block. | 2011-07-28 |
20110185119 | PARITY GENERATOR FOR REDUNDANT ARRAY OF INDEPENDENT DISCS TYPE MEMORY - In a Redundant Array of Independent Discs (RAID) type memory, dual parities P and Q are generated by a dual XOR engine that performs a plain XOR operation for parity P and a weighted XOR operation for parity Q. The plain and weighted XOR operations may be performed in a single pass. | 2011-07-28 |
20110185120 | METHOD FOR PLACEMENT OF VIRTUAL VOLUME HOT-SPOTS IN STORAGE POOLS USING ONGOING LOAD MEASUREMENTS AND RANKING - The present invention is directed to a method for providing data element placement in a storage system via a Dynamic Storage Tiering (DST) mechanism, such that improved system efficiency is promoted. For example, the DST mechanism may implement an algorithm for providing data element placement. The data elements (ex.—virtual volume hot-spots) may be placed into storage pools, such that usage of higher performing storage pools is maximized. Hot-spots may be detected by dynamically measuring load on LBA ranges. Performance of the storage pools may be measured on an ongoing basis. Further, the hot-spots may be ranked according to load, while storage pools may be ranked according to measured performance. If a hot-spot's load decreases, the hot-spot may be moved to a lower performing storage pool. If a hot-spot's load increases, the hot-spot may be moved to a higher performing storage pool. | 2011-07-28 |
20110185121 | MIRRORING MULTIPLE WRITEABLE STORAGE ARRAYS - Systems, methods, and computer program products for mirroring dual writeable storage arrays are provided. Various embodiments provide configurations including two or more mirrored storage arrays that are each capable of being written to by different hosts. When commands to write data to corresponding mirrored data blocks within the respective storage arrays are received from different hosts at substantially the same time, write priority for writing data to the mirrored data blocks is given to one of the storage arrays based on a predetermined criterion or multiple predetermined criteria. | 2011-07-28 |
20110185122 | STORAGE SYSTEM AND METHOD OF PROCESSING DATA USING THE SAME - A storage system includes a plurality of data processing devices connected in series. One of the data processing devices either accesses a first data storage device or transmits an access command output from a host to an next data processing device in the series according to the access command. The data processing device determines whether to access a second data storage device according to the received access command. | 2011-07-28 |
20110185123 | STORAGE DEVICE - A storage device is provided with a file I/O interface control device and a plurality of disk pools. The file I/O interface control device sets one of a plurality of storage hierarchies defining storage classes, respectively, for each of LUs within the disk pools, thereby forming a file system in each of the LUs. The file I/O interface control device migrates at least one of the files from one of the LUs to another one of the LUs of an optimal storage class, based on static properties and dynamic properties of each file. | 2011-07-28 |
20110185124 | STORAGE SYSTEM THAT EXECUTES PERFORMANCE OPTIMIZATION THAT MAINTAINS REDUNDANCY - One storage area is selected from two or more storage areas of a high load physical storage device, a physical storage device with a lower load than that of the physical storage device is selected, and it is judged whether the redundancy according to the RAID level corresponding to the logical volume decreases when the data elements stored in the selected storage area are transferred to the selected low load physical storage device. If the result of this judgment is that the redundancy does not decrease, the data elements stored in the selected storage area are transferred to a buffer area of the selected low load physical storage device and the logical address space of the logical volume that corresponds to the selected storage area is associated with the buffer area. | 2011-07-28 |
20110185125 | RESOURCE SHARING TO REDUCE IMPLEMENTATION COSTS IN A MULTICORE PROCESSOR - A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently. | 2011-07-28 |
20110185126 | MULTIPROCESSOR SYSTEM - When a processor has transitioned to an operation stop state, it is possible to reduce the power consumption of a cache memory while maintaining the consistency of cache data. A multiprocessor system includes first and second processors, a shared memory, first and second cache memories, a consistency management circuit for managing consistency of data stored in the first and second cache memories, a request signal line for transmitting a request signal for a data update request from the consistency management circuit to the first and second cache memories, an information signal line for transmitting an information signal for informing completion of the data update from the first and second cache memories to the consistency management circuit, and a cache power control circuit for controlling supply of a clock signal and power to the first and second cache memories in accordance with the request signal and the information signal. | 2011-07-28 |
20110185127 | PROCESSOR CIRCUIT WITH SHARED MEMORY AND BUFFER SYSTEM - The processor circuit ( | 2011-07-28 |
20110185128 | Memory access method and information processing apparatus - To maintain data consistency in an information processing apparatus in which a nodes are coupled, takeout information indicating that data of the node is taken out to a secondary memory of another node is stored in a directory of each node. When a cache miss occurs during a memory access to a secondary memory of one node, the one node judges whether a destination of the memory access is a main or the secondary memory thereof. If the memory access is destination is the main or secondary memory of the one node, the directory is indexed and retrieved to judge whether a directory hit occurs, and if no directory hit occurs, a memory access is performed by the one node based on the memory access. | 2011-07-28 |
20110185129 | SECONDARY JAVA HEAPS IN SHARED MEMORY - A computing system includes a first virtual machine associated with a memory region readable by the first virtual machine, and a first private memory region. A data object is created by the first virtual machine in the sharable memory region, readable and writeable by the first virtual machine and a second virtual machine. A mapping is established between the first virtual machine and a particular area of the shareable memory region. The computing system includes the second virtual machine associated with a second private memory region, and a reference to the particular area of the shareable memory region. The mapping enables both the first virtual machine and second virtual machine to read and write second data in the shareable memory region without creating a copy of the second data in the first and second private memory regions. | 2011-07-28 |
20110185130 | COMPUTER SYSTEM AND STORAGE CONSOLIDATION MANAGEMENT METHOD - In order to properly use resources according to the application or search for available resources in an environment in which a block storage apparatus and a file storage apparatus coexist, knowledge and experience of applications and storage apparatuses, as well manpower were required. Thus, a policy pre-defined with a preferred type of interface and a preferred type of storage area for each type of application that is loaded in the host computers is predetermined, configuration information is collected from each storage apparatus, each intermediate storage apparatus and each host computer, respectively, a combination of a storage apparatus, an intermediate storage apparatus and a host computer that is suitable for the type of application designated by a user is detected based on the collected configuration information of each storage apparatus, each intermediate storage apparatus and each host computer, the policy, and the type of application designated by the user, and the detected combination is presented to the user. | 2011-07-28 |
20110185131 | RECORDING CONTROL DEVICE - A recording control device includes: an interface unit | 2011-07-28 |
20110185132 | METHOD AND SYSTEM FOR STORING MEMORY COMPRESSED DATA ONTO MEMORY COMPRESSED DISKS - In a computer system supporting memory compression and wherein data is stored on a disk in a different compressed format, and wherein an IOA (input/output adaptor)/IOP (input/output processor) selectively reads from and writes to a main memory through a direct memory access (DMA) operation, a method for transmitting compressed data from the IOA/IOP to the main memory includes reserving a set of free memory sectors to contain the data in said main memory, sending to the IOA/IOP addresses of said memory sectors, copying the data from the IOA/IOP to said memory sectors using said DMA operation, constructing at the IOA/IOP compressed memory directory information defining how and where the data is stored in memory, sending the memory directory information to a memory controller, and storing the memory directory information in the compressed memory directory structure. | 2011-07-28 |
20110185133 | System and Method for Identifying Locations Within Data - Described are computer-based methods and apparatuses, including computer program products, for removing redundant data from a storage system. In one example, a data delineation process delineates data targeted for de-duplication into regions using a plurality of markers. The de-duplication system determines which of these regions should be subject to further de-duplication processing by comparing metadata representing the regions to metadata representing regions of a reference data set. The de-duplication system identifies an area of data that incorporates the regions that should be subject to further de-duplication processing and de-duplicates this area with reference to a corresponding area within the reference data set. | 2011-07-28 |
20110185134 | TEMPORARY STATE SERVICE PROTOCOL - A temporary state service protocol is utilized by clients to temporarily store and access data within a temporary data store between different requests. Each client associated with a web page can create data in the data store independently from other clients for the same web page. An Application Programming Interface (API) is used to manage and interact with the data in the data store. The procedures in temporary state service protocol allow clients to add, modify, retrieve, and delete data in the data store. The clients may also use the API to place and remove virtual locks on instances of the data. | 2011-07-28 |
20110185135 | STORAGE APPARATUS AND ITS CONTROL METHOD - In a storage apparatus and its control method including multiple first virtual volumes to be provided to a host system and multiple pools each having a memory capacity, and equipped with a function of dynamically allocating a storage area to the first virtual volumes from the pools associated with the first virtual volumes in accordance with the usage status of the first virtual volumes, the unused capacity in each of the pools is managed, and, when the unused capacity of one of the pools falls below a predetermined threshold value, a part of the unused capacity of the other pools is allocated to the one pool. It is thereby possible to realize a highly reliable storage apparatus and its control method. | 2011-07-28 |
20110185136 | MOVING LARGE DYNAMIC DATASETS VIA INCREMENTAL CHANGE SYNCHRONIZATION - Incremental change synchronization for moving large data sets may be provided. Source data to be moved may be identified and a snapshot of the data may be created. The data may be moved to a new datastore and a second snapshot may be created. The snapshots may be compared to identify any data elements that have been modified and the modified elements may be copied to the new datastore. | 2011-07-28 |
20110185137 | CONCURRENT COPY OF SYSTEM CONFIGURATION GLOBAL METADATA - Method, system, and computer program product embodiments for concurrent copy of system configuration global metadata in a data storage system are provided. In one exemplary embodiment, a global data rank is quiesced, followed by an unquiesce of the global data rank except for a global metadata area. The global metadata area is updated in memory, and then unquiesced. A current range of the global metadata area to be copied is quiesced. The current range of the global metadata area is copied from a source area to a target area. The current range is unquiesced. The steps of quiescing an additional current range, copying the range from a source area to a target area, and unquiescing the current range continue until the entire global metadata area has been copied. | 2011-07-28 |
20110185138 | METHOD AND APPARATUS FOR CONTROLLING ACCESS TO A COMPUTING DEVICE - A computing device having controlled access and a method for controlling access there to are provided, the computing device comprising a memory device, a display device, and an input device. Data for rendering a map is retrieved from the memory device. The display device is controlled to render the map using the data. Geographic location data representative of a sequence of geographic locations selected from the map is received, via the input device. The geographic location data is converted to received password data. The received password data is compared to stored password data. If a match is found, access is granted to the computing device. | 2011-07-28 |
20110185139 | COMPUTER SYSTEM AND ITS CONTROL METHOD - This invention intends to provide the computer system equalizing the storage capacity immediately and appropriately to multiple real logical areas dynamically providing storage capacity to virtual logical areas. This invention is the computer system which, in the process of performing the dynamic allocation of storage areas to virtual volumes in response to accesses from the higher-level device, when adding pool volumes to the pool, migrates storage areas among multiple logical areas, and maintains the balance of the storage capacity. | 2011-07-28 |
20110185140 | METHOD AND APPARATUS TO SUPPORT DETERMINING STORAGE AREA UNIT SIZE - An information system comprises a host computer; a management computer; and a storage system including a storage controller and a plurality of storage volumes, the storage system configured to provide thin provisioned volumes from the plurality of storage volumes to the host computer for input/output. Each thin provisioned volume includes a plurality of segments which are provided by chunks of the storage volumes in the storage system. The storage controller is configured to assign a chunk to a segment on demand, analyze effectiveness of different chunk sizes for a chunk to be assigned to a segment and provide a report of the analyzed effectiveness to the management computer, and determine a size of a chunk to be assigned to a segment based on input from the management computer after the management computer receives the report of analyzed effectiveness. | 2011-07-28 |
20110185141 | DATA MIGRATION IN A DISPERSED STORAGE NETWORK - A method begins by processing module determining data to migrate, wherein the data is stored as a plurality of sets of encoded data slices in a first set of dispersed storage (DS) units. The method continues with the processing module retrieving at least a read threshold number of encoded data slices for each set of the plurality of sets of encoded data slices and dispersed storage error decoding the at least the read threshold number of encoded data slices in accordance with error coding dispersal storage function parameters to reproduce the data. The method continues with the processing module dispersed storage error encoding the data in accordance with second error coding dispersal storage function parameters to produce a plurality of sets of second encoded data slices and sending at least a write threshold number of second encoded data slices to a second set of DS units for storage therein. | 2011-07-28 |
20110185142 | INFORMATION PROCESSING APPARATUS AND DATA SAVING ACCELERATION METHOD OF THE INFORMATION PROCESSING APPARATUS - According to one embodiment, an information processing apparatus includes a first storage, a second storage, a data saving module, and a data saving acceleration module. The data saving module is configured to save data stored in the first storage to the second storage after compressing the data stored in the first storage. The data saving acceleration module is configured to reserve a storage area on the first storage and to write predetermined data to the reserved storage area in order to fill the reserved storage area with regular data with high compression efficiency, when the data saving module saves the data stored in the first storage to the second storage. | 2011-07-28 |
20110185143 | RESET DAMPENER - A memory reset system including a first memory socket and a second memory socket. A reset signal generator can generate a reset signal to the first memory socket. A dampener circuit can receive the reset signal from the reset signal generator and transmit a dampened reset signal to the second memory socket. | 2011-07-28 |
20110185144 | Low-Contention Update Buffer Queuing for Small Systems - A method for queuing update buffers to enhance garbage collection. The method includes running an application thread and providing, for the application thread, a data structure including current and finished update buffer slots. The method includes providing an update buffer for the application thread and storing a pointer to the update buffer in the current update buffer slot. The method includes storing null in the finished update buffer slot and, with the application thread, writing to the update buffer. The thread may write a pointer to the filled update buffer in the finished update buffer slot after the buffer is filled. The method includes using a garbage collector thread to inspect the finished update buffer slot and claim filled buffers and change the pointer to null. The thread then obtains an empty update buffer and updates the current update buffer slot to point to the new buffer. | 2011-07-28 |
20110185145 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor storage device comprises nonvolatile memories, memory controllers connected to the nonvolatile memories, and an arbitration module. The arbitration module is configured to control a timing of permitting one of operations of program, erase, and read of the memory controllers. | 2011-07-28 |
20110185146 | MULTIPLE ACCESS TYPE MEMORY AND METHOD OF OPERATION - A method for accessing a memory includes receiving a first address wherein the first address corresponds to a demand fetch, receiving a second address wherein the second address corresponds to a speculative prefetch, providing first data from the memory in response to the demand fetch in which the first data is accessed asynchronous to a system clock, and providing second data from the memory in response to the speculative prefetch in which the second data is accessed synchronous to the system clock. The memory may include a plurality of pipeline stages in which providing the first data in response to the demand fetch is performed such that each pipeline stage is self-timed independent of the system clock and providing the second data in response to the speculative prefetch is performed such that each pipeline stage is timed based on the system clock to be synchronous with the system clock. | 2011-07-28 |
20110185147 | EXTENT ALLOCATION IN THINLY PROVISIONED STORAGE ENVIRONMENT - Method, apparatus, and computer program product embodiment for allocating a plurality of extents in a thinly provisioned computing storage environment are provided. In one such embodiment, subsequent to a write request and previous to entering a cache of the computing storage environment, a determination is made, for a logical extent, whether a real extent is available. Pursuant to determining the availability of the real extent, the logical extent is allocated to the real extent by updating system metadata associated with the logical extent. | 2011-07-28 |
20110185148 | Data Management Method in Storage Pool and Virtual Volume in DKC - A storage system connected to a computer and a management computer, includes storage devices accessed by the computer, and a control unit for controlling the storage devices. A first-type logical device corresponding to a storage area set in at least one of the storage devices and a second-type logical device that is a virtual storage area are provided. The control unit sets at least two of the first-type logical devices different in a characteristic as storage areas included in a storage pool through mapping. The first-type logical device stores data by allocating a storage area of the second-type logical device to a storage area of the first-type logical device mapped to the storage pool. The characteristic of the second-type logical device can be changed by changing the allocated storage area of the second-type logical device to a storage area of another first-type logical device. | 2011-07-28 |
20110185149 | DATA DEDUPLICATION FOR STREAMING SEQUENTIAL DATA STORAGE APPLICATIONS - Data deduplication compression in a streaming storage application, is provided. The disclosed deduplication process provides a deduplication archive that enables storage of the archive to, and extraction from, a streaming storage medium. One implementation involves compressing fully sequential data stored in a data repository to a sequential streaming storage, by: splitting fully sequential data into data blocks; hashing content of each data block and comparing each hash to an in-memory lookup table for a match, the in-memory lookup table storing all hashes that have been encountered during the compression of the fully sequential data; for each data block without a hash match, adding the data block as a new data block for compression of fully sequential data; and encoding duplicate data blocks using the in-memory lookup table into data segments. | 2011-07-28 |
20110185150 | Low-Overhead Misalignment and Reformatting Support for SIMD - Systems and methods for performing single instruction multiple data (SIMD) operations on a data set. The methods may include examining a structure of the data set to determine what reorganization may be necessary to facilitate SIMD processing. The method may include selecting a stored bit mask corresponding to the organization of the data set and loading the bit mask into an application specific register (ASR). Subsequently, the data may be reorganized inline according to the ASR as the data is loaded into the SIMD functional unit such that the SIMD functional unit may operate on the data set. The results of the SIMD operation may be written to a results register. | 2011-07-28 |
20110185151 | Data Processing Architecture - A parallel processor is described which is operated in a SIMD manner. The processor comprises: a plurality of processing elements connected in a string and grouped into a plurality of processing units, wherein each processing unit comprises a plurality of processing elements which each have direct interconnections with all of the other processing elements within the respective processing unit, the interconnections enabling data transfer between any two elements within a unit to be effected in a single clock cycle. | 2011-07-28 |
20110185152 | RECONFIGURABLE CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction. | 2011-07-28 |
20110185153 | SIMULTANEOUS EXECUTION RESUMPTION OF MULTIPLE PROCESSOR CORES AFTER CORE STATE INFORMATION DUMP TO FACILITATE DEBUGGING VIA MULTI-CORE PROCESSOR SIMULATOR USING THE STATE INFORMATION - A multi-core microprocessor includes first and second processing cores and a bus coupling the first and second processing cores. The bus conveys messages between the first and second processing cores. The cores are configured such that: the first core stops executing user instructions and interrupts the second core via the bus, in response to detecting a predetermined event; the second core stops executing user instructions, in response to being interrupted by the first core; each core outputs its state after it stops executing user instructions; and each core waits to begin fetching and executing user instructions until it receives a notification from the other core via the bus that the other core is ready to begin fetching and executing user instructions. In one embodiment, the predetermined event comprises detecting that the first core has retired a predetermined number of instructions. In one embodiment, microcode waits for the notification. | 2011-07-28 |