30th week of 2013 patent applcation highlights part 14 |
Patent application number | Title | Published |
20130187138 | ORGANIC EL DISPLAY UNIT, METHOD OF MANUFACTURING THE SAME, AND SOLUTION USED IN METHOD - An organic electroluminescence display unit including: a lower electrode for each device; a first hole injection/transport layer provided on the lower electrode for each device; a second organic light emitting layer of the first color provided on the first hole injection/transport layer for the second organic electroluminescence device; a second hole injection/transport layer provided on the entire surfaces of the second organic light emitting layer and the first hole injection/transport layer for the first organic electroluminescence device, and being made of a low molecular material; a blue first organic light emitting layer provided on the entire surface of the second hole injection/transport layer; and an electron injection/transport layer having at least one of electron injection characteristics and electron transport characteristics, and an upper electrode that are provided in sequence on the entire surface of first organic light emitting layer. | 2013-07-25 |
20130187139 | DISPLAY DEVICE - A display device includes, on a substrate, light emitting elements each formed by sequentially stacking a first electrode layer, an organic layer including a light emission layer, and a second electrode layer and arranged in first and second directions which cross each other, a drive circuit including drive elements that drive light emitting elements, and a wiring extending in the first direction, and an insulating layer disposed in a gap region sandwiched by the light emitting elements neighboring in the second direction and having a recess or a projection. The wiring is disposed in an overlap region overlapping with the recess or the projection in the insulating layer in a thickness direction, in the gap region, and the second electrode layers in the light emitting elements neighboring in the second direction are separated from each other by the recess or the projection in the insulating layer. | 2013-07-25 |
20130187140 | CHRYSENE DERIVATIVE MATERIALS - There is provided an electroluminescent composition. The composition includes a material having Formula I | 2013-07-25 |
20130187141 | ORGANIC EL ELEMENT, TRANSLUCENT SUBSTRATE AND METHOD OF MANUFACTURING ORGANIC EL ELEMENT - An organic EL element includes a transparent substrate; a first electrode; an organic light emitting layer formed on the first electrode; and a second electrode formed on the organic light emitting layer, wherein a scattering layer including a base material made of glass and scattering substances dispersed in the base material is provided on the transparent substrate, and a light extraction assistance layer is provided between the scattering layer and the first electrode, the light extraction assistance layer being made of an inorganic material other than glass. | 2013-07-25 |
20130187142 | Display Device - The present invention is intended to suppress power consumption of an EL display. In accordance with the brightness of an image to be displayed in a pixel portion, the contrast of the image is determined whether to be inverted or not, and the number of bits of the digital video signal to be input into the pixel portion is reduced, and the magnitude of a current to flow through the EL element is allowed to be maintained at a constant level even when a temperature of an EL layer changes by providing the EL display with another EL element to be used for monitoring a temperature. | 2013-07-25 |
20130187143 | ORGANIC EL DEVICE AND ANTHRACENE DERIVATIVE - An organic EL device includes: an anode for injecting holes; a phosphorescent-emitting layer; a fluorescent-emitting layer; and a cathode for injecting electrons. The phosphorescent-emitting layer contains a phosphorescent host and a phosphorescent dopant for phosphorescent emission. The fluorescent-emitting layer contains a fluorescent host and a fluorescent dopant for fluorescent emission. The fluorescent host is at least one of an asymmetric anthracene derivative represented by a formula (1) below and a pyrene derivative represented by a formula (2) below. | 2013-07-25 |
20130187144 | RADIATION CURABLE COMPOSITION - The present invention relates to a curable composition, which comprises a) at least one radiation-curable resin, b) at least one specific anti-oxidant and c) at least one photoinitiator salt. The invention further relates to a cured product made from the curable composition. The curable compositions and/or the cured products thereof are particularly suitable as laminating adhesives, sealants, and/or encapsulants for electronic or optoelectronic devices. | 2013-07-25 |
20130187145 | ORGANIC LIGHT-EMITTING COMPOSITION COMPRISING ANTHRANTHENE DERIVATES AND DEVICE AND METHOD USING THE SAME - Composition comprising a fluorescent light-emitting material and a triplet-accepting unit comprising an optionally substituted compound of formula (I): The composition may be used in an organic light-emitting device; the optionally substituted compound of formula (I) may be blended with or attached to the fluorescent light emitting material; and the composition may be deposited by solution deposition. | 2013-07-25 |
20130187146 | ORGANIC LIGHT-EMITTING DEVICE AND METHOD - Composition which may be useful in an organic light emitting diode, the composition having a fluorescent light-emitting polymer with light-emitting repeat units, and a triplet-accepting unit bound to the light-emitting polymer. | 2013-07-25 |
20130187147 | ORGANIC LIGHT-EMITTING DEVICE AND METHOD - Composition for use in an organic light-emitting device, the composition having a fluorescent light-emitting material and a triplet-accepting material subject to the following energetic scheme: 2×T | 2013-07-25 |
20130187148 | MULTI-DEVICE OLED - The invention describes a multi-device OLED ( | 2013-07-25 |
20130187149 | THIN-FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a thin film transistor. The thin film transistor is characterized in having a source interconnect layer and a drain interconnect layer. The source electrode and the drain electrode are respectively disposed above and in contact with the source interconnect layer and the drain interconnect layer. The semiconductor layer is in contact with both the source interconnect layer and the drain interconnect layer, but is not in contact with the source electrode and the drain electrode. | 2013-07-25 |
20130187150 | SEMICONDUCTOR DEVICE - A transistor in which a short-channel effect is not substantially caused and which has switching characteristics even in the case where the channel length is short is provided. Further, a highly integrated semiconductor device including the transistor is provided. A short-channel effect which is caused in a transistor including silicon is not substantially caused in the transistor including an oxide semiconductor film. The channel length of the transistor including the oxide semiconductor film is greater than or equal to 5 nm and less than 60 nm, and the channel width thereof is greater than or equal to 5 nm and less than 200 nm. At this time, the channel width is made 0.5 to 10 times as large as the channel length. | 2013-07-25 |
20130187151 | SEMICONDUCTOR DEVICE - Provided is a transistor which has favorable transistor characteristics and includes an oxide semiconductor, and a highly reliable semiconductor device which includes the transistor including the oxide semiconductor. In the semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode are stacked in this order, a sidewall insulating film is formed along side surfaces and a top surface of the gate electrode, and the oxide semiconductor film is subjected to etching treatment so as to have a cross shape having different lengths in the channel length direction or to have a larger length than a source electrode and a drain electrode in the channel width direction. Further, the source electrode and the drain electrode are formed in contact with the oxide semiconductor film. | 2013-07-25 |
20130187152 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A metal element of a metal film is introduced into the oxide semiconductor film by performing heat treatment in the state where the oxide semiconductor film is in contact with the metal film, so that a low-resistance region having resistance lower than that of a channel formation region is formed. A region of the metal film, which is in contact with the oxide semiconductor film, becomes a metal oxide insulating film by the heat treatment. After that, an unnecessary metal film is removed. Thus, the metal oxide insulating film can be formed over the low-resistance region. | 2013-07-25 |
20130187153 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A highly reliable semiconductor device including a transistor using an oxide semiconductor is provided. In a semiconductor device including a bottom-gate transistor including an oxide semiconductor layer, a first insulating layer is formed in contact with the oxide semiconductor layer, and an oxygen doping treatment is performed thereon, whereby the first insulating layer is made to contain oxygen in excess of the stoichiometric composition. The formation of the second insulating layer over the first insulating layer enables excess oxygen included in the first insulating layer to be supplied efficiently to the oxide semiconductor layer. Accordingly, the highly reliable semiconductor device with stable electric characteristics can be provided. | 2013-07-25 |
20130187154 | OXIDE SEMICONDUCTOR DEVICE - Disclosed is a technique for suppressing fluctuation of device characteristics in thin film transistors using an oxide semiconductor film as a channel layer. In a thin film transistor using an oxide semiconductor film as a channel layer ( | 2013-07-25 |
20130187155 | METHOD OF MANUFACTURING A THIN FILM TRANSISTOR SUBSTRATE AND THIN FILM TRANSISTOR SUBSTRATE MANUFACTURED BY THE SAME - A method of manufacturing a thin film transistor substrate ( | 2013-07-25 |
20130187156 | THREE DIMENSIONAL INTEGRATED CIRCUIT HAVING A RESISTANCE MEASURMENT STRUCTURE AND METHOD OF USE - A three-dimensional integrated circuit (3DIC) including a top chip having at least one active device and an interposer having conductive routing layers and vias. The 3DIC further includes a plurality of conductive connectors configured to electrically connect the top chip and the interposer. The 3DIC further includes a conductive line over at least one of the top chip or the interposer. The conductive line traces a perimeter of top chip or interposer parallel to an outer edge of the top chip or interposer. The conductive line is configured to electrically connect the conductive connectors. The 3DIC further includes at least one testing element over at least one of the top chip or the interposer. The testing element is configured to electrically connect to the plurality of conductive connectors. | 2013-07-25 |
20130187157 | METHODS OF HEATING INTEGRATED CIRCUITS AT LOW TEMPERATURES AND DEVICES USING THE METHODS - A method of heating an integrated circuit (IC) may include sensing a temperature of the IC, comparing the sensed temperature with a reference temperature and generating a comparison signal; and enabling a heating element that heats the IC based on the comparison signal. An IC may include a thermal sensor configured to sense a temperature of the IC, compare the sensed temperature with a reference temperature, and generate a comparison signal. The IC may include a heating element configured to be enabled to heat the IC based on the comparison signal. An IC may include a heating element and a thermal sensor. The sensor may be configured to sense a temperature of the IC and generate a control signal based on the sensed temperature and a reference temperature. The element may be enabled to heat the IC or disabled from heating the IC based on the control signal. | 2013-07-25 |
20130187158 | SEMICONDUCTOR DEVICE - The invention prevents a short circuit between bonding wires, between device pads, or between the bonding wire and the device pad due to a cut residue portion of a scribe TEG pad coming off from an end portion of a semiconductor chip. A scribe TEG pad on a semiconductor wafer is formed of a plurality of rectangular pads each extending on a scribe line toward a device forming region. The semiconductor wafer is divided into semiconductor chips by dicing. At this time, the length of each of cut residue portions of the scribe TEG pad remaining on an end portion of the semiconductor chip is shorter than an interval between the end portions of openings of a passivation film on adjacent device pads. | 2013-07-25 |
20130187159 | INTEGRATED CIRCUIT AND METHOD OF FORMING AN INTEGRATED CIRCUIT - An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench. | 2013-07-25 |
20130187160 | INTEGRATED FIELD EFFECT TRANSISTORS WITH HIGH VOLTAGE DRAIN SENSING - An integrated circuit includes a junction field effect transistor (JFET) and a power metal oxide semiconductor field effect transistor (MOSFET) on a same substrate. The integrated circuit includes a drain sense terminal for sensing the drain of the power MOSFET through the JFET. The JFET protects a controller or other electrical circuit coupled to the drain sense terminal from high voltage that may be present on the drain of the power MOSFET. The JFET and the power MOSFET share a same drift region, which includes an epitaxial layer formed on the substrate. The integrated circuit may be packaged in a four terminal small outline integrated circuit (SOIC) package. The integrated circuit may be employed in a variety of applications including as an ideal diode. | 2013-07-25 |
20130187161 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A photolithography process for forming an island-shaped semiconductor layer is omitted, and a transistor is formed by at least two photolithography processes: a photolithography process for forming a gate electrode (including a wiring or the like formed from the same layer as the gate electrode) and a photolithography process for forming a source electrode and a drain electrode (including a wiring or the like formed from the same layer as the source electrode and the drain electrode). By using electron beam exposure, a transistor in which a distance between the source electrode and the drain electrode (channel length) is short can be formed. For example, a transistor whose channel length is less than 50 nm can be obtained. | 2013-07-25 |
20130187162 | THIN FILM TRANSISTOR SUBSTRATE AND PROCESS FOR PRODUCTION THEREOF - A TFT substrate | 2013-07-25 |
20130187163 | ORGANIC LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - An organic light emitting diode (OLED) display with an improved light efficiency and a method of manufacturing the OLED display are disclosed. The OLED display includes a substrate, an insulation layer on the substrate and having concave portions, first electrodes on the insulation layer, pixel defining layers (PDLs) on the insulation layer and configured to define the first electrodes into pixels, organic light emitting layers on the first electrodes as defined by the pixels, and a second electrode on the organic light emitting layers. Each of the concave portions includes a bottom surface and inclined parts. Each of the first electrodes is on the bottom surface and the inclined parts of one of the concave portions. Embossings are on a part of a surface of the PDLs. | 2013-07-25 |
20130187164 | THIN-FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, DISPLAY UNIT, AND ELECTRONIC APPARATUS - There are provided a thin-film transistor suppressing influence of light and having stable characteristics, and a method of manufacturing the thin-film transistor, as well as a display unit and an electronic apparatus. The thin-film transistor includes: a gate electrode; an oxide semiconductor film having a channel region that faces the gate electrode; and a protective film covering at least the channel region and containing an aluminum lower oxide (Al | 2013-07-25 |
20130187165 | Semiconductor Device, and Manufacturing Method Thereof - In a display device such as a liquid crystal display device, a large-sized display screen is realized under low power consumption. A surface of a source wiring line of a pixel portion employed in an active matrix type liquid crystal display device is processed by way of a plating process operation so as to lower a resistance value of this source wiring line. The source wiring line of the pixel portion is manufactured at a step different from a step for manufacturing a source wiring line of a drive circuit portion. Further, electrodes of a terminal portion are processed by a plating process operation so as to reduce a resistance value thereof. | 2013-07-25 |
20130187166 | LIGHT-EMITTING DEVICE - According to present invention, system on panel without complicating the process of TFT can be realized, and a light-emitting device that can be formed by lower cost than that of the conventional light-emitting device can be provided. A light-emitting device is provided in which a pixel portion is provided with a pixel including a light-emitting element and a TFT for controlling supply of current to the light-emitting element; a TFT included in a drive circuit and a TFT for controlling supply of current to the light-emitting element include a gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor film, which overlaps with the gate electrode via the gate insulating film, a pair of second semiconductor films formed over the first semiconductor film; the pair of second semiconductor films are doped with an impurity to have one conductivity type; and the first semiconductor film is formed by semiamorphous semiconductor. | 2013-07-25 |
20130187167 | THIN FILM TRANSISTOR ARRAY PANEL AND ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING THE SAME, METHOD FOR CUTTING WIRE IN THIN FILM TRANSISTOR ARRAY PANEL - A thin film transistor display panel includes a plurality of pixels arranged in a matrix format, the plurality of pixels include thin film transistors, respectively, a plurality of first signal lines connected with the pixels, a plurality of second signal lines connected with the pixels, the plurality of second signal lines cross the first signal lines in an insulated manner, at least one of the second signal lines includes a cut portion, and an organic repairing member overlaps the cut portion | 2013-07-25 |
20130187168 | GaN-CONTAINING SEMICONDUCTOR LIGHT EMITTING DEVICE - A GaN-containing semiconductor light emitting device includes: an n-type semiconductor layer formed of GaN-containing semiconductor, an active layer formed on the n-type semiconductor layer, formed of GaN-containing semiconductor, and having a multiple quantum well structure including a plurality of barrier layers and well layers stacked alternately, and a p-type semiconductor layer formed on the active layer and formed of GaN-containing semiconductor, wherein: the barrier layers comprise: a first barrier layer disposed nearest to the n-type semiconductor layer among the barrier layers and formed of a GaN/AlGaN layer, and second barrier layers disposed nearer to the p-type semiconductor layer than the first barrier layer and including an InGaN/GaN layer which has a layered structure of a InGaN sublayer and a GaN sublayer; and the well layers are each formed of an InGaN layer having a narrower band gap than that in the InGaN sublayer. | 2013-07-25 |
20130187169 | SYSTEMS AND METHODS FOR DEPOSITING MATERIALS ON EITHER SIDE OF A FREESTANDING FILM USING SELECTIVE THERMALLY-ASSISTED CHEMICAL VAPOR DEPOSITION (STA-CVD), AND STRUCTURES FORMED USING SAME - Embodiments of the present invention provide systems and methods for depositing materials on either side of a freestanding film using selectively thermally-assisted chemical vapor deposition (STA-CVD), and structures formed using same. A freestanding film, which is suspended over a cavity defined in a substrate, is exposed to a fluidic CVD precursor that reacts to form a solid material when exposed to heat. The freestanding film is then selectively heated in the presence of the precursor. The CVD precursor preferentially deposits on the surface(s) of the freestanding film. | 2013-07-25 |
20130187170 | METHOD FOR PRODUCING ALUMINUM NITRIDE CRYSTALS - Provided is a method for producing inexpensive and high-quality aluminum nitride crystals. Gas containing N atoms is introduced into a melt of a Ga—Al alloy, whereby aluminum nitride crystals are made to epitaxially grow on a seed crystal substrate in the melt of the Ga—Al alloy. A growth temperature of aluminum nitride crystals is set at not less than 1000 degrees C. and not more than 1500 degrees C., thereby allowing GaN to be decomposed into Ga metal and nitrogen gas. | 2013-07-25 |
20130187171 | METHOD TO FORM SILICIDE CONTACT IN TRENCHES - A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region. | 2013-07-25 |
20130187172 | NITRIDE SEMICONDUCTOR EPITAXIAL WAFER AND FIELD EFFECT NITRIDE TRANSISTOR - A nitride semiconductor epitaxial wafer includes a substrate, a GaN layer provided over the substrate, and an AlGaN layer provided over the GaN layer. The GaN layer has a wurtzite crystal structure, and a ratio c/a of a lattice constant c in a c-axis orientation of the GaN layer to a lattice constant a in an a-axis orientation of the GaN layer is not more than 1.6266. | 2013-07-25 |
20130187173 | CONDUCTIVITY MODULATION IN A SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR - In one general aspect, a silicon carbide bipolar junction transistor (BJT) can include a collector region, a base region on the collector region, and an emitter region on the base region. The silicon carbide BJT can include a base contact electrically contacting the base region where the base region having an active part interfacing the emitter region. The silicon carbide BJT can also include an intermediate region of semiconductor material having at least a part extending from the active part of the base region to the base contact where the intermediate region having a doping level higher than a doping level of the active part of the base region. | 2013-07-25 |
20130187174 | LIGHT-EMITTING DIES INCORPORATING WAVELENGTH-CONVERSION MATERIALS AND RELATED METHODS - In accordance with certain embodiments, semiconductor dies are embedded within polymeric binder to form, e.g., freestanding white light-emitting dies and/or composite wafers containing multiple light-emitting dies embedded in a single volume of binder. | 2013-07-25 |
20130187175 | MULTI-LAYER ARRAY TYPE LED DEVICE - A multi-layer array type LED device is provided, which includes a substrate, an encapsulation body, two lead frames, a plurality of LED dices, and a set of optical lens. The outer circumferential edge and the upper and lower periphery of the substrate are completely encapsulated by the encapsulation body so that the multi-layer array type LED device can be tightly packaged. In the present invention, a fluorescent layer is disposed between an optical grease layer and a silica gel protection layer, and thereby the fluorescent layer is protected, and is capable of preventing moisture from permeating therein. On the other hand, in the present invention, the reflection coefficient of the optical grease layer is at least larger than a certain value so that the probability of the light emitted out of the optical chamber can be increased. | 2013-07-25 |
20130187176 | SILICONE RESIN - A silicone resin is provided. The silicone resin may be effectively used to encapsulate a semiconductor element, for example, a light-emitting element of a light-emitting diode. | 2013-07-25 |
20130187177 | DISPLAY PANEL MANUFACTURING METHOD AND DISPLAY PANEL - A method of manufacturing a display panel includes a sub-step of forming a photosensitive material layer for formation of a second layer on a first layer, a sub-step of disposing, over the photosensitive material layer, a photomask having a different degree of transparency in a first region and a second region thereof, the first region overlapping the photosensitive material layer, in plan view, at a location for formation of a second aperture, and the second region being a remainder of the photomask other than the first region, and a sub-step of exposing the photosensitive material layer via the photomask. In plan view, the area of the first region in the photomask is larger than the area of a first aperture in the first layer. | 2013-07-25 |
20130187178 | LIGHT-EMITTING DIES INCORPORATING WAVELENGTH-CONVERSION MATERIALS AND RELATED METHODS - In accordance with certain embodiments, semiconductor dies are embedded within polymeric binder to form, e.g., freestanding white light-emitting dies and/or composite wafers containing multiple light-emitting dies embedded in a single volume of binder. | 2013-07-25 |
20130187179 | LIGHT EMITTING DIODE WITH IMPROVED DIRECTIONALITY - A light emitting diode (LED) is provided that includes a host substrate formed from a first material, an n-type layer formed over the host substrate, an active region formed over the n-type layer, and a p-type layer formed over the active region. A layer is formed adjacent to the host substrate and includes a second material, the second material being different from the first material or having a refractive index different from a refractive index of the first material. Further, the second material is formed with a tapered outwards sidewall profile. | 2013-07-25 |
20130187180 | LIGHT EMITTING DIODE FOR PLANT GROWTH - The present invention is a lighting device for plant growth, it is composed of a blue LED chip as the light source with different colors of phosphor powders. The wave length of blue chip falls in the range of 440-460 nm which stimulates stoma opening to absorb carbon dioxide. By formulating the right recipe of phosphors, the emitted light will have the spectra very close to that of light necessary for plant photosynthesis. It has the combined functions of good plant photosynthesis, stoma opening stimulation and some photomorphogenesis in one single device. It is a very prominent invention of artificial lights for plant growth ever seen. | 2013-07-25 |
20130187181 | SEMICONDUCTOR LIGHT-RECEIVING DEVICE - A semiconductor light-receiving device includes two lenses; and a concave region, a height of the sidewall being higher than a top of the lenses, a distance between a position H and a lower edge of the sidewall vertical to a line segment C | 2013-07-25 |
20130187182 | WIRING SUBSTRATE, LIGHT EMITTING DEVICE, AND MANUFACTURING METHOD OF WIRING SUBSTRATE - There is provided a wiring substrate. The wiring substrate includes: a heat sink; an insulating member on the heat sink; a wiring pattern embedded in the insulating member and including a first surface and a second surface opposite to the first surface, the second surface contacting the insulating member; and a metal layer on the first surface of the wiring pattern, wherein an exposed surface of the metal layer is flush with an exposed surface of the insulating member. | 2013-07-25 |
20130187183 | LIGHT-EMITTING DIODE CHIP - A light-emitting diode chip is specified, comprising
| 2013-07-25 |
20130187184 | WAVELENGTH CONVERTED LIGHT EMITTING DEVICE - Embodiments of the invention include a semiconductor light emitting device ( | 2013-07-25 |
20130187185 | Electronic Article and Method of Forming - An electronic article includes an optoelectronic semiconductor having a refractive index of 3.7±2 and a dielectric layer disposed on the optoelectronic semiconductor. The dielectric layer has a thickness of at least 50 μm and a refractive index of 1.4±0.1. The electronic article includes a gradient refractive index coating (GRIC) that is disposed on the optoelectronic semiconductor and that has a thickness of from 50 to 400 nm. The refractive index of the GRIC varies along the thickness from 2.7±0.7 to 1.5±0.1. The GRIC also includes a gradient of a carbide and an oxycarbide along the thickness. The carbide and the oxycarbide each independently include at least one silicon or germanium atom. The article is formed by continuously depositing the GRIC using plasma-enhanced chemical vapor deposition in a dual frequency configuration and subsequently disposing the dielectric layer on the GRIC. | 2013-07-25 |
20130187186 | Optoelectronic Component - An optoelectronic component with short circuit protection is provided, comprising a first electrode layer ( | 2013-07-25 |
20130187187 | Light-Emitting Device, Display Device, and Semiconductor Device - A light-emitting device which includes a semiconductor layer; a first insulating layer over the semiconductor layer; a gate electrode and a first conductive layer over the first insulating layer; a second insulating layer over the gate electrode and the first conductive layer; source and drain electrodes and a second conductive layer over the second insulating layer; a third insulating layer over the source and drain electrodes and the second conductive layer; a first electrode and a third conductive layer over the third insulating layer; a planarization film covering an end portion of the first electrode; an electroluminescent layer over the first electrode; and a second electrode over the electroluminescent layer and the planarization film is provided. The second electrode is electrically connected to the third conductive layer through an opening portion provided in the planarization film. The opening portion overlaps with the first, second, and third conductive layers. | 2013-07-25 |
20130187188 | MOLDED PACKAGE AND LIGHT EMITTING DEVICE - A molded package includes a molded resin and a lead. The molded resin has a recess portion provided on an upper surface of the molded resin to accommodate a light emitting component. The lead is partially exposed from a bottom surface of the recess portion of the molded resin to be electrically connected to the light emitting component and extends below a side wall of the recess portion. The lead has a groove formed on a surface of the lead at least partially along the side wall. The groove has an inside upper edge and an outside upper edge and is filled with the molded resin so that the inside upper edge is exposed from the bottom surface of the recess portion and the outside upper edge is embedded within the molded resin. | 2013-07-25 |
20130187189 | HEAT SINK BIMETALLIC PILLAR BUMP AND THE LED HAVING THE SAME - The invention relates to a heat sink bimetallic pillar bump that is mainly disposed inside of a LED. The heat sink bimetallic pillar bump comprises a heat absorbing section composed of a first metal and a heat dissipating section firmly connected with the heat absorbing section. The heat dissipating section is composed of a second metal. The first metal has a thermal conductivity greater than that of the second metal. The LED chip is disposed on the heat absorbing section. The heat absorbing section with high thermal conductivity quickly transfers the heat generated by the LED chip to the heat dissipating section. This makes the heat from the LED chip to be dissipated quickly, which therefore achieves purposes of improving the heat dissipation efficiency of the LED and other kinds of IC chips and prolonging the lifespan of the LED and other kinds of IC chips. | 2013-07-25 |
20130187190 | WIRING SUBSTRATE, LIGHT EMITTING DEVICE, AND MANUFACTURING METHOD OF WIRING SUBSTRATE - There is provided a wiring substrate. The wiring substrate includes: a heat sink; a first insulating layer on the heat sink; a wiring pattern on the first insulating layer, wherein the wiring pattern is configured to mount a light emitting element thereon; and a second insulating layer on the first insulating layer such that the wiring pattern is exposed from the second insulating layer. | 2013-07-25 |
20130187191 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MULTIPLE LEAD FRAME FOR SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device that is excellent in radiating heat and that can be molded into a sealing shape having intended optical characteristics by die molding is provided. The semiconductor light emitting device includes: a lead frame including a plate-like semiconductor light emitting element mounting portion having an LED chip mounted on a main surface, and a plate-like metal wire connecting portion extending over a same plane as the semiconductor light emitting element mounting portion; a metal wire electrically connecting the LED chip and the metal wire connecting portion; a thermosetting resin molded by die molding or dam-sheet molding so as to completely cover the LED chip and the metal wire; and a resin portion provided to surround the lead frame and having the thickness not greater than the thickness of the lead frame. | 2013-07-25 |
20130187192 | Optoelectronic Component and Method for the Production Thereof - An optoelectronic component has a semiconductor chip and a carrier, which is bonded to the semiconductor chip by means of a bonding layer of a metal or a metal alloy. The semiconductor chip includes electrical connection regions facing the carrier and the carrier includes electrical back contacts on its back remote from the semiconductor chip. The back contacts are connected electrically conductively to the first electrical or second connection region respectively, in each case by at least one via extending through the carrier. The first and/or second electrical back contact is connected to the first or second electrical connection region respectively by at least one further via extending through the carrier. | 2013-07-25 |
20130187193 | SHUNTING LAYER ARRANGEMENT FOR LEDS - A shunting pattern on a surface of an LED die comprises an array of metal dots having widths that are on the order of 2Lt-5Lt (where Lt is transfer length) so as not to block a significant amount of light, yet have low contact resistance to the semiconductor current spreading layer. Contact resistance is not significantly reduced with widths greater than 2Lt. Each dot represents a current injection area. For a minimum 2Lt width and 50 square dots per mm2, the top surface area of an LED die will have about 1% of its surface covered by the dots. To cause the current to be evenly distributed over the top surface of the LED, the dots are connected with a grid of very thin metal connectors, having widths much less than 2Lt. In one embodiment, a wire bond electrode is formed near the middle of the top surface of the LED to create a more uniform current distribution. | 2013-07-25 |
20130187194 | PEC BIASING TECHNIQUE FOR LEDS - Each LED in an array of LEDs mounted on a submount wafer has at least a first semiconductor layer exposed and connected to a first electrode of each LED. The submount wafer has a first metal portion bonded to the first electrode of each LED for providing an energization current to each LED. The submount wafer also has a second metal portion running along and proximate to the first metal portion but not electrically connected to the first metal portion. The second metal portion may be interdigitated with the first metal portion. The second metal portion is connected to a bias voltage. When the wafer is immersed in an electrically conductive solution for electrochemical (EC) etching of the exposed first semiconductor layer, the solution electrically connects the second metal portion to the first metal portion for biasing the first semiconductor layer during the EC etching. | 2013-07-25 |
20130187195 | Power Transistor - A cell field has an edge and a center, an individual device cells are connected in parallel. A first type of device cells has a body region with a first size and a source region with a second size implemented in the body region, and a second type of device cells has a body region of the first size and in which a source region is omitted or the source region is smaller than the second size. The cell field includes non-overlapping cell regions, each including the same plurality of device cells. At least one sequence of cell regions is arranged between the edge and center of the cell field in which the frequency of device cells of the second type monotonically increases from cell region to cell region in the direction of the center, and one cell region of the sequence of cell regions includes or adjoins the center. | 2013-07-25 |
20130187196 | Integrated Circuit Including Field Effect Transistor Structures with Gate and Field Electrodes and Methods for Manufacturing and Operating an Integrated Circuit - An integrated circuit includes a first and a second field effect transistor structure. The first field effect transistor structure includes a first gate electrode structure and a first field electrode structure. The second field effect transistor structure includes a second gate electrode structure and a second field electrode structure. The first and the second gate electrode structures are electrically separated from each other. The first and the second field electrode structures are separated from each other. | 2013-07-25 |
20130187197 | HIGH ELECTRON MOBILITY TRANSISTOR AND MANUFACTURING METHOD THEREOF - Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film. | 2013-07-25 |
20130187198 | HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE - A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer. | 2013-07-25 |
20130187199 | SOLID STATE IMAGE PICKUP DEVICE AND MANUFACTURING METHOD THEREFOR - A MOS-type solid-state image pickup device includes a photoelectric conversion unit having a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type forming a pn-junction with the first semiconductor region, and a third semiconductor region of the first conductive type disposed on the second semiconductor region. In addition, a transfer gate electrode is disposed on an insulation film and transfers a carrier from the second semiconductor region to a fourth semiconductor region of the second conductivity type, an amplifying MOS transistor having a gate electrode is connected to the fourth semiconductor region, and a fifth semiconductor region of the second conductivity type is continuously disposed to the second semiconductor region, disposed under the gate electrode. An entire surface of the third semiconductor region is covered with the insulation film, and a side portion of the third semiconductor region that is laterally opposite to the transfer gate is in contact with the first semiconductor region. | 2013-07-25 |
20130187200 | TRANSISTOR-BASED PARTICLE DETECTION SYSTEMS AND METHODS - Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow. | 2013-07-25 |
20130187201 | Sensor Device and Method - A sensor device includes a semiconductor chip. The semiconductor chip has a sensing region sensitive to mechanical loading. A pillar is mechanically coupled to the sensing region. | 2013-07-25 |
20130187202 | SPACER PROFILE ENGINEERING USING FILMS WITH CONTINUOUSLY INCREASED ETCH RATE FROM INNER TO OUTER SURFACE - Interlayer dielectric gap fill processes are enhanced by forming gate spacers with a tapered profile. Embodiments include forming a gate electrode on a substrate, depositing a spacer material over the gate electrode and substrate, the spacer layer having a first surface nearest the gate electrode and substrate, a second surface furthest from the gate electrode and substrate, and a continuously increasing etch rate from the first surface to the second surface, and etching the spacer layer to form a spacer on each side of the gate electrode. Embodiments further include forming the spacer layer by depositing a spacer material and continuously decreasing the density of the spacer material during deposition or depositing a carbon-containing spacer material and causing a gradient of carbon content in the spacer layer. | 2013-07-25 |
20130187203 | FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE - Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape. | 2013-07-25 |
20130187204 | HIGH FREQUENCY SEMICONDUCTOR SWITCH - There is provided a high frequency semiconductor switch for improving insertion loss characteristics and harmonic characteristics by providing good voltage distribution in a gate wiring. The field effect transistor includes a source wiring electrically connected to a source region formed on a substrate and extending unidirectionally; a drain wiring electrically connected to a drain region formed on the substrate and extending in parallel with the source wiring; a gate having a parallel portion extending between the source wiring and the drain wiring in approximately parallel with the source wiring and the drain wiring; a gate wiring applying voltage to the gate; and a gate via electrically connecting the gate to the gate wiring, the parallel portion including two ends and formed with a path applying voltage to each of the two ends from the gate via. | 2013-07-25 |
20130187205 | EPITAXIAL REPLACEMENT OF A RAISED SOURCE/DRAIN - Disclosed is a semiconductor article which includes a semiconductor substrate; a gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to the gate structure, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. Also disclosed is a method of making the semiconductor article. | 2013-07-25 |
20130187206 | FinFETs and Methods for Forming the Same - A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions. | 2013-07-25 |
20130187207 | REPLACEMENT SOURCE/DRAIN FINFET FABRICATION - A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched to expose a first region of the fin. A portion of the first region is then doped with a dopant. | 2013-07-25 |
20130187208 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction. | 2013-07-25 |
20130187209 | SEMICONDUCTOR DEVICES HAVING ENCAPSULATED STRESSOR REGIONS AND RELATED FABRICATION METHODS - Apparatus and related fabrication methods are provided for semiconductor device structures having silicon-encapsulated stressor regions. One semiconductor device includes a semiconductor substrate, a gate structure overlying the semiconductor substrate, stressor regions formed in the semiconductor substrate proximate the gate structure, and a silicon material overlying the stressor regions, the silicon material encapsulating the stressor regions. | 2013-07-25 |
20130187210 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING THE SAME - In a photoelectric conversion apparatus including charge storing portions in its imaging region, isolation regions for the charge storing portions include first isolation portion each having a PN junction, and second isolation portions each having an insulator. A second isolation portion is arranged between a charge storing portion and at least a part of a plurality of transistors. | 2013-07-25 |
20130187211 | Multi-Layer Integrated Circuit Package - A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop. | 2013-07-25 |
20130187212 | HYBRID ELECTRICAL CONTACTS - Devices having hybrid-vertical contacts. In certain embodiments, a substrate includes a lower patterned layer that has a target conductor. A hybrid-vertical contact may be disposed directly on the target conductor. The hybrid vertical contact may include a lower-vertical contact directly on the target conductor and an upper-vertical contact directly on the lower-vertical contact. The upper-vertical contact may have an upper width that is greater than a lower width of the lower-vertical contact. | 2013-07-25 |
20130187213 | METHOD OF MAKING A NON-VOLATILE DOUBLE GATE MEMORY CELL - A method of making a non-volatile double-gate memory cell. The gate of the control transistor is formed with a relief of a semiconductor material on a substrate. The control gate of the memory transistor is formed with a sidewall of the relief of a semiconductor material configured to store electrical charge. A first layer is deposited so as to cover the stack of layers. The first layer is etched so as to form a first pattern juxtaposed on the relief. A second layer is formed on the first pattern. The second layer is etched so as to form on the first pattern a second pattern having a substantially plane upper face. | 2013-07-25 |
20130187214 | MULTI-SEMICONDUCTOR MATERIAL VERTICAL MEMORY STRINGS, STRINGS OF MEMORY CELLS HAVING INDIVIDUALLY BIASABLE CHANNEL REGIONS, MEORY ARRAYS INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSSING AND FORMING THE SAME - Multi-semiconductor vertical memory strings, strings of memory cells having individually biasable channel regions, arrays incorporating such strings and methods for forming and accessing such strings are provided. For example non-volatile memory devices are disclosed that utilize NAND strings of serially-connected non-volatile memory cells. One such string can include two or more serially connected non-volatile memory cells each having a channel region. Each memory cell of the two or more serially connected non-volatile memory cells shares a common control gate and each memory cell of the two or more serially connected non-volatile memory cells is configured to receive an individual bias to its channel region. | 2013-07-25 |
20130187215 | METHODS OF FORMING NANOSCALE FLOATING GATE - A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer. | 2013-07-25 |
20130187216 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - Provided is a P-channel non-volatile semiconductor memory device with improved write characteristics. In the P-channel non-volatile semiconductor memory device, a resistive element is formed and connected to a control gate. A delay effect of the resistive element connected to the control gate is utilized to increase a potential of the control gate so as to cancel out a decrease in floating gate potential caused by hot electrons injected by writing. This can prevent the weakening of an electric field between a pinch-off point and a drain, which leads to a decrease in amount of generated DAHEs in writing. Thus, write characteristics can be improved. | 2013-07-25 |
20130187217 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device is provided in which memory strings, which are formed by providing a plurality of transistors having gate electrode films on sides of columnar semiconductor films in a height direction of the columnar semiconductor films via charge storage layers, are substantially perpendicularly arranged in a matrix shape on a substrate. A coupling section made of a semiconductor material that connects lower portions of the columnar semiconductor films forming a pair of the memory strings adjacent to each other in a predetermined direction is provided. Each of the columnar semiconductor films is formed of a generally single-crystal-like germanium film or silicon germanium film. | 2013-07-25 |
20130187218 | ESD PROTECTION CIRCUIT - A device which includes a substrate defined with a device region having an ESD protection circuit is disclosed. The ESD protection circuit has a transistor. The transistor includes a gate having first and second sides. A first diffusion region is disposed adjacent to the first side of the gate and a second diffusion region is disposed in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. A drift isolation region is disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. A drain well having dopants of the first polarity type is disposed under the second diffusion region and within the first device well. | 2013-07-25 |
20130187219 | High-Voltage Vertical Transistor With a Varied Width Silicon Pillar - In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. | 2013-07-25 |
20130187220 | VERTICAL MEMORY DEVICES, APPARATUSES INCLUDING VERTICAL MEMORY DEVICES, AND METHODS FOR FORMING SUCH VERTICAL MEMORY DEVICES AND APPARATUSES - Methods of forming vertical memory devices include forming first trenches, at least partially filling the first trenches with a polysilicon material, and forming second trenches generally perpendicular to the first trenches. The second trenches may be formed by removing one of silicon and oxide with a first material removal act and by removing the other of silicon and oxide in a different second material removal act. Methods of forming an apparatus include forming isolation trenches, at least partially filling the isolation trenches with a polysilicon material, and forming word line trenches generally perpendicular to the isolation trenches, the word line trenches having a depth in a word line end region about equal to or greater than a depth thereof in an array region. Word lines may be formed in the word line trenches. Semiconductor devices, vertical memory devices, and apparatuses are formed by such methods. | 2013-07-25 |
20130187221 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film. | 2013-07-25 |
20130187222 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a target etch layer, forming a first mask pattern on the target etch layer, wherein the first mask pattern includes line patterns extended in parallel in a first direction, forming a second mask pattern configured to include openings at positions where the openings overlap with spaces between the line patterns, before or after forming the first mask pattern, wherein each of the openings has a hole form and a first interval between the adjacent openings in the first direction is shorter than a second interval between the adjacent openings in a second direction that crosses the first direction, and forming holes by etching the target etch layer using the first mask pattern and the second mask pattern as a barrier. | 2013-07-25 |
20130187223 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate trench | 2013-07-25 |
20130187224 | INTEGRATION OF TRENCH MOS WITH LOW VOLTAGE INTEGRATED CIRCUITS - A high voltage trench MOS and its integration with low voltage integrated circuits is provided. Embodiments include forming, in a substrate, a first trench with a first oxide layer on side surfaces; a narrower second trench, below the first trench with a second oxide layer on side and bottom surfaces, and spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on side and top surfaces of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region. | 2013-07-25 |
20130187225 | HIGH VOLTAGE MOSFET DEVICE - A HV MOSFET device includes a substrate, a deep well region, a source/body region, a drain region, a gate structure, and a first doped region. The deep well region includes a boundary site and a middle site. The source/body region is formed in the deep well region and defines a channel region. The first doped region is formed in the deep well region and disposed under the gate structure, and having the first conductivity type. There is a first ratio between a dopant dose of the first doped region and a dopant dose of the boundary site of the deep well region. There is a second ratio between a dopant dose of the first doped region and a dopant dose of the middle site of the deep well region. A percentage difference between the first ratio and the second ratio is smaller than or equal to 5%. | 2013-07-25 |
20130187226 | LATERAL DOUBLE DIFFUSED MOS TRANSISTORS AND METHODS OF FABRICATING THE SAME - A lateral double diffused MOS transistor including substrate of a first conductivity type, drift region of a second conductivity type and body region of the first conductivity type disposed in the substrate, source region of the second conductivity type disposed in the body region, drain region of the second conductivity type disposed in the drift region, isolation layer disposed in the drift region to surround sidewalls of the drain region, gate insulation layer and gate electrode sequentially stacked generally on the body region, first field plate extending from the gate electrode to overlap the drift region and to overlap a portion of the isolation layer, second field plate disposed above the isolation layer spaced apart from the first field plate, and coupling gate disposed above the isolation layer generally between the drain region and the second field plate, wherein the coupling gate is electrically connected to the second field plate. | 2013-07-25 |
20130187227 | FLATBAND SHIFT FOR IMPROVED TRANSISTOR PERFORMANCE - An integrated circuit includes MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit includes MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. | 2013-07-25 |
20130187228 | FinFET Semiconductor Devices with Improved Source/Drain Resistance and Methods of Making Same - Disclosed herein are various FinFET semiconductor devices with improved source/drain resistance and various methods of making such devices. One illustrative device disclosed herein includes a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches at least partially define a fin for the device, an etch stop layer positioned above a bottom surface of each of the trenches, and a metal silicide region formed on all exposed surfaces of the fin that are positioned above an upper surface of the etch stop layer. | 2013-07-25 |
20130187229 | SEMICONDUCTOR DEVICE WITH A LOW-K SPACER AND METHOD OF FORMING THE SAME - A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions. | 2013-07-25 |
20130187230 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. | 2013-07-25 |
20130187231 | ESD PROTECTION CIRCUIT - A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors. | 2013-07-25 |
20130187232 | SEMICONDUCTOR DEVICE - In the semiconductor device including an ESD protection N-type MOS transistor having a sufficient ESD protective function, a drain region of the ESD protection N-type MOS transistor is electrically connected to a drain contact region via a drain extended region. The drain extended region is provided on a side surface and a lower surface of an ESD protection trench isolation region, and is formed of an impurity diffusion region of the same conductivity type as that of the drain region. The drain contact region is formed of an impurity diffusion region of the same conductivity type as that of the drain region. | 2013-07-25 |
20130187233 | SEMICONDUCTOR MEMORY DEVICES - A semiconductor memory device may include: a well impurity layer including a cell array region and a well drive region adjacent to the cell array region, the well impurity layer having a first conductivity type; at least one word line on the well impurity layer; at least one bit line crossing the at least one word line on the well impurity layer of the cell array region, the at least one bit line connected to a drain region in the well impurity layer, and the drain region having a second conductivity type; and a well drive line crossing the at least one word line on the well impurity layer of the well drive region, the well drive line connected to the well impurity layer of the first conductivity type. | 2013-07-25 |
20130187234 | STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES - Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed. | 2013-07-25 |
20130187235 | COMPOSITE DUMMY GATE WITH CONFORMAL POLYSILICON LAYER FOR FINFET DEVICE - The present disclosure involves a FinFET. The FinFET includes a fin structure formed over a substrate. A gate dielectric layer is least partially wrapped around a segment of the fin structure. The gate dielectric layer contains a high-k gate dielectric material. The FinFET includes a polysilicon layer conformally formed on the gate dielectric layer. The FinFET includes a metal gate electrode layer formed over the polysilicon layer. The present disclosure provides a method of fabricating a FinFET. The method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure. The method includes forming a polysilicon layer over the gate dielectric layer, wherein the polysilicon layer is formed in a conformal manner. The method includes forming a dummy gate layer over the polysilicon layer. | 2013-07-25 |
20130187236 | Methods of Forming Replacement Gate Structures for Semiconductor Devices - Disclosed herein are methods of forming replacement gate structures. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define a gate cavity, forming a layer of insulating material in the gate cavity and forming a layer of metal within the gate cavity above the layer of insulating material. The method further includes forming a sacrificial material in the gate cavity so as to cover a portion of the layer of metal and thereby define an exposed portion of the layer of metal, performing an etching process on the exposed portion of the layer of metal to thereby remove the exposed portion of the layer of metal from within the gate cavity, and, after performing the etching process, removing the sacrificial material and forming a conductive material above the remaining portion of the layer of metal. | 2013-07-25 |
20130187237 | STRUCTURE AND METHOD FOR TRANSISTOR WITH LINE END EXTENSION - The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side. | 2013-07-25 |