30th week of 2014 patent applcation highlights part 16 |
Patent application number | Title | Published |
20140203381 | PROCESS AND APPARATUS FOR TRANSFORMING NITRIDATION/OXIDATION AT EDGES, AND PROTECTING EDGES OF MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) LAYERS - Material surrounding a magnetic tunnel junction (MTJ) device region of a multi-layer starting structure is etched, forming an MTJ device pillar having an MTJ layer with a chemically damaged peripheral edge region. De-nitridation or de-oxidation, or both, restore the chemically damaged peripheral region to form an edge-restored MTJ layer. An MTJ edge restoration assist layer is formed on the edge-restored MTJ layer. An MTJ-edge-protect layer is formed on the insulating MTJ-edge-restoration-assist layer. | 2014-07-24 |
20140203382 | BORON CARBIDE FILMS EXHIBITS EXTRAORDINARY MAGNETOCONDUCTANCE AND DEVICES BASED THEREON - Boron carbide polymers prepared from orthocarborane icosahedra cross-linked with a moiety A wherein A is selected from the group consisting of benzene, pyridine. 1, 4-diaminobenzene and mixtures thereof give positive magnetoresistance effects of 30%-80% at room temperature. The novel polymers may be doped with transitional metals to improve electronic and spin performance. These polymers may be deposited by any of a variety of techniques, and may be used in a wide variety of devices including magnetic tunnel junctions, spin-memristors and non-local spin valves. | 2014-07-24 |
20140203383 | PERPENDICULAR MAGNETORESISTIVE MEMORY ELEMENT - A perpendicular magnetoresistive memory element comprises a three-terminal structure having a thick multilayered recording layer connected to a middle electrode and a functional layer having rocksalt crystal structure interfacing to the recording layer. The interface crystal grain structures between the functional layer and the recording layer provides an electric field manipulated perpendicular anisotropy enabling a low spin transfer write current. | 2014-07-24 |
20140203384 | Push-Pull Magnetoresistive Sensor Bridges and Mass Fabrication Method - A multi-chip push-pull magnetoresistive bridge sensor utilizing magnetic tunnel junctions is disclosed. The magnetoresistive bridge sensor is composed of a two or more magnetic tunnel junction sensor chips placed in a semiconductor package. For each sensing axis parallel to the surface of the semiconductor package, the sensor chips are aligned with their reference directions in opposition to each other. The sensor chips are then interconnected as a push-pull half-bridge or Wheatstone bridge using wire bonding. The chips are wire-bonded to any of various standard semiconductor lead frames and packaged in inexpensive standard semiconductor packages. | 2014-07-24 |
20140203385 | MAGNETIC MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetic memory comprises an electrode, a memory layer which is formed on the electrode and has magnetic anisotropy perpendicular to a film plane, and in which a magnetization direction is variable, a tunnel barrier layer formed on the memory layer, and a reference layer which is formed on the tunnel barrier layer and has magnetic anisotropy perpendicular to the film plane, and in which a magnetization direction is invariable. The memory layer has a positive magnetostriction constant on a side of the electrode, and a negative magnetostriction constant on a side of the tunnel barrier layer. | 2014-07-24 |
20140203386 | Shallow Junction Photodiode for Detecting Short Wavelength Light - The present invention is a photodiode or photodiode array having improved ruggedness for a shallow junction photodiode which is typically used in the detection of short wavelengths of light. In one embodiment, the photodiode has a relatively deep, lightly-doped P zone underneath a P+ layer. By moving the shallow junction to a deeper junction in a range of 2-5 μm below the photodiode surface, the improved device has improved ruggedness, is less prone to degradation, and has an improved linear current. | 2014-07-24 |
20140203387 | SEMICONDUCTOR CHIP PACKAGE AND METHOD FOR MANUFACTURING THEREOF - Disclosed herein is a semiconductor chip package, which includes a semiconductor chip, a plurality of vias, an isolation layer, a redistribution layer, and a packaging layer. The vias extend from the lower surface to the upper surface of the semiconductor chip. The vias include at least one first via and at least one second via. The isolation layer also extends from the lower surface to the upper surface of the semiconductor chip, and part of the isolation layer is disposed in the vias. The sidewall of the first via is totally covered by the isolation layer while the sidewall of the second via is partially covered by the isolation layer. The redistribution layer is disposed below the isolation layer and fills the plurality of vias, and the packaging layer is disposed below the isolation layer. | 2014-07-24 |
20140203388 | OPTICAL SENSOR WITH INTEGRATED PINHOLE - An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light. The metal layer further includes a pinhole configured to collimate the incident light, and the plurality of cathodes form a rotational symmetry of order n with respect to an axis of the pinhole | 2014-07-24 |
20140203389 | Solid-State Photodetector Pixel and Photodetecting Method - A pixel is formed in a semiconductor substrate (S) with a plane surface for use in a photodetector. It comprises an active region for converting incident light (In) into charge carriers, photogates (PGL, PGM, PGR) for generating a lateral electric potential (Φ(x)) across the active region, and an integration gate (IG) for storing charge carriers generated in the active region and a dump site (Ddiff). The pixel further comprises separation-enhancing means (SL) for additionally enhancing charge separation in the active region and charge transport from the active region to the integration gate (IG). The separation-enhancing means (SL) are for instance a shield layer designed such that for a given lateral electric potential (Φ(x)), the incident light (In) does not impinge on the section from which the charge carriers would not be transported to the integration gate (IG). | 2014-07-24 |
20140203390 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - An solid-state imaging device includes a pixel region formed on a semiconductor substrate, an effective pixel region and a shielded optical black region in the pixel region, a multilayer wiring layer formed on a surface of the side opposite to a light incident side of the semiconductor substrate, a supporting substrate bonded to a surface of the multilayer wiring layer side, and an antireflection structure that is formed on the bonding surface side of the supporting substrate. | 2014-07-24 |
20140203391 | INTEGRATED CIRCUIT INCLUDING A DIRECTIONAL LIGHT SENSOR - An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface. The integrated circuit also includes a directional light sensor. The directional light sensor includes a plurality of photodetectors located on the major surface. The directional light sensor also includes one or more barriers, wherein each barrier is positioned to shade one or more of the photodetectors from light incident upon the integrated circuit from a respective direction. The directional light sensor is operable to determine a direction of light incident upon the integrated circuit by comparing an output signal of at least two of the photodetectors. | 2014-07-24 |
20140203392 | SEMICONDUCTOR RADIATION DETECTOR - A semiconductor radiation detector having a semiconductor substrate and first and second metal layers. The semiconductor substrate has substantially planar upper and lower opposing surfaces which have respective first and second surface areas. The first and second surface areas are defined by prospective dice lines. The first metal layer is on the substantially planar upper surface such that the first metal layer will have a surface area less than the first surface area of the substantially planar upper surface as defined by spaces on the substantially planar upper surface between the first metal layer and the prospective dice lines which define the first surface area. The second metal layer is on the substantially planar lower opposing surface. | 2014-07-24 |
20140203393 | SEMICONDUCTOR DEVICE - A semiconductor device having high breakdown voltage and high reliability without forming an embedded injection layer with high position accuracy. The semiconductor device includes a base as an active area of a second conductivity type formed on a surface layer of a semiconductor layer of a first conductivity type to constitute a semiconductor element; guard rings as a plurality of first impurity regions of the second conductivity type formed on the surface layer of the semiconductor layer spaced apart from each other to respectively surround the base in plan view; and an embedded injection layer as a second impurity region of the second conductivity type embedded in the surface layer of the semiconductor layer to connect at least two bottom portions of the plurality of guard rings. | 2014-07-24 |
20140203394 | Chip With Through Silicon Via Electrode And Method Of Forming The Same - The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening. | 2014-07-24 |
20140203395 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands; an insulation layer formed on the surface and having a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices. Therefore, the mounting density of the passive devices is improved. | 2014-07-24 |
20140203396 | Electrical Fuse Structure and Method of Formation - An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device. | 2014-07-24 |
20140203397 | Methods and Apparatus for Inductors and Transformers in Packages - Methods and apparatus for forming a semiconductor device package with inductors and transformers using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top die and a bottom die, or between a die and an interposer. An inductor can be formed by a redistribution layer within a bottom device and a micro-bump line above the bottom device connected to the RDL. The inductor may be a symmetric inductor, a spiral inductor, a helical inductor which is a vertical structure, or a meander inductor. A pair of inductors with micro-bump lines can form a transformer. | 2014-07-24 |
20140203398 | Integrated Magnetic Core Inductors with Interleaved Windings - A coupled inductor topology for a thin-film magnetic core power inductor that enables efficient integrated power conversion. Coupled magnetic core inductors with interleaved windings inductors comprise magnetic films and partially or fully interleaved conductors. Methods described herein are suitable for integration into monolithic, chip stacking fabrication or other traditional semiconductor device fabrication techniques and equipment. Soft ferromagnetic materials exhibiting high permeability and low coercivity are deposited using thin-film techniques. A plurality of electrical conductors surround at least one ferromagnetic core giving rise to two or more windings. Windings are coupled to one another through magnetic core(s). Windings are used to control permeability, inductance and magnetic saturation, finding particular utility in high magnetic flux applications. | 2014-07-24 |
20140203399 | Integrated Circuits with Magnetic Core Inductors and Methods of Fabrications Thereof - In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil. | 2014-07-24 |
20140203400 | METAL-INSULATOR-METAL CAPACITOR FORMATION TECHNIQUES - Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes. | 2014-07-24 |
20140203401 | METAL-ON-METAL (MOM) CAPACITORS HAVING LATERALLY DISPLACED LAYERS, AND RELATED SYSTEMS AND METHODS - Metal-on-Metal (MoM) capacitors having laterally displaced layers and related systems and methods are disclosed. In one embodiment, a MoM capacitor includes a plurality of vertically stacked layers that are laterally displaced relative to one another. Lateral displacement of the layers minimizes cumulative surface process variations making a more reliable and uniform capacitor. | 2014-07-24 |
20140203402 | SOLID STATE DRIVE - Provided is a solid state drive suitable for an increase in capacity. The solid state drive includes a flash memory, and a capacitor electrically connected to the flash memory. The capacitor is composed of an electric double layer capacitor including an electrolyte solution containing propylene carbonate. | 2014-07-24 |
20140203403 | ELECTRICAL DEVICE HAVING MOVABLE ELECTRODE - A movable electric device includes: a first and second fixed electrodes formed on a support substrate, and having opposing electrode surfaces which are substantially perpendicular to the surface of the support substrate, and define a cavity therebetween; a movable member having a movable electrode having a first end disposed near the first fixed electrode and a second end disposed near the second fixed electrode, and bent spring member continuing from at least one of the first and second ends of the movable electrode, and including part which is bent in thickness direction of the movable electrode; and first and second anchors disposed on the support substrate and supporting the movable member at its opposite ends. | 2014-07-24 |
20140203404 | SPIRAL METAL-ON-METAL (SMOM) CAPACITORS, AND RELATED SYSTEMS AND METHODS - Spiral metal-on-metal (MoM or SMoM) capacitors and related systems and methods of forming MoM capacitors are disclosed. In one embodiment, a MoM capacitor disposed in a semiconductor die is disclosed. The MoM capacitor comprises a first electrode coupled to a first trace. The first trace is coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments. The MoM capacitor also comprises a second electrode coupled to a second trace. The second trace is coiled in the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments. Reduced variations in the capacitance allow circuit designers to build circuits with tighter tolerances and generally improve circuit reliability. | 2014-07-24 |
20140203405 | METHOD TO DYNAMICALLY TUNE PRECISION RESISTANCE - A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging. | 2014-07-24 |
20140203406 | ISOLATION STRUCTURE OF HIGH-VOLTAGE DRIVING CIRCUIT - An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area. | 2014-07-24 |
20140203407 | METHOD FOR LOW TEMPERATURE BONDING AND BONDED STRUCTURE - A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO | 2014-07-24 |
20140203408 | METHOD OF PRODUCING COMPOSITE WAFER AND COMPOSITE WAFER - There is provided a method that includes forming a sacrificial layer and the semiconductor crystal layer on a semiconductor crystal layer formation wafer in the stated order, bonding together the semiconductor crystal layer formation wafer and a transfer-destination wafer such that a first surface of the semiconductor crystal layer and a second surface of the transfer-destination wafer face each other, and splitting the transfer-destination wafer from the semiconductor crystal layer formation wafer with the semiconductor crystal layer remaining on the transfer-destination wafer side, by etching away the sacrificial layer by immersing the semiconductor crystal layer formation wafer and the transfer-destination wafer wholly or partially in an etchant. Here, the transfer-destination wafer includes an inflexible wafer and an organic material layer, and a surface of the organic material layer is the second surface. | 2014-07-24 |
20140203409 | Integrated Circuit Structures, Semiconductor Structures, And Semiconductor Die - Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed. | 2014-07-24 |
20140203410 | DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS - Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer. | 2014-07-24 |
20140203411 | PRODUCTION METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE - A semiconductor wafer, includes: a plurality of element regions; a surface electrode that is disposed in each of the plurality of element regions; an insulating layer that is disposed in each of the plurality of element regions and of which height from a front side surface of the semiconductor wafer is higher than that of the surface electrode in a periphery of the surface electrode; and a dicing line groove that is formed in a front side surface of the semiconductor wafer, that surrounds the surface electrode with the insulating layer therebetween, of which height from the front side surface of the semiconductor wafer is lower than that of the insulating layer, and that extends to a perimeter of the semiconductor wafer; in which the insulating layer is formed with a communication passage that extends from a side of the surface electrode to the dicing line groove. | 2014-07-24 |
20140203412 | THROUGH SILICON VIAS FOR SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad. | 2014-07-24 |
20140203413 | Composite Substrate, Semiconductor Chip Having a Composite Substrate and Method for Producing Composite Substrates and Semiconductor Chips - A composite substrate has a carrier and a utility layer. The utility layer is attached to the carrier by means of a dielectric bonding layer and the carrier contains a radiation conversion material. Other embodiments relate to a semiconductor chip having such a composite substrate, a method for producing a composite substrate and a method for producing a semiconductor chip with a composite substrate. | 2014-07-24 |
20140203414 | Method Of Modifying Surfaces - The invention provides a method for chemically modifying a surface of a substrate, preferably a silicon substrate, including the steps of providing a substrate having at least a portion of a surface thereof coated with an organic coating composition including unsaturated moieties forming a surface coating, and introducing a vapour phase reactive intermediate species based on a Group 14 or Group 15 element from the Periodic Table of Elements to the substrate whereupon the reactive intermediate species is able to react with a number of the unsaturated moieties in the coating composition thereby chemically modifying the surface coating. Also disclosed is a surface-modified substrate obtained or obtainable by the method, and uses thereof in the fabrication of MEMS and IC devices. | 2014-07-24 |
20140203415 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, DELAMINATION METHOD, AND TRANSFERRING METHOD - A substrate and a delamination film are separated by a physical means, or a mechanical means in a state where a metal film formed over a substrate, and a delamination layer comprising an oxide film including the metal and a film comprising silicon, which is formed over the metal film, are provided. Specifically, a TFT obtained by forming an oxide layer including the metal over a metal film; crystallizing the oxide layer by heat treatment; and performing delamination in a layer of the oxide layer or at both of the interface of the oxide layer is formed. | 2014-07-24 |
20140203416 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package includes: a substrate; a signal pad and a ground pad disposed on the substrate; a first and a second conducting layers disposed on the substrate and electrically connected to the signal pad and the ground pad, respectively, wherein the first and the second conducting layers extend from an upper surface of the substrate towards a lower surface of the substrate along a first and a second side surfaces of the substrate, respectively, and the first and the second conducting layers protrude from the lower surface; and a protection layer disposed on the substrate, wherein the protection layer completely covers the entire portion of the first conducting layer located on the first side surface of the substrate, and the entire portion of the second conducting layer located on the second side surface of the substrate is not covered by the protection layer. | 2014-07-24 |
20140203417 | MITIGATION OF FAR-END CROSSTALK INDUCED BY ROUTING AND OUT-OF-PLANE INTERCONNECTS - In accordance with one aspect of the present description, a transmission line such as a microstrip or stripline transmission line, has stub-shaped projections adapted to compensate simultaneously for both far-end crosstalk (FEXT) induced by inductive coupling between the transmission line and an adjacent transmission line, and also far-end crosstalk induced by inductive coupling between the vertical electrical interconnect at the far end of the transmission line and an adjacent vertical electrical interconnect electrically connected to the adjacent transmission line. In another aspect of the present description, a microstrip transmission line may have multiple stubby line sections having different resistances and impedances to more gradually transition from to the typically low impedance characteristics of vertical interconnects such as the PTH vias and socket connectors. Other aspects are described. | 2014-07-24 |
20140203418 | LEAD FRAME AND A METHOD OF MANUFACTURING THEREOF - A method of manufacturing a lead frame, comprising the steps of: providing an electrically-conductive base material having first and second planar sides; forming a patterned conductive layer on the first planar side of the base material; etching the second planar side of the base material at portions with respect to exposed portions on the first planar side of the base material comprising the patterned conductive layer, to form partially-etched portions on the second planar side of the base material; providing a non-conductive filling material over the second planar side of the base material, wherein the filling material fills spaces inside the partially-etched portions on the second planar side of the base material to form adjacent portions of the filling material and a plurality of conductive portions on the second planar side of the base material; and etching the exposed portions of the first planar side of the base material comprising the patterned conductive layer to form partially-etched portions on the first planar side of the base material that combine with the partially-etched portions on the second planar side of the base material to thereby form a plurality of separate conductive regions on the first planar side of the base material, each conductive region being electrically conductive with at least a respective one of the plurality of conductive portions on the second planar side of the base material. | 2014-07-24 |
20140203419 | Half-Bridge Package with a Conductive Clip - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe. | 2014-07-24 |
20140203420 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE PRODUCED USING PRODUCTION METHOD - A method for producing a semiconductor device includes laser welding to bond an upper terminal and a lower terminal as internal wiring members of the semiconductor device. When the upper terminal is fixed to the lower terminal by the laser welding, a gap between an upper surface of the lower terminal and a lower surface of the upper terminal is equal to or more than 20 μm and equal to or less than 400 μm. | 2014-07-24 |
20140203421 | MICRO-ELECTRO MECHANICAL SYSTEM (MEMS) STRUCTURES AND METHODS OF FORMING THE SAME - A device includes a first substrate bonded with a second substrate structure. The second substrate structure includes an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the outgasing prevention structure. | 2014-07-24 |
20140203422 | Microchip with Blocking Apparatus and Method of Fabricating Microchip - A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect. | 2014-07-24 |
20140203423 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - The present specification relates to a semiconductor device in which a metal plate is attached onto a surface of a resin package, and provides a structure in which the metal plate is not easy to separate. The semiconductor device disclosed in the present specification includes semiconductor chips (IGBT, diode), a resin package molding the semiconductor chips, and metal plates fixed onto the surface of the resin package. An anchoring member is bridged between two points on a back face of the metal plate. A space between one of the metal plates and the anchoring member is filled with a molding resin of the resin package. The anchoring member firmly bites the resin package, and therefore, the metal plate is difficult to be released from the resin package. | 2014-07-24 |
20140203424 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - An electronic device includes a substrate; an element configured to be formed on the substrate; a sidewall member configured to enclose the element on the substrate; a cover member configured to be disposed on the sidewall member, and to partition a space around the element along with the sidewall member on the substrate; and a seal member configured to be disposed outside of the sidewall member, to bond the sidewall member and the cover member to a surface of the substrate, and to seal the space. | 2014-07-24 |
20140203425 | HEAT DISSIPATING DEVICE - A heat dissipating device includes a semiconductor packaging structure having a stator set and a semiconductor element provided therein, a fan wheel set pivotally connected to the semiconductor packaging structure, and a guiding structure having a guiding channel. The guiding structure receives the semiconductor packaging structure and the fan wheel set. The fan wheel set includes a plurality of blades located above the surface of the semiconductor packaging structure. The stator set and the semiconductor element controls the first blades. The blades extend beyond side surfaces the semiconductor packaging structure and have their sizes increased, such that the airflow volume can be increased without changing the size of the semiconductor packaging structure. | 2014-07-24 |
20140203426 | SEMICONDUCTOR DEVICE INCLUDING COOLER - A semiconductor device includes a package and a cooler. The semiconductor package includes a semiconductor element, a metal member, and a molding member for encapsulating the semiconductor element and the metal member. The metal member has a metal portion thermally connected to the semiconductor element, an insulating layer on the metal portion, and a conducting layer on the insulating layer. The conducting layer is at least partially exposed outside the molding member and serves as a radiation surface for radiating heat of the semiconductor element. The cooler has a coolant passage through which a coolant circulates to cool the conducting layer. The conducting layer and the cooler are electrically connected together. | 2014-07-24 |
20140203427 | LOW ALPHA PARTICLE EMISSION ELECTRICALLY-CONDUCTIVE COATING - An electrically conductive paste providing low alpha particle emission is provided. A resin and conductive particles are mixed, and a curing agent is added. A solvent is subsequently added. The electrically conductive paste including a resin compound is formed by mixing the mixture in a high shear mixer. The electrically conductive paste can be applied to a surface of an article to form a coating, or can be molded into an article. The solvent is evaporated, and the electrically conductive paste is cured to provide a graphite-containing resin compound. The graphite-containing resin compound is electrically conductive, and provides low alpha particle emission at a level suitable for a low alpha particle emissivity coating. | 2014-07-24 |
20140203428 | CHIP STACK WITH ELECTRICALLY INSULATING WALLS - A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint. | 2014-07-24 |
20140203429 | FAN-OUT PACKAGE STRUCTURE AND METHODS FOR FORMING THE SAME - A package includes a device die including a first plurality of metal pillars at a top surface of the device die. The package further includes a die stack including a plurality of dies bonded together, and a second plurality of metal pillars at a top surface of the die stack. A polymer region includes first portions encircling the device die and the die stack, wherein a bottom surface of the polymer region is substantially level with a bottom surface of the device die and a bottom surface of the die stack. A top surface of the polymer region is level with top ends of the first plurality of metal pillars and top ends of the second plurality of metal pillars. Redistribution lines are formed over and electrically coupled to the first and the second plurality of metal pillars. | 2014-07-24 |
20140203430 | INTERCONNECTION DESIGNS AND MATERIALS HAVING IMPROVED STRENGTH AND FATIGUE LIFE - Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large diameter. | 2014-07-24 |
20140203431 | SEMICONDUCTOR DEVICE - To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W | 2014-07-24 |
20140203432 | Method for Packaging Quad Flat Non-Leaded Package Body, and Package Body - A method for packaging a quad flat non-leaded (QFN) package body. The method includes: etching an upper surface of a metal plate to process a groove to form a bond wire bench, a component bench, and a bump; processing the bump to a preset height, and assembling a component on the component bench; packaging the processed metal plate to form a package body, and exposing the surface of the processed bump on an upper surface of the package body to form a top lead; and etching a lower surface of the package body to process a bottom lead. In the present invention, large passive components can be stacked on the QFN package body with a top lead; the structure is simplified while the reliability of the welding joints is improved; a plurality of components can be stacked through the top lead to overcome the limitations of component stacking. | 2014-07-24 |
20140203433 | IN-SITU THERMOELECTRIC COOLING - Methods and structures for thermoelectric cooling of 3D semiconductor structures are disclosed. Thermoelectric vias (TEVs) to form a thermoelectric cooling structure. The TEVs are formed with an etch process similar to that used in forming electrically active through-silicon vias (TSVs). However, the etched cavities are filled with materials that exhibit the thermoelectric effect, instead of a conductive metal as with a traditional electrically active TSV. The thermoelectric materials are arranged such that when a voltage is applied to them, the thermoelectric cooling structure carries heat away from the interior of the structure from the junction where the thermoelectric materials are electrically connected. | 2014-07-24 |
20140203434 | Semiconductor Integrated Circuit and Fabricating the Same - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a precursor. A decomposable polymer layer (DPL) is deposited between the conductive features of the precursor. The DPL is annealed to form an ordered periodic pattern of different types of polymer nanostructures. One type of polymer nanostructure is decomposed by a first selectively to form a trench. The trench is filled by a dielectric layer to form a dielectric block. The remaining types of polymer nanostructures are decomposed by a second selectively etching to form nano-air-gaps. | 2014-07-24 |
20140203435 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 2014-07-24 |
20140203436 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis. | 2014-07-24 |
20140203437 | Method Of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs. | 2014-07-24 |
20140203438 | Methods and Apparatus of Packaging of Semiconductor Devices - Methods and apparatuses for forming an under-bump metallization (UBM) pad above a dielectric layer are disclosed. The dielectric layer may be above a metal layer and comprises a first opening and a second opening surrounding the first opening, which divide the dielectric layer into a first area and a second area. An UBM pad extends into and fills the first opening of the dielectric layer, above the first area between the first opening and the second opening, and may further extends down at least partly into the second opening covering a part or the whole of the second opening of the dielectric layer. The UBM pad may further extend over a part of the second area of the dielectric layer if the UBM pad fills the whole of the second opening of the dielectric layer. A solder ball may be mounted on the UBM pad. | 2014-07-24 |
20140203439 | Through Silicon Via Structure and Method - A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via. | 2014-07-24 |
20140203440 | MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURE THEREOF - A microelectronic assembly may include a substrate having an opening extending between first and second oppositely facing surfaces of the substrate, the opening elongated in a first direction; and at least one microelectronic element having a front face facing and attached to the first surface of the substrate and a plurality of contacts at the front face overlying the opening, the microelectronic element having first and second opposite peripheral edges extending away from the front face. The first peripheral edge extends beyond, or is aligned in the first direction with, an inner edge of the opening, and the opening extends beyond the second peripheral edge. | 2014-07-24 |
20140203441 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Possible to form an opening having a sufficient opening diameter in a region sandwiched between a pair of bit lines and thereby provide a semiconductor device in which a high-quality contact using the opening is formed. | 2014-07-24 |
20140203442 | WIRING STRUCTURES FOR THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction. The upper wordline may include a recessed portion that extends for only a portion of the upper wordline in a transverse direction and the lower wordline may include a wiring area exposed by the recessed portion of the upper wordline. The wiring structures may also include an upper contact plug contacting the upper wordline and a lower contact plug contacting the wiring area. The upper and lower contact plugs may extend in a vertical direction. | 2014-07-24 |
20140203443 | Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core - A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar. | 2014-07-24 |
20140203444 | SEMICONDUCTOR DEVICE AND POWER SOURCE DEVICE - A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area. | 2014-07-24 |
20140203445 | MITIGATING PATTERN COLLAPSE - One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example. | 2014-07-24 |
20140203446 | THROUGH SILICON VIA DEVICE HAVING LOW STRESS, THIN FILM GAPS AND METHODS FOR FORMING THE SAME - Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion. | 2014-07-24 |
20140203447 | METAL LINES HAVING ETCH-BIAS INDEPENDENT HEIGHT - A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures. | 2014-07-24 |
20140203448 | RANDOM CODED INTEGRATED CIRCUIT STRUCTURES AND METHODS OF MAKING RANDOM CODED INTEGRATED CIRCUIT STRUCTURES - Randomized coded arrays and methods of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles. Also, a physically unclonable function embodied in a circuit. | 2014-07-24 |
20140203449 | INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH METAL LAYER CONNECTION TO THROUGH-SEMICONDUCTOR VIA - Integrated circuits and methods of forming integrated circuits are provided herein, in which a plurality of semiconductor devices is formed on a semiconductor substrate. At least one through-semiconductor via is formed in the semiconductor substrate and an interlayer dielectric layer is formed overlying the at least one through-semiconductor via and the plurality of semiconductor devices. A first pattern is etched in the interlayer dielectric layer over the at least one through-semiconductor via, and a second pattern different from the first pattern is etched in the interlayer dielectric layer over the same through-semiconductor via as the first pattern. At least one interconnect via is embedded within the interlayer dielectric layer, in electrical communication with one of the at least one through-semiconductor vias. A metal-containing material is deposited in the first pattern and the second pattern to form a first metal layer in electrical communication with the at least one interconnect via. | 2014-07-24 |
20140203450 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package is provided, including a substrate having a top surface, a bottom surface opposing the top surface, a via communicating the top surface with the bottom surface, and a stator set formed by circuits; an axial tube axially installed in the via of the substrate; a plurality of electronic components mounted on the top surface of the substrate and electrically connected to the substrate; an encapsulant formed on the top surface of the substrate for encapsulating the electronic components and the axial tube; and an impeller axially coupled to the axial tube via the bottom surface of the substrate. In the semiconductor package, the stator set is formed in the substrate by a patterning process. Therefore, the thickness of the semiconductor package is reduced significantly. | 2014-07-24 |
20140203451 | ELECTRONIC DEVICE PACKAGE AND PACKAGING SUBSTRATE FOR THE SAME - The present application provides an electronic device package. The package includes a packaging substrate having first and second surfaces opposing one another. First and second electrode patterns are formed on the first surface and first and second external terminals connected to the first and second electrode patterns. The second electrode pattern is electrically insulated from the first electrode pattern and surrounds the first electrode pattern An electronic device is mounted on the first surface of the packaging substrate and includes first and second electrodes disposed on a surface thereof facing the packaging substrate. The first and second electrodes are positioned on the first and second electrode patterns, respectively. | 2014-07-24 |
20140203452 | ACTIVE CHIP ON CARRIER OR LAMINATED CHIP HAVING MICROELECTRONIC ELEMENT EMBEDDED THEREIN - A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity. | 2014-07-24 |
20140203453 | AIR-DIELECTRIC FOR SUBTRACTIVE ETCH LINE AND VIA METALLIZATION - A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via. | 2014-07-24 |
20140203454 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - A semiconductor device includes an analog integrated circuit and a digital integrated circuit provided on a major surface of a substrate. An analog ground terminal is provided for the analog integrated circuit, and digital ground terminals are provided for the digital integrated circuit. An analog ground layer is stacked on the substrate so as to face the analog integrated circuit, and digital ground layers are stacked on the substrate so as to face the digital integrated circuit. The analog ground terminal is connected to the analog ground layer, and the digital ground terminals are connected to the digital ground layers, respectively. | 2014-07-24 |
20140203455 | Feature Patterning Methods and Structures Thereof - Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer. | 2014-07-24 |
20140203456 | Pre-Applying Supporting Materials between Bonded Package Components - A structure includes a first package component, and a second package component over and bonded to the first package component. A supporting material is disposed in a gap between the first package component and the second package component. A molding material is disposed in the gap and encircling the supporting material. | 2014-07-24 |
20140203457 | STACKED DIE PACKAGE, SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A stacked die package includes a package substrate, a first die mounted on the package substrate and electrically connected to the package substrate, a second die electrically connected to the package substrate, and an interposer mounted on the package substrate and including a plurality of vertical electrical connection means electrically connecting the package substrate to the second die. At least part of the first die is disposed between the second die and the package substrate in a vertical direction. | 2014-07-24 |
20140203458 | DICING TAPE-INTEGRATED FILM FOR SEMICONDUCTOR BACK SURFACE - The present invention provides a dicing tape-integrated film for semiconductor back surface, including a film for flip chip type semiconductor back surface for protecting a back surface of a semiconductor element flip chip-connected onto an adherend, and a dicing tape, the dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material, the film for flip chip type semiconductor back surface being formed on the pressure-sensitive adhesive layer, in which the pressure-sensitive adhesive layer is a radiation-curable pressure-sensitive adhesive layer whose pressure-sensitive adhesive force toward the film for flip chip type semiconductor back surface is decreased by irradiation with a radiation ray. | 2014-07-24 |
20140203459 | STEAM HUMIDIFICATION SYSTEM - A steam distribution apparatus having a heat exchanger header defining a chamber; steam distribution apparatus communicating with the heat exchanger chamber; a source of steam at a pressure higher than atmospheric; a heat exchanger having one end communicating with the source of steam and another end for communicating with the chamber and steam dispersion apparatus; and a valve. The valve operates the heat exchanger in an open-loop configuration which supplies humidification steam to the steam distribution apparatus at atmospheric pressure and operates the heat exchanger in a closed-loop at the steam pressure higher than atmospheric for heating the heat exchanger chamber wherein condensate within the chamber or steam distribution apparatus can be converted back to humidification steam. | 2014-07-24 |
20140203460 | LASER SINTERING SYSTEMS AND METHODS FOR REMOTE MANUFACTURE OF HIGH DENSITY PELLETS CONTAINING HIGHLY RADIOACTIVE ELEMENTS - The invention relates to remotely operated laser sintering systems and methods for manufacturing pellets containing highly radioactive elements. The highly radioactive elements can be recovered from used nuclear fuels. The systems and methods of the invention employ a feed composition including one or more highly radioactive elements and a ceramic matrix material. The feed composition is distributed in the form of a layer and sintered by directing at least one laser beam to form a pattern in the layer of the feed composition. The pattern corresponds to the shape of the pellet. Further, the sintering process can be repeated as necessary to achieve a pre-determined pellet height. | 2014-07-24 |
20140203461 | POLYCRYSTALLINE SINTERED NANO-GRAN ZINC SULFIDE CERAMICS FOR OPTICAL WINDOWS - A method is provided for producing an article which is transparent to visible and infrared radiation. The method includes the steps of forming a green body from a population of nanoparticles; depositing a layer of ZnS powder over the green body, thereby producing a covered green body; and sintering the covered green body, thereby producing a sintered product. | 2014-07-24 |
20140203462 | METHOD OF MANUFACTURING PLATE WORKPIECE WITH SURFACE MICROSTRUCTURES - A method of manufacturing a plate workpiece with surface microstructures is provided. Before press-molding, a preform is placed between a first mold with a pattern and a second mold, and is disposed on the second mold. Next, the first mold and the second mold are heated to a transition temperature of the preform, and then pressed against the preform to impress the pattern onto the preform to obtain a patterned preform. Finally, the patterned preform is cooled with the second mold and shrunk to obtain the plate workpiece with surface microstructures. Since the patterned preform is uniformly cooled from bottom to top by thermal conduction, the temperature field is isothermal in a horizontal distribution. Therefore, a plate workpiece with high accuracy surface microstructures is obtained, and is useful for carrying multiple optical fibers in optical communication. | 2014-07-24 |
20140203463 | MULTI-LAYER SURGICAL GUIDE - A drill guide employs multiple layers of materials with different mechanical properties in order to achieve concurrent goals of rigidity, fit and retention. For example, a rigid exterior shell and a soft interior may be used together to securely and precisely fit a drill guide to a surgical site. | 2014-07-24 |
20140203464 | SYSTEMS AND METHODS FOR FORMING A NANOPORE IN A LIPID BILAYER - A method of forming a nanopore in a lipid bilayer is disclosed. A nanopore forming solution is deposited over a lipid bilayer. The nanopore forming solution has a concentration level and a corresponding activity level of pore molecules such that nanopores are substantially not formed un-stimulated in the lipid bilayer. Formation of a nanopore in the lipid bilayer is initiated by applying an agitation stimulus level to the lipid bilayer. In some embodiments, the concentration level and the corresponding activity level of pore molecules are at levels such that less than 30 percent of a plurality of available lipid bilayers have nanopores formed un-stimulated therein. | 2014-07-24 |
20140203465 | Cosmetic Multi-Layered Wiper - A multi-layered wiper for removing a product (e.g., a cosmetic product) from an applicator. The multi-layered wiper comprises a wiping body having a wiping face, an acute wiping tip, and vertical slits, formed of a first material, over-molded to a retention body, formed of another material harder than the first material. By virtue of having a multi-layered wiper comprising a wiping body, formed of a first material, over-molded to a retention body, formed of another material, harder than the first material, the multi-layered wiper is capable of providing exceptional installation characteristics, while simultaneously providing exceptional wiping characteristics. | 2014-07-24 |
20140203466 | CLOSED LOOP CONTROL OF AUXILIARY INJECTION UNIT - A method and apparatus of controlling commencement of an injection of a melt stream of moldable material from an auxiliary injection unit. A sensor is placed in an injection molding system to sense a condition related to an injection of a first melt stream of a first moldable material provided by a primary injection unit. Commencement of a second melt stream of a second moldable material from the auxiliary injection unit is initiated upon the sensed condition related to the injection of the first melt stream being detected at a preselected value. The sensed condition may be a pressure, velocity or temperature of the first melt stream as provided by a direct sensor, a force or strain on a hot runner component as provided by an indirect sensor or the occurrence of a function of the injection molding system as provided by a functional sensor. | 2014-07-24 |
20140203467 | METHOD OF FORMING GRAPHENE NANOMESH - A method of reducing the diameter of pores formed in a graphene sheet includes forming at least one pore having a first diameter in the graphene sheet such that the at least one pore is surrounded by passivated edges of the graphene sheet. The method further includes chemically reacting the passivated edges with a chemical compound. The method further includes forming a molecular brush at the passivated edges in response to the chemical reaction to define a second diameter that is less than the initial diameter of the at least one pore. | 2014-07-24 |
20140203468 | Polymer Composites - The present disclosure pertains to resins/filler composites that are formed via a resin infusion process. Certain embodiments are directed to methods and systems that may be used to produce a moulded composite article. An exemplary method comprising: a) filling to a predetermined level a mould tool with particles; b) infusing a resin composition into the mould tool filled with the particles in order to form a composite; c) vibrating the mould tool for a portion of time at one or more of the following stages: during the filling with the particles, after the filling with particles, during the infusing of the resin composition and after the infusions of the resin composition; wherein the composite comprises between 10% to 50% by weight of the resin composition and between 50% to 90% by weight of the particles; and d) curing the composite to form a moulded composite article. | 2014-07-24 |
20140203469 | GRAPHENE-SULFUR NANOCOMPOSITES FOR RECHARGEABLE LITHIUM-SULFUR BATTERY ELECTRODES - Rechargeable lithium-sulfur batteries having a cathode that includes a graphene-sulfur nanocomposite can exhibit improved characteristics. The graphene-sulfur nanocomposite can be characterized by graphene sheets with particles of sulfur adsorbed to the graphene sheets. The sulfur particles have an average diameter less than 50 nm. | 2014-07-24 |
20140203470 | APPARATUS AND METHOD FOR PRODUCING LAYERED MATS - The invention relates to an apparatus for forming a layered mat of non-oriented particles in a particle board production process, comprising first rollers for size-fractionating a continuous stream of particles into a first and a second fraction; second rollers arranged lower than the first rollers, to receive the first fraction, the second rollers being capable of further size-fractionating said first fraction; and third rollers arranged lower than the second rollers, for receiving said second fraction, the third rollers being capable for further size-fractionating said second fraction; the apparatus further comprising a receiving surface, movable along a longitudinal dimension of the apparatus, and arranged to receive said fractionated first fraction and said fractionated second fraction from said second and third rollers, at different longitudinal positions; wherein the first rollers and the third rollers are pin-type rollers. | 2014-07-24 |
20140203471 | METHOD OF MOLDING GAS HYDRATE PELLET - A method is for molding a gas hydrate pellet for improving convenience of handling of a natural gas hydrate during transportation and storage, and thereby improving the practical use of the natural gas hydrate. Gas hydrate slurry is fed in a compression chamber, and pressure and compression are applied to the gas hydrate slurry by advancing a compression plunger. At that time, a stroking speed of the compression plunger is set minimum, preferably less than a value expressed by a stroke length of the compression plunger at compression×10 | 2014-07-24 |
20140203472 | NOVEL ORIENTED POLYMER COMPOSITE ARTICLE, COMPOSITION AND METHOD OF MANUFACTURE - The disclosure generally relates to a solid state non-proportional, adjustable, tapered drawing die and an oriented polymer article formed therefrom. More specifically, embodiments relate to a non-proportional draw die used to produce oriented, dimensionally accurate, symmetric or asymmetric polymer composite profiles having simple profiles or complicated profiles with multiple edges. Moreover, the draw die of the disclosure prevents natural flattening of the edges of the final profile during the solid state die drawing process of the oriented polymer composite. | 2014-07-24 |
20140203473 | MULTI-LAYERED FUEL TUBING - The invention describes a flexible tubular article for transport of volatile hydrocarbons comprising: (a) an inner layer of a polyvinylidene difluoride (PVDF) polymer or a polyvinylidene difluoride copolymer; (b) an intermediate thermoplastic polyurethane (TPU) layer extruded in tubular form over the inner PVDF layer, and (c) a polyvinyl chloride polymer extruded in tubular form over the outside surface of the intermediate layer and being coextensive therewith. The tubular articles of the invention have a maximum permeation rating of 15 g/m | 2014-07-24 |
20140203474 | DEVICE FOR COATING ELECTRICALLY CONDUCTIVE WIRES - The present invention relates to a device for coating electrically conductive wires, comprising multiple units in the following arrangement:
| 2014-07-24 |
20140203475 | ANTIMICROBIAL, MOLDED LAMINATE SHOPPING CART PART AND METHOD OF MANUFACTURING SAME - An antimicrobial, molded laminate shopping cart part and method of manufacturing same are provided. The part, such as a small child seat, includes a structural carrier made from a thermoplastic resin and having an outer surface. The part further includes a formed plastic film sheet having upper and lower surfaces. The lower surface is bonded to the outer surface of the carrier. The film sheet includes an outer clear plastic layer including at least one antimicrobial agent disbursed throughout the plastic layer. The antimicrobial agent exhibits controlled migration through the clear plastic to the outer surface of the clear plastic layer. | 2014-07-24 |
20140203476 | A METHOD OF TREATING A NET MADE FROM ULTRA-HIGH-MOLECULAR-WEIGHT POLYETHYLENE - A method of treating a net ( | 2014-07-24 |
20140203477 | Method and Apparatus for Fabricating Composite Stringers - Method and tooling apparatus for forming a composite charge into a stringer having an I-shaped cross-section. A substantially flat composite charge is placed on a die set and pressed formed into a die set cavity to form a stringer hat. A stringer base is formed by press forming the composite charge against the die set. The die set is used to compress the stringer hat into a stringer web having a bulb on one end thereof. A stringer cap is formed by press forming the bulb within a recess in the die set. | 2014-07-24 |
20140203478 | SYSTEM AND METHOD FOR MOLDING SOFT FLUID-FILLED IMPLANT SHELLS - Systems and methods for molding shells for fluid-filled prosthetic implants, including spinning and rotating dip- or spray-mandrels during a devolatilization step to ensure an even covering. The mandrels may be spun during the dipping or spraying step, and/or afterward while a solvent evaporates until a gum state is formed. The techniques are particularly useful for forming hollow shells from silicone dispersions for soft implants, such as breast implants. | 2014-07-24 |
20140203479 | METHOD AND SYSTEM FOR REUSE OF MATERIALS IN ADDITIVE MANUFACTURING SYSTEMS - Embodiments of the present invention are directed to a system and method for reusing surplus material generated by an Additive Manufacturing system in the process of manufacturing a 3-dimensional (3D) object. Surplus material removed from deposited layers and purged material used for printing head maintenance are transferred to back to the printing system to be deposited within subsequent layers. The reusable material may be deposited within the boundaries of a cross section of the 3-dimensional object to become part of 3D object or outside the boundaries of a cross section of the 3-dimensional object as part of the support construction, which is removed from the finished product. According to embodiments of the invention, a portion of the waste material for disposal may be deposited and cured layer by layer to form a waste block, concurrently with printing the layers of the 3D dimensional object. The fully cured waste block may be then disposed of in a safe manner. | 2014-07-24 |
20140203480 | PRODUCTION OF UNIT DOSE CONSTRUCTS - Dissolvable unit dose constructs and their method of manufacture are disclosed in which the unit dose constructs are formed of a composition including a polymer matrix that includes a water soluble polymer, active ingredient, and a liquid carrier. The composition is deposited directly, such as by stenciling, to form individual unit doses without the need to cut and convert long, continuous rolls of film. | 2014-07-24 |