27th week of 2009 patent applcation highlights part 17 |
Patent application number | Title | Published |
20090166786 | Image Sensor and Method for Manufacturing the Same - An image sensor includes a metal interconnection and readout circuitry over a first substrate, an image sensing device, and an ion implantation isolation layer. The image sensing device is over the metal interconnection, and an ion implantation isolation layer is in the image sensing device. The image sensing device includes first, second and third color image sensing units, and ion implantation contact layers. The first, second and third color image sensing units are stacked in or on a second substrate. The ion implantation contact layers are electrically connected to the first, second and third color image sensing units, respectively. | 2009-07-02 |
20090166787 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor includes a circuitry, a substrate, an electrical junction region, a high concentration first conduction type region, and a photodiode. The circuitry includes a transistor and is formed on and/or over the substrate. The electrical junction region is formed in one side of the transistor. The high concentration first conduction type region is formed on and/or over the electrical junction region. The photodiode is formed over the circuitry. | 2009-07-02 |
20090166788 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Provided is an image sensor and a method for manufacturing the same. In the image sensor, a semiconductor substrate has a readout circuitry formed thereon. An interlayer insulating layer including a lower metal line is on the semiconductor substrate, the lower metal line being electrically connected with the readout circuitry. A buffer insulating layer is on the interlayer insulating layer. A lower electrode penetrates the buffer insulating layer to be connected with the lower metal line. A crystalline semiconductor layer is on the buffer insulating layer, the crystalline semiconductor layer being partially connected with the lower electrode. A photodiode is in the crystalline semiconductor layer. | 2009-07-02 |
20090166789 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor includes a first substrate and a photodiode. A circuitry including a metal interconnection is formed over the first substrate. The photodiode is formed over a first substrate, and contacts the metal interconnection. The circuitry of the first substrate includes a transistor over the first substrate, an electrical junction region at a side of the transistor, and a first conduction type region. The first conduction type region is connected to the metal interconnection and contacts the electrical junction region. | 2009-07-02 |
20090166790 | Image Sensor and Method for Manufacturing the Same - An image sensor may comprise circuitry, a first lower electrode, a photodiode, an upper electrode, a second lower electrode, and an upper interconnection. The circuitry may comprise a first lower interconnection and a second lower interconnection over a dielectric of a substrate. The first lower electrode, the photodiode, and the upper electrode may be sequentially formed over the first lower interconnection. The second lower electrode may comprise a passivation layer over the second lower interconnection. The upper interconnection may be formed over the second lower electrode and electrically connected to the upper electrode. | 2009-07-02 |
20090166791 | METHOD FOR MANUFACTURING IMAGE SENSOR - Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, an interlayer insulating layer including a metal line may be formed on and/or over a semiconductor substrate. A lower electrode layer connected with the metal line may be formed on and/or over the interlayer insulating layer. A photoresist pattern may be formed on and/or over the lower electrode layer and may form lower electrodes separated from each other. The photoresist pattern may be removed. A polymer with Cl group that may be generated when removing the photoresist pattern may be removed. According to embodiments, by removing the polymer, photons that may be generated in a photo diode may be more easily gathered, which may enhance an image quality of an image sensor. | 2009-07-02 |
20090166792 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to an image sensor and a method of forming an image sensor. According to embodiments, an image sensor may include a first substrate and a photodiode. A circuitry including a metal interconnection may be formed on and/or over the first substrate. The photodiode may be formed over a first substrate, and may contact the metal interconnection. The circuitry of the first substrate may include a first transistor, a second transistor, an electrical junction region, and a first conduction type region. The first and second transistors may be formed over the first substrate. According to embodiments, an electrical junction region may be formed between the first transistor and the second transistor. The first conduction type region may be formed at one side of the second transistor, and may be connected to the metal interconnection. | 2009-07-02 |
20090166793 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to an image sensor. According to embodiments, an image sensor may include a metal interconnection, readout circuitry, a first substrate, an image sensing device, and a second conduction type interfacial layer. The metal interconnection and the readout circuitry may be formed on and/or over the first substrate. The image sensing device may include a first conduction type conduction layer and a second conduction type conduction layer and may be electrically connected to the metal interconnection. The second conduction type interfacial layer may be formed in a pixel interface of the image sensing device. | 2009-07-02 |
20090166794 | TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY THERMOCOUPLES DISTRIBUTED IN THE CONTACT STRUCTURE - By forming thermocouples in a contact structure of a semiconductor device, respective extension lines of the thermocouples may be routed to any desired location within the die, without consuming valuable semiconductor area in the device layer. Thus, an appropriate network of measurement points of interest may be provided, while at the same time allowing the application of well-established process techniques and materials. Hence, temperature-dependent signals may be obtained from hot spots substantially without being affected by design constraints in the device layer. | 2009-07-02 |
20090166795 | SCHOTTKY DIODE OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method includes forming a first conductive type buried layer on a semiconductor substrate, forming a second conductive type epi-layer on the semiconductor substrate using an epitaxial growth method such that the epi-layer surrounds the buried layer, forming a first conductive type plug from the surface of the semiconductor substrate to the buried layer, forming a first conductive type well, which is horizontally spaced from the first conductive type plug, from the surface of the semiconductor substrate to the buried layer, and forming a plurality of metal contacts as an anode and cathode of the schottky diode, respectively, by making electrical connection to the well and plug. | 2009-07-02 |
20090166796 | METHOD FOR MANUFACTURING INTEGRATED CIRCUIT AND SEMICONDUCTOR STRUCTURE OF INTEGRATED CIRCUIT - A method for manufacturing an integrated circuit includes: performing ion implantation on a wafer to make a chip in the wafer have an original doping concentration; dividing the chip into a plurality of regions; and controlling at least one region of plurality of the regions to not have further ion implantation performed thereon, thereby making the region only have single ion implantation performed thereon utilize the original doping concentration as a doping concentration of N-wells or P-wells of transistors in the region. Additionally, the region corresponds to signal output circuits of the integrated circuit. | 2009-07-02 |
20090166797 | HIGH-VOLTAGE INTEGRATED CIRCUIT DEVICE INCLUDING HIGH-VOLTAGE RESISTANT DIODE - Provided is a high-voltage integrated circuit device including a high-voltage resistant diode. The device includes a low-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a ground voltage, a high-voltage circuit region having a plurality of semiconductor devices, which operate with respect to a voltage that varies from the ground voltage to a high voltage, a junction termination and a first isolation region electrically isolating the low-voltage circuit region from the high-voltage circuit region, a high-voltage resistant diode formed between the low-voltage circuit region and the high-voltage circuit region, and a second isolation region surrounding the high-voltage resistant diode and electrically isolating the high-voltage resistant diode from the low-voltage circuit region and the high-voltage circuit region. Therefore, a leakage current of the high-voltage resistant diode can be prevented. | 2009-07-02 |
20090166798 | DESIGN METHODOLOGY FOR GUARD RING DESIGN RESISTANCE OPTIMIZATION FOR LATCHUP PREVENTION - A design structure is disclosed for a circuit optimizing guard ring design by optimizing the path resistance value between the components of the parasitic lateral bipolar transistors in a CMOS circuit and the power supply or ground. By comparing the calculated path resistance value to a maximum resistance number derived from specifications, elements that need further redesign are identified. Repeated redesign with several redesign options eventually lead to an optimized guard ring structure that provides area-efficient and sufficient latchup protection for the CMOS circuit. A design structure employing such an optimized guard ring is also provided. | 2009-07-02 |
20090166799 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SUCH A SEMICONDUCTOR DEVICE - The invention relates to a method of manufacturing a semiconductor device ( | 2009-07-02 |
20090166800 | INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING A DOUBLET STRUCTURE OF STRESSED MATERIALS - By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed. | 2009-07-02 |
20090166801 | FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a fuse of a semiconductor device comprises forming an island-type metal fuse in a region where a laser is irradiated, so that laser energy may not be dispersed in a fuse blowing process, thereby improving repair efficiency. | 2009-07-02 |
20090166802 | SEMICONDUCTOR DEVICE WITH FUSE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor with a fuse includes providing a substrate, forming an insulation layer over the substrate, forming a polysilicon hard mask to form a metal contact over the insulation layer, forming a first mask pattern to form a fuse over the polysilicon hard mask, and removing the polysilicon hard mask exposed by the first hard mask pattern to form a polysilicon fuse connected to a portion of the polysilicon hard mask. | 2009-07-02 |
20090166803 | SEMICONDUCTOR DEVICE WITH FUSE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor with a fuse includes providing a substrate, forming an insulation layer over the substrate, forming a polysilicon hard mask to form a metal contact over the insulation layer, forming a first mask pattern to form a fuse over the polysilicon hard mask, and removing the polysilicon hard mask exposed by the first hard mask pattern to form a polysilicon fuse connected to a portion of the polysilicon hard mask. | 2009-07-02 |
20090166804 | FORMING INDUCTOR AND TRANSFORMER STRUCTURES WITH MAGNETIC MATERIALS USING DAMASCENE PROCESSING FOR INTEGRATED CIRCUITS - Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at least one via structure disposed in a first dielectric layer, forming a second dielectric layer disposed on the first magnetic layer, forming at least one conductive structure disposed in the second dielectric layer, forming a third layer of dielectric material disposed on the conductive structure, forming a second layer of magnetic material disposed in the third layer of dielectric material and in the second layer of dielectric material, wherein the first and second layers of the magnetic material are coupled to one another. | 2009-07-02 |
20090166805 | Metal Insulator Metal Capacitor and Method of Manufacturing the Same - Disclosed are a metal insulator metal (MIM) capacitor and a method of manufacturing a MIM capacitor. The MIM capacitor includes a lower metal interconnection layer, a dielectric layer pattern formed on the lower metal interconnection layer, and a third metal layer pattern formed on the dielectric layer pattern. The dielectric layer pattern has a concave surface that can be formed by performing an isotropic etching process. Accordingly, the third metal layer pattern fills the concave surface, resulting in a larger surface contact area between the dielectric material and the metal material of the MIM capacitor. | 2009-07-02 |
20090166806 | EPITAXIAL SEMICONDUCTOR LAYER AND METHOD - A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include advantages such as reduced lattice mismatch at an epitaxial interface between two different semiconductor materials. One advantageous application of such an interface includes an electrical-optical communication structure. Methods such as deposition of layers at an elevated temperature provide easy formation of semiconductor structures with a modified lattice constant that permits an improved epitaxial interface. | 2009-07-02 |
20090166807 | INTEGRATED SEMICONDUCTOR OPTICAL DEVICE - A semiconductor laser (a first semiconductor optical device) and an optical modulator (a second semiconductor optical device) are integrated on the same n-type InP substrate. The semiconductor laser butt-joined to the optical modulator. Each of the semiconductor laser and the optical modulator has a Be-doped p-type InGaAs contact layer. The p-type InGaAs contact layers have a Be-doping concentration of 7×10 | 2009-07-02 |
20090166808 | LASER PROCESSING METHOD AND SEMICONDUCTOR CHIP - A laser processing method is provided, which, even when a substrate formed with a laminate part including a plurality of functional devices is thick, can cut the substrate and laminate part with a high precision. | 2009-07-02 |
20090166809 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURE - A reliable semiconductor device is provided which comprises lower and upper IGBTs | 2009-07-02 |
20090166810 | Semiconductor Device Crack-Deflecting Structure and Method - The invention relates to microelectronic semiconductor devices, and to mass-production of the same on semiconductor wafers with novel crack-deflecting structures and methods. According to the invention, a semiconductor device includes an active circuit area surrounded by an inactive area and circumscribed with a bulwark having a crack-deflecting face oriented toward the periphery of the device. Embodiments of the invention are disclosed, in which a semiconductor device, or multiple devices on a wafer, include bulwarks having series of minor arcs with their chords oriented toward the peripheries of the devices. Additional embodiments of the invention described include bulwarks having series of right angles oriented toward the peripheries of the devices. Examples of the invention also include preferred embodiments wherein the bulwarks further comprise series of discrete pickets, parallel bulwarks, and bulwarks in combination with scribe seals. | 2009-07-02 |
20090166811 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a semiconductor chip and through electrodes formed passing through the semiconductor chip. A ground layer connected to the through electrode and a patch antenna connected to the through electrode are provided through an inorganic insulating layer formed of SiO | 2009-07-02 |
20090166812 | SEMICONDUCTOR AND AN ARRANGEMENT AND A METHOD FOR PRODUCING A SEMICONDUCTOR - The present invention relates generally to semiconductors, material layers within semiconductors, a production method of semiconductors, and a manufacturing arrangement for producing semiconductors. A semiconductor according to the invention includes at least one layer with a surface, produced by laser ablation, wherein the uniform surface area to be produced includes at least an area 0.2 dm | 2009-07-02 |
20090166813 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer on the first semiconductor layer, etching the second semiconductor layer and the first semiconductor layer to form a first groove passing through the second semiconductor layer and the first semiconductor layer, forming a first support having tensile stress in the first groove, etching the second semiconductor layer to form a second groove that exposes the first semiconductor layer, forming a cavity between the second semiconductor layer and the semiconductor substrate by etching the first semiconductor layer through the second groove, forming an insulating film in the cavity, and forming a buried film having tensile stress in the second groove. | 2009-07-02 |
20090166814 | INTERLAYER DIELECTRIC MATERIAL IN A SEMICONDUCTOR DEVICE COMPRISING STRESSED LAYERS WITH AN INTERMEDIATE BUFFER MATERIAL - A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased. | 2009-07-02 |
20090166815 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including a compound semiconductor laminated structure having a plurality of compound semiconductor layers formed over a semiconductor substrate, a first insulation film covering at least a part of a surface of the compound semiconductor laminated structure, and a second insulation film formed on the first insulation film, wherein the second insulation film includes more hydrogen than the first insulation film. | 2009-07-02 |
20090166816 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device may include: forming an oxide film pattern and a poly film pattern over a semiconductor substrate to expose a portion of the surface of the semiconductor substrate; and then forming a spacer composed of a first insulating material on sidewalls of the oxide film pattern and the poly film pattern; and then forming a second insulating film over the semiconductor substrate including the spacer and the poly film, the second insulating film having a first portion formed over the exposed portion of the semiconductor substrate, a second portion formed over the poly film pattern and a third portion formed at an incline between the first and second portions. | 2009-07-02 |
20090166817 | EXTREME LOW-K DIELECTRIC FILM SCHEME FOR ADVANCED INTERCONNECTS - An extreme low-k (ELK) dielectric film scheme for advanced interconnects includes an upper ELK dielectric layer and a lower ELK dielectric with different refractive indexes. The refractive index of the upper ELK dielectric layer is greater than the refractive index of the lower ELK dielectric layer. | 2009-07-02 |
20090166818 | Positive Photosensitive Resin Composition, and Semiconductor Device and Display Therewith - Disclosed is a positive photosensitive resin composition containing (A) an alkali-soluble resin, (B) a diazoquinone compound, (d1) an activated silicon compound and (d2) an aluminum complex. Also disclosed is a positive photosensitive resin composition containing (A) an alkali-soluble resin, (B) a diazoquinone compound, (C) a compound having two or more oxetanyl groups in one molecule and (D) a catalyst for accelerating the ring-opening reaction of the oxetanyl groups of the compound (C). | 2009-07-02 |
20090166819 | CHIPSET PACKAGE STRUCTURE - A chipset package structure includes a carrier, a plurality of pinouts, at least one semiconductor package preforms, at least one electromagnetic shielding layer and a protective layer. The pinouts are disposed on the carrier. The semiconductor package preforms is disposed on the second surface of the carrier and electrically connected to the pinouts. The electromagnetic shielding layer is disposed on the semiconductor package preforms and the electromagnetic shielding layer. At least one of the electromagnetic shielding layers comprises a carbon nanotube film structure. The protective layer covers the electromagnetic shielding layer. | 2009-07-02 |
20090166820 | TSOP LEADFRAME STRIP OF MULTIPLY ENCAPSULATED PACKAGES - A method of fabricating a semiconductor leadframe package from a strip including multiply encapsulated leadframe packages, and a leadframe package formed thereby are disclosed. An entire row or column of leadframes gets encapsulated together. Encapsulating an entire row or column reduces the keep-out area between adjacent leadframe packages, which allows the internal leads of each leadframe and the semiconductor die coupled thereto to be lengthened. | 2009-07-02 |
20090166821 | Leadframe Design for QFN Package with Top Terminal Leads - A semiconductor package includes a leadframe. A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion. The top portion forms a top terminal lead structure. A second lead finger is electrically connected to the first lead finger. A portion of the second lead finger forms a bottom terminal lead structure. A portion of the second lead finger corresponds to a bottom surface of the semiconductor package. A surface of the substantially flat, top portion corresponds to a top surface of the semiconductor package. | 2009-07-02 |
20090166822 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SHIELDING - An integrated circuit package system comprising: providing an elevated tiebar; forming a die paddle connected to the elevated tiebar; attaching an integrated circuit die over the die paddle adjacent the elevated tiebar; attaching a shield over the elevated tiebar and the integrated circuit die; and forming an encapsulant over a portion of the elevated tiebar, the die paddle, and the integrated circuit die. | 2009-07-02 |
20090166823 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LEAD LOCKING STRUCTURE - A mountable integrated circuit package system includes: providing a base; depositing a photoresist on the base; patterning the photoresist with an opening; filling the opening with a metal; depositing a further metal on the metal to form a lead pad; removing the photoresist; attaching a die over the base; bonding wires between the die and the lead pad; encapsulating the die and the lead pad in an encapsulation formed into a lead pad lock adjacent the lead pad; and removing the base. | 2009-07-02 |
20090166824 | LEADLESS PACKAGE SYSTEM HAVING EXTERNAL CONTACTS - A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an external coating layer in the indentations in the chip carrier; layering a conductive layer on top of the external coating layer; depositing an internal coating layer on the conductive layer; patterning the internal coating layer and the conductive layer to define external contact terminals with a T-shape profile; connecting an integrated circuit die to the external contact terminals; encapsulating the integrated circuit die and external contact terminals; and separating the chip carrier from the external coating layer. | 2009-07-02 |
20090166825 | System and Apparatus for Wafer Level Integration of Components - In a semiconductor package, a substrate has an active surface containing a plurality of active circuits. An adhesive layer is formed over the active surface of the substrate, and a known good unit (KGU) is mounted to the adhesive layer. An interconnect structure electrically connects the KGU and active circuits on the substrate. The interconnect structure includes a wire bond between a contact pad on the substrate and a contact pad on the KGU, a redistribution layer on a back surface of the substrate, opposite the active surface, a through hole via (THV) through the substrate that electrically connects the redistribution layer and wire bond, and solder bumps formed in electrical contact with the redistribution layer. The KGU includes a KGU substrate for supporting the KGU, a semiconductor die disposed over the KGU substrate, and an encapsulant formed over the semiconductor die. | 2009-07-02 |
20090166826 | LEAD FRAME DIE ATTACH PADDLES WITH SLOPED WALLS AND BACKSIDE GROOVES SUITABLE FOR LEADLESS PACKAGES - Disclosed are die paddle structures for leadframes and methods of attaching die to the die paddles. An exemplary die paddle comprises a sloped wall disposed around an attachment area for a die, where the sloped wall has an obtuse angle of inclination with respect to the attachment area. In one exemplary die-attachment process, solder material is disposed on the attachment area and/or the metalized back surface of a die, the die is placed over the attachment area and substantially within the opening defined by the sloped wall, and the solder is reflowed while the die is allowed to float over the reflowed solder free of external forces from a die-placement tool and to align itself to the sloped wall. Die paddles and attachment methods of the invention reduce the alignment tolerances needed to place the die. | 2009-07-02 |
20090166827 | MECHANICAL ISOLATION FOR MEMS DEVICES - A device according to the present invention includes a MEMS device supported on a first side of a die. A first side of an isolator is attached to the first side of the die. A package is attached to the first side of the isolator, with at least one electrically conductive attachment device attaching the die to the isolator and attaching the isolator to the package. The isolator may include isolation structures and a receptacle. | 2009-07-02 |
20090166828 | ETCHED SURFACE MOUNT ISLANDS IN A LEADFRAME PACKAGE - A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package includes a leadframe and one or more semiconductor die affixed to a die paddle of the leadframe. The leadframe is formed with a plurality of electrical terminals that get surface mounted to a host PCB. The leadframe further includes one or more extended leads, at least one of which includes an electrically conductive island which gets surface mounted to the host PCB with the electrical terminals. The islands effectively increase the number terminals within the package without adding footprint to the package. | 2009-07-02 |
20090166829 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element group in an arrangement direction of the electrode pads;
| 2009-07-02 |
20090166830 | Metallic cover of miniaturization module - A metallic cover of a miniaturization module includes a substrate, a SMD chip unit and a metallic cover, the metallic cover embracing the SMD chip unit and having at least one sizing hole and a plurality of venting holes, the venting holes being disposed around the sizing hole, and the sizing hole and the venting holes being positioned above the SMD chip unit so that glue portions fill up slits between the metallic cover and the SMD chip unit. The venting holes stop the glue portion from running over the second chip unit. The glue-filled slits between the top lid and the SMD chip unit provides a strong support to prevent any deformation of the metallic cover when the metallic cover is tested and processed. | 2009-07-02 |
20090166831 | SENSOR SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - This invention provides a sensor semiconductor package and a method for fabricating the same. The method includes: mounting on a substrate a sensor chip having a sensor area; electrically connecting the sensor chip and the substrate by means of bonding wires; forming on a transparent member an adhesive layer with an opening corresponding in position to the sensor area; and mounting the transparent member on the substrate via the adhesive layer while heating the substrate, such that the adhesive layer melts, to thereby encapsulate the periphery of the sensor chip and the bonding wires while exposing the sensor area from the adhesive layer. Thus, the sensor area is sealed by the transparent member cooperative with the adhesive layer, making the sensor semiconductor package thus-obtained dam-free, light, thin, and compact, and incurs low process costs. Also, the product reliability is enhanced since the bonding wires are encapsulated by the adhesive layer without severing concern. | 2009-07-02 |
20090166832 | STACKED FLIP-ASSEMBLED SEMICONDUCTOR CHIPS EMBEDDED IN THIN HYBRID SUBSTRATE - A semiconductor system having a substrate ( | 2009-07-02 |
20090166833 | SEMICONDUCTOR UNIT WHICH INCLUDES MULTIPLE CHIP PACKAGES INTEGRATED TOGETHER - A semiconductor unit includes an interface plate, a supporting plate integrally formed with the interface plate, two chip packages positioned at opposite sides of the supporting plate, and leading traces running in the interface plate and the supporting plate, connected with the chip packages respectively. | 2009-07-02 |
20090166834 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKING INTERPOSER - A mountable integrated circuit package system includes: forming a base integrated circuit package system includes: providing a first substrate, and forming a package encapsulation having a cavity over the first substrate with the first substrate partially exposed within the cavity; and mounting an interposer including a central aperture over the package encapsulation and the first substrate with the central aperture over the cavity. | 2009-07-02 |
20090166835 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERPOSER - An integrated circuit package system including: providing a base substrate; coupling a base integrated circuit on the base substrate; forming a double side molded interposer unit over the base integrated circuit including: providing an interposer substrate having an interposer top and an interposer bottom, mounting a first integrated circuit to the interposer bottom and electrically connected thereto, mounting a second integrated circuit to the interposer top and electrically connected thereto, and molding a first chip cover on the first integrated circuit and a second chip cover on the second integrated circuit; and coupling an external component to the double side molded interposer unit. | 2009-07-02 |
20090166836 | STACKED WAFER LEVEL PACKAGE HAVING A REDUCED SIZE - A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads. | 2009-07-02 |
20090166837 | COMBINATION OF CHIP PACKAGE UNITS - A combination includes a first chip package unit and a second chip package unit on which the first chip package unit is placed. Each of the first and second chip package units includes a substrate having a first surface, a second surface, a chip package electrically connected to the first surface, and a plurality of bonding pads formed on the first and second surfaces. The bonding pads on the first surface of the first chip package unit are respectively electrically connected with the bonding pads on the surface of the second chip package unit. The chip packages electrically connected to the first surfaces are enclosed by the substrates, and the bonding pads on the second surfaces are configured as interface terminals of the combination. | 2009-07-02 |
20090166838 | LAMINATED MOUNTING STRUCTURE AND MEMORY CARD - To provide a stacked mounting structure in which the number of semiconductor chips that can be stacked is greater than conventionally, as well as a method for fabricating the same, each semiconductor chip has electrodes provided at least at one end in the stacked mounting structure, and a board holding the semiconductor chips at the one end is folded with at least two of the semiconductor chips being stacked so as to at least partially overlap with each other. | 2009-07-02 |
20090166839 | SEMICONDUCTOR STACK DEVICE AND MOUNTING METHOD - A semiconductor stack device having semiconductor chips stacked therein, wherein pads | 2009-07-02 |
20090166840 | WAFER-LEVEL STACK PACKAGE - A wafer-level stack package includes semiconductor chips, first connection members, a second connection member, a substrate and an external connection terminal. The semiconductor chips have a power/ground pad and a signal pad. The first connection members are electrically connected to the power/ground pad and the signal pad of each of the semiconductor chips. The second connection member is electrically connected to at least one of the power/ground pads of each of the semiconductor chips, the power/ground pads being connected to the first connection members. The substrate supports the stacked semiconductor chips, the substrate including wirings that are electrically connected to the first connection members and the second connection member. The external connection terminal is provided on a surface of the substrate opposite to a surface where the semiconductor chips are stacked, wherein the external connection terminals are electrically connected to the wirings, respectively. | 2009-07-02 |
20090166841 | PACKAGE SUBSTRATE EMBEDDED WITH SEMICONDUCTOR COMPONENT - A package substrate embedded with a semiconductor component includes a substrate, a semiconductor chip, a first dielectric layer, a first circuit layer and first conductive vias. The substrate is formed with an opening for allowing the semiconductor chip to be secured therein. The semiconductor chip has an active surface and an inactive surface, wherein a plurality of electrode pads are formed on the active surface thereof and a passivation layer disposed thereon. The first dielectric layer is disposed both on the substrate and the passivation layer, wherein vias are formed at locations corresponding to those of the electrode pads and penetrating the dielectric layer and the passivation layer to expose the electrode pads therefrom. The first circuit layer is disposed on the first dielectric layer and electrically connected to the first conductive vias. The first conductive vias are disposed in the openings of the dielectric and passivation layers and the first circuit layer is electrically connected to the electrode pads, thereby allowing the first conductive vias to be electrically connected to the electrode pads of the chip. | 2009-07-02 |
20090166842 | LEADFRAME FOR SEMICONDUCTOR PACKAGE - A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness. | 2009-07-02 |
20090166843 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip including a first conducting element, and a second conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a first location. It further includes a third conducting element arranged outside the semiconductor chip and electrically connected to the first conducting element at a second location, and a fourth conducting element arranged outside the semiconductor chip. A vertical projection of the fourth conducting element on the chip crosses the first conducting element between the first location and the second location. | 2009-07-02 |
20090166844 | METAL COVER ON FLIP-CHIP MATRIX-ARRAY (FCMX) SUBSTRATE FOR LOW COST CPU ASSEMBLY - In some embodiments, a metal cover on flip-chip matrix-array (FCMX) substrate for low cost CPU assembly is presented. In this regard, an apparatus is introduced comprising a plurality of integrated circuit dice coupled with a substrate, a thermal interface material on top surfaces of the dice, and a metal plate on top of the thermal interface material on top of the dice. Other embodiments are also disclosed and claimed. | 2009-07-02 |
20090166845 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXTENDED CORNER LEADS - An integrated circuit package system including: forming a die pad, wherein the die pad has a tiebar at a corner; forming a lead wherein the lead is connected to the tiebar; connecting an integrated circuit die to the die pad; and forming an encapsulation, having an edge, over the integrated circuit die with the lead extending from and beyond the edge. | 2009-07-02 |
20090166846 | PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS - Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device. | 2009-07-02 |
20090166847 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package is provided. The semiconductor chip package comprises a package substrate having a first surface and a second surface opposite to the first surface. A through hole extends through the package substrate. A semiconductor chip is disposed on the first surface of the package substrate, wherein a bottom surface of the semiconductor chip covers one end of the through hole. At least two bonding fingers are disposed on the second surface of the package substrate and arranged on sides of the through hole. A conductive line is disposed on the second surface of the package substrate and between the two bonding fingers and the through hole, wherein two terminals of the conductive line are electrically connected to the two bonding fingers, respectively. | 2009-07-02 |
20090166848 | Method for Enhancing the Adhesion of a Passivation Layer on a Semiconductor Device - In a method for making a semiconductor component, an integrated circuit is provided with a chip pad on an active side. A conductive track is connected to the chip pad and a passivation layer covers the conductive track. Forming the conductive track includes structuring an uneven sidewall for form closure with the passivation layer. | 2009-07-02 |
20090166849 | SEMICONDUCTOR CHIP - A semiconductor chip includes a die mounted on a packaging substrate. The die includes a semiconductor substrate; inter-metal dielectric layers on the semiconductor substrate; levels of metal interconnection, wherein at least two potential equivalent metal traces are formed in a level of the metal interconnection; a passivation layer disposed over the two metal traces, wherein two openings are formed in the passivation layer to expose portions of the two metal traces; a conductive member externally mounted on the passivation layer between the two openings; and a redistribution layer formed over the conductive member. | 2009-07-02 |
20090166850 | High-Power Semiconductor Die Packages With Integrated Heat-Sink Capability and Methods of Manufacturing the Same - An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it. | 2009-07-02 |
20090166851 | Power semiconductor module - A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base. | 2009-07-02 |
20090166852 | SEMICONDUCTOR PACKAGES WITH THERMAL INTERFACE MATERIALS - A method comprises providing a layer of nano particles between a semiconductor die and a slug; and sintering the layer of nano particles to provide thermal interface material to bond the semiconductor die to a heat spreader formed by the slug. The sintering temperature of the nano particles is around 50° C. to around 200° C. | 2009-07-02 |
20090166853 | MULTI-LAYER STACKED WAFER LEVEL SEMICONDUCTOR PACKAGE MODULE - A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad. | 2009-07-02 |
20090166854 | Thermal Interface with Non-Tacky Surface - A thermal interface member includes a bulk layer and a surface layer that is disposed on at least a portion of a surface of the bulk layer. The surface layer is highly thermally conductive, has a melting point exceeding a solder reflow temperature, and has a maximum cross-sectional thickness of less than about 10 microns. | 2009-07-02 |
20090166855 | Cooling solutions for die-down integrated circuit packages - Systems for cooling the backside of a semiconductor die located in a die-down integrated circuit (IC) package are described. The IC package is attached to the topside of a printed circuit board (PCB) with the backside of the die residing below the topside surface of the PCB. A cooling plate is attached to the backside of the die and thermally connected to a heat sink located above the topside surface of the PCB via conduits that pass through openings in the PCB. | 2009-07-02 |
20090166856 | Semiconductor Device - A semiconductor device is provided whereby the signal interference among a plurality of function blocks is reduced. | 2009-07-02 |
20090166857 | Method and System for Providing an Aligned Semiconductor Assembly - A semiconductor assembly is provided that includes a first substrate that has a first surface. A second substrate is coupled to and spaced apart from the first substrate. The second substrate has a second surface facing the first surface of the first substrate. The second substrate includes a set of cavities. A set of non-conductive pillars is disposed on and protrudes from the first surface of the first substrate. The set of non-conductive pillars is configured and positioned to engage the set of cavities of the second substrate to align the second substrate with the first substrate. | 2009-07-02 |
20090166858 | LGA SUBSTRATE AND METHOD OF MAKING SAME - An LGA substrate includes a core ( | 2009-07-02 |
20090166859 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including a wafer having an electrode pad; an insulating layer that is formed on the wafer and has an exposure hole formed in one side thereof, the exposure layer exposing the electrode pad, and a support post formed in the other side, the support post having a buffer groove; a redistribution layer that is formed on the top surface of the insulating layer and has one end connected to the electrode pad and the other end extending to the support post; an encapsulation layer that is formed on the redistribution layer and the insulating layer and exposes the redistribution layer formed on the support post; and a solder bump that is provided on the exposed portion of the redistribution layer. | 2009-07-02 |
20090166860 | FLEXIBLE FILM AND DISPLAY DEVICE COMPRISING THE SAME - A flexible film is provided. The flexible film includes a dielectric film; and a metal layer disposed on the dielectric film, wherein the ratio of the thickness of the metal layer to the thickness of the dielectric film is about 1:3 to 1:10. Therefore, it is possible to improve the peel strength, dimension stability, and tensile strength of a flexible film by limiting the ratio of the thicknesses of a dielectric film and a metal layer of the flexible film. | 2009-07-02 |
20090166861 | WIRE BONDING OF ALUMINUM-FREE METALLIZATION LAYERS BY SURFACE CONDITIONING - In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond structure in test regions may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks in these device areas. Moreover, reliable wire bond connections may be obtained by providing a protection layer, such as an oxide layer, after exposing the respective contact metal, such as copper, nickel and the like, thereby providing highly uniform process conditions during the subsequent wire bonding process. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices. For example, nickel contact elements may be formed above copper-based contact areas wherein the nickel may provide a base for wire bonding or forming a bump material thereon. | 2009-07-02 |
20090166862 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including a wafer having an electrode pad; an insulation layer that is formed on the wafer and has an exposure hole exposing the electrode pad; a redistribution layer that is formed on the insulation layer and the exposure hole of the insulation layer and has one end connected to the electrode pad; a conductive post that is formed at the other end of the redistribution layer; an encapsulation layer that is formed on the redistribution layer and the insulation layer such that the upper end portion of the conductive post is exposed; and a solder bump that is formed on the exposed upper portion of the conducive post. | 2009-07-02 |
20090166863 | Semiconductor device and method of manufacturing the same - A semiconductor-device manufacturing method includes: forming terminals on a wafer and across each of dicing lines along which the wafer is cut into a plurality of semiconductor chips; preparing a plurality of pre-cut substrates each including a substrate body capable of being cut along corresponding one of cutting lines into a pair of same structured substrate pieces, connection pads provided on a top surface of the substrate body, and external terminals formed on a bottom surface of the substrate body and connected to the connection pads; mounting the pre-cut substrates onto the wafer while the cutting lines of the pre-cut substrates match the dicing lines; and simultaneously dicing the wafer and the pre-cut substrates along the dicing lines matching the cutting lines. | 2009-07-02 |
20090166864 | METHOD TO PREVENT COPPER MIGRATION IN A SEMICONDUCTOR PACKAGE - A semiconductor package comprises a semiconductor die, a substrate that is coupled to the die, a trace formed in the substrate that comprises a first conductive material, e.g., copper, doped with a second conductive material, e.g., aluminum, the first conductive material has a first diffusivity that is lower than a second diffusivity of the second conductive material to prevent migration of the first conductive material. | 2009-07-02 |
20090166865 | MANUFACTURABLE RELIABLE DIFFUSION-BARRIER - Devices and methods are presented to fabricate diffusion barrier layers on a substrate. Presently, barrier layers comprising a nitride layer and a pure metal layer are formed using a physical vapor deposition (PVD) process that requires multiple ignition steps, and results in nitride-layer thicknesses of no less than 2 nm. This invention discloses devices and process to produce nitride-layers of less than <1 nm, while allowing for formation of a pure metal layer on the nitride-layer without re-igniting the plasma. To achieve this, the flow of nitrogen gas is cut off either before the plasma is ignited, or before the formation of a continuous-flow plasma. This ensures that a limited number of nitrogen atoms is deposited in conjunction with metal atoms on the substrate, thereby allowing for controlled thickness of the nitride layer. | 2009-07-02 |
20090166866 | CONTACT METALLIZATION FOR SEMICONDUCTOR DEVICES - Methods for forming metal contacts to silicon substrates in semiconductor devices for contact diameters less than 60 nm and the devices formed from such processes are described. The methods includes the steps of pre-cleaning the silicon surface where the metal contact will be formed, depositing a silicide material and a sacrificial liner, forming the silicide material, removing or stripping the non-reacted portions of the silicide material non-reacted portions of the sacrificial liner, optionally performing an additional oxide clean, and depositing the liner and the metal for the contact. Such a process allows the formation of W contacts with dimension of 60 nm and below without a significant amount of defects. | 2009-07-02 |
20090166867 | METAL INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DEVICES - Cu interconnect structures using a bottomless liner to reduce the copper interfacial electron scattering and lower the electrical resistance are described in this application. The interconnect structures comprise a nucleation layer and a liner layer that may be formed by an oxide or nitride. The bottom portion of the liner layer is removed to expose the nucleation layer. Since the liner is bottomless, the nucleation layer is exposed during Cu deposition and serves to catalyze copper nucleation and enable selective growth of copper near the bottom (where the nucleation layer is exposed), rather than near the liner sidewalls. Thus, copper may be selectively grown with a bottom-up fill behavior than can reduce or eliminate formation of voids. Other embodiments are described. | 2009-07-02 |
20090166868 | Semiconductor devices including metal interconnections and methods of fabricating the same - A semiconductor device includes a first interlayer dielectric including a trench on a semiconductor layer, a mask pattern on the first interlayer dielectric, a first conductive pattern in the trench, and a second interlayer dielectric on the mask pattern. The second interlayer dielectric includes an opening over the first conductive pattern. A second conductive pattern is in the opening and is electrically connected to the first conductive pattern. The first conductive pattern has an upper surface lower than an upper surface of the mask pattern. | 2009-07-02 |
20090166869 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING METAL INTERCONNECTION LAYER THEREOF - Technologies related to forming metal lines of a semiconductor device are disclosed. A method of forming metal lines of a semiconductor device may include forming at least one interlayer insulating layer on a semiconductor substrate, forming via holes and trenches in the at least one interlayer insulating layer, forming an anti-diffusion film on the via holes and the trenches, depositing a seed Cu layer on the anti-diffusion film, after the seed Cu layer is deposited, depositing rhodium (Rh), and forming Cu line on the deposited Rh. The Rh improves an adhesive force between Cu layers and prevents oxide materials or a corrosion phenomenon from occurring on the seed Cu layer. Accordingly, occurrence of delamination in subsequent processes (for example, annealing and CMP) can be prevented or reduced. | 2009-07-02 |
20090166870 | METAL LINE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier has a multi-layered structure of a V layer, a V | 2009-07-02 |
20090166871 | METAL LINE OF SEMICONDUCTOR DEVICE WITHOUT PRODUCTION OF HIGH RESISTANCE COMPOUND DUE TO METAL DIFFUSION AND METHOD FOR FORMING THE SAME - A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WN | 2009-07-02 |
20090166872 | Memory Word lines with Interlaced Metal Layers - A memory device with improved word line structure is disclosed. The memory device includes a plurality of polysilicon strips substantially parallel to each other on the substrate, the plurality of polysilicon strips arranged in two interleaved groups of a first group and a second group. The memory device further includes a first layer of conductive strips forming a plurality of bit lines and a second layer of meal strips, the second layer of conductive strips overlying the polysilicon strips and coupled to the first group of polysilicon strips. In addition, the memory device includes a third layer of conductive strips forming one or more power line, and a fourth layer of metal strips, the fourth layer of conductive strips overlying the second layer of conductive strips and coupled to the second group of polysilicon strips to form a new word line structure having a low resistance. | 2009-07-02 |
20090166873 | INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF THE SAME - The interconnecting structure for a semiconductor die includes a die having bonding pads on an active surface; a core attached the side wall (edge) of the die by adhesion material; an isolating base adhered on the active surface of the die by adhesion glue; a through silicon via (TSV) open from the back side of the die to expose the bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via; solder balls melted on terminal pads, wherein the terminal pads located on the core and/or the die. | 2009-07-02 |
20090166874 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device and manufacturing method thereof are provided. The semiconductor device can include an interlayer dielectric layer on a substrate, a metal layer on the interlayer dielectric layer, and an impure anti-reflection film on the metal layer. The impure anti-reflection film can be formed through an in situ process. | 2009-07-02 |
20090166875 | METHODS FOR PREPARING AND DEVICES WITH TREATED DUMMY MOATS - Devices and methods are presented to fabricate dummy moats in an isolation region on a substrate. Presently, dummy moats are prone to losing impedance after the silicidation process. In high-voltage devices, silicided dummy moats reduce the breakdown voltage between active regions, particularly when the dummy moat overlaps or is in close proximity to a junction. The present devices and methods disclose a dummy moat covered with an oxide layer. During the silicidation process, the dummy moat and other designated isolation regions remain non-silicided. Thus, high and stable breakdown voltages are maintained. | 2009-07-02 |
20090166876 | SEMICONDUCTOR DEVICE AND DIE BONDING MATERIAL - In a semiconductor device bonded to a motherboard with a bonding material having a melting point of 200° C. to 230° C., a bonding material | 2009-07-02 |
20090166877 | ELECTRO-OPTIC DEVICE AND A METHOD FOR PRODUCING THE SAME - The present invention relates to a planar electro-optic device and a method for producing the same. The device comprises an embedded woven structure of conductive wires ( | 2009-07-02 |
20090166878 | Semiconductor Device and Method of Fabricating the Same - Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an interlayer dielectric film on a substrate, a plug in the interlayer dielectric film, a metal layer on the plug, and an impure anti-reflective coating (ARC) layer on the metal layer. | 2009-07-02 |
20090166879 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip, a package substrate, a first attaching member, a second attaching member, a connecting member and a molding member. The package substrate has a central region and an edge region. The first attaching member attaches the semiconductor chip to the central region of the package substrate. The second attaching member is arranged in the edge region of the package substrate. The second attaching member includes first attaching patterns extending in a first direction, and second attaching patterns extending in a second direction. The connecting member electrically connects the semiconductor chip to the package substrate. The molding member is attached to the package substrate using the second attaching member to molding the semiconductor chip. | 2009-07-02 |
20090166880 | ELECTRICAL BONDING PAD - An electrical bonding pad for an integrated circuit, comprising an encapsulation layer for receiving electrical signals and for covering a portion of a stack of conductive layers. The pad further comprises a conductive area in the stack, with the conductive area being at least partially covered by the encapsulation layer. The conductive area is intended for the passage of electrical signals received by the encapsulation layer and traveling towards a circuit core, and is electrically insulated from the encapsulation layer in a manner that at least partially decouples the electrical signals received from the encapsulation layer. | 2009-07-02 |
20090166881 | AIR-GAP ILD WITH UNLANDED VIAS - A spacer is adjacent to a conductive line. Vias that do not completely land on the conductive line land on the spacer and do not punch through into a volume below the spacer. | 2009-07-02 |
20090166882 | METHOD FOR FORMING METAL LINE IN SEMICONDUCTOR DEVICE - A method for forming a metal line in a semiconductor device includes patterning a part of a first interlayer insulating film over a semiconductor substrate to form a contact hole therein, depositing a first metal in the contact hole to form a metal contact plug, forming a second interlayer insulating film over a semiconductor substrate where the metal contact plug is formed, etching the second interlayer insulating film to form a trench, removing residual gases from the formation of the metal contact plug after the formation of the trench, and depositing a second metal in the trench to form a metal film connected to the metal contact plug. Accordingly, it is possible to avoid the etching of the contact plug by removing the residual gases such as carbon and fluorine, after the formation of a trench. | 2009-07-02 |
20090166883 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING IMPROVED POWER SUPPLY WIRING - In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply wire to the lower cell power-supply wire. The supplementary power-supply wire and the lower cell power-supply wire are connected by two vias. The supplementary power-supply wire and the upper power-supply wire are connected by a single via. Current from the supplementary power-supply wire is divided by the two vias and then supplied to the lower cell power-supply wire. Therefore, when power is supplied from the upper power-supply wire to the lower cell power-supply wire, current concentration at the connection points of the lower cell power-supply wire to the vias is decreased, thereby reducing wire breaks caused by EM (electro migration). | 2009-07-02 |
20090166884 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a semiconductor substrate having a conductive layer; an interlayer dielectric layer formed on the semiconductor substrate, the interlayer dielectric layer having a hole with a taper angled at the hole's upper portion; a diffusion barrier layer formed on the hole and the interlayer dielectric layer; and a seed layer formed on the diffusion barrier layer. | 2009-07-02 |
20090166885 | INTEGRATED CIRCUIT PACKAGE WITH IMPROVED CONNECTIONS - An integrated circuit package system comprising: providing an integrated circuit die; forming a top paddle over the integrated circuit die wherein the top paddle has planar dimensions smaller than planar dimensions of the integrated circuit die; forming leads adjacent the top paddle; attaching first connectors to the integrated circuit die and the top paddle; attaching second connectors to the integrated circuit die and the leads; and forming an encapsulant over the first connectors, the second connectors, the integrated circuit die, and the top paddle. | 2009-07-02 |