26th week of 2013 patent applcation highlights part 15 |
Patent application number | Title | Published |
20130161577 | Dielectric Fluids Compositions and Methods - Green compositions and technologies are provided. In an embodiment, the present invention provides a method of providing dielectric fluids, heat transfer fluids or cooling fluids. The dielectric fluid, heat transfer fluid, or cooling fluid can comprise one or more by-product or co-product containing glyceride and fatty acid mixtures extracted from an ethanol process. In an embodiment, the present invention provides compositions of dielectric fluids, heat transfer fluids or cooling fluids. The dielectric fluid, heat transfer fluid, or cooling fluid can comprise one or more glyceride and fatty acid mixtures extracted from an ethanol process. | 2013-06-27 |
20130161578 | ROOFING GRANULES WITH HIGH SOLAR REFLECTANCE, ROOFING MATERIALS WITH HIGH SOLAR REFLECTANCE, AND THE PROCESS OF MAKING THE SAME - Roofing granules include a core having an average ultraviolet transmission of greater than sixty percent and an average near infrared reflectance of greater than sixty percent and a UV coating layer on the exterior surface. The coating provides UV opacity, while the core provides near infrared reflectance. | 2013-06-27 |
20130161579 | REMOTE-PIVOTING METHOD AND TOOL FOR IMPLEMENTING SAME - A method and a tool for remotely pivoting an element mounted in a structure is provided. The method includes exerting a lever effect on the element by way of a control bearing on the structure coupled to a connection engaged with the element to cause it to pivot in a pivoting plane. The method also includes applying an angular offset to this connection in a plane different from the pivoting plane, in which the lever effect is produced, in order to render the control remotely operable. | 2013-06-27 |
20130161580 | Wildcat - A wildcat for a windlass for dropping down or hoisting an anchor for a marine vehicle, the anchor being coupled to an end of a chain ( | 2013-06-27 |
20130161581 | FLANGE SEPARATION APPARATUS - A flange separation apparatus includes a hydraulic cylinder and a movable member coupled with the hydraulic cylinder. The hydraulic cylinder includes an open end and a plurality of first spreading portions extended outwards from the open end. The movable member includes a movement portion and a plurality of second spreading portions connecting to the movement portion. The first and second spreading portions are perpendicular to the axis of the hydraulic cylinder and formed respectively varying first thickness and varying second thickness. As the hydraulic cylinder and movable member are parallel with the axis of flanges, operation space can be reduced. Moreover, through the first and second spreading portions, the flanges spaced from each other at different distances can be separated. | 2013-06-27 |
20130161582 | CONDUCTIVE BRIDGING MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a conductive bridging memory device includes a first wiring layer having a plurality of first wiring portions extending in a first direction, a second wiring layer having a plurality of second wiring portions extending in a second direction crossing the first direction, and a resistance change layer provided continuously along a plane having the first direction and the second direction between the first wiring layer and the second wiring layer. Each of the first wiring portions includes a first wiring extending in the first direction. Each of the second wiring portions includes a second wiring extending in the second direction, and an ion metal layer provided between the second wiring and the resistance change layer and extending in the second direction. | 2013-06-27 |
20130161583 | Stacked RRAM Array With Integrated Transistor Selector - The present invention provides a resistive memory array arranged in a 3D stack comprising a plurality of resistivity switching memory elements laid out in an array in a first and second direction, and stacked in a third direction, a plurality of first electrodes and a plurality of second electrodes extending in the first direction, each first electrode and each second electrode being associated with the at least one resistivity switching memory element, and a plurality of transistor devices, each transistor device being electrically coupled to one of the resistivity switching memory elements, an inversion or accumulation channel of a transistor device being adapted for forming a switchable resistivity path in the third direction, between the electrically coupled resistivity switching memory element and the associated second electrode, wherein the memory array furthermore comprises at least one third electrode provided in a trench through the stack. | 2013-06-27 |
20130161584 | Light Emitting Diode (LED) Using Three-Dimensional Gallium Nitride (GaN) Pillar Structures with Planar Surfaces - A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer. | 2013-06-27 |
20130161585 | LIGHT EMITTING DEVICE - A light emitting device is disclosed. The light emitting device includes a light emitting structure including a first conductive-type semiconductor layer, an active layer, and a second conductive-type semiconductor layer, a light-transmissive conductive layer disposed on the second conductive-type semiconductor layer and having a plurality of open regions through which the second conductive-type semiconductor layer is exposed, and a second electrode disposed on the light-transmissive conductive layer so as to extend beyond at least one of the open regions, wherein the second electrode contacts the second conductive-type semiconductor layer in the open regions and contacts the light-transmissive conductive layer in regions excluding the open regions. | 2013-06-27 |
20130161586 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND PRODUCTION METHOD THEREFOR - The present invention provides a Group III nitride semiconductor light-emitting device which is intended to relax stress applied to a light-emitting layer. The light-emitting device includes an MQW layer, and an n-side superlattice layer formed below the MQW layer. The n-side superlattice layer is formed by repeatedly depositing layer units, each unit including an InGaN layer, a GaN layer, and an n-GaN layer which are sequentially deposited from the side of the sapphire substrate. In the n-side superlattice layer, an InGaN layer more proximal to the MQW layer has a higher In compositional proportion. The In compositional proportion of the InGaN layer (which is most proximal to the MQW layer) of the n-side superlattice layer is 70% to 100% of the In compositional proportion of the InGaN layer (which is most proximal to the n-side superlattice layer) of the MQW layer. | 2013-06-27 |
20130161587 | GRAPHENE DEVICES AND METHODS OF MANUFACTURING THE SAME - A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating layer may be on the capping layer to cover the region of the channel layer, and a gate may be on the gate insulating layer. | 2013-06-27 |
20130161588 | Implant Free Quantum Well Transistor, Method for Making Such an Implant Free Quantum Well Transistor and Use of Such an Implant Free Quantum Well Transistor - An implant free quantum well transistor wherein the doped region comprises an implant region having an increased concentration of dopants with respect to the concentration of dopants of adjacent regions of the substrate, the implant region being substantially positioned at a side of the quantum well region opposing the gate region. | 2013-06-27 |
20130161589 | ORGANIC SEMICONDUCTOR TRANSISTOR - Provided is an organic semiconductor transistor including plural electrodes, and an organic semiconductor layer containing at least one fluorene compound represented by the following formula (I): | 2013-06-27 |
20130161590 | ORGANIC LIGHT EMITTING DEVICE WITH ENHANCED LIFESPAN - An organic light emitting device, and a manufacturing method of the same, in which in a light emitting layer, an electron trap material is introduced so as to improve a light emitting property and an operating characteristic and to prolong a life span. | 2013-06-27 |
20130161591 | MATERIAL FOR ORGANIC ELECTROLUMINESCENT ELEMENT, AND ORGANIC ELECTROLUMINESCENT ELEMENT - A material for an organic electroluminescence device including at least one of compounds shown by the following formula (Ia), (Ib), (IIa), (IIb), (III), (IVa) or (IVb): | 2013-06-27 |
20130161592 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An OLED device is discussed which includes: a drive thin film transistor formed on a substrate; an organic light emitting diode configured with first electrode, a light emission layer and a second electrode which are sequentially formed on the substrate provided with the drive thin film transistor; a barrier film disposed on the substrate with the organic light emitting element and configure to include a retardation film, an optically isotropic film and a thin layer interposed between the retardation film and the optically isotropic film; and a polarizing plate disposed on the barrier film and configured to prevent reflection of external light. | 2013-06-27 |
20130161593 | Light-Emitting Element, Light-Emitting Device, and Electronic Device - A light-emitting element includes a first electrode, a first light-emitting layer formed over the first electrode, a second light-emitting layer formed on and in contact with the first light-emitting layer to be in contact therewith, and a second electrode formed over the second light-emitting layer. The first light-emitting layer includes a first light-emitting substance and a hole-transporting organic compound, and the second light-emitting layer includes a second light-emitting substance and an electron-transporting organic compound. Substances are selected such that a difference in LUMO levels between the first light-emitting substance, the second light-emitting substance, and the electron-transporting organic compound is 0.2 eV or less, a difference in HOMO levels between the hole-transporting organic compound, the first light-emitting substance, and the second light-emitting substance is 0.2 eV or less, and a difference in LUMO levels between the hole-transporting organic compound and the first light-emitting substance is greater than 0.3 eV. | 2013-06-27 |
20130161594 | CONDUCTING FORMULATION - The invention relates to novel formulations comprising an organic semiconductor (OSC) and a conductive additive, to their use as conducting inks for the preparation of organic electronic (OE) devices, especially organic photovoltaic (OPV) cells, to methods for preparing OE devices using the novel formulations, and to OE devices and OPV cells prepared from such methods and formulations. | 2013-06-27 |
20130161595 | Organic Light Emitting Display Device and Method of Manufacturing the Same - Provided are a method of manufacturing an organic light emitting display device and an organic light emitting display device manufactured by the method. The method includes calculating a peak-luminance current density for each of a red sub-pixel, a blue sub-pixel, a green sub-pixel, and a white sub-pixel, calculating an average use current density for each of the red sub-pixel, blue sub-pixel, green sub-pixel, and white sub-pixel; determining a size of each sub-pixel with the peak-luminance current density and the average use current density, and forming the sub-pixels with the determined sizes of the respective sub-pixels. The present invention sets the size of each sub-pixel in consideration of a peak-luminance current density and an average use current density, thus easily achieving the peak luminance and enhancing the color-coordinate life. | 2013-06-27 |
20130161596 | PHOTOVOLTAIC DEVICE - An apparatus includes a substrate; and a photoactive layer disposed on the substrate. The photoactive layer includes an electron acceptor material; an electron donor material; and a material having dipoles. | 2013-06-27 |
20130161597 | METHOD OF INCORPORATING A BLACK PHOTO STRIPE OVER PARYLENE LAYER - A method of incorporating a structurally integrated black photo stripe over an OLED based light blocking means by sandwiching the black photo stripe between two layers of polymeric layers, above the OLED stack, seal and RGB color filter layer. | 2013-06-27 |
20130161598 | Iridium Complex, Light-Emitting Element, Light-Emitting Device, Electronic Device, and Lighting Device - A tris-type iridium complex in which a ligand having a distinctive nitrogen-containing five-membered heterocyclic skeleton is coordinated is provided. The ligand has a nitrogen-containing five-membered heterocyclic skeleton composed of 2 to 4 nitrogen atoms and one or more carbon atoms. In the skeleton, an aryl group is bonded to a carbon atom on both sides of which nitrogen atoms are positioned, and a tricycloalkyl group having a bridge structure and having 9 or 10 carbon atoms is bonded to one of the two nitrogen atoms positioned on both the sides of the carbon atom. The tricycloalkyl group having a bridge structure and having 9 or 10 carbon atoms may be an adamantyl group or a noradamantyl group. | 2013-06-27 |
20130161599 | ELECTRO-CHEMICAL SENSORS, SENSOR ARRAYS AND CIRCUITS - An electro-chemical sensor includes a first electrode, a second electrode spaced apart from the first electrode, and a semiconductor channel in electrical contact with the first and second electrodes. The semiconductor channel includes a trapping material. The trapping material reduces an ability of the semiconductor channel to conduct a current of charge carriers by trapping at least some of the charge carriers to localized regions within the semiconductor channel. The semiconductor channel includes at least a portion configured to be exposed to an analyte to be detected, and the trapping material, when exposed to the analyte, interacts with the analyte so as to at least partially restore the ability of the semiconductor channel to conduct the current of charge carriers. | 2013-06-27 |
20130161600 | FORMATION OF CONJUGATED POLYMERS FOR SOLID-STATE DEVICES - Disclosed herein is a facile process for the formation of conjugated polymers inside or outside assembled solid-state devices. One process generally involves applying a voltage to a device comprising at least two electrodes, a combination of an electrolyte composition and a electroactive monomer disposed between the electrodes, and a potential source in electrical connection with the at least two electrodes; wherein the applying voltage polymerizes the electroactive monomer into a conjugated polymer. Also disclosed are electrochromic articles prepared from the process and solid-state devices comprising a composite of an electrolyte composition and a conjugated polymer. | 2013-06-27 |
20130161601 | Light-Emitting Element, Light-Emitting Device, and Electronic Device - It is an object of the present invention to provide a light-emitting element with high light emission efficiency. It is another object of the present invention to provide a light-emitting element with a long lifetime. A light-emitting device is provided, which includes a light-emitting layer, a first layer, and a second layer between first electrode and a second electrode, wherein the first layer is provided between the light-emitting layer and the first electrode, the second layer is provided between the light-emitting layer and the second electrode, the first layer is a layer for controlling the hole transport, the second layer is a layer for controlling the electron transport, and a light emission from the light-emitting layer is obtained when voltage is applied to the first electrode and the second electrode so that potential of the first electrode is higher than potential of the second electrode. | 2013-06-27 |
20130161602 | PROCESS FOR MODIFYING ELECTRODES IN AN ORGANIC ELECTRONIC DEVICE - The present invention relates to a process for modifying the electrodes in an organic electronic (OE) device, in particular an organic field effect transistor (OFET), and to an OE device prepared by using such a process. | 2013-06-27 |
20130161603 | PHOSPHAPHENANTHRENE-CARBAZOLE-BASED ORGANIC LIGHT-EMITTING COMPOUND, AND ORGANIC LIGHT-EMITTING DEVICE COMPRISING SAME - Provided are a phosphaphenanthrene-carbazole-based organic light-emitting compound having superior light emitting properties, and an organic light-emitting device including the same. | 2013-06-27 |
20130161604 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A pixel structure and a manufacturing method thereof are provided. The pixel structure includes a substrate, a scan line, a data line, a first insulating layer, an active device, a second insulating layer, a common electrode and a first pixel electrode. The data line crossed to the scan line is disposed on the substrate and includes a linear transmitting part and a cross-line transmitting part. The first insulating layer covering the scan line and the linear transmitting part is disposed between the scan line and the cross-line transmitting part. The active device, including a gate, an oxide channel, a source and a drain, is connected to the scan line and the data line. The second insulating layer is disposed on the oxide channel and the linear transmitting part. The common electrode is disposed above the linear transmitting part. The first pixel electrode is connected to the drain. | 2013-06-27 |
20130161605 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof was devised. In addition, the portions of the source electrode and the drain electrode which are proximate to the channel formation region are formed in a later step than the other portions thereof, whereby a bottom-gate transistor with a short channel length can be manufactured. | 2013-06-27 |
20130161606 | SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING THE SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTOR ELEMENT - A structure including an oxide semiconductor layer which is provided over an insulating surface and includes a channel formation region and a pair of low-resistance regions between which the channel formation region is positioned, a gate insulating film covering a top surface and a side surface of the oxide semiconductor layer, a gate electrode covering a top surface and a side surface of the channel formation region with the gate insulating film positioned therebetween, and electrodes electrically connected to the low-resistance regions is employed. The electrodes are electrically connected to at least side surfaces of the low-resistance regions, so that contact resistance with the source electrode and the drain electrode is reduced. | 2013-06-27 |
20130161607 | SEMICONDUCTOR DEVICE - A semiconductor device with high productivity and high yield is provided. The semiconductor device includes a word line, a capacitor line, a first bit line, a second bit line, and a first transistor and a second transistor each of which includes a gate, a source, and a drain. The first transistor and the second transistor at least partly overlap with each other, and the gates of the first transistor and the second transistor are connected to the word line. A capacitor is formed between at least part of the capacitor line and each of the drains of the first transistor and the second transistor. The first bit line is connected to the source of the first transistor, and the second bit line is connected to the source of the second transistor. | 2013-06-27 |
20130161608 | SEMICONDUCTOR DEVICE - Provided is a transistor which includes an oxide semiconductor film and has stable electrical characteristics. In the transistor, over an oxide film which can release oxygen by being heated, a first oxide semiconductor film which can suppress oxygen release at least from the oxide film is formed. Over the first oxide semiconductor film, a second oxide semiconductor film is formed. With such a structure in which the oxide semiconductor films are stacked, the oxygen release from the oxide film can be suppressed at the time of the formation of the second oxide semiconductor film, and oxygen can be released from the oxide film in later-performed heat treatment. Thus, oxygen can pass through the first oxide semiconductor film to be favorably supplied to the second oxide semiconductor film. Oxygen supplied to the second oxide semiconductor film can suppress the generation of oxygen deficiency, resulting in stable electrical characteristics. | 2013-06-27 |
20130161609 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The number of manufacturing steps is reduced to provide a semiconductor device with high productivity and low cost. A semiconductor device with low power consumption and high reliability is provided. A photolithography process for forming an island-shaped semiconductor layer is omitted, and a semiconductor device is manufactured through at least four photolithography processes: a step for forming a gate electrode (including a wiring or the like formed from the same layer), a step for forming a source electrode and a drain electrode (including a wiring or the like formed from the same layer), a step for forming a contact hole, and a step for forming a pixel electrode. In the step for forming the contact hole, a groove portion is formed, whereby formation of a parasitic transistor is prevented. The groove portion overlaps with the wiring with an insulating layer provided therebetween. | 2013-06-27 |
20130161610 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A highly reliable semiconductor device which includes a transistor including an oxide semiconductor is provided. In a semiconductor device including a bottom-gate transistor including an oxide semiconductor layer, a stacked layer of an insulating layer and a metal film is provided in contact with the oxide semiconductor layer. Oxygen doping treatment is performed in a manner such that oxygen is introduced into the insulating layer and the metal film from a position above the metal film. Thus, a region containing oxygen in excess of the stoichiometric composition is formed in the insulating layer, and the metal film is oxidized to form a metal oxide film. Further, resistivity of the metal oxide film is greater than or equal to 1×10 | 2013-06-27 |
20130161611 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Release of oxygen at a side surface of an island-shaped oxide semiconductor film is controlled and decrease in resistance is prevented. A semiconductor device includes an island-shaped oxide semiconductor film at least partly including a crystal, a first gate insulating film provided to cover at least a side surface of the island-shaped oxide semiconductor film, and a second gate insulating film provided to cover at least the island-shaped oxide semiconductor film and the first gate insulating film. The first gate insulating film is an insulating film that supplies oxygen to the island-shaped oxide semiconductor film, and the second gate insulating film is an insulating film which has a low oxygen-transmitting property | 2013-06-27 |
20130161612 | DISPLAY DEVICE AND IMAGE DISPLAY SYSTEM EMPLOYING THE SAME - A display device and an image display system employing the same are provided. The display device includes a thin film transistor and a storage capacitor. The thin film transistor includes a channel. The storage capacitor includes a transparent metal electrode made of the same material as the channel, and a pixel electrode disposed on the transparent metal electrode electrically connected to the thin film transistor. | 2013-06-27 |
20130161613 | Ultraviolet Sensor and Method for Manufacturing the Same - An ultraviolet sensor that includes a p-type semiconductor layer principally composed of (Ni, Zn)O, an n-type semiconductor layer composed of ZnO which is joined to the p-type semiconductor layer, an internal electrode embedded in the p-type semiconductor layer, and first and second terminal electrodes formed at both ends of the p-type semiconductor layer. The surface roughness of the p-type semiconductor layer is 1.5 μm or less, and preferably 0.3 μm or more and 1.0 μm or less. In a manufacturing process, the formed product prior to firing and/or the p-type semiconductor layer after firing is polished by barrel polishing so that the surface roughness Ra thereof is 1.0 μm or less. Thereby, light absorption efficiency can be improved to directly detect a desired large photocurrent and secure high reliability, and a spectral property can be controlled to strongly respond to various wavelength bands of ultraviolet light. | 2013-06-27 |
20130161614 | NANOSTRUCTURED FILMS AND RELATED METHODS - Nanostructured films including a plurality of nanowells, the nanowells having a pore at the top surface of the film, the pore defining a channel that extends downwardly towards the bottom surface of the film are provided. Also provided are methods including exposing a growth substrate to an anodizing bath, applying ultrasonic vibrations to the anodizing bath, and generating a current through the anodizing bath to form the nanostructured film. The nanostructured films may be formed from TiO | 2013-06-27 |
20130161615 | MEASURING CURRENT AND RESISTANCE USING COMBINED DIODES/RESISTOR STRUCTURE TO MONITOR INTEGRATED CIRCUIT MANUFACTURING PROCESS VARIATIONS - A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure. | 2013-06-27 |
20130161616 | Substrate for Chip on Film - The present invention discloses a substrate including a flexible film, a plurality of sprocket holes disposed along a first direction on two sides of the flexible film, and a plurality of first chip zones disposed along the first direction on the flexible film, of which each first chip zone includes at least a testing module, an input module, a chip and an output module disposed along a second direction, where the first direction is orthogonal to the second direction. | 2013-06-27 |
20130161617 | METHOD FOR MEASURING IMPURITY CONCENTRATION PROFILE, WAFER USED FOR SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SAME - According to an embodiment, a method for measuring an impurity concentration profile uses a wafer including a semiconductor layer. The method includes measuring an impurity concentration profile in a depth direction from each surface of a plurality of first portions, each of the first portions being included in any one of a plurality of first regions provided in the semiconductor layer. Each of the first regions has a different size and is surrounded by a second region including a second portion having a different structure from the first portion. The method includes determining a change between the impurity concentration profiles measured in the first regions. | 2013-06-27 |
20130161618 | SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure. | 2013-06-27 |
20130161619 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A silicon carbide substrate includes: an n type drift layer having a first surface and a second surface opposite to each other; a p type body region provided in the first surface of the n type drift layer; and an n type emitter region provided on the p type body region and separated from the n type drift layer by the p type body region. A gate insulating film is provided on the p type body region so as to connect the n type drift layer and the n type emitter region to each other. A p type Si collector layer is directly provided on the silicon carbide substrate to face the second surface of the n type drift layer. | 2013-06-27 |
20130161620 | COMPOSITION FOR AN OXIDE THIN FILM, A PREPARATION METHOD OF THE COMPOSITION, A METHOD FOR FORMING AN OXIDE THIN FILM USING THE COMPOSITION, AN ELECTRONIC DEVICE INCLUDING THE OXIDE THIN FILM, AND A SEMICONDUCTOR DEVICE INCLUDING THE OXIDE THIN FILM - Provided are a composition for an oxide thin film, a preparation method of the composition, a method for forming an oxide thin film using the composition, an electronic device including the oxide thin film, and a semiconductor device including the oxide thin film. The composition for the oxide thin film includes a metal precursor and nitric acid-based stabilizer. The metal precursor includes at least one of a metal nitrate, a metal nitride, and hydrates thereof. | 2013-06-27 |
20130161621 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed. | 2013-06-27 |
20130161622 | THIN FILM TRANSISTOR SUBSTRATE MANUFACTURING METHOD THEREOF, DISPLAY - An embodiment of the invention provides a manufacturing method of a thin film transistor substrate including: sequentially forming a gate electrode, a gate insulating layer covering the gate electrode, an active material layer, and a photo-sensitive material layer on a first substrate; performing a photolithography process by using a half tone mask to form a photo-sensitive protective layer which is above the gate electrode and has a first recess and a second recess; etching the active material layer by using the photo-sensitive protective layer as a mask to form an active layer; removing a portion of the photo-sensitive protective layer at bottoms of the first recess and the second recess to expose a first portion and a second portion of the active layer respectively; forming a first electrode connecting to the first portion; and forming a second electrode connecting to the second portion. | 2013-06-27 |
20130161623 | SEMICONDUCTOR DEVICE - The present invention intends to realize a narrow flame of a system on panel. In addition to this, a system mounted on a panel is intended to make higher and more versatile in the functionality. In the invention, on a panel on which a pixel portion (including a liquid crystal element, a light-emitting element) and a driving circuit are formed, integrated circuits that have so far constituted an external circuit are laminated and formed. Specifically, of the pixel portion and the driving circuit on the panel, on a position that overlaps with the driving circuit, any one kind or a plurality of kinds of the integrated circuits is formed by laminating according to a transcription technique. | 2013-06-27 |
20130161624 | DISPLAY DEVICE - The present invention relates to a display device, which includes a substrate; a first conductive layer disposed on the substrate and including a first terminal; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer and including a second terminal; a second insulating layer disposed on the second conductive layer; a profile relieving member disposed on the second insulating layer; and a contact assistant disposed on the profile relieving member, in which the profile relieving member covers a portion of an edge of at least one of the first terminal and the second terminal. | 2013-06-27 |
20130161625 | ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer. | 2013-06-27 |
20130161626 | ARRAY SUBSTRATE FOR FLAT DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - Embodiments relate to an array substrate for a flat display device and a method of fabricating the same for reducing an over etch at a portion of the substrate where a data line is applied in a diagonal shape during the etching of the data line. As a result, disconnection of the data line may be reduced, which in turn reduces the failure rate of the flat display devices and enhances process yield. | 2013-06-27 |
20130161627 | PHOTOELECTRIC CONVERSION APPARATUS, IMAGING APPARATUS USING THE SAME, AND MANUFACTURING METHOD THEREOF - A photoelectric conversion apparatus includes: an active matrix-type TFT array substrate on which photoelectric conversion elements and thin film transistors are arranged in a matrix shape, wherein the photoelectric conversion element connects with a drain electrode via a contact hole opened through a first interlayer insulation film provided above the thin film transistor, wherein a data line and a bias line are connected with the source electrode and the photoelectric conversion element via respective contact holes opened through the second interlayer insulation, and wherein at least a part of the photoelectric conversion element is fixed to have a shape different from a normal pixel between pixels adjacent to each other in an extending direction of the gate line, and an electrical connection between the photoelectric conversion element and the data line is cut off in the transistor of the pixel having the different shape. | 2013-06-27 |
20130161628 | FLEXIBLE SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, IMAGE DISPLAY DEVICE USING THE SAME AND METHOD FOR MANUFACTURING THE IMAGE DISPLAY DEVICE - There is provided a method for manufacturing a flexible semiconductor device. The manufacturing method of the flexible semiconductor device of the present invention comprising the steps of: forming a gate electrode; forming a gate insulating film so that the gate insulating film contacts with the gate electrode; forming a semiconductor layer on the gate insulating film such that the semiconductor layer is opposed to the gate electrode; forming source and drain electrodes so that the source and drain electrodes contact with the semiconductor layer; forming a flexible film layer so that the flexible film layer covers the semiconductor layer and the source and drain electrodes; forming vias in the flexible film layer; forming a first metal layer by disposing a metal foil onto the flexible film layer, and thereby a semiconductor device precursor is provided; and subjecting the first metal layer to a processing treatment to form a wiring from a part of the first metal layer, wherein, in the step of the processing treatment of the first metal layer, the wiring is formed in a predetermined position by using at least one of the vias as an alignment marker. | 2013-06-27 |
20130161629 | ZERO SHRINKAGE SMOOTH INTERFACE OXY-NITRIDE AND OXY-AMORPHOUS-SILICON STACKS FOR 3D MEMORY VERTICAL GATE APPLICATION - Methods are provided for depositing a stack of film layers for use in vertical gates for 3D memory devices, by depositing a sacrificial nitride film layer at a sacrificial film deposition temperature greater than about 550° C.; depositing an oxide film layer over the nitride film layer, at an oxide deposition temperature of about 600° C. or greater; repeating the above steps to deposit a film stack having alternating layers of the sacrificial films and the oxide films; forming a plurality of holes in the film stack; and depositing polysilicon in the plurality of holes in the film stack at a polysilicon process temperature of about 700° C. or greater, wherein the sacrificial film layers and the oxide film layers experience near zero shrinkage during the polysilicon deposition. Flash drive memory devices may also be made by these methods. | 2013-06-27 |
20130161630 | THIN-FILM SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THIN-FILM SEMICONDUCTOR DEVICE - A method for fabricating a thin-film semiconductor device according to the present disclosure includes: preparing a glass substrate; forming, above the glass substrate, an undercoat layer including a nitride film; forming a barrier layer above the undercoat layer; forming a molybdenum metal layer above the barrier layer; forming a gate electrode from the molybdenum metal layer; forming a gate insulating film above the gate electrode; forming a non-crystalline silicon layer as a non-crystalline semiconductor layer above the gate insulating film; forming a polycrystalline semiconductor layer including a polysilicon layer by annealing the non-crystalline silicon layer using a continuous-wave (CW) laser, the non-crystalline silicon layer being crystallized by the annealing; and forming a source electrode and a drain electrode above the polysilicon layer. Part of the barrier layer changes into a layer including oxygen atoms as a major component by the annealing when forming the polysilicon layer. | 2013-06-27 |
20130161631 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device and method for manufacturing the same are discussed. The display device according to an embodiment includes a substrate, a gate metal line disposed on the substrate, a gate insulating film configured to insulate the gate metal line, a data metal line disposed on the gate insulating film, and a protection film disposed at an area where the gate metal line and the data metal line overlap each other between the gate metal line and the data metal line. | 2013-06-27 |
20130161632 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - An OLED apparatus including a thin film transistor including an activation layer, a gate electrode insulated from the activation layer and including a lower gate electrode and an upper gate electrode, an interlayer insulation film covering the gate electrode, and a source and drain electrode on the insulation film and contacting the activation layer; an OLED including a pixel electrode electrically connected to the thin film transistor, an intermediate layer including an emissive layer, and an opposite electrode; a blister prevention layer on a same level as the activation layer; a gate insulation layer covering the activation layer and the blister prevention layer and insulating the activation layer from the gate electrode; and an interconnection unit including first and second layers on a portion of the gate insulation layer overlying the blister prevention layer, wherein the blister prevention layer protects the interconnection unit on the gate insulation layer from blistering. | 2013-06-27 |
20130161633 | METHOD AND SYSTEM FOR JUNCTION TERMINATION IN GAN MATERIALS USING CONDUCTIVITY MODULATION - A semiconductor structure includes a GaN substrate having a first surface and a second surface opposing the first surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a first GaN epitaxial layer of the first conductivity type coupled to the second surface of the GaN substrate and a second GaN epitaxial layer of a second conductivity type coupled to the first GaN epitaxial layer. The second GaN epitaxial layer includes an active device region, a first junction termination region characterized by an implantation region having a first implantation profile, and a second junction termination region characterized by an implantation region having a second implantation profile. | 2013-06-27 |
20130161634 | METHOD AND SYSTEM FOR FABRICATING EDGE TERMINATION STRUCTURES IN GAN MATERIALS - A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure. | 2013-06-27 |
20130161635 | METHOD AND SYSTEM FOR A GAN SELF-ALIGNED VERTICAL MESFET - A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region. | 2013-06-27 |
20130161636 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES USING THERMAL SPRAY PROCESSES, AND SEMICONDUCTOR STRUCTURES FABRICATED USING SUCH METHODS - Methods for fabricating a semiconductor substrate include forming a first substrate layer over a surface of a first semiconductor layer, and thermally spraying a second substrate layer on a side of the first substrate layer opposite the first semiconductor layer. At least one additional semiconductor layer is epitaxially grown over the first semiconductor layer on a side thereof opposite the first substrate layer. At least one of the first substrate layer and the second substrate layer may be formulated to exhibit a Coefficient of Thermal Expansion (CTE) closely matching a CTE of at least one of the first semiconductor layer and the at least one additional semiconductor layer. Semiconductor structures are fabricated using such methods. | 2013-06-27 |
20130161637 | SEMICONDUCTOR DEVICES INCLUDING SUBSTRATE LAYERS AND OVERLYING SEMICONDUCTOR LAYERS HAVING CLOSELY MATCHING COEFFICIENTS OF THERMAL EXPANSION, AND RELATED METHODS - Embodiments relate to semiconductor structures and methods of forming semiconductor structures. The semiconductor structures include a substrate layer having a CTE that closely matches a CTE of one or more layers of semiconductor material formed over the substrate layer. In some embodiments, the substrate layers may comprise a composite substrate material including two or more elements. The substrate layers may comprise a metal material and/or a ceramic material in some embodiments. | 2013-06-27 |
20130161638 | HIGH ELECTRON MOBILITY TRANSISTOR STRUCTURE WITH IMPROVED BREAKDOWN VOLTAGE PERFORMANCE - A HEMT includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer, and a passivation material layer having one or more buried portions contacting or almost contacting the UID GaN layer. A carrier channel layer at the interface of the donor-supply layer and the UID GaN layer has patches of non-conduction in a drift region between the gate and the drain. A method for making the HEMT is also provided. | 2013-06-27 |
20130161639 | DRAIN INDUCED BARRIER LOWERING WITH ANTI-PUNCH-THROUGH IMPLANT - An integrated circuit containing an MOS transistor with epitaxial source and drain regions may be formed by implanting a retrograde anti-punch-through layer prior to etching the source drain regions for epitaxial replacement. The anti-punch-through layer is disposed between stressor tips of the epitaxial source and drain regions, and does not substantially extend into the epitaxial source and drain regions. | 2013-06-27 |
20130161640 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device is provided that prevents development of cracks, that has nitride semiconductor thin films with uniform thicknesses and good growth surface flatness, and is thus consistent in characteristics, and that can be fabricated at a satisfactory yield. In this nitride semiconductor device, the nitride semiconductor thin films are grown on a substrate having an off-angle between a direction normal to the surface of ridges and the crystal direction <0001>. This helps either reduce or intentionally promote diffusion or movement of the atoms or molecules of a source material of the nitride semiconductor thin films through migration thereof. As a result, a nitride semiconductor growth layer with good surface flatness can be formed, and thus a nitride semiconductor device with satisfactory characteristics can be obtained. | 2013-06-27 |
20130161641 | TRANSISTOR WITH ENHANCED CHANNEL CHARGE INDUCING MATERIAL LAYER AND THRESHOLD VOLTAGE CONTROL - High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region. | 2013-06-27 |
20130161642 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises an SOI substrate; a semiconductor fin formed on the SOI substrate, the semiconductor fin having a first side and a second side which are opposite to each other and stand upward on a surface of the SOI substrate, and a trench which is opened at a central portion of the second side and opposite to the first side; a channel region formed in the fin and being between the first side and the trench at the second side; source and drain regions formed in the fin and sandwiching the channel region; and a gate stack formed on the SOI substrate and being adjacent to the first side of the fin, wherein the gate stack comprises a first gate dielectric extending away from the first side and being adjacent to the channel region, a first conductor layer extending away from the first side and being adjacent to the first gate dielectric, a second gate dielectric extending away from the first side and being adjacent laterally to one side of the first conductor layer, and a second conductor layer extending away from the first side and being adjacent laterally to one side of the second gate dielectric. The embodiments of the invention can be applied in manufacturing an FinFET. | 2013-06-27 |
20130161643 | Method for Fabricating Three-Dimensional Gallium Nitride Structures with Planar Surfaces - A method is provided for fabricating three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. After providing a substrate, the method grows a GaN film overlying a top surface of the substrate and forms cavities in a top surface of the GaN film. The cavities are formed using a laser ablation, ion implantation, sand blasting, or dry etching process. The cavities in the GaN film top surface are then wet etched, forming planar sidewalls extending into the GaN film. More explicitly, the cavities are formed into a c-plane GaN film top surface, and the planar sidewalls are formed perpendicular to a c-plane, in the m-plane or a-plane family. | 2013-06-27 |
20130161644 | SEMICONDUCTOR MODULE - Provided is a semiconductor module having high inrush-current tolerance. A semiconductor module includes a switching element formed of a wide bandgap semiconductor, and a free wheel diode connected in antiparallel with the switching element, wherein the free wheel diode is made of silicon and has negative temperature characteristics. | 2013-06-27 |
20130161645 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a principal surface, and an insulating film formed on the principal surface and continuously covering a top surface of a first boundary region and a top surface of a second boundary region, the first boundary region including a boundary between a well layer and a RESURF layer, the second boundary region including a boundary between the RESURF layer and a first impurity region. The semiconductor device further includes a plurality of lower field plates formed in the insulating film in such a manner that the plurality of lower field plates do not lie directly above the first and second boundary regions, and a plurality of upper field plates formed on the insulating film in such a manner that the plurality of upper field plates do not lie directly above the first and second boundary regions. | 2013-06-27 |
20130161646 | SEMICONDUCTOR SUBSTRATE - A semiconductor substrate has a main surface and formed of single crystal silicon carbide. The main surface includes a central area, which is an area other than the area within 5 mm from the outer circumference. When the central area is divided into square areas of 1 mm×1 mm, in any square area, density of dislocations of which Burgers vector is parallel to <0001> direction is at most 1×10 | 2013-06-27 |
20130161647 | INGOT, SUBSTRATE, AND SUBSTRATE GROUP - An ingot, a substrate, and a substrate group are obtained each of which is made of silicon carbide and is capable of suppressing variation of characteristics of semiconductor devices. The ingot is made of single-crystal silicon carbide, and has p type impurity. The ingot has a thickness of 10 mm or greater in a growth direction thereof. Further, the ingot has an average carrier density of 1×10 | 2013-06-27 |
20130161648 | Diamond Semiconductor System and Method - Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer. | 2013-06-27 |
20130161649 | STRUCTURE AND METHOD FOR INCREASING STRAIN IN A DEVICE - A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device having a source region and a drain region, the NFET CMOS including: an n-type doped layer in at least one of the source region and the drain region, wherein the n-type doped layer includes substitutional carbon and has a memorized tensile stress induced by a stress memorization technique (SMT). | 2013-06-27 |
20130161650 | DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME - A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. | 2013-06-27 |
20130161651 | LOW 1C SCREW DISLOCATION 3 INCH SILICON CARBIDE WAFER - A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1 c screw dislocation density from about 500 cm | 2013-06-27 |
20130161652 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) includes a substrate, a buffer layer and an epitaxial structure. The substrate has a first surface with a patterning structure formed thereon. The patterning structure includes a plurality of projections. The buffer layer is arranged on the first surface of the substrate. The epitaxial structure is arranged on the buffer layer. The epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer arranged on the buffer layer in sequence. The first semiconductor layer has a second surface attached to the active layer. A distance between a peak of each the projections and the second surface of the first semiconductor layer is ranged from 0.5 μm to 2.5 μm. | 2013-06-27 |
20130161653 | ELECTROLUMINESCENCE DEVICE USING INDIRECT BANDGAP SEMICONDUCTOR - This invention provides an electroluminescence device comprising an indirect bandgap semiconductor layer, such as silicon or germanium, having a local conduction-band minimum at the Γ-point in an E-k diagram for using as a light emitting layer, and a direct bandgap semiconductor layer formed by a heterojunction on the indirect bandgap semiconductor layer for using as an electron supply means transporting electrons from a Γ-valley to a Γ-valley when a forward-biased voltage is applied, wherein a light emission is occurred by recombining the electrons transported to the Γ-valley of the indirect bandgap semiconductor layer with holes located at a valance band maximum of the indirect bandgap semiconductor layer. | 2013-06-27 |
20130161654 | REFLECTIVE LAYER ON DIELECTRIC LAYER FOR LED ARRAY - A light emitting diode array is described. The array includes a first light emitting diode with a first electrode and a second light emitting diode with a second electrode. The second light emitting diode is separated from the first light emitting diode. A first dielectric layer is positioned between the first light emitting diode and the second light emitting diode. An interconnect is located at least partially on the first dielectric layer that connects the first electrode to the second electrode. A second dielectric layer is formed over the first dielectric layer and the interconnect. A reflective layer is formed over the second dielectric layer. A permanent substrate is coupled to the reflective layer. | 2013-06-27 |
20130161655 | WHITE LED ASSEMBLY WITH LED STRING AND INTERMEDIATE NODE SUBSTRATE TERMINALS - A white LED assembly includes a string of series-connected blue LED dice mounted on a substrate. The substrate has a plurality of substrate terminals. A first of the substrate terminals is coupled to be a part of first end node of the string. A second of the substrate terminals is coupled to be a part of an intermediate node of the string. A third of the substrate terminals is coupled to be a part of a second end node of the string. Other substrate terminals may be provided and coupled to be parts of corresponding other intermediate nodes of the string. A single contiguous amount of phosphor covers all the LED dice, but does not cover any of the substrate terminals. In one example, the amount of phosphor contacts the substrate and has a circular periphery. All the LEDs are mounted to the substrate within the circular periphery. | 2013-06-27 |
20130161656 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus including: a substrate; a plurality of pixels that are formed on the substrate and each have a light emission area from which visible rays are emitted and a transmission area through which external light is transmitted; a pixel circuit portion disposed in each light emission area of the plurality of pixels; a first electrode that is disposed in each light emission area and is electrically connected to the pixel circuit portion; an intermediate layer that is formed on the first electrode and includes an organic emissive layer; a second electrode formed on the intermediate layer; and a capping layer that is disposed on the second electrode and includes a first capping layer corresponding to the light emission area and a second capping layer corresponding to the transmission area. Accordingly, electrical characteristics and image quality of the organic light-emitting display apparatus may be improved. | 2013-06-27 |
20130161657 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MAKING SAME - A light emitting diode package includes a triangular supporting member, a first substrate and a second substrate adhered on first and second inclined sidewalls the supporting member, respectively, a first LED chip and a second LED chip secured on the first substrate and the second substrate, respectively, and a package layer covering the first LED chip and a second LED chip. The first inclined sidewall and a bottom surface of the supporting member cooperatively form a first angle therebetween, and the second inclined sidewall and the bottom surface cooperatively form a second angle therebetween. The first angle and the second angle each range between 0 degree and 90 degrees. A method for making the light emitting diode package is also provided. | 2013-06-27 |
20130161658 | LIGHT EMITTER DEVICES AND COMPONENTS WITH IMPROVED CHEMICAL RESISTANCE AND RELATED METHODS - Light emitter devices, components and methods are disclosed. In one aspect, a light emitter component of a light emitter device is disclosed. The light emitter component can include a silver (Ag) portion at least partially disposed over a surface of the component. The component can further include a protective layer at least partially disposed over the Ag portion, the protective layer at least partially including an organic barrier material that increases or improves chemical resistance of the Ag portion. In some aspects, the protective layer includes a polyxylylene (e.g., poly(p-xylylene), a substituted poly(p-xylylene), a fluorocarbon containing poly(p-xylylene), and/or any other polymer prepared from a xylylene and/or comprising —CH | 2013-06-27 |
20130161659 | LIGHT-EMITTING DEVICE - A light-emitting device includes a substrate, and a plurality of light-emitting elements that are mounted on the substrate and each include an LED chip and a phosphor layer on a surface thereof. A maximum deviation in a value of a chromaticity coordinate x of light emitted from the plurality of light-emitting elements is not less than 0.0125. | 2013-06-27 |
20130161660 | LIGHT-EMITTING DEVICE - A light-emitting device includes a substrate, and a plurality of light-emitting elements that are mounted on the substrate and each emit light within a same color region. The plurality of light-emitting elements satisfy at least one of a first condition and a second condition. The first condition is that a maximum deviation in peak wavelength of light emitted from the plurality of light-emitting elements is not less than 1.25 nm. The second condition is that a maximum deviation in threshold voltage of the plurality of light-emitting elements is not less than 0.05 V. | 2013-06-27 |
20130161661 | CIRCUIT BOARD, DISPLAY MODULE, AND ELECTRONIC APPARATUS - A circuit board includes: a first substrate provided with a device section, the device section including one or a plurality of active devices; a plurality of first wiring layers each extending from the device section toward a periphery of the first substrate; and a plurality of second substrates each opposed to and bonded to the first wiring layer at the periphery of the first substrate and each having a second wiring layer, the second wiring layer being electrically connected to each of the first wiring layers. The first substrate has a cutout in one or more regions each facing one of the plurality of second substrates. | 2013-06-27 |
20130161662 | LIGHTING DEVICE - In a first aspect of the present invention, a lighting device including a metal plate, an electrical insulation layer that is smaller in size than an outline of the metal plate and arranged on an upper surface of the metal plate, a light-emitting element mounted on the electrical insulation layer, and a first connecting electrode and a second connecting electrode electrically connected to the light-emitting element and arranged on the electrical insulation layer. | 2013-06-27 |
20130161663 | ELECTRO-OPTIC DISPLAYS, AND COMPONENTS FOR USE THEREIN - An electro-optic display comprises a substrate ( | 2013-06-27 |
20130161664 | ELECTROLUMINESCENT ELEMENT, DISPLAY DEVICE AND LIGHTING DEVICE - An electroluminescent element ( | 2013-06-27 |
20130161665 | LIGHT-EMITTING DEVICE AND SURFACE LIGHT SOURCE DEVICE USING SAME - A light emitting device includes: a light-emitting element | 2013-06-27 |
20130161666 | DIRECTLY PATTERNED LATERAL HYBRID COLOR OLED ARRAYS SYSTEM AND METHOD - A display situated on a substrate surface is provided. The display includes a first light emitting sub-pixel situated on the substrate surface. The first light-emissive layer includes fluorescent material. The display also includes a second light emitting sub-pixel situated on the substrate surface. The second light-emissive layer includes phosphorescent material. The first light emitting sub-pixel and the second light emitting sub-pixel may be arranged proximate to each other on the substrate surface. The first light emitting sub-pixel and the second light emitting sub-pixel may be arranged laterally adjacent to each other on the substrate surface. A display situated on a substrate is provided first and second light-emissive layers interposed between a first base electrode and a first transparent electrode. The first light emitting sub-pixel further includes a first interlayer interposed between the first and second light-emissive layers. | 2013-06-27 |
20130161667 | PATTERNED REFLECTIVE LAYER ON DIELECTRIC LAYER FOR LED ARRAY - A light emitting diode array includes a first light emitting diode with a first electrode and a second light emitting diode with a second electrode. A first dielectric layer is positioned between the light emitting diodes. A first portion of the first dielectric layer at least partially covers the first light emitting diode and a second portion of the first dielectric layer at least partially covers the second light emitting diode. An interconnect is located at least partially on the first dielectric layer. The interconnect connects the first electrode to the second electrode. A reflective layer is formed over at least the first and second portions of the first dielectric layer. A permanent substrate is coupled to a side of the light emitting diodes having the reflective layer. | 2013-06-27 |
20130161668 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD FOR PRODUCING SAME, AND DISPLAY DEVICE - A semiconductor light-emitting device ( | 2013-06-27 |
20130161669 | LIGHT-EMITTING DIODE WITH CURRENT DIFFUSION STRUCTURE AND A METHOD FOR FABRICATING THE SAME - An LED with a current diffusion structure comprises an N-type semiconductor layer, a light emitting layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode and a current blocking layer. The N-type semiconductor layer, light emitting layer and P-type semiconductor layer form a sandwich structure. The N-type and P-type electrodes are respectively arranged on the N-type and P-type semiconductor layers. The current blocking layer has the pattern of the N-type electrode and is embedded inside the N-type semiconductor layer. Thereby not only current generated by the N-type electrode detours the current blocking layer and uniformly passes through the light emitting layer, but also prevents interface effect to increase impedance. Thus is promoted lighting efficiency of LED. Further, as main light-emitting regions of the light emitting layer are far from the N-type electrode, light shielded by the N-type electrode is reduced and illumination of LED is thus enhanced. | 2013-06-27 |
20130161670 | LIGHT EMITTING DIODE PACKAGES AND METHODS OF MAKING - Light emitting, diode (LED) packages and processes with improved heat dissipation. In certain embodiments, only metal solder resides in the space between the leadframe and the circuit board, providing good heat conduction from the LED chip to the circuit board. In certain embodiments, sidewalls of the leadframe are tilted to provide improved light emission. | 2013-06-27 |
20130161671 | LIGHT EMITTING DIODE WITH SIDEWISE LIGHT OUTPUT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode (LED) includes a substrate, an electrode structure positioned on the substrate, an LED component electrically connected to the electrode structure, and a lens structure positioned on the substrate and covering the LED component. The lens structure includes a rugged structure adjacent to the substrate; the roughness of the rugged structure decreases gradually along a direction from a center of the lens structure center toward a peripheral edge thereof. The present disclosure also provides a method for manufacturing the LED light source. | 2013-06-27 |
20130161672 | LIGHT EMITTING DIODE PACKAGE WITH IMPROVED OPTICAL LENS STRUCTURE - An LED package includes a substrate, two electrodes, an LED die and a lens. The substrate includes a top surface, a bottom surface, a plurality of side surfaces interconnecting the top surface with the bottom surface, and two opposite notches depressed downward from lateral peripheral portions of the top surface. The two electrodes penetrate through the substrate, and each of the two electrodes is exposed at both the top surface and the bottom surface of the substrate. The LED die is arranged on the substrate and electrically connected to the two electrodes. The lens is arranged on the substrate and covers the LED die. The lens includes a contacting surface adjoining the top surface of the substrate, and two protrusions extending from lateral peripheral portions of the contacting surface and respectively embedded in the two notches. | 2013-06-27 |
20130161673 | LIGHT EMITTING DIODE PACKAGE HAVING FLUORESCENT FILM DIRECTLY COATED ON LIGHT EMITTING DIODE DIE AND METHOD FOR MANUFACTURING THE SAME - A method for packaging an LED, includes steps: providing a supporting board and then dripping a gel mixed with fluorescent therein on the supporting board; scraping the gel over the supporting board with a scraper form a gelatinous fluorescent film on the supporting board, and solidifying the gelatinous fluorescent film pieces to form a solidified fluorescent film; cutting the solidified fluorescent film into individual pieces, and peeling the solid fluorescent films from the supporting board; attaching one piece of the fluorescent film on a light outputting surface of an LED die; mounting the LED die on a substrate, and electrically connecting the LED die to the circuit structure; and forming an encapsulation on the substrate to cover the LED die. | 2013-06-27 |
20130161674 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - A semiconductor light emitting element includes a stacked body, a metal reflection layer and a metal pad portion. The stacked body is made of In | 2013-06-27 |
20130161675 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device. The light emitting device comprises a light emitting structure comprising a plurality of compound semiconductor layers; and a light extraction structure on the light emitting structure. The light extraction structure comprises a plurality of first layers and a plurality of second layers which are alternately disposed with each other to have a negative refraction index. | 2013-06-27 |
20130161676 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - The invention provides a Group III nitride semiconductor light-emitting device which has a light extraction face at the n-layer side and which provides high light emission efficiency. The light-emitting device is produced through the laser lift-off technique. The surface of the n-GaN layer of the light-emitting device is roughened. On the n-GaN layer, a transparent film is formed. The transparent film satisfies the following relationship: 0.28≦n×d | 2013-06-27 |