26th week of 2015 patent applcation highlights part 64 |
Patent application number | Title | Published |
20150179599 | DIE SUBSTRATE ASSEMBLY AND METHOD - A die comprising a body of semiconductor material, said body configured to receive a solder layer of gold containing alloy for use in die bonding said die to a substrate, wherein the die includes an interface layer on a surface of the body for receiving the solder layer, the interface layer having a plurality of sub-layers of different metals. | 2015-06-25 |
20150179600 | GRID ARRAY CONNECTION DEVICE AND METHOD - A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results. | 2015-06-25 |
20150179601 | REMOVAL APPARATUSES FOR SEMICONDUCTOR CHIPS - An apparatus for removing a semiconductor chip from a board may include: a laser configured to irradiate the board with a laser beam to heat bumps mounting the semiconductor chip on the board; a picker configured to separate the semiconductor chip from the board; a vacuum portion configured to provide a vacuum to the picker; and an intake. If solder pillars, that are residues of the bumps, are melted by the laser beam, the intake removes the solder pillars using the vacuum provided from the vacuum portion. An apparatus for removing a semiconductor chip from a board may include: a stage configured to support the board on which the semiconductor chip is mounted by bumps; a laser configured to irradiate the board with a laser beam to heat the bumps mounting the semiconductor chip on the board; and a picker configured to separate the semiconductor chip from the board. | 2015-06-25 |
20150179602 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE INK AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system and method of manufacture thereof including: an integrated circuit die having a contact pad; a redistribution layer on the contact pad, the redistribution layer having a chip contact, a trace, and a bump pad, the redistribution layer having a curved top surface and sidewalls which are planar; an upper passivation layer on the sidewalls of the redistribution layer with the area above the bump pad of the redistribution layer exposed from the upper passivation layer; and an external interconnect attached over the bump pad. | 2015-06-25 |
20150179603 | METHOD FOR PRODUCING COMPOSITE STRUCTURE WITH METAL/METAL BONDING - Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m | 2015-06-25 |
20150179604 | METHOD FOR BONDING SUBSTRATES - This invention relates to a method for bonding of a first contact area of a first at least largely transparent substrate to a second contact area of a second at least largely transparent substrate, on at least one of the contact areas an oxide being used for bonding, from which an at least largely transparent interconnection layer is formed with an electrical conductivity of at least 10e1 S/cm | 2015-06-25 |
20150179605 | Method for Aligning Micro-Electronic Components - Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid. | 2015-06-25 |
20150179606 | METHOD OF PROCESSING A SEMICONDUCTOR WAFER - A method of processing a semiconductor wafer includes forming semiconductor dies in the semiconductor wafer, each die having an active region containing devices of an integrated circuit and an edge region surrounding the active region, adjacent ones of the dies being separated by a scribe line. The method further includes forming interconnect wiring over the active region of each semiconductor die in an interlayer dielectric, forming ancillary wiring over the edge region of each die in the interlayer dielectric, forming a passivation on the interlayer dielectric, forming bond pads over the interconnect wiring of each die, the bond pads of each die being in electrical connection with the interconnect wiring of that die, and forming additional bond pads over the ancillary wiring of each semiconductor die, the additional bond pads of each die being in electrical connection with the interconnect wiring of that die. | 2015-06-25 |
20150179607 | Semiconductor Packaging Structure and Process - A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow. | 2015-06-25 |
20150179608 | EMBEDDED PACKAGES HAVING A CONNECTION JOINT GROUP - An embedded package includes a first semiconductor chip embedded in a package substrate, a second semiconductor chip disposed over a first surface of the package substrate, and a group of external connection joints disposed on the first surface of the package substrate and between a sidewall of the second semiconductor chip and an edge of the embedded package. Related memory cards and related electronic systems are also provided. | 2015-06-25 |
20150179609 | METHOD FOR INTERCONNECTING DIE AND SUBSTRATE IN AN ELECTRONIC PACKAGE - A method for interconnecting a die on a substrate of an electronic package. The method includes the steps of forming a plurality of free-end wire bonds on the die, wherein the free-end wire bonds are upstanding from the die, and encapsulating the free-end wire bonds in an encapsulation layer. Planarizing the encapsulation layer is performed so that the free-end wire bonds are exposed for electrical connection. Interconnecting the free-end wire bonds is provided by applying an interconnection layer on the encapsulation layer. | 2015-06-25 |
20150179610 | COMPLIANT DIELECTRIC LAYER FOR SEMICONDUCTOR DEVICE - Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through silicon via interposer or substrate, a compliant dielectric material may be added to a surface of silicon material body to form a compliant dielectric layer. The compliant dielectric layer provides a thermal buffer and a stress buffer for a resulting IC package. The compliant dielectric material may be selected such that the coefficient of thermal expansion of the compliant dielectric material approximately matches the coefficient of thermal expansion of the circuit board on which the IC package is mounted. The compliant dielectric material may be selected such that it has a deformability that is greater than the silicon material body. Multiple sub-layers of compliant dielectric material may be used. | 2015-06-25 |
20150179611 | THREE-DIMENSIONAL PACKAGE STRUCTURE AND THE METHOD TO FABRICATE THEREOF - The present invention discloses a three-dimensional package structure which can achieve a relatively high utilization of an internal space thereof, so that the size of electronic package structure can be reduced. The three-dimensional package structure comprises a substrate, a first plurality of discrete conductive components and a connecting structure. The substrate has a top surface and a bottom surface. The first plurality of discrete conductive components are disposed over the bottom surface of the substrate. The connecting structure is disposed over the bottom surface of the substrate for encapsulating the first plurality of discrete electronic components. The connecting structure comprises at least one insulating layer and a plurality of conductive patterns separated by the at least one insulating layer. The plurality of conductive patterns are disposed over the first plurality of discrete electronic components for electrically connecting the first plurality of discrete electronic components. | 2015-06-25 |
20150179612 | 3DIC Interconnect Apparatus and Method - An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug. | 2015-06-25 |
20150179613 | 3DIC Interconnect Apparatus and Method - An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls and a bottom of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug. | 2015-06-25 |
20150179614 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a semiconductor device, including: a first substrate that includes a first wiring; a second substrate that is disposed facing the first substrate and includes a second wiring, the second wiring being connected to the first wiring through a connection terminal, and the second substrate being smaller in area than the first substrate; a first resin layer that is filled in a gap between the first substrate and the second substrate and covers a region, on the first substrate, in an outer periphery of the second substrate; an organic film pattern that is provided on the first substrate and surrounds the first resin layer; and a second resin layer that covers the first substrate, the organic film pattern, the first resin layer, and the second substrate. | 2015-06-25 |
20150179615 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To improve reliability of a semiconductor device. In a conductive material that electrically couples a Cu pillar electrode and a lead, an alloy part comprised of an alloy of tin and copper is formed inside this conductive material. At this time, the alloy part contacts both the Cu pillar electrode and the lead, and the Cu pillar electrode and the lead are bound through the alloy part. Similarly, also in FIG. | 2015-06-25 |
20150179616 | Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate - A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. | 2015-06-25 |
20150179617 | THERMALLY ENHANCED HEAT SPREADER - A three dimensional integrated circuit (3DIC) includes a first substrate and a heat spreading structure embedded in the first substrate. The 3DIC further includes a die electrically connected to the first substrate, wherein the die is thermally connected to the heat spreading structure. The 3DIC further includes a plurality of memory units on the die, wherein the die is between the plurality of memory units and the first substrate, and the plurality of memory units is thermally connected to the heat spreading structure by the die. The 3DIC further includes an external cooling unit on the plurality of memory units, wherein the plurality of memory units is between the die and the external cooling unit, and the die is thermally connected to the external cooling unit by the plurality of memory units. | 2015-06-25 |
20150179618 | PACKAGE-ON-PACKAGE MODULES, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME - Package-on-package (PoP) modules are provided. The PoP module includes a lower package and an upper package disposed over the lower package. The lower package includes a lower substrate and a lower chip disposed over a top surface of the lower substrate. The upper package includes an upper substrate, a plurality of upper chips disposed over a top surface of the upper substrate, and an upper molding member disposed over the plurality of upper chips. The upper molding member is divided into at least two parts which are separated from each other by a trench. Related memory cards and related electronic systems are also provided. | 2015-06-25 |
20150179619 | STUB MINIMIZATION WITH TERMINAL GRIDS OFFSET FROM CENTER OF PACKAGE - A microelectronic package includes a microelectronic element having memory storage array function overlying a first surface of a substrate, the microelectronic element having a plurality of contacts aligned with an aperture in the substrate. First terminals which are configured to carry all address signals transferred to the package can be exposed within a first region of a second substrate surface, the first region disposed between the aperture and a peripheral edge of the substrate. The first terminals may be configured to carry all command signals, bank address signals and command signals transferred to the package, the command signals being write enable, row address strobe, and column address strobe. | 2015-06-25 |
20150179620 | SEMICONDUCTOR DEVICE - A semiconductor element is sandwiched between a lower and upper surface of a cooling body. A connection circuit and a communication device are provided on the lower surface of the cooling body. A drive circuit and a communication device are provided on the upper surface of the cooling body. These components are encapsulated by a resin. The connection circuit generates a control signal in response to a signal from outside. The communication device transmits the control signal. The communication device receives the control signal and supplies the control signal to the drive circuit, which drives the semiconductor element in response to the control signal. The resin electrically insulates the connection circuit and the communication device from the communication device and the drive circuit enabling prevention of breakdown of the connection circuit caused by an application of a high voltage from the drive circuit to the connection circuit. | 2015-06-25 |
20150179621 | MODULE - A low profile module is provided that has a high functionality achieved by increasing the component mounting density. In spite of achieving high functionality in a module | 2015-06-25 |
20150179622 | SOLDER PAD DEVICE AND METHOD - An electronic device including a solder pad structure and methods of forming an electrical interconnection are shown. Solder pads including one or more projections extending from the pads are shown where the projections occupy only a fraction of a surface area of the pads. Processes such as thermal compression bonding using solder pads as described area also shown. | 2015-06-25 |
20150179623 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device having improved reliability. | 2015-06-25 |
20150179624 | Process for Forming Package-on-Package Structures - A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material. | 2015-06-25 |
20150179625 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer. | 2015-06-25 |
20150179626 | METHOD OF MAKING STACKED MULTI-CHIP PACKAGING STRUCTURE - A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the metal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip. | 2015-06-25 |
20150179627 | PERFORMANCE-DRIVEN AND GRADIENT-AWARE DUMMY INSERTION FOR GRADIENT-SENSITIVE ARRAY - The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width. | 2015-06-25 |
20150179628 | SEMICONDUCTOR STRUCTURE FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor structure is arranged on an integrated circuit, the integrated circuit includes a seal ring arranged at outer periphery of the integrated circuit, a metal ring arranged at an inner side of the seal ring and a power bus arranged at a side of the metal ring. The semiconductor structure includes a first P type electrode area, a second P type electrode area and a first N type electrode area. The first P type electrode area is formed at a position on a P well corresponding to the seal ring, and coupled to the seal ring. The second P type electrode area is formed at a position on the P well corresponding to the metal ring, and coupled to the metal ring. The first N type electrode area is formed at a position corresponding to the power bus, and coupled to the power bus. | 2015-06-25 |
20150179629 | SEMICONDUCTOR STRUCTURE FOR ELECTROSTATIC DISCHARGE PROTECTION - A semiconductor structure includes a P well formed on a P type substrate; a first N type electrode area formed on a central region of the P well; a first insulating area formed on the P well and surrounding the first N type electrode area; a second N type electrode area formed on the P well and surrounding the first insulating area; a second insulating area formed on the P well and surrounding the second N type electrode area; and a P type electrode area formed on the P well and surrounding the second insulating area; wherein periphery outlines of the first N type electrode area and the second N type electrode area are both 8K sided polygons or circles, and K is a positive integer. | 2015-06-25 |
20150179630 | ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a first NMOS transistor coupled to a power line, a second NMOS transistor coupled between the first transistor and a ground, a detection unit, providing a detection signal when an ESD event occurs at the power line, and a trigger unit, turning on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors. The trigger unit includes a first PMOS transistor coupled between the power line and a gate of the second NMOS transistor, a fourth resistor, and a second PMOS transistor, having a gate coupled to the cathode of the diode for receiving the detection signal. | 2015-06-25 |
20150179631 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device including a deep doped region of a first conductivity type, a well region of a second conductivity type, a base region of the first conductivity type, an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor (MOS). The well region is disposed in the deep doped region. The base region is disposed in the well region and is not connected to the deep doped region. The IGBT is disposed on the well region at the first side of the base region, and includes a first doped region of the second conductivity type disposed in the base region. The MOS is disposed on the well region and the deep well region at the second side of the base region, and includes a second doped region of the second conductivity type disposed in the base region. | 2015-06-25 |
20150179632 | SEMICONDUCTOR DEVICE COMPRISING AN E-FUSE AND A FET - A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate. | 2015-06-25 |
20150179633 | Reverse Blocking Transistor Device - A transistor device includes at least one transistor cell. The cell includes a drift region, a source region, a body region arranged between the source region and the drift region, and a drain region. The drift region is arranged between the body region and the drain region. A gate electrode is adjacent the body region and dielectrically insulated from the body region by a gate dielectric. A channel region of a doping type complementary to a doping type of the drain region is arranged between the drift region and the drain region. A drift control region is adjacent the drift region and dielectrically insulated from the drift region and the channel region by a drift control region dielectric. A first switch is coupled between the drift control region and the drain region. | 2015-06-25 |
20150179634 | INTEGRATED SEMICONDUCTOR DEVICE - An integrated semiconductor device having a stabilization function includes a substrate layer, an insulating layer, ground plane layer formed between the substrate layer and the insulating layer and a signal plane layer formed on a surface of the insulating layer facing away from the substrate layer. An n-port, e.g. a transistor, is formed within the substrate layer on a first side of the substrate layer. A via hole is formed through the insulating layer. A resistor is formed within the ground plane layer. | 2015-06-25 |
20150179635 | SEMICONDUCTOR DEVICE, LIGHT-EMITTING DEVICE, AND ELECTRONIC DEVICE - An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor. | 2015-06-25 |
20150179636 | Semiconductor Device - A semiconductor device includes at least one field effect transistor structure, which is formed on a semiconductor substrate. The field effect transistor structure includes a drift region, a body region, a source region and a gate. The source region and the drift region include at least mainly a first conductivity type, wherein the body region includes at least mainly a second conductivity type. The body region includes at least one low doping dose portion extending from the drift region to at least one of the source region or an electrical contact interface of the body region at a main surface of the semiconductor substrate, wherein a doping dose within the low doping dose portion of the body region is less than 3 times a breakdown charge. | 2015-06-25 |
20150179637 | Semiconductor Devices - A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region. The first doping region includes at least one low doping dose portion extending from the main surface of the semiconductor substrate to the second doping region. A doping dose within the low doping dose portion of the first doping region is less than 3 times a breakdown charge. Additionally, the semiconductor device includes a first electrode structure in contact with the first doping region at the main surface of the semiconductor substrate. The work function of the first electrode structure at the main surface of the semiconductor substrate is larger than 4.9 eV or lower than 4.4 eV. | 2015-06-25 |
20150179638 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n | 2015-06-25 |
20150179639 | SEMICONDUCTOR STRUCTURES INCLUDING FLUIDIC MICROCHANNELS FOR COOLING AND RELATED METHODS - Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material. | 2015-06-25 |
20150179640 | COMMON FABRICATION OF DIFFERENT SEMICONDUCTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES - A multi-device semiconductor structure including a p-type logic device, a p-type memory device, a n-type logic device and a n-type memory device are provided on a bulk silicon substrate. Each of these devices includes a dielectric layer and either a n-type or a p-type work function layer disposed over the dielectric layer. Some of the various device types of the multi-device semiconductor structure are protected, and impurities, such as aluminum and/or nitrogen, are added to the exposed work function layers to achieve one or more other desired work functions with different threshold voltages. | 2015-06-25 |
20150179641 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device including a substrate, a first element isolation film pattern, and a second element isolation film pattern. The substrate includes a first region and a second region. The first element isolation film pattern is in the first region and corresponds to a first active region. The second element isolation film pattern is in the second region and corresponds to a second active region. The first element isolation film pattern includes a first material and the second element isolation film pattern includes a second material different from the first material. | 2015-06-25 |
20150179642 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern. | 2015-06-25 |
20150179643 | Semiconductor Component with Transistor - One aspect relates to a semiconductor component with a semiconductor body, a first main contact pad, a second main contact pad, a normally-on first transistor monolithically integrated in the semiconductor body and a normally-off second transistor monolithically integrated in the semiconductor body. The first transistor is a high electron mobility transistor having a first gate electrode and a first load path controllable via a first gate electrode, and the second transistor has a second gate electrode and a second load path controllable via the second gate electrode. The first load path and the second load path are electrically connected in series between the first main contact pad and the second main contact pad. | 2015-06-25 |
20150179644 | FINFET INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION - Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric. | 2015-06-25 |
20150179645 | SEMICONDUCTOR DEVICE WITH EPITAXIAL STRUCTURES - A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures spaced apart from each other are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure. The cap simultaneously surrounds the epitaxial structures, and at least two adjacent caps are merged together. | 2015-06-25 |
20150179646 | FLIP-FLOP LAYOUT ARCHITECTURE IMPLEMENTATION FOR SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and third and fourth gate electrodes are provided on the NMOSFET region. A connection contact is provided to connect the second gate electrode with the third gate electrode, and a connection line is provided on the connection contact to cross the connection contact and connect the first gate electrode to the fourth gate electrode. | 2015-06-25 |
20150179647 | CMOS INVERTERS AND FABRICATION METHODS THEREOF - A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure. | 2015-06-25 |
20150179648 | MULTI-LAYER SEMICONDUCTOR STRUCTURES FOR FABRICATING INVERTER CHAINS - Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures. | 2015-06-25 |
20150179649 | Thyristor-Based Memory Cells, Devices and Systems Including the Same and Methods for Forming the Same - Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F | 2015-06-25 |
20150179650 | FLOATING BODY MEMORY CELL HAVING GATES FAVORING DIFFERENT CONDUCTIVITY TYPE REGIONS - A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described. | 2015-06-25 |
20150179651 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a bit line structure on a substrate, the bit line structure having a polysilicon layer pattern doped with impurities, and a metal layer pattern on the polysilicon layer pattern, a first spacer surrounding and contacting a sidewall of the bit line structure, the first spacer having a constant thickness, and a capacitor contact structure on the substrate, an air gap being defined between the capacitor contact structure and the first spacer. | 2015-06-25 |
20150179652 | PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE - A patterned structure of a semiconductor device includes a substrate, at least a first patterned structure, and at least a second patterned structure. The first patterned structure is a single-layered structure, and the second patterned structure is a multi-layered structure. The width of the second patterned structure is greater than the width of the first patterned structure. | 2015-06-25 |
20150179653 | METHOD AND APPARATUS FOR IMPROVING READ MARGIN FOR AN SRAM BIT-CELL - Described is a 6T SRAM cell which comprises: a first n-type transistor with a gate terminal coupled to word-line, source/drain terminal coupled to a first bit-line and drain/source terminal coupled to a first node; and a second n-type transistor with a source terminal coupled to a first supply node, a drain terminal coupled to the first node, and a gate terminal for coupling to multiple terminals, wherein the gate terminal includes a capacitor to increase coupling capacitance of the second n-type transistor. Described is a method which comprises: forming a metal gate in a first direction; forming a first spacer in the first direction on one side of the metal gate, the first spacer having a first dimension; and forming a second spacer in the first direction on another side of the metal gate, the second spacer having a second dimension which is substantially different from the first dimension. | 2015-06-25 |
20150179654 | EPITAXIAL SOURCE/DRAIN DIFFERENTIAL SPACERS - A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over gates of both transistors, performing an epitaxial spacer anisotropic etch process to form epitaxial spacers on vertical surfaces adjacent to the first transistor gate and removing the epitaxial spacer layer from the second transistor gate, subsequently performing a source/drain etch process and a source/drain epitaxial process to form source/drain epitaxial regions in the substrate adjacent to the first and second gates, such that the first source/drain epitaxial regions are separated from the first gate by a lateral space which is at least 2 nanometers larger than a second lateral space separating the second source/drain epitaxial regions from the second gate. An integrated circuit formed by the recited process. | 2015-06-25 |
20150179655 | STATIC RANDOM ACCESS MEMORY (SRAM) CELLS INCLUDING VERTICAL CHANNEL TRANSISTORS AND METHODS OF FORMING THE SAME - A static random access memory (SRAM) cell can include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor, a second pull-down transistor, a first access transistor, and a second access transistor, all being coupled together in a 6 transistor SRAM cell, wherein each of the transistors is configured as a vertical channel transistor. | 2015-06-25 |
20150179656 | CT-NOR DIFFERENTIAL BITLINE SENSING ARCHITECTURE - Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor. The pass transistor, in turn, enables current flow between two metal bitlines of the semiconductor memory architecture. Accordingly, a relative voltage or relative current of the two metal bitlines can be measured and utilized to determine a program or erase state of a transistor of the serial array of transistors. In a particular aspect, a transistor with small capacitance is chosen for the pass transistor, resulting in a fast correspondence of the pass transistor gate voltage/current relative to transistor array current. This can equate to fast read times for the transistor array, based on differential sensing of the two metal bitlines. | 2015-06-25 |
20150179657 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device is provided with a semiconductor channel region; a first insulating layer including an oxide film disposed in contact with the semiconductor channel region, an yttrium oxide containing film disposed on the oxide film, and a hafnium oxide film having an orthorhombic phase III structure disposed on the yttrium oxide containing film; and a control electrode disposed on the first insulating layer. | 2015-06-25 |
20150179658 | Semiconductor Memory Devices and Manufacturing Methods Thereof - A semiconductor memory device and a manufacturing method of the semiconductor memory device are provided. The semiconductor memory device can include a substrate in which a cell area and a peripheral area are defined, a first gate insulating layer on the peripheral area, and a poly gate layer on the first gate insulating layer to form a combined stack, wherein the combined stack of the first gate insulating layer and the first poly gate layer is absent from the cell area. | 2015-06-25 |
20150179659 | MULTILEVEL CONTACT TO A 3D MEMORY ARRAY AND METHOD OF MAKING THEREOF - A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate. The plurality of electrically conductive layers form a stepped pattern in the contact region, where each respective electrically insulating layer includes a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall. | 2015-06-25 |
20150179660 | Three Dimensional NAND Device with Channel Located on Three Sides of Lower Select Gate and Method of Making Thereof - A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode. | 2015-06-25 |
20150179661 | VERTICAL CHANNEL-TYPE 3D SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A vertical channel-type 3D semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the device includes a multi-layer film formed by depositing alternating layers of insulation and an electrode material on a substrate. The device also includes through-holes formed by etching the film to the substrate. The device also includes gate stacks formed by depositing barrier storage and a tunnel layers in sequence on inner walls of the through-holes. The device also includes hollow channels formed by depositing a channel material on the tunnel layer. The device also includes drains for bit-line connection in top portions of the hollow channels. The device also includes sources formed in contact regions between through-holes and the substrate in bottom portions of the hollow channels. | 2015-06-25 |
20150179662 | COBALT-CONTAINING CONDUCTIVE LAYERS FOR CONTROL GATE ELECTRODES IN A MEMORY STRUCTURE - A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt. | 2015-06-25 |
20150179663 | MULTI-LEVEL CONTACT TO A 3D MEMORY ARRAY AND METHOD OF MAKING - A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers. | 2015-06-25 |
20150179664 | HETEROGENEOUS SEMICONDUCTOR MATERIAL INTEGRATION TECHNIQUES - Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands. | 2015-06-25 |
20150179665 | METHOD FOR PRODUCING STRAINED SEMI-CONDUCTOR BLOCKS ON THE INSULATING LAYER OF A SEMI-CONDUCTOR ON INSULATOR SUBSTRATE - Method for producing a microelectronic device comprising: | 2015-06-25 |
20150179666 | WIRING STRUCTURE OF ARRAY SUBSTRATE - The present disclosure relates to the technical field of liquid crystal display. The wiring structure of the array substrate according to the present disclosure includes an RGB combined line serving as data lines in a curing process, an OE combined line serving as scan lines in the curing process, an array substrate common line, a color filter substrate common line, and corresponding RGB curing pad, OE curing pad, an array substrate curing pad and a color filter substrate curing pad which are connected to the RGB combined line, the OE combined line, the array substrate common line and the color filter substrate common line respectively and are configured to receive respective voltages. The present disclosure reduces the number of curing bus lines by improving the conventional design, which helps to reduce the peripheral wires of the array substrate, increase the buffer space for design layout and alleviate the risk of manufacturing defects. This leads to progress over prior art. | 2015-06-25 |
20150179667 | TFT ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - A TFT array substrate includes a first electrode layer and a second electrode layer disposed below the first electrode layer. The first electrode layer includes a strip-like first electrode, and the second electrode layer is a sheet-like electrode. The strip-like first electrode includes a bent portion. The second electrode layer includes at least one opening, the opening is located below the bent portion. | 2015-06-25 |
20150179668 | THIN FILM TRANSISTOR ARRAY SUBSTRATE, METHOD FOR FABRICATING THE SAME AND DISPLAY - A TFT array substrate, a method for fabricating the same and a display are disclosed. The TFT array substrate comprises: a plurality of gate lines, a plurality of data lines and a plurality of pixel regions defined by intersecting the plurality of gate lines and the plurality of data lines, a pixel electrode is disposed in each of the pixel regions. The TFT array substrate further comprises: a gate electrode formed on a substrate; a black matrix and an active layer sequentially formed above the gate electrode, the gate electrode and the active layer are isolated from each other via the black matrix overlaying the gate electrode; a source electrode and a drain electrode both formed on the active layer; a color filter layer formed on the source electrode, the drain electrode and the active layer; the pixel electrode is disposed on the color filter layer and connected to the drain electrode by way of a via hole penetrating through the color filter layer. | 2015-06-25 |
20150179669 | METHOD OF MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE - A method of manufacturing an array substrate, an array substrate and a display device are provided. The method of manufacturing the array substrate includes: forming a pattern of a gate metal layer including a gate line and a gate electrode and preserving photoresist at a position on the pattern of the gate metal layer corresponding to a gate lead hole; sequentially forming a gate insulating thin film, a semiconductor thin film and a source/drain metal thin film; removing the photoresist preserved at the position on the pattern of the gate metal layer corresponding to the gate lead hole, and forming the gate lead hole; forming a pattern of a source/drain metal layer including a source electrode, a drain electrode and a data line and a semiconductor layer; and forming a pattern including a pixel electrode layer and a channel. | 2015-06-25 |
20150179670 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel includes a first substrate on which an electrode line and a switching element are disposed, a second substrate positioned opposite the first substrate, a seal provided between the first substrate and the second substrate, a pad electrode that vertically overlaps the seal and is electrically connected to the electrode line, and a side electrode which is connected to one end of the pad electrode and includes a portion positioned on an exterior facing side of the seal. | 2015-06-25 |
20150179671 | PIXEL ARRAY AND DISPLAY PANEL - A pixel array and a display panel are provided. The pixel array includes a plurality of pixel units. Each of the pixel units includes a first scan line, a second scan line, a data line, a first thin-film transistor, a second thin-film transistor, a first pixel electrode and a second pixel electrode. The first thin-film transistor is electrically connected to the first scan line and the data line. The first pixel electrode is electrically connected to the first thin-film transistor. The second thin-film transistor is electrically connected to the second scan line and the data line. The second pixel electrode is electrically connected to the second thin-film transistor. The orthogonal projection pattern of the first thin-film transistor on XY plane and the orthogonal projection pattern of the second thin-film transistor on XY plane are substantially the same. | 2015-06-25 |
20150179672 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE, AND ELECTRONIC APPARATUS - A thin film transistor and a method for manufacturing the same, an array substrate including the thin film transistor, and an electronic apparatus including the thin film transistor or provided with the array substrate. The thin film transistor includes: a gate electrode, a gate insulating layer, an active layer, and a source electrode and a drain electrode, the active layer is formed of a mixture including a semiconductor nano-material and a photoresist material. The method for manufacturing the thin film transistor includes: preparing a mixture including a semiconductor nano-material and a photoresist material; applying the mixture over a substrate, and forming a patterned active layer by exposure and development. | 2015-06-25 |
20150179673 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an SRAM is formed on an SOI substrate in a chip region. Also, in a TEG region, an element structure of an SRAM in which a contact plug is connected to a semiconductor substrate is formed on the semiconductor substrate exposed from an SOI layer and a BOX film as a TEG used for the VC inspection. | 2015-06-25 |
20150179674 | HARD COATING FILM AND DISPLAY DEVICE USING THE SAME - Disclosed is a display device that includes a display element including a plurality of thin film transistors; and a hard coating film on the display element, the hard coating film including: a base film; and a hard coating layer on the base film, the hard coating layer including a photo-curable resin composition and a plurality of porous particles. | 2015-06-25 |
20150179675 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured. | 2015-06-25 |
20150179676 | DISPLAY DEVICE - With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. Due to the increase in the numbers of gate lines and signal lines, it is difficult to mount an IC chip having a driver circuit for driving the gate and signal lines by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit for driving the pixel portion are formed over one substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor is used. The driver circuit as well as the pixel portion is provided over the same substrate, whereby manufacturing costs are reduced. | 2015-06-25 |
20150179677 | LIQUID CRYSTAL DISPLAY ARRAY SUBSTRATES AND A METHOD FOR MANUFACTURING THE SAME - A liquid crystal display array substrate and a method for manufacturing the same are provided herein, wherein, the array substrate comprises, first gate lines, arranged on a substrate in parallel, to transfer a gate signal to a display cell; data lines, arranged on a different layer of the substrate from the first gate line but in a direction perpendicular thereto, to transfer a source driver signal to the cell; buses of common electrode lines forming frame structure and outlet lines extending from the buses; and branches of the common electrode lines intersecting with the buses, wherein, switches are placed at the intersections between the buses and the branches. Such a design can greatly increase the rate of detection of open-circuit failures, so that the failures can be repaired timely, and thus the yield of the display can be increased and the cost be saved. | 2015-06-25 |
20150179678 | LIQUID CRYSTAL DISPLAY ARRAY SUBSTRATE, SOURCE DRIVING CIRCUIT AND BROKEN LINE REPAIRING METHOD - The present disclosure disclosed an array substrate of a liquid crystal display, a source driving circuit, and a method for repairing the broken line. The method includes: gate lines, arranged in parallel on a base for transmitting scan signals to a display panel; data lines, arranged on the base in a manner that the data lines are on different layers from that in which the gate lines are located, and are oriented vertically to the gate lines, for transmitting source driving signals to the display panel; and two or more repairing lines, arranged on the base and including a first group of terminals and a second group of terminals, wherein the first group of terminals is pending; the second group of terminals is connected with the output end of a source driving circuit. The design of the present disclosure is simple, and thus the method for repairing the broken line is convenient so as to improve the productivity. | 2015-06-25 |
20150179679 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - Embodiments of the present invention provide an array substrate, a manufacturing method thereof and a display device. The method for manufacturing the array substrate comprises: forming a pattern of an active layer of a switching thin-film transistor (TFT) and a pattern of a corresponding pixel electrode on a base substrate, in which the active layer of the switching TFT and the pixel electrode are on the same layer. | 2015-06-25 |
20150179680 | DISPLAY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE - A display device according to the present disclosure includes: a transistor section that includes a gate insulating film, a semiconductor layer, and a gate electrode layer, the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section that includes a first metal film and a second metal film, the first metal film being disposed at a same level as wiring layers that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film in between; and a display element that is configured to be controlled by the transistor section. | 2015-06-25 |
20150179681 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, DISPLAY UNIT, AND ELECTRONIC APPARATUS - A semiconductor device includes: a transistor having an oxide semiconductor film; and a retention capacitor having a first conductive film and a second conductive film, the first conductive film containing an oxide material and being in contact with the oxide semiconductor film, and the second conductive film facing the first conductive film with an insulating film in between. | 2015-06-25 |
20150179682 | Semiconductor Device and Method for Manufacturing the Same - It is an object to obtain a liquid crystal display device in which a contact defect is reduced, increase in contact resistance is suppressed, and an opening ratio is high. The present invention relates to a liquid crystal display device having a substrate; a thin film transistor provided over the substrate, which includes a gate wiring, a gate insulating film, an island-shaped semiconductor film, a source region, and a drain region; a source wiring which is provided over the substrate and is connected to the source region; a drain electrode which is provided over the substrate and is connected to the drain region; an auxiliary capacitor provided over the substrate; a pixel electrode connected to the drain electrode; and a protective film fanned so as to cover the thin film transistor and the source wiring, where the protective film has an opening, and the auxiliary capacitor is formed in the area where the opening is formed. | 2015-06-25 |
20150179683 | High Productivity Combinatorial Material Screening for Metal Oxide Films - Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor (e.g. ZnO | 2015-06-25 |
20150179684 | High Productivity Combinatorial Material Screening for Stable, High-Mobility Non-Silicon Thin Film Transistors - Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor deposition, metal-based patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate. | 2015-06-25 |
20150179685 | Assembling Method for Array Substrate and Color Filter Substrate of Liquid Crystal Display - The present invention discloses an assembling method for array substrate and color filter substrate of liquid crystal display, which comprises: coating a seal on a color filter substrate; forming multiple sealing points at the predetermined position between an array substrate with liquid crystal and the color filter substrate; rotating the color filter substrate to fit the array substrate; irradiating the sealing points using a light source to cure the sealing points, so that the array substrate and the color filter substrate are bonded. According to the embodiment of the present invention, it can be aligned precisely during assembling process of the array substrate and the color filter substrate, which avoids the poor substrate alignment caused by handling or flip and then improves the product yield. | 2015-06-25 |
20150179686 | METHOD OF MANUFACTURING A TFT-LCD ARRAY SUBSTRATE - A thin film transistor liquid crystal display (TFT-LCD) array substrate comprises a gate line, a data line, a pixel electrode and a thin film transistor. The pixel electrode and the thin film transistor are formed in a pixel region defined by intersecting of the gate line and the data line, and the thin film transistor comprises a gate electrode, a semiconductor layer, a source electrode and a drain electrode. Two separate parts of the surface of the semiconductor layer are treated by a surface treatment to form into an ohmic contact layer, and the source electrode and the drain electrode are connected with the semiconductor layer through the ohmic contact layer in the two separate parts, respectively. | 2015-06-25 |
20150179687 | Array Substrate of Liquid Crystal Display Device and Method of Fabricating the Same - An array substrate of a liquid crystal display device and a method of fabricating the array substrate. A gate electrode of a thin film transistor of the array substrate is formed. The gate electrode has an edge region surrounding an interior region of the gate electrode and the edge region of the gate electrode is thicker than the interior region of the gate electrode. A semiconductor layer is formed over the gate electrode. A source electrode and a drain electrode of the thin film transistor are formed that define a channel region in the semiconductor layer. The channel region is located over the interior region of the gate electrode. Additionally, the gate electrode may be formed with a half-tone mask that results in the edge region of the gate electrode being thicker than the interior region of the gate electrode. | 2015-06-25 |
20150179688 | IMAGING APPARATUS, IMAGING SYSTEM AND MANUFACTURING METHOD OF IMAGING APPARATUS - One embodiment according to the present disclosure is an imaging apparatus including pixels. The pixel includes a junction type field effect transistor (JFET) provided in a semiconductor substrate. The JFET includes a gate region and a channel region. An orthogonal projection of the gate region onto a plane parallel to a surface of the semiconductor substrate intersects an orthogonal projection of the channel region onto the plane. Each of a source-side portion of the orthogonal projection of the channel region and a drain-side portion of the orthogonal projection of the channel region protrudes out of the orthogonal projection of the gate region. | 2015-06-25 |
20150179689 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a display area and a non-display area. The non-display area includes at least one light sensor each including a light blocking layer on a substrate and for blocking light emitted from a backlight source; an insulating layer on the light blocking layer; a amorphous silicon layer on the insulating layer at a location corresponding to the light blocking layer and for sensing external light; an input electrode and an output electrode on the amorphous silicon layer and not contacting each other. The input electrode and the output electrode both contact the amorphous silicon layer, a part of the amorphous silicon layer between the input electrode and the output electrode forms a conductive channel. The output electrode is connected with a photoelectric detection circuit for inputting drain current generated by the conductive channel into the photoelectric detection circuit. | 2015-06-25 |
20150179690 | MECHANISMS FOR FORMING IMAGE SENSOR DEVICE - Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate. The image sensor device also includes an active region in the semiconductor substrate and surrounded by the isolation structure. The active region includes a light sensing region and a doped region, and the doped region has a horizontal length and a vertical length. A ratio of the horizontal length to the vertical length is in a range from about 1 to about 4. | 2015-06-25 |
20150179691 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A solid-state imaging device and method of making a solid-state imaging device are described herein. By way of example, the solid-state imaging device includes a first wiring layer formed on a sensor substrate and a second wiring layer formed on a circuit substrate. The sensor substrate is coupled to the circuit substrate, the first wiring layer and the second wiring layer being positioned between the sensor substrate and the circuit substrate. A first electrode is formed on a surface of the first wiring layer, and a second electrode is formed on a surface of the second wiring layer. The first electrode is in electrical contact with the second electrode. | 2015-06-25 |
20150179692 | SOLID-STATE IMAGING APPARATUS AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a solid-state imaging apparatus is provided. The method includes forming, above a substrate having an effective pixel region and a non-effective pixel regions, a structure including first and second members located above the effective and non-effective pixel regions respectively, and a third member covering the first and second members, forming, above the third member, a mask having first and second apertures located above the first and second members respectively, and forming a first hole exposing the first member by etching the structure through the first aperture and a second hole exposing the second member by etching the structure through the second aperture. In the etching, the first and second holes are concurrently formed and etching of the structure is finished based on that the second hole has reached the second member. | 2015-06-25 |
20150179693 | SOLID-STATE IMAGE SENSOR, METHOD OF PRODUCING THE SAME, AND ELECTRONIC APPARATUS - A solid-state image sensor includes a pixel formed, upon forming a structure where a photoelectric conversion layer is laminated on a wiring layer constituting a pixel circuit, by forming at least the photoelectric conversion layer and a wiring layer bonding layer on a different substrate from a semiconductor substrate in which the wiring layer is formed, and by bonding the wiring layer bonding film of the different substrate and the wiring layer of the semiconductor substrate together. | 2015-06-25 |
20150179694 | SOLID-STATE IMAGING APPARATUS - The present invention relates to a solid-state imaging apparatus including a first substrate having a plurality of photoelectric conversion units and a second substrate having a plurality of readout circuits. The first substrate is provided with a plurality of first conductive patterns that are electrically separated from one another and the second substrate is provided with a plurality of second conductive patterns that are electrically separated from one another. The first conductive patterns each include a first partial pattern extending in a first direction. The second conductive patterns each include a partial pattern extending in a second direction different from the first direction. The first partial pattern has a length extending in the first direction longer than a length thereof in the second direction. | 2015-06-25 |
20150179695 | IMAGE SENSOR PIXEL FOR HIGH DYNAMIC RANGE IMAGE SENSOR - An image sensor pixel for use in a high dynamic range image sensor includes a first photodiode and a second photodiode. The first photodiode include a first doped region, a first lightly doped region, and a first highly doped region disposed between the first doped region and the first lightly doped region. The second photodiode disposed in has a second full well capacity substantially equal to a first full well capacity of the first photodiode. The second photodiode includes a second doped region, a second lightly doped region, and a second highly doped region disposed between the second doped region and the second lightly doped region. The first photodiode can be used to for measuring low light and the second photodiode can be used for measuring bright light. | 2015-06-25 |
20150179696 | PHOTODETECTOR CIRCUIT AND SEMICONDUCTOR DEVICE - To provide a photodetector circuit capable of obtaining signals in different periods without being affected by characteristics of a photoelectric conversion element. The photodetector circuit has n signal output circuits (n is a natural number of 2 or more) connected to the photoelectric conversion element. Further, the n signal output circuits each include the following: a transistor whose gate potential varies in accordance with the amount of light entering the photoelectric conversion element; a first switching element which holds the gate potential of the transistor; and a second switching element which controls a signal output from the transistor. Thus, after data based on the amount of light entering the photoelectric conversion elements is held as the gate potentials of the transistors, the second switching elements are turned on, whereby signals in different periods can be obtained without being affected by characteristics of the photoelectric conversion element. | 2015-06-25 |
20150179697 | SEMICONDUCTOR INTEGRATED CIRCUIT, ELECTRONIC DEVICE, SOLID-STATE IMAGING APPARATUS, AND IMAGING APPARATUS - A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate. | 2015-06-25 |
20150179698 | IMAGING APPARATUS, IMAGING SYSTEM AND MANUFACTURING METHOD OF IMAGING APPARATUS - A junction type field effect transistor (JFET) in a substrate includes channel and source regions of a first conductivity type and first through fourth gate regions of a second conductivity type. The first and second gate regions are disposed in a direction along a surface of the substrate. The third and fourth gate regions are disposed in the direction. The first and third gate regions are disposed in a depth direction. The first gate region is disposed between the surface and the third gate region. The second and fourth gate regions are disposed in the depth direction. The second gate region is disposed between the surface and the fourth gate region. The channel region includes a first region disposed between the first and third gate regions and a second region disposed between the second and fourth gate regions. The source region is disposed between the first and second gate regions. | 2015-06-25 |