25th week of 2013 patent applcation highlights part 52 |
Patent application number | Title | Published |
20130157366 | Rotation System for Cell Growth Chamber of a Cell Expansion System and Method of Use Therefor - A system and method for rotating a cell growth chamber of a cell expansion system includes a rotatable member for engaging a chamber coupling attached to the cell growth chamber. The rotatable member includes an independently operable mechanism for engaging a rotatable fitting associated with the chamber coupling. In at least one embodiment, the chamber coupling is selectively rotatable by turning the rotatable member, thereby rotating the cell growth chamber around a first axis. The cell growth chamber is also selectively rotatable around a second axis by turning the rotatable fitting associated with the chamber coupling. Other novel aspects include a way of attaching the cell growth chamber to the shaft assembly, and a new tube routing clip. | 2013-06-20 |
20130157367 | NANOFIBERS WITH EXCELLENT BIODEGRADABILITY AND BIOCOMPATIBILITY AND METHOD FOR PRODUCING THE SAME - The invention provides a method for producing nanofibers of an aliphatic polyester resin (a biodegradable resin) with higher productivity than heretofore achieved, for example, without the need of cumbersome steps such as drawing and with operability at normal temperature. The method for producing nanofibers according to the invention includes (1) an extrusion step of extruding an organic solvent solution (S) into filaments in an aqueous solution (W) including a surfactant (SF) and water, the organic solvent solution (S) including an aliphatic polyester resin (A | 2013-06-20 |
20130157368 | INDUCED PLURIPOTENT STEM CELLS PREPARED FROM HUMAN KIDNEY-DERIVED CELLS - We have disclosed an induced pluripotent stem cell and the method of preparing the induced pluripotent stem cell from a human kidney-derived cell. More particularly, we have disclosed a human kidney-derived iPS cell which may be differentiated into cells of ectoderm, mesoderm, and endoderm lineages. | 2013-06-20 |
20130157369 | METHOD FOR IMPROVED TRANSFORMATION USING AGROBACTERIUM - Methods to increase transformation frequency in plants when using | 2013-06-20 |
20130157370 | Transformation Vector Comprising Transposon, Microorganisms Transformed with the Vector, and Method for Producing L-Lysine Using the Microorganism - The present invention relates to a transformation vector comprising the partial fragments of a gene encoding transposase, a microorganism transformed with the vector, and a method of producing lysine using the microorganism. | 2013-06-20 |
20130157371 | Anaerobic Digestion Process Monitoring Device and Method Thereof - Disclosed herein are a device and method for accurately extracting individual organic acid and/or Total Volatile Fatty Acid (VFA), ammonium (NH | 2013-06-20 |
20130157372 | WASTE RAMP FOR REAGENT CARDS - An automated analyzer for reagent cards having a leading end, a trailing end and a length between the leading end and the trailing end comprises a travel surface assembly having a card travel surface and an edge. A test analyzing mechanism is adjacent to the travel surface, and a waste receptacle is adjacent to the edge below the travel surface. The waste receptacle has a side and a waste cavity. A ramp member positioned below the travel surface has an end and a sloped surface, and is movable between an extended position where the sloped surface extends into the waste cavity, and a retracted position where the end is spaced from the side a distance greater than the length of the reagent card. A moving mechanism operably coupled with the ramp member is configured to move the ramp member between the extended position and the retracted position. | 2013-06-20 |
20130157373 | SYSTEMS AND METHODS FOR HEMOGLOBIN ANALYSIS - Systems and methods for hemoglobin analysis. At least one embodiment of a stabilizing system comprises a stabilizing agent useful to completely or substantially prevent degradation or inactivation of a glycosylated hemoglobin (HbA1c) in a body fluid and a detection agent capable of detecting the HbA1c. | 2013-06-20 |
20130157374 | METHOD FOR QUANTIFYING THE AMOUNT OF CHOLESTEROL IN HIGH-DENSITY LIPOPROTEIN 3 - A method that enables quantification of cholesterol in high-density lipoprotein 3 (HDL3) in a test sample without requiring a laborious operation is disclosed. The method for quantifying cholesterol in HDL3 comprises: Step 1 wherein a surfactant that reacts with lipoproteins other than high-density lipoprotein 3 is reacted with a test sample to transfer cholesterol to the outside of the reaction system; and Step 2 wherein cholesterol remaining in the reaction system is quantified. The method enables specific quantification of HDL3 cholesterol in a test sample using an automatic analyzer without requirement of a laborious operation such as ultracentrifugation or pretreatment. Further, quantification of the HDL2 cholesterol level can also be carried out by subtracting the HDL3 cholesterol level from the total HDL cholesterol level obtained by a conventional method for quantifying the total HDL cholesterol in a test sample. | 2013-06-20 |
20130157375 | COMPOUND - In one aspect, there is provided a fluorescent iron-binding compound bound to a solid phase. Also provided is a method for detecting non-transferrin bound iron in a sample, comprising contacting the sample with a fluorescent iron-binding compound bound to a solid phase and detecting a fluorescent signal derived from the fluorescent iron-binding compound bound to the solid phase, wherein the fluorescent signal is indicative of non-transferrin bound iron levels in the sample. Further provided is use of a fluorescent iron-binding compound bound to a solid phase to detect non-transferrin bound iron in a sample. | 2013-06-20 |
20130157376 | Thermal Cycler Calibration Device and Related Methods - Methods, devices, and systems are provided for calibrating heat sources of thermal cyclers. | 2013-06-20 |
20130157377 | AMMONIA COMPOUND CONCENTRATION MEASURING DEVICE AND AMMONIA COMPOUND CONCENTRATION MEASURING METHOD - An ammonia compound concentration measuring device includes: a pipe unit through which the circulating gas flows; a converter which is disposed in the pipe unit and converts an ammonia compound into ammonia; a measurement device which measures a first measurement value as a concentration of ammonia contained in a first circulating gas flowing inside a pipe line passing through the converter in the circulating gas flowing inside the pipe unit and a second measurement value as a concentration of ammonia contained in a second circulating gas flowing inside a pipe line not passing through the converter in the circulating gas flowing inside the pipe unit; and a controller which controls operations of the pipe unit and the measurement device and calculates the concentration of the ammonia compound of the measurement subject contained in the circulating gas from a difference between the first measurement value and the second measurement value. | 2013-06-20 |
20130157378 | ATTENUATING DYE FOR INTERROGATING MULTIPLE SURFACES, AND METHOD THEREOF - A device including a shallow chamber for analyzing a plurality of target analytes in a body fluid using the signal generated by fluorescent detector molecules each specific for a target analyte, an attenuating dye for attenuating the signal emitted by fluorescent detector molecules specifically bound to the surfaces of the chamber other than an optically clear surface, and method for determining the signal generated by each of the plurality of analytes. | 2013-06-20 |
20130157379 | DIAGNOSTIC DETECTION DEVICES AND METHODS - Described herein are methods and devices for detecting the presence of an analyte in a liquid sample. In some embodiments, methods and devices for the detection of an antigen in a body fluid using a plurality of species-specific antibodies are provided. A sandwich complex may be formed using primary antibodies derived from two different species. | 2013-06-20 |
20130157380 | MULTIASSAY IMMUNOCHROMATOGRAPHIC CHIP - A multiassay immunochromatographic chip comprises: a viscous bottom lining ( | 2013-06-20 |
20130157381 | SAMPLE TESTING APPARATUS AND METHOD - Apparatus for performing an assay to detect the presence of an analyte in a test sample. A housing defines a slot for receiving a sample collector, and a capsule contains a buffer liquid, the capsule being sealed by an openable lid, and being connected to the housing such that insertion of a sample collector into the slot causes the lid to open releasing the buffer liquid into the slot. The housing further defines an incubation chamber containing or configured to receive a reagent, and an aperture permitting liquid communication between said slot and the incubation chamber. The apparatus comprises one or more test elements, a substantially liquid tight sealing member separating the incubation chamber and the test element(s), and an activation mechanism operable to open said liquid tight sealing member thereby bringing at least a portion of the or each test element into liquid communication with said incubation chamber. | 2013-06-20 |
20130157382 | PROFILE METHOD IN MAGNETIC WRITE HEAD FABRICATION - A method according to one embodiment includes depositing a dielectric hard mask layer above a polymer mask under-layer; forming a photoresist mask above the hard mask layer; transferring the image of the photoresist mask onto the hard mask layer using reactive ion etching, thereby defining a hard mask; determining that a critical dimension bias of the hard mask is within or outside a specification; and changing a level of an input source power used during a subsequent reactive ion etching step to move the critical dimension bias towards a target critical dimension bias when the critical dimension bias of the hard mask is outside the specification. Additional embodiments are also disclosed. | 2013-06-20 |
20130157383 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask. | 2013-06-20 |
20130157384 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a first insulation layer over a bottom layer, selectively removing a portion the first insulation layer to form a first trench that exposes the bottom layer, forming spacers on inner sidewalls of the first trench; forming a pillar-shaped second insulation layer in the first trench between the spacers, removing the spacers to form a second trench between the pillar-shaped second insulation layer and the first insulation layer, and burying a conductive layer in the second trench. | 2013-06-20 |
20130157385 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a bottom-electrode metal layer over a substrate, planarizing the bottom-electrode metal layer by a first thickness through a chemical mechanical polishing (CMP) process, etching the bottom-electrode metal layer by a second thickness through a wet etching process, forming a plurality of layers of a magnetic tunneling junction (MTJ) element over the bottom-electrode metal layer, forming a top electrode over the plurality of layers, and forming the MTJ element and a bottom electrode by etching the plurality of layers and the bottom-electrode metal layer using the top electrode as an etch mask. | 2013-06-20 |
20130157386 | SEMICONDUCTOR APPARATUS AND REPAIRING METHOD THEREOF - A semiconductor apparatus includes a semiconductor chip through-line for transmitting signals commonly to a plurality of stacked semiconductor chips. The apparatus includes a first test pulse signal transmission unit configured to transmit a first test pulse signal to a first end of the semiconductor chip through-line when a power-up operation is performed; a second test pulse signal transmission unit configured to transmit a second test pulse signal to a second end of the semiconductor chip through-line after the first test pulse signal is transmitted; a first signal reception unit coupled to the first end of the semiconductor chip through-line, and configured to receive signals transmitted from the first and second test pulse signal transmission units; and a second signal reception unit coupled to the second end of the semiconductor chip through-line, and configured to receive the signals transmitted by the first and second test pulse signal transmission units. | 2013-06-20 |
20130157387 | Multi-zone EPD Detectors - The present disclosure relates to a semiconductor body etching apparatus having a multi-zone end point detection system. In some embodiments, the multi-zone end point detection system has a processing chamber that houses a workpiece that is etched according to an etching process. A plurality of end point detector (EPD) probes are located within the processing chamber. Respective EPD probes are located within different zones in the processing chamber, thereby enabling the detection of end point signals from multiple zones within the processing chamber. The detected end point signals are provided from the plurality of EPD probes to an advanced process control (APC) unit. The APC unit is configured to make a tuning knob adjustment to etching process parameters based upon the detected end point signals and to thereby account for etching non-uniformities. | 2013-06-20 |
20130157388 | ETCH RATE DETECTION FOR ANTI-REFLECTIVE COATING LAYER AND ABSORBER LAYER ETCHING - A method and apparatus for etching a photomask substrate with enhanced process monitoring is provided. In one embodiment, a method of determining an etching endpoint includes performing an etching process on a first tantalum containing layer through a patterned mask layer, directing a radiation source having a first wavelength from about 200 nm and about 800 nm to an area uncovered by the patterned mask layer, collecting an optical signal reflected from the area covered by the patterned mask layer, analyzing a waveform obtained the reflected optical signal reflected from the substrate from a first time point to a second time point, and determining a first endpoint of the etching process when a slope of the waveform is changed about 5 percent from the first time point to the second time point. | 2013-06-20 |
20130157389 | Multiple-Patterning Overlay Decoupling Method - A method for fabricating a semiconductor device is disclosed. An exemplary method includes forming a first structure in a first layer by a first exposure and determining placement information of the first structure. The method further includes forming a second structure in a second layer overlying the first layer by a second exposure and determining placement information of the second structure. The method further includes forming a third structure including first and second substructures in a third layer overlying the second layer by a third exposure. Forming the third structure includes independently aligning the first substructure to the first structure and independently aligning the second substructure to the second structure | 2013-06-20 |
20130157390 | ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - An ion implantation method includes transporting ions to a wafer as an ion beam, causing the wafer to undergo wafer mechanical slow scanning and also causing the ion beam to undergo beam fast scanning or causing the wafer to undergo wafer mechanical fast scanning in a direction perpendicular to a wafer slow scanning direction, irradiating the wafer with the ion beam by using the wafer slow scanning in the wafer slow scanning direction and the beam fast scanning of the ion beam or the wafer fast scanning of the wafer in the direction perpendicular to the wafer slow scanning direction, measuring a two-dimensional beam shape of the ion beam before ion implantation into the wafer, and defining an implantation and irradiation region of the ion beam by using the measured two-dimensional beam shape to thereby regulate the implantation and irradiation region. | 2013-06-20 |
20130157391 | METHODS AND SYSTEMS FOR INSPECTING BONDED WAFERS - A method of inspecting a bonded wafer | 2013-06-20 |
20130157392 | Method of Manufacturing Light Emitting Device - A method of manufacturing a light emitting device is provided which requires low cost, is easy, and has high throughput. The method of manufacturing a light emitting device is characterized in that: a solution containing a light emitting material is ejected to an anode or cathode under reduced pressure; a solvent in the solution is volatilized until the solution reaches the anode or cathode; and the remaining light emitting material is deposited on the anode or cathode to form a light emitting layer. A burning step for reduction in film thickness is not required after the solution application. Therefore, the manufacturing method, which requires low cost and is easy but which has high throughput, can be provided. | 2013-06-20 |
20130157393 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included. | 2013-06-20 |
20130157394 | LIGHT EMITTING SYSTEM WITH ADJUSTABLE WATT EQUIVALENCE - A light emitting diode assembly and method of manufacturing the same. The light emitting diode assembly has a heat sink. The assembly additionally has a platform assembly with a substrate having driving elements including a plurality of light emitting diode elements disposed thereon. The driving elements and light emitting diode elements are in electric communication with an AC input to produce an initial light output. The plurality of light emitting diodes emit an initial light output that is a first predetermined amount of lumens in a first lumen range and emit an initial light output that is a second predetermined amount of lumens in a second lumen range current is changed without the need to change the manufacturing process. | 2013-06-20 |
20130157395 | Light-Emitting Diode (LED) Package Systems - A package system includes a substrate having at least one first thermally conductive structure through the substrate. At least one second thermally conductive structure is disposed over the at least one first thermally conductive structure. At least one light-emitting diode (LED) is disposed over the at least one second thermally conductive structure. | 2013-06-20 |
20130157396 | METHOD OF FORMING ENCAPSULATION SUBSTRATE FOR AN ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode (OLED) display device and method of fabrication that includes a substrate having a device region, an outer dam region and an encapsulation region. The encapsulation region includes an inner dam region, an outer dam region and an encapsulation region that correspond to the device region. An encapsulation agent is formed in the encapsulation region of the encapsulation substrate, and filling dams are formed of the same material in the outer dam region and the inner dam region of the encapsulation substrate. | 2013-06-20 |
20130157397 | MANUFACTURING METHOD, SURFACE-EMITTING LASER DEVICE, SURFACE-EMITTING LASER ARRAY, OPTICAL SCANNER, AND IMAGE FORMING APPARATUS - A manufacturing method for manufacturing a surface-emitting laser device includes the steps of forming a laminated body in which a lower reflecting mirror, a resonator structure including an active layer, and an upper reflecting layer having a selective oxidized layer are laminated on a substrate; etching the laminated body to form a mesa structure having the selective oxidized layer exposed at side surfaces thereof; selectively oxidizing the selective oxidized layer from the side surfaces of the mesa structure to form a constriction structure in which a current passing region is surrounded by an oxide; forming a separating groove at a position away from the mesa structure; passivating an outermost front surface of at least a part of the laminated body exposed when the separating groove is formed; and coating a passivated part with a dielectric body. | 2013-06-20 |
20130157398 | DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - To achieve promotion of stability of operational function of display device and enlargement of design margin in circuit design, in a display device including a pixel portion having a semiconductor element and a plurality of pixels provided with pixel electrodes connected to the semiconductor element on a substrate, the semiconductor element includes a photosensitive organic resin film as an interlayer insulating film, an inner wall face of a first opening portion provided at the photosensitive organic resin film is covered by a second insulating nitride film, a second opening portion provided at an inorganic insulating film is provided on an inner side of the first opening portion, the semiconductor and a wiring are connected through the first opening portion and the second opening portion and the pixel electrode is provided at a layer on a lower side of an activation layer. | 2013-06-20 |
20130157399 | DOUBLE GATE THIN-FILM TRANSISTOR AND OLED DISPLAY APPARATUS INCLUDING THE SAME - A double gate thin-film transistor (TFT), and an organic light-emitting diode (OLED) display apparatus including the double gate TFT, includes a double gate thin-film transistor (TFT) including: a first gate electrode on a substrate; an active layer on the first gate electrode; source and drain electrodes on the active layer; a planarization layer on the substrate and the source and drain electrodes, and having an opening corresponding to the active layer; and a second gate electrode in the opening. | 2013-06-20 |
20130157400 | Fabrication System and Manufacturing Method of Light Emitting Device - The present invention provides a vapor deposition method and a vapor deposition system of film formation systems by which EL materials can be used more efficiently and EL materials having superior uniformity with high throughput rate are formed. According to the present invention, inside a film formation chamber, an evaporation source holder in a rectangular shape in which a plurality of containers sealing evaporation material is moved at a certain pitch to a substrate and the evaporation material is vapor deposited on the substrate. Further, a longitudinal direction of an evaporation source holder in a rectangular shape may be oblique to one side of a substrate, while the evaporation source holder is being moved. Furthermore, it is preferable that a movement direction of an evaporation source holder during vapor deposition be different from a scanning direction of a laser beam while a TFT is formed. | 2013-06-20 |
20130157401 | METHOD FOR PRODUCING A SELECTIVE DOPING STRUCTURE IN A SEMICONDUCTOR SUBSTRATE IN ORDER TO PRODUCE A PHOTOVOLTAIC SOLAR CELL - A method for producing a selective doping structure in a semiconductor substrate in order produce a photovoltaic solar cell. The method includes the following steps: A) applying a doping layer ( | 2013-06-20 |
20130157402 | SOLAR CELL SYSTEM MANUFACTURING METHOD - A method for manufacturing a solar cell system includes the following steps. First, a number of P-N junction cell preforms are provided. The number of the P-N junction cell preforms is M. The M P-N junction cell preforms is named from a first P-N junction cell preform to a Mth P-N junction cell preform. Second, the M P-N junction cell preforms are arranged along a straight line. Third, an inner electrode preform is formed between each two adjacent P-N junction cell preforms, wherein at least one inner electrode is a carbon nanotube array. Axial directions of the carbon nanotubes in the carbon nanotube array are parallel to the straight line. | 2013-06-20 |
20130157403 | COMPOUNDS FOR PHOTOVOLTAICS - A species for use, for example, in a charge transfer layer of a photovoltaic device, the species comprising an acceptor group to which is fused a tuning group. The species can be a small molecule, polymer or oligomer, and monomers for producing said polymer, photovoltaic devices comprising said species, and methods for producing said device, are also provided. | 2013-06-20 |
20130157404 | DOUBLE-SIDED HETEROJUNCTION SOLAR CELL BASED ON THIN EPITAXIAL SILICON - One embodiment of the present invention provides a double-sided heterojunction solar cell. The solar cell includes a lightly doped epitaxial crystalline Si (c-Si) base layer, a front-side passivation layer situated on the front side of the lightly doped epitaxial c-Si base layer, a back-side passivation layer situated on the back side of the lightly doped epitaxial c-Si base layer, a front-side emitter situated on the surface of the front-side passivation layer, a back surface field (BSF) layer situated on the surface of the back-side passivation layer, a front-side electrode, and a back-side electrode. | 2013-06-20 |
20130157405 | MANUFACTURING METHODS FOR SEMICONDUCTOR DEVICES - A method of manufacturing semiconductor assemblies is provided. The manufacturing method includes thermally processing a first semiconductor assembly comprising a first semiconductor layer disposed on a first support and thermally processing a second semiconductor assembly comprising a second semiconductor layer disposed on a second support. The first and second semiconductor assemblies are thermally processed simultaneously, and the first and second semiconductor assemblies are arranged such that the first semiconductor layer faces the second semiconductor layer during the thermal processing. | 2013-06-20 |
20130157406 | LOW- COST SOLUTION APPROACH TO DEPOSIT SELENIUM AND SULFUR FOR CU(IN,GA)(SE,S)2 FORMATION - Methods of forming copper indium gallium diselenide (CIGS) layers for photovoltaic devices are disclosed. In one aspect, a solution based selenization method in the formation of CIGS is provided. In some embodiments a substrate containing elemental copper (Cu), indium (In) and gallium (Ga) is coated with a solution comprising a source of selenium (Se) dissolved in a solvent. After coating with the selenium based solution, the substrate is heated to form the CIGS layer. Coating of the substrate with the selenium based solution may be carried out by dip coating, slit casting, gap coating, ink-jet type coating, among other techniques. The solution based selenization method disclosed herein provides high material utilization and low cost, unlike vacuum based processes. | 2013-06-20 |
20130157407 | APPARATUS FOR INLINE PROCESSING OF Cu(In,Ga)(Se,S)2 EMPLOYING A CHALCOGEN SOLUTION COATING MECHANISM - Apparatus and method for the formation of copper indium gallium diselenide (CIGS) photovoltaic devices are disclosed. In one aspect, an inline production apparatus and method is described comprising sputter deposition and solution based selenization, followed by thermal annealing. Copper, indium and gallium are sputter deposited on one or more substrates in a sputter chamber. The substrates are then coated with a solution comprising a source of selenium in a selenium coating chamber. After coating with the selenium based solution, the substrates are heated in an annealing chamber to form a CIGS layer on the substrate. Substrates are conveyed though each of the chambers in a continuous manner, which provides for low-cost, fast throughput, inline production of CIGS photovoltaic devices. | 2013-06-20 |
20130157408 | ABSORBER LAYER FOR A THIN FILM PHOTOVOLTAIC DEVICE WITH A DOUBLE-GRADED BAND GAP - A gallium-containing alloy is formed on the light-receiving surface of a CIGS absorber layer, and, in conjunction with a subsequent selenization or anneal process, is converted to a gallium-rich region at the light-receiving surface of the CIGS absorber layer. A second gallium-rich region is formed at the back contact surface of the CIGS absorber layer during selenization, so that the CIGS absorber layer has a double-graded gallium concentration that increases toward the light-receiving surface and toward the back contact surface of the CIGS absorber layer. The double-graded gallium concentration advantageously produces a double-graded bandgap profile for the CIGS absorber layer. | 2013-06-20 |
20130157409 | SELECTIVE ATOMIC LAYER DEPOSITION OF PASSIVATION LAYERS FOR SILICON-BASED PHOTOVOLTAIC DEVICES - Embodiments of the invention generally provide methods for forming a silicon-based photovoltaic device. In one embodiment, a method includes forming a pattern inhibitor layer on a back surface of a substrate, wherein the pattern inhibitor layer covers a first portion of the back surface and a second portion of the back surface remains substantially free of the pattern inhibitor layer. The method further includes forming a passivation layer containing aluminum oxide on the second portion of the back surface and maintaining the pattern inhibitor layer substantially free of the passivation layer during a selective atomic layer deposition (S-ALD) process. Additionally, the method includes removing the pattern inhibitor layer from the back surface to reveal the first portion of the back surface and subsequently forming a contact layer on the first portion of the back surface. | 2013-06-20 |
20130157410 | Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions - Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals. | 2013-06-20 |
20130157411 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere. | 2013-06-20 |
20130157412 | CHIP ON WAFER BONDER - The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer. | 2013-06-20 |
20130157413 | SEMICONDUCTOR PACKAGE INCLUDING FLIP CHIP CONTROLLER AT BOTTOM OF DIE STACK - A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations. | 2013-06-20 |
20130157414 | STACKED-DIE PACKAGE AND METHOD THEREFOR - Consistent with an example embodiment, there is a semiconductor device comprised of a combination of device die. The semiconductor device comprises a package substrate having groups of pad landings. A first device die is anchored to the package substrate, the first device die having been wire-bonded to a first group of pad landings. At least one subsequent device die is anchored to the first device die. The at least one subsequent device die has an underside profile with recesses defined therein, the recesses of a size are defined to accommodate wires bonded to the first device die; the at least one subsequent device is wire bonded to a second group of pad landings. | 2013-06-20 |
20130157415 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - There is provided a method for producing a semiconductor device, capable of suppressing generation of voids at an interface between a semiconductor element and an under-fill sheet to produce a semiconductor device with high reliability. The method includes providing a sealing sheet having a support and an under-fill material laminated on the support; thermally pressure-bonding a circuit surface of a semiconductor wafer, on which a connection member is formed, and the under-fill material of the sealing sheet under conditions of a reduced-pressure atmosphere of 10000 Pa or less, a bonding pressure of 0.2 MPa or more and a heat pressure-bonding temperature of 40° C. or higher; dicing the semiconductor wafer to form a semiconductor element with the under-fill material; and electrically connecting the semiconductor element and the adherend through the connection member while filling a space between the adherend and the semiconductor element using the under-fill material. | 2013-06-20 |
20130157416 | METHODS OF FORMING A SEMICONDUCTOR DEVICE - A method and structure for a semiconductor device, the device including a handle wafer, a diamond layer formed directly on a front side of the handle wafer, and a thick oxide layer formed directly on a back side of the handle wafer, the oxide of a thickness to counteract tensile stresses of the diamond layer. Nitride layers are formed on the outer surfaces of the diamond layer and thick oxide layer and a polysilicon is formed on outer surfaces of the nitride layers. A device wafer is bonded to the handle wafer to form the semiconductor device. | 2013-06-20 |
20130157417 | METHOD OF MANUFACTURING SUBSTRATE FOR MOUNTING ELECTRONIC DEVICE - A method of manufacturing a substrate for mounting an electronic device, includes forming at least one through-hole in a plate-shaped substrate body in a thickness direction thereof. An electrode substrate having at least one core on an upper surface thereof is formed such that the at least one core corresponds to the at least one through-hole. The electrode substrate is coupled to the substrate body by inserting the at least one core into the at least one through-hole. A portion of the coupled electrode substrate is removed except for the at least one core. | 2013-06-20 |
20130157418 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base carrier; forming a conductive post on the base carrier, the conductive post having a top protrusion with a protrusion top side; mounting a base integrated circuit over the base carrier; and forming a base encapsulation over the base integrated circuit, the base encapsulation having an encapsulation top side and an encapsulation recess with the conductive post partially exposed within the encapsulation recess, the encapsulation top side above the protrusion top side. | 2013-06-20 |
20130157419 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The objective of the present invention is to provide a method of manufacturing a semiconductor device having less contamination of a semiconductor chip and good productivity. The present invention is a method of manufacturing a semiconductor device having a semiconductor chip, with the steps of preparing a plurality of semiconductor chips, preparing a resin sheet having a thermosetting resin layer, arranging the plurality of semiconductor chips on the thermosetting resin layer, arranging a cover film on the plurality of semiconductor chips, and embedding the plurality of semiconductor chips in the thermosetting resin layer by a pressure applied through the arranged cover film, in which the contact angle of the cover film to water is 90° or less. | 2013-06-20 |
20130157420 | Methods of Forming Graphene-Containing Switches - Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive structure may be formed to extend upwardly from the bottom electrode. Dielectric material may be formed along a sidewall of the first electrically conductive structure, while leaving a portion of the bottom electrode exposed. A graphene structure may be formed to be electrically coupled with the exposed portion of the bottom electrode. A second electrically conductive structure may be formed on an opposing side of the graphene structure from the first electrically conductive structure. A top electrode may be formed over the graphene structure and electrically coupled with the second electrically conductive structure. The first and second electrically conductive structures may be configured to provide an electric field across the graphene structure. | 2013-06-20 |
20130157421 | METHODS FOR THE FABRICATION OF INTEGRATED CIRCUITS INCLUDING BACK-ETCHING OF RAISED CONDUCTIVE STRUCTURES - Embodiments of a method for fabricating an integrated circuit are provided. In one embodiment, the method includes producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, and a gate stack over the channel region. At least one raised electrically-conductive structure is formed over at least one of the S/D regions and separated from the gate stack by a lateral gap. The raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance between the raised electrically-conductive structure and the gate stack during operation of the completed semiconductor device. | 2013-06-20 |
20130157422 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A highly reliable semiconductor device which includes a transistor including an oxide semiconductor is provided. In the semiconductor device including a bottom-gate transistor including an oxide semiconductor layer, a stacked layer of an insulating layer and an aluminum film is provided in contact with the oxide semiconductor layer. Oxygen doping treatment is performed in such a manner that oxygen is introduced to the insulating layer and the aluminum film from a position above the aluminum film, whereby a region containing oxygen in excess of the stoichiometric composition is formed in the insulating layer, and the aluminum film is oxidized to form an aluminum oxide film. | 2013-06-20 |
20130157423 | MOSFETs WITH REDUCED CONTACT RESISTANCE - A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor's source region and/or the transistor's drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy. | 2013-06-20 |
20130157424 | Method for improved mobility using hybrid orientaion technology (HOT) in conjunction with - A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation. | 2013-06-20 |
20130157425 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a cooling function component including an active region made of an impurity region and formed on a surface of a semiconductor layer, an N-type gate made of a semiconductor including an N-type impurity, a P-type gate made of a semiconductor including a P-type impurity, a first metal wiring connected to the N-type gate, the P-type gate and the active region, a second metal wiring connected to the P-type gate and the N-type gate, and a heat releasing portion connected to the second metal wiring for releasing heat to the outside. | 2013-06-20 |
20130157426 | METHOD FOR PRODUCING A CONDUCTIVE NANOPARTICLE MEMORY DEVICE - A method for producing a memory device with nanoparticles, comprising the steps of:
| 2013-06-20 |
20130157427 | ETCHING COMPOSITION AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - The present invention provides an etching composition, comprising a silyl phosphate compound, phosphoric acid and deionized water, and a method for fabricating a semiconductor, which includes an etching process employing the etching composition. The etching composition of the invention shows a high etching selectivity for a nitride film with respect to an oxide film. Thus, when the etching composition of the present invention is used to remove a nitride film, the effective field oxide height (EEH) may be easily controlled by controlling the etch rate of the oxide film. In addition, the deterioration in electrical characteristics caused by damage to an oxide film or etching of the oxide film may be prevented, and particle generation may be prevented, thereby ensuring the stability and reliability of the etching process. | 2013-06-20 |
20130157428 | Methods of Manufacturing Semiconductor Devices Including Transistors - A method of manufacturing a semiconductor device includes forming a gate insulation layer pattern on a substrate, forming a sacrificial layer including impurities on the gate insulation layer pattern, annealing the sacrificial layer so that the impurities in the sacrificial layer diffuse into the gate insulation layer pattern, removing the sacrificial layer, and forming a gate electrode on the gate insulation layer pattern. | 2013-06-20 |
20130157429 | HIGH VOLTAGE TRANSISTOR USING DILUTED DRAIN - An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations. | 2013-06-20 |
20130157430 | Electrostatic Discharge Protection Device and Method - Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well. | 2013-06-20 |
20130157431 | STRUCTURE AND METHOD FOR THERMAL TREATMENT WITH EPITAXIAL SICP THERMAL STABILITY IMPROVEMENT - The present disclosure provides a method for making an integrated circuit in one embodiment. The method includes providing a semiconductor substrate having an active region and a first gate stack disposed on the semiconductor substrate in the active region; forming in-situ phosphorous-doped silicon carbide (SiCP) features on the semiconductor substrate and disposed on sides of the first gate stack; replacing the first gate stack with a second gate stack having a high k dielectric material layer; and thereafter performing a millisecond annealing (MSA) process with a thermal profile having a first thermal wavelet and a second thermal wavelet. | 2013-06-20 |
20130157432 | ENHANCING INTEGRITY OF A HIGH-K GATE STACK BY PROTECTING A LINER AT THE GATE BOTTOM DURING GATE HEAD EXPOSURE - Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided. | 2013-06-20 |
20130157433 | METHODS FOR FORMING ELECTROSTATIC DISCHARGE PROTECTION CLAMPS WITH INCREASED CURRENT CAPABILITIES - Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 12013-06-20 | |
20130157434 | PHASE CHANGE MEMORY APPARATUS AND FABRICATION METHOD THEREOF - A phase change memory apparatus is provided that includes a first electrode of a bar type having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode. | 2013-06-20 |
20130157435 | Materials and Methods of Forming Controlled Void - The present invention is a process for forming an air gap within a substrate, the process comprising: providing a substrate; depositing a sacrificial material by deposition of at least one sacrificial material precursor; depositing a composite layer; removal of the porogen material in the composite layer to form a porous layer and contacting the layered substrate with a removal media to substantially remove the sacrificial material and provide the air gaps within the substrate; wherein the at least one sacrificial material precursor is selected from the group consisting of: an organic porogen; silicon, and a polar solvent soluble metal oxide and mixtures thereof. | 2013-06-20 |
20130157436 | FORMING THROUGH SUBSTRATE VIAS - A method is provided for establishing through substrate vias (TSVs) within a substrate. The method includes: forming at least one recess in a front-side of a wafer; filling, at least partially, the at least one recess with a sacrificial material from the front-side of the wafer; thinning the wafer from a back-side to reveal the at least one recess at least partially filled with the sacrificial material; removing from the back-side of the wafer the sacrificial material from the at least one recess; and filling the at least one recess from the back-side of the wafer with a conductive material to provide the at least one through substrate via. | 2013-06-20 |
20130157437 | PATTERN FORMING METHOD - According to one embodiment, firstly, an inversion pattern having a periodic pattern in which a first line pattern and a space are inversed and a non-periodic pattern arranged at an interval which is substantially equal to the width of the first line pattern from the end of the periodic pattern is formed above a processing object so as to correspond to the plurality of spaces between a plurality of first line patterns in a first pattern and the space between the first pattern and a second pattern. Next, a sidewall film is formed around the inversion pattern, and the periodic pattern is removed selectively. Thereafter, the processing object is etched using the sidewall pattern formed of the sidewall film and the non-periodic pattern surrounded by the sidewall film as masks. | 2013-06-20 |
20130157438 | SUBSTRATE HOLDING UNIT, SUBSTRATE BONDING APPARATUS, MULTI-LAYERED SUBSTRATE MANUFACTURING APPARATUS, SUBSTRATE BONDING METHOD, MULTI-LAYER SUBSTRATE MANUFACTURING METHOD, AND MULTI-LAYERED SEMICONDUCTOR APPARATUS MANUFACTURING METHOD - Provided is a substrate holding unit that holds a pair of substrates that are aligned and layered, comprising a first holding member that holds one of the substrates; a plurality of members to be joined that are connected to the first holding member; a second holding member that holds the other of the substrates to face the one of the substrates; a plurality of joining members that exert an adhesion force on the members to be joined and are connected to the second holding member at positions corresponding to positions of the members to be joined; and an adhesion restricting section that restricts the adhesion force until the substrates are aligned. | 2013-06-20 |
20130157439 | CHIP ASSEMBLY WITH A CORELESS SUBSTRATE EMPLOYING A PATTERNED ADHESIVE LAYER - A patterned adhesive layer including holes is employed to attach a coreless substrate layer to a stiffener. The patterned adhesive layer is confined to kerf regions, which are subsequently removed during singulation. Each hole in the patterned adhesive layer has an area that is greater than the area of a bottomside interconnect footprint of the coreless substrate. The patterned adhesive layer may include a permanent adhesive that is thermally curable or ultraviolet-curable. The composition of the stiffener can be tailored so that the thermal coefficient of expansion of the stiffener provides tensile stress to the coreless substrate layer at room temperature and at the bonding temperature. The tensile stress applied to the coreless substrate layer prevents or reduces warpage of the coreless substrate layer during bonding. Upon dicing, bonded stacks of a semiconductor chip and a coreless substrate can be provided without adhesive thereupon. | 2013-06-20 |
20130157440 | Composite wafer for fabrication of semiconductor devices - A composite wafer includes a first substrate having a first vertical thickness and a top surface, the top surface being prepared in a state for subsequent semiconductor material epitaxial deposition. A carrier substrate is disposed beneath the first substrate. The carrier substrate has a second vertical thickness greater than the first vertical thickness. An interlayer bonds the first substrate to the carrier substrate. | 2013-06-20 |
20130157441 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device fabricating method includes forming an etch target layer and a first hard mask layer over a substrate, forming a second hard mask pattern having lines over the first hard mask layer, forming a third hard mask layer over the second hard mask pattern, forming a sacrificial pattern over the third hard mask layer, forming a cell spacer on sidewalls of the sacrificial pattern, removing the sacrificial pattern, etching the third hard mask layer using the cell spacer as an etch barrier, etching the first hard mask layer using the third hard mask pattern and the second hard mask pattern as etch barriers, forming an elliptical opening having an axis pointing in a second direction by etching the etch target layer, and forming a silicon layer that fills the elliptical opening. | 2013-06-20 |
20130157442 | DEFECT REDUCTION IN SEEDED ALUMINUM NITRIDE CRYSTAL GROWTH - Bulk single crystal of aluminum nitride (AlN) having an areal planar defect density≦100 cm | 2013-06-20 |
20130157443 | PRODUCTION OF ELECTRONIC SWITCHING DEVICES - A technique of producing one or more electronic switching devices, each switching device comprising a semiconductor channel between two electrodes, and a dielectric element separating said semiconductor channel from a switching electrode, the method comprising: depositing onto a substrate a layer of material for at least partly forming said semiconductor channel or said dielectric element of said one or more switching devices by transferring said material onto said substrate from a rotating first roller. | 2013-06-20 |
20130157444 | SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a super junction structure includes: multiple first columns extending in a current flowing direction; and multiple second columns extending in the current flowing direction. The first and second columns are alternately arranged in an alternating direction. Each first column provides a drift layer. The first and second columns have a boundary therebetween, from which a depletion layer expands in case of an off-state. At least one of the first columns and the second columns have an impurity dose, which is inhomogeneous by location with respect to the alternating direction. | 2013-06-20 |
20130157445 | POLYCRYSTALLINE ALUMINUM NITRIDE BASE MATERIAL FOR CRYSTAL GROWTH OF GaN-BASE SEMICONDUCTOR AND METHOD FOR MANUFACTURING GaN-BASE SEMICONDUCTOR USING THE SAME - There is provided a polycrystalline aluminum nitride base material having a linear expansion coefficient similar to GaN. The polycrystalline aluminum nitride base material as a substrate material for crystal growth of GaN-base semiconductors has a mean linear expansion coefficient of 4.9×10 | 2013-06-20 |
20130157446 | SUBSTRATE SHEET - The invention provides a method for producing a flexible barrier sheet ( | 2013-06-20 |
20130157447 | SINGLE CRYSTAL SILICON TFTS MADE BY LATERAL CRYSTALLIZATION FROM A NANOWIRE SEED - A method can include depositing a thin metal film on a substrate of a sample, establishing a metal island on the substrate by patterning the thin metal film, and annealing the sample to de-wet the metal island and form a metal droplet from the metal island. The method can also include growing a nanowire on the substrate using the metal droplet as a catalyst, depositing a thin film of a semiconductor material on the sample, annealing the sample to allow for lateral crystallization to form a crystal grain, and patterning the crystal grain to establish a crystal island. An electronic device can be fabricated using the crystal island. | 2013-06-20 |
20130157448 | METHOD FOR MANUFACTURING A SILICON CARBIDE WAFER AND RESPECTIVE EQUIPMENT - An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer of the first material on the first layer. | 2013-06-20 |
20130157449 | METHOD FOR FORMING METAL GATE - A method for forming metal gates is provided. In the method, a substrate with a first region and a second region is provided. Dummy gate structures and an ILD layer is formed on the substrate. Dummy gates of the dummy gate structures are removed to form openings respectively within the two regions. Work function layers are respectively formed to overlay the openings. A metal layer is formed on the work function layers and then a CMP process is performed until the ILD layer is exposed, thereby forming the metal gates within the two regions at the same time. Only one CMP process is performed to the metal layer, so that over polishing of the ILD layer may be reduced and thickness of metal gates may be more accurately controlled. | 2013-06-20 |
20130157450 | Methods of Forming Metal Silicide Regions on Semiconductor Devices - Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer. | 2013-06-20 |
20130157451 | METHODS OF FORMING GATE STRUCTURES FOR REDUCED LEAKAGE - Integrated circuits containing transistors are provided. A transistor may include a gate structure formed over an associated well region. The well region may be actively biased and may serve as a body terminal. The well region of one transistor may be formed adjacent to a gate structure of a neighboring transistor. If the gate structure of the neighboring transistor and the well region of the one transistor are both actively biased and are placed close to one another, substantial leakage may be generated. Computer-aided design tools may be used to identify actively driven gate terminals and well regions and may be used to determine whether each gate-well pair is spaced sufficiently far from one another. If a gate-well pair is too close, the design tools may locate an existing gate cut layer and extend the existing gate cut layer to cut the actively driven gate structure. | 2013-06-20 |
20130157452 | SEMICONDUCTOR DEVICE INCLUDING POLYSILICON RESISTOR AND METAL GATE RESISTOR AND METHODS OF FABRICATING THEREOF - A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. | 2013-06-20 |
20130157453 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming first auxiliary patterns, alternately forming first material layers and second material layers on the sidewalls of the first auxiliary patterns so that a gap region between the first auxiliary patterns adjacent to each other is filled, removing the second material layers, and forming charge storage layers in respective regions from which the second material layers have been removed. | 2013-06-20 |
20130157454 | SELF-ALIGNED WET ETCHING PROCESS - A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators. | 2013-06-20 |
20130157455 | Electrical Contact Alignment Posts - An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly. | 2013-06-20 |
20130157456 | METHODS RELATING TO THE FABRICATION OF DEVICES HAVING CONDUCTIVE SUBSTRATE VIAS WITH CATCH-PAD ETCH-STOPS - An electronic device having a conductive substrate via extending between a conductor on a rear face and a conductor over a front face of the substrate includes a multi-layered etch-stop beneath the front surface conductor. The etch-stop permits use of a single etchant to penetrate both the substrate and any overlying semiconductor and/or dielectric without attacking the overlying front surface conductor. This is especially important when the semiconductor and dielectric are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop is preferably a stack of N≧2 pairs of sub-layers, where a first sub-layer comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer comprises etch resistant material (e.g., Ni). In a further embodiment, where the device includes field effect transistors having feedback sensitive control gates, the etch-stop material is advantageously used to form gate shields. | 2013-06-20 |
20130157457 | INTERCONNECTS FOR STACKED NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure. | 2013-06-20 |
20130157458 | SEMICONDUCTOR DEVICE HAVING A COPPER PLUG - Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer. | 2013-06-20 |
20130157459 | METHOD FOR FABRICATING INTERCONNECTING LINES INSIDE VIA HOLES OF SEMICONDUCTOR DEVICE - A method for fabricating interconnecting lines inside via holes of a semiconductor device comprises steps of providing a template having a receiving trench and a connection surface both on the same side of the template; filling an electric-conduction material into the receiving trench; connecting a substrate having at least one via hole with the connection surface to interconnect the via hole with the receiving trench; heating the electric-conduction material to a working temperature to liquefy a portion of the electric-conduction material and make it flows from the receiving trench into the via hole; and cooling the electric-conduction material to form an interconnecting line inside the via hole. The present invention fabricates interconnecting lines by a heat-forming method, which features simple steps and has advantages of shorter fabrication time, lower fabrication complexity, higher fabrication efficiency, higher yield and lower fabrication cost. | 2013-06-20 |
20130157460 | METHODS FOR ANNEALING A METAL CONTACT LAYER TO FORM A METAL SILICIDATION LAYER - Methods for annealing a contact metal layer for a metal silicidation process are provided in the present invention. In one embodiment, a method for annealing a contact metal layer for a silicidation process in a semiconductor device includes providing a substrate having a contact metal layer disposed thereon in a thermal annealing processing chamber, providing a heat energy to the contact metal layer in the thermal processing chamber, supplying a gas mixture including a nitrogen gas and a hydrogen gas while providing the heat energy to the contact layer in the thermal processing chamber, wherein the nitrogen gas and the hydrogen gas is supplied at a ratio between about 1:10 and about 1:1, and forming a metal silicide layer on the substrate. | 2013-06-20 |
20130157461 | METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - A method for fabricating a semiconductor device includes forming an etch-target layer over a substrate having a first region and a second region, stacking first and second hard mask layers over the etch-target layer, forming spacer patterns over the second hard mask layer of the first area, etching the second hard mask layer using the spacer patterns as an etch barrier, forming a hard mask pattern over the first hard mask layer of the second region, etching the first hard mask layer using the second hard mask layer of the first region and the hard mask pattern of the second region as etch barriers, removing the hard mask pattern of the second region, and etching the etch-target layer using the first and second hard mask layers of the first region and the first hard mask layer of the second region as etch barriers. | 2013-06-20 |
20130157462 | METHOD OF FORMING PATTERN FOR SEMICONDUCTOR DEVICE - The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element. | 2013-06-20 |
20130157463 | NEAR-INFRARED ABSORBING FILM COMPOSITION FOR LITHOGRAPHIC APPLICATION - The present invention relates to a near-infrared (NIR) film composition for use in vertical alignment and correction in the patterning of integrated semiconductor wafers and a pattern forming method using the composition. The NIR absorbing film composition includes a NIR absorbing dye having a polymethine cation and a crosslinkable anion, a crosslinkable polymer and a crosslinking agent. The patterning forming method includes aligning and focusing a focal plane position of a photoresist layer by sensing near-infrared emissions reflected from a substrate containing the photoresist layer and a NIR absorbing layer formed from the NIR absorbing film composition under the photoresist layer. The NIR absorbing film composition and the pattern forming method are especially useful for forming material patterns on a semiconductor substrate having complex buried topography. | 2013-06-20 |
20130157464 | PLANARIZING METHOD - According to one embodiment, a planarizing method is proposed. In the planarizing method, a surface to be processed of an object to be processed including a silicon oxide film is planarized in a processing solution by bringing the surface to be processed into contact with or close proximity with the surface of a solid-state plate on which fluorine is adsorbed. The bonding energy between fluorine and the solid-state plate is lower than that between fluorine and silicon. | 2013-06-20 |
20130157465 | METHODS FOR STRIPPING PHOTORESIST AND/OR CLEANING METAL REGIONS - Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma. | 2013-06-20 |