21st week of 2016 patent applcation highlights part 57 |
Patent application number | Title | Published |
20160148817 | GALLIUM NITRIDE SUBSTRATE AND OPTICAL DEVICE USING THE SAME - A method of processing a gallium nitride substrate, includes providing a gallium nitride substrate, polishing a surface of the gallium nitride substrate, and cleaning the polished surface of the gallium nitride substrate. The polished surface includes a GaLα/CKα peak intensity ratio in energy dispersive X-ray microanalysis (EDX) spectrum which is not less than 2, the EDX spectrum being obtained in an EDX of the surface of the gallium nitride substrate using a scanning electron microscope (SEM) at an accelerating voltage of 3 kV. | 2016-05-26 |
20160148818 | TITANIUM OXIDE FILM REMOVAL METHOD AND APPARATUS - In a titanium oxide film removal method and apparatus, a silicon substrate having the titanium oxide film is supported on a spin chuck. A first mixed aqueous solution including hydrofluoric acid and non-oxidizing acid or a second mixed aqueous solution including hydrofluoric acid and organic acid is supplied to the silicon substrate while rotating the silicon substrate together with the spin chuk. The first or the second aqueous solution comes into contact with the titanium oxide film existing on the silicon substrate to remove the titanium oxide film by a reaction between the first or the second mixed aqueous solution and the titanium oxide film. | 2016-05-26 |
20160148819 | Method for Producing a Material-Bonding Connection between a Semiconductor Chip and a Metal Layer - A method for producing a material-bonding connection between a semiconductor chip and a metal layer is disclosed. For this purpose, a semiconductor chip, a metal layer, which has a chip mounting portion, and also a bonding medium containing a metal powder are provided. The metal powder is sintered in a sintering process. In this case, throughout a prescribed sintering time, the prescribed requirements are met, that the bonding medium is arranged between the semiconductor chip and the metal layer and extends right through from the semiconductor chip to the metal layer, that the semiconductor chip and the metal layer are pressed against one another in a pressing-pressure range that lies above a minimum pressing pressure, that the bonding medium is kept in a temperature range that lies above a minimum temperature and that a sound signal is introduced into the bonding medium. | 2016-05-26 |
20160148820 | PACKAGE-ON-PACKAGE STRUCTURES AND METHODS OF MANUFACTURE THEREOF - A method for manufacturing a package-on-package structure may include: providing a support structure having a package attached to an inclined surface of the support structure, the package comprising: a first chip package; a second chip package disposed over the first chip package; and a standoff gap between the first chip package and the second chip package, wherein a first side of the package is disposed higher on the inclined surface of the support structure than a second side of the package; and dispensing an underfill into the standoff gap, the underfill flowing through the standoff gap from the first side of the package to the second side of the package. | 2016-05-26 |
20160148821 | METHODS AND SYSTEMS TO ENHANCE PROCESS UNIFORMITY - A semiconductor processing chamber may include a remote plasma region, and a processing region fluidly coupled with the remote plasma region. The processing region may be configured to house a substrate on a support pedestal. The support pedestal may include a first material at an interior region of the pedestal. The support pedestal may also include an annular member coupled with a distal portion of the pedestal or at an exterior region of the pedestal. The annular member may include a second material different from the first material. | 2016-05-26 |
20160148822 | SUBSTRATE CARRIER USING A PROPORTIONAL THERMAL FLUID DELIVERY SYSTEM - A substrate carrier is described that uses a proportional thermal fluid delivery system In one example the apparatus includes a heat exchanger to provide a thermal fluid to a fluid channel of a substrate carrier and to receive the thermal fluid from the fluid channel, the thermal fluid in the fluid channel to control the temperature of the carrier during substrate processing. A proportional valve controls the rate of flow of thermal fluid from the heat exchanger to the fluid channel, A temperature controller receives a measured temperature from a thermal sensor of the carrier and controls the proportional valve in response to the measured temperature to adjust the rate of flow. | 2016-05-26 |
20160148823 | BAKING DEVICE FOR A WAFER COATED WITH A COATING CONTAINING A SOLVENT - A baking device for a wafer coated with a coating containing a solvent is described, having a baking chamber, a support for the wafer, an inlet for a purge gas, and an evacuation for the purge gas charged with solvent evaporated from the coating. The inlet is formed as a diffusion element arranged above the wafer so as to admit the purge gas evenly over substantially the entire surface of the wafer, and the evacuation is formed as an evacuation ring which radially surrounds the diffusion element and is arranged at a ceiling of the baking chamber. | 2016-05-26 |
20160148824 | Method and Apparatus of Manufacturing a Semiconductor Device by Forming a Film on a Substrate - Provided is a technique including forming a film by performing a cycle a predetermined number of times. The cycle includes: (a) forming a discontinuous first layer including the first element and having a thickness of less than one atomic layer on the substrate by supplying a gas containing the first element into a process vessel accommodating the substrate; and (b) forming a second layer including the first element and the second element by supplying a gas containing the second element into the process vessel to modify the first layer under a condition where a modifying reaction of the first layer by the gas containing the second element is not saturated. | 2016-05-26 |
20160148825 | SUBSTRATE STORING CONTAINER - The lateral substrate support part has: a plurality of plate parts, which have a parallel positional relationship, and support end portions of a plurality of substrates; and a plate-part support part, which supports the plate part, and is fixed to a side wall. The plate-part support part has: a groove-forming portion having a groove formed therein, said groove linearly extending over the whole plate parts in the direction intersecting the plate parts; a protrusion, which is formed in the groove, and which protrudes such that the protrusion reduces the width of the groove in the direction orthogonal to the direction in which the groove extends; and a positioned part that is formed at a center portion of the groove in the direction in which the groove extends. | 2016-05-26 |
20160148826 | DEVICE AND METHOD FOR ALIGNING SUBSTRATES - A method for alignment and contact-making of a first substrate with a second substrate using several detection units as well as a corresponding device. | 2016-05-26 |
20160148827 | SUBSTRATE PROCESSING SYSTEM - A substrate processing system includes: a holding plate provided to be rotatable around a vertical axis; a substrate holding member provided on the holding plate to hold a substrate; a rotary drive unit that rotates the substrate in a predetermined direction; and a processing fluid supply unit that supplies a processing liquid to the substrate. The substrate holding member includes a first side portion provided at a position facing the substrate and a second side portion and a third side portion that are adjacent to the first side portion. The first side portion includes a gripping portion configured to grip an end surface of the substrate. The second side portion forms a pointed end portion with the first side portion, and includes a liquid flow guide portion that guides the processing liquid to a lower side of the substrate after the processing liquid is supplied to the substrate. | 2016-05-26 |
20160148828 | DETACHABLE HIGH-TEMPERATURE ELECTROSTATIC CHUCK ASSEMBLY - A detachable high-temperature electrostatic chuck assembly including a chuck body for supporting a substrate, an interface plate coupled to the chuck body by a sealing ring, the sealing ring defining a pocket between the chuck body and the interface plate that is sealed from a surrounding vacuum environment, and a cooling plate disposed between the chuck body and the interface plate. An interface between the chuck body and the cooling plate is located within the pocket. | 2016-05-26 |
20160148829 | DEVICE AND METHOD FOR TRANSFERRING SUBSTRATE FOR FORMING COMPUND SEMICONDUCTOR FILM, AND SYSTEM AND METHOD FOR FORMING COMPUND SEMICONDUCTOR FILM - A transferring device includes a supporting part configured to support a substrate holder, an elevation member configured to raise and lower a substrate at a substrate holding portion of the substrate holder, and a shielding member configured to be raised and lowered by the elevation member. The shielding member is interposed between the substrate and the elevation member when the elevation member receives the substrate. When the substrate is held on the substrate holding portion, the shielding member shields, at a backside of the substrate, a hole in the substrate holder through which the elevation member is inserted. In a state where the elevation member is raised, the substrate is mounted on the shielding member, or the substrate on shielding member is transferred therefrom. | 2016-05-26 |
20160148830 | SUBSTRATE TRANSFER SYSTEM AND SUBSTRATE PROCESSING SYSTEM - A substrate transfer system includes a substrate transfer robot. The substrate transfer robot is provided between a first apparatus and a second apparatus which has a wall provided opposite to the substrate transfer robot and having an opening on the wall. The substrate transfer robot is configured to transfer a substrate from the first apparatus to the second apparatus via the opening and includes a base having a first axis, an arm body, and a hand. The arm body has a proximal end and a distal end and is connected to the base at the proximal end to rotate around the first axis. The substrate transfer robot includes a minimum distance from the first axis to an outermost portion of the arm body and the hand in a radius direction from the first axis being larger than a distance between the first axis and the opening on the wall. | 2016-05-26 |
20160148831 | Method and Apparatus to Assist the Processing of Deformed Substrates - A method and apparatus for detecting and handling deformed substrates, thus allowing them to be processed, and for increasing device yield on the substrate is herein disclosed. A sensor detects deformity, then the substrate is flattened, allowing a support to hold it securely. | 2016-05-26 |
20160148832 | SEMICONDUCTOR DEVICE WITH BURIED LOCAL INTERCONNECTS - Embodiments of the present invention provide methods for fabricating a semiconductor device with buried local interconnects. One method may include providing a semiconductor substrate with fins etched into the semiconductor substrate; forming a first set of spacers along the sides of the fins; depositing a tungsten film over the top surface of the substrate; etching the tungsten film to form a buried local interconnect; forming a set of gates and a second set of spacers; forming a source and drain region adjacent to the fins; depositing a first insulating material over the top surface of the substrate; and creating contact between the set of gates and the source and drain region using an upper buried local interconnect. | 2016-05-26 |
20160148833 | SEMICONDUCTOR DEVICE HAVING A SHALLOW TRENCH ISOLATION STRUCTURE AND METHODS OF FORMING THE SAME - A method includes a patterned hard mask layer formed over a substrate. The substrate is etched using the patterned hard mask layer to form a trench therein but leaving at least one elongated portion of the substrate inside the trench. A first isolation layer is formed over the patterned hard mask layer. The first isolation layer fills the trench and covers the at least one elongated portion of the substrate. A portion of the first isolation layer is removed to expose the at least one elongated portion of the substrate. The at least one elongated portion of the substrate is thereafter removed to form a first opening. A second isolation layer is formed over the first opening, the patterned hard mask layer, and the first isolation layer, the second isolation layer sealing the first opening to form an air gap. | 2016-05-26 |
20160148834 | SOI WAFER FABRICATION METHOD AND SOI WAFER - An SOI wafer fabrication method includes a second process for forming an oxide layer by oxidizing a lamination surface of a support-substrate-forming wafer, third and fourth processes for forming a dopant-containing diffusion layer on a lamination surface of an active-layer-forming wafer and an oxide layer that is provided in contact with the diffusion layer and is capable of preventing the dopant from diffusing, and a fifth process for laminating the support-substrate-forming wafer and the active-layer-forming wafer at the lamination surfaces thereof and applying heat treatment to the laminated wafers. | 2016-05-26 |
20160148835 | SET OF STEPPED SURFACES FORMATION FOR A MULTILEVEL INTERCONNECT STRUCTURE - A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities. | 2016-05-26 |
20160148836 | Vias and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor device includes a first metal line in a first insulating layer, and a via having a portion surrounding a portion of a first sidewall of the first metal line. | 2016-05-26 |
20160148837 | METHOD OF TREATING A POROUS DIELECTRIC LAYER AND A METHOD OF FABRICATING A SEMICONDUCTOR DEVICE USING THE SAME - A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor. | 2016-05-26 |
20160148838 | ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE - Embodiments of the disclosure disclose an array substrate and a fabrication method thereof, and a display device. The fabrication method of the array substrate comprises: forming a thin film transistor; forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode; treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode; and forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer. | 2016-05-26 |
20160148839 | USE OF AN INHIBITOR MOLECULE IN CHEMICAL VAPOR DEPOSITION TO AFFORD DEPOSITION OF COPPER ON A METAL SUBSTRATE WITH NO DEPOSITION ON ADJACENT SIO2 SUBSTRATE - Provided herein are methods for selectively forming layers of metal films on one portion of a substrate while leaving adjacent portions of the substrate uncoated. The methods provide for selectively depositing metal films on a conductive surface, such as ruthenium oxide, disposed on or near an insulating portion of the substrate, such as a silicon dioxide (SiO | 2016-05-26 |
20160148840 | THROUGH SILICON VIAS AND THERMOCOMPRESSION BONDING USING INKJET-PRINTED NANOPARTICLES - Apparatus and method for filling and optionally bumping through-silicon vias (TSVs) in device circuits utilizing inkjet printheads for ejecting sufficiently small droplets of conductive nanoparticle inks into the TSVs. Ejected drops are accurately impinged along the length of each TSV within a substrate being heated to drive evaporation of the solvent carrying the metal nanoparticles into the trenches while not de-encapsulating the particles. Once all TSVs are filled, and optionally bumped, to a desired level while they are being heated then bonding and sintering can be performed, such as utilizing thermocompression bonding to another integrated circuit. | 2016-05-26 |
20160148841 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a first via having a first diameter in a first main surface of a semiconductor substrate having a first thickness, after forming a first insulating film on a bottom surface and a side surface of the first via, forming a first through electrode inside the first via a first barrier metal film, after forming the first through electrode, processing the semiconductor substrate from a second main surface on an opposite side of the first main surface to reduce the first thickness of the semiconductor substrate to a second thickness thinner than the first thickness, after processing the semiconductor substrate, forming a third insulating film on the second main surface of the semiconductor substrate, and after forming the third insulating film, sequentially processing the third insulating film and the semiconductor substrate. | 2016-05-26 |
20160148842 | DICING OF LOW-K WAFERS - Consistent with an example embodiment, there is a method for sawing a wafer substrate, the wafer substrate having a front-side surface containing active devices separated by saw lanes and a back-side surface having undergone back grinding, the saw lanes having process control monitor (PCM) devices present therein. The method comprises: with a blade of a first kerf, sawing the back-side surface in tracks corresponding to the saw lanes, to a first depth; laser grooving (LG) the saw lanes, to an LG depth, on the front-side surface of the wafer substrate until PCM devices are substantially removed, the LG having a preset beam diameter; and with a blade of a second kerf, the second kerf less than the first kerf, sawing the front-side surface of the wafer substrate about the center of the saw lanes until the active devices are separated from one another. | 2016-05-26 |
20160148843 | PACKAGE SUBSTRATE DIVIDING METHOD - A package substrate is divided into a plurality of device packages. An adhesive tape is attached to a back side of the substrate by cutting the substrate along a plurality of division lines formed on a front side of the substrate. The substrate includes a device portion partitioned into a plurality of device package regions by the division lines, and a marginal portion surrounding the device portion. A first ultraviolet light is applied to reduce the adhesive force of the adhesive tape in the marginal portion. The adhesive tape is partially peeled from the substrate in the marginal portion, and the substrate is cut along each division line by using a cutting blade to thereby divide the substrate into the device packages. In the dividing step, the marginal portion separated from the substrate is scattered by rotation of the cutting blade and thereby removed from the adhesive tape. | 2016-05-26 |
20160148844 | MOS Transistor Structure and Method - A method comprises depositing a first dielectric layer on a top surface of a substrate, implanting ions of a first conductivity type into the substrate, forming a first trench and a second trench in the substrate, forming a first gate in the first trench and a second gate in the second trench and forming a first drain/source region, a second drain/source region and a third drain/source region with the first conductivity type, wherein the first drain/source region and the second drain/source region are formed on opposing sides of the first gate and the third drain/source region and the second drain/source region are formed on opposing sides of the second gate. | 2016-05-26 |
20160148845 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer. | 2016-05-26 |
20160148846 | SEMICONDUCTOR STRUCTURE CONTAINING LOW-RESISTANCE SOURCE AND DRAIN CONTACTS - Semiconductor structures having a source contact and a drain contact that exhibit reduced contact resistance and methods of forming the same are disclosed. In one embodiment of the present application, the reduced contact resistance is provided by forming a layer of a dipole metal or metal-insulator-semiconductor (MIS) oxide between an epitaxial semiconductor material (providing the source region and the drain region of the device) and an overlying metal semiconductor alloy. In yet other embodiment, the reduced contact resistance is provided by increasing the area of the source region and drain region by patterning the epitaxial semiconductor material that constitutes at least an upper portion of the source region and drain region of the device. | 2016-05-26 |
20160148847 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes preparing a semiconductor substrate having a first and a second voltage device portion, each including a first and a second conductive type MOS region, forming a first gate insulating layer on the first and the second voltage device portion, removing the first gate insulating layer from the first conductive type MOS region of the first voltage device portion to expose a part of the semiconductor substrate, forming a first semiconductor layer on the first conductive type MOS region of the first voltage device portion, and removing the first gate insulating layer from the second conductive type MOS region of the first voltage device portion to expose a part of the semiconductor substrate. | 2016-05-26 |
20160148848 | METHODS FOR EXTREME ULTRAVIOLET MASK DEFECT MITIGATION BY MULTI-PATTERNING - Methods for extreme ultraviolet (EUV) mask defect mitigation by using multi-patterning lithography techniques. In one exemplary embodiment, a method for fabricating an integrated circuit including identifying a position of a defect in a first EUV photolithographic mask, the photolithographic mask including a desired pattern and transferring the desired pattern to a photoresist material disposed on a semiconductor substrate. Transferring the desired pattern further transfers an error pattern feature to the photoresist material as a result of the defect in the first EUV photolithographic mask. The method further includes, using a second photolithographic mask, transferring a trim pattern to the photoresist material, wherein the trim pattern removes the error pattern feature from the photoresist material. | 2016-05-26 |
20160148849 | VOLTAGE CONTRAST CHARACTERIZATION STRUCTURES AND METHODS FOR WITHIN CHIP PROCESS VARIATION CHARACTERIZATION - A method for designing, a structure, method of inspecting and a computer system for designing voltage contrast integrated circuit characterization. The design method includes selecting a design level of a mask design shapes file; selecting a region of the design level having an open region having no design shapes and an adjacent circuit region having circuit design shapes; selecting a sub-region of the circuit region adjacent to the open region; copying design shapes of the sub-region to generate a characterization cell identical to the sub-region; modifying the characterization cell to generate a passive voltage contrast characterization cell; and placing the passive voltage contrast characterization cell into the open region adjacent to the sub-region to generate a modified design level. | 2016-05-26 |
20160148850 | PROCESS CONTROL TECHNIQUES FOR SEMICONDUCTOR MANUFACTURING PROCESSES - Techniques for measuring and/or compensating for process variations in a semiconductor manufacturing processes. Machine learning algorithms are used on extensive sets of input data, including upstream data, to organize and pre-process the input data, and to correlate the input data to specific features of interest. The correlations can then be used to make process adjustments. The techniques may be applied to any feature or step of the semiconductor manufacturing process, such as overlay, critical dimension, and yield prediction. | 2016-05-26 |
20160148851 | DRY ETCHING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A first etching rate of the first conductive film is calculated by acquiring correlation between an opening ratio of an etching mask and an etching rate of an etching target film, and then, performing a first dry etching to a first conductive film formed on a first wafer. Next, a second etching mask is formed on a second conductive film formed on a second wafer, and an etching time of the second conductive film is determined from the correlation between the opening ratio and the etching rate, the first etching rate, and a film thickness of the second conductive film when the second conductive film is subjected to a second dry etching in time-controlled etching. | 2016-05-26 |
20160148852 | SEMICONDUCTOR DEVICE - An insertion vertical electrode region and part of a case-contact horizontal electrode region of an electrode insertion part of an external electrode is inserted and molded in an intra-case insertion region of a housing case. Inserting the case-contact horizontal electrode region, which serves as part of the electrode insertion part, in the intra-case insertion region allows the upper and lower surfaces of the case-contact horizontal electrode region to be in contact with the intra-case insertion region | 2016-05-26 |
20160148853 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate including a metal plate, an insulating plate, and a circuit plate laminated sequentially in order; a semiconductor element fixed to the circuit plate; a wiring member connected to an electrode provided on a surface of the semiconductor element, the circuit plate, or the electrode and the circuit plate; a plastic housing having a hollow shape to receive the insulating substrate, the semiconductor element, and the wiring member therein, the plastic housing having an inner frame on an inner surface and a step formed in a front end of the inner frame; and a sealing material made of a thermosetting resin to seal the insulating substrate, the semiconductor element, and the wiring member inside the plastic housing. | 2016-05-26 |
20160148854 | PACKAGING SUBSTRATE WITH BLOCK-TYPE VIA AND SEMICONDUCTOR PACKAGES HAVING THE SAME - A packaging substrate includes a core layer having a first surface and a second surface. A group of ground pads is disposed on the second surface within a central region. A group of first power pads is disposed on the second surface within the central region. A plurality of signal pads is disposed on the second surface within a peripheral region that encircles the central region on the second surface. A first block-type via is embedded in the core layer within the central region. The group of ground pads is electrically connected to the first block-type via. A second block-type via is embedded in the core layer within the central region. The group of first power pads is electrically connected to the second block-type via. | 2016-05-26 |
20160148855 | PACKAGING DEVICE AND MANUFACTURING METHOD THEREOF - A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode. | 2016-05-26 |
20160148856 | ELECTRONIC DEVICE HAVING HEAT CONDUCTING MEMBER - An electronic device includes a semiconductor module, a wiring substrate, a case member and a heat conducting member. The heat conducting member thermally connects predetermined portions of wiring patterns and a heat conducting pattern of the wiring substrate to a predetermined heat conduction region of a surface of the case member opposing to the wiring substrate. The predetermined heat conduction region is located further from the wiring substrate than a surface of a body portion opposing to the case member. The heat conducting pattern is disposed adjacent to at least one of non-terminal projecting surfaces of the body portion on a surface of the wiring substrate. The heat conducting pattern has a surface that is not covered with solder resist at least at a part. As a result, an area of a heat conducting passage increases and heat radiation performance can be increased. | 2016-05-26 |
20160148857 | Semicondutor Device and Method of Manufacture - A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die. | 2016-05-26 |
20160148858 | METHOD OF FORMING THROUGH-HOLE IN SILICON SUBSTRATE, METHOD OF FORMING ELECTRICAL CONNECTION ELEMENT PENETRATING SILICON SUBSTRATE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY - The present invention herein relates to a method of forming a through-hole in a silicon substrate. The present invention herein also relates to a method of forming an electrical connection element which penetrates through the silicon substrate, and to a semiconductor device manufactured thereby. More particularly, the present invention herein relates to a method of forming in a silicon substrate a through-hole capable of reducing roughness in a side wall of the through-hole and exhibiting low permittivity, by alternatingly laminating cationic and anionic polymer on the through-hole that has a dent on the side wall to form a porous elastic layer, and also relates to a method of forming an electrical connection that penetrates through the silicon substrate, and to a semiconductor device manufactured thereby. | 2016-05-26 |
20160148859 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points. | 2016-05-26 |
20160148860 | LEADFRAME BASED LIGHT EMITTER COMPONENTS AND RELATED METHODS - Leadframe based light emitter components and methods are provided. In some aspects, a leadframe based light emitter component includes a leadframe element, an electrical device connected to a portion of the leadframe element, and a molded cup encasing portions of the leadframe element and the electrical device connected thereto. A method of providing a leadframe based light emitter component includes providing a leadframe element, connecting an electrical device to a portion of the leadframe element, and molding a body over portions of the leadframe element and the electrical device. | 2016-05-26 |
20160148861 | FIRST-PACKAGED AND LATER-ETCHED THREE-DIMENSIONAL FLIP-CHIP SYSTEM-IN-PACKAGE STRUCTURE AND PROCESSING METHOD THEREFOR - A first-packaged and later-etched three-dimensional flip-chip system-in-package structure and a processing method thereof are provided. The package structure includes: a pad ( | 2016-05-26 |
20160148862 | SEMICONDUCTOR MODULE - A common connecting section for connection to terminals at the same potential in circuits is placed outside a mold section to allow a reduction in size of a semiconductor module | 2016-05-26 |
20160148863 | NON-CONTIGUOUS DUMMY STRUCTURE SURROUNDING THROUGH-SUBSTRATE VIA NEAR INTEGRATED CIRCUIT WIRES - A three-dimensional (3-D) integrated circuit wiring including a plurality of stacked dielectric levels formed on a substrate includes a plurality of non-contiguous dummy walls patterned in a corresponding dielectric level around a circuit wire keep out zone (KOZ). The non-contiguous dummy walls are formed in the circuit wire KOZ and have an outer side and an opposing inner side that extend along a first direction to define a length. A circuit wire segment is located at a first metal level and a second circuit wire segment is located at a second metal level different from the first metal level. The first and second metal levels are located adjacent the inner side of at least one non-contiguous dummy wall. | 2016-05-26 |
20160148864 | INTEGRATED DEVICE PACKAGE COMPRISING HETEROGENEOUS SOLDER JOINT STRUCTURE - Some features pertain to an integrated circuit device that includes a first package substrate, a first die coupled to the first package substrate, a second package substrate, and a solder joint structure coupled to the first package substrate and the second package substrate. The solder joint structure includes a solder comprising a first melting point temperature, and a conductive material comprising a second melting point temperature that is less than the first melting point temperature. In some implementations, the conductive material is one of at least a homogeneous material and/or a heterogeneous material. In some implementations, the conductive material includes a first electrically conductive material and a second material. The conductive material is an electrically conductive material. | 2016-05-26 |
20160148865 | Electronic Circuit Board, Semiconductor Device Using the Same and Manufacturing Method for the Same - The present invention aims to provide an electronic circuit board with insulation reliability improved by increasing volume resistivity of a ceramics substrate fabricated by an aerosol deposition method, a semiconductor device using it and a manufacturing method therefor. The present invention provides the electronic circuit board which includes a metal material, and an insulating film formed on a front surface of the metal material and including an inorganic material containing a crystal of a grain diameter of 10 to 20 nm and in which the insulating layer is less than 0.08 g/cm | 2016-05-26 |
20160148866 | ELECTRICAL INTERCONNECT FOR AN ELECTRONIC PACKAGE - Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a trench formed into one surface of the dielectric layer and a signal conductor that fills the trench and extends above the one surface of dielectric layer. The electrical interconnect further includes a conductive reference layer mounted on an opposing side of the dielectric layer. The conductive reference layer is electromagnetically coupled to the signal conductor when current passes through the signal conductor. | 2016-05-26 |
20160148867 | NANOSCALE INTERCONNECT STRUCTURE - An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is located above a first area of the undercut region. The first conductive structure comprises a first conductive metal portion having a diffusion barrier portion located on one sidewall surface of the first conductive metal portion and having a metal liner located on another sidewall surface and a bottom surface of the first conductive metal portion. A second conductive structure is located above a second area of the undercut region. The second conductive structure comprises a second conductive material portion having a diffusion barrier portion located on one sidewall surface of the second conductive material portion and having a metal liner located on another sidewall surface and a bottom surface of the second conductive metal portion. A gap is located between the first and second conductive structures. | 2016-05-26 |
20160148868 | PRECISION INTRALEVEL METAL CAPACITOR FABRICATION - A method for fabricating, within an integrated circuit (IC), a capacitor that includes a first plate formed within a recess of a metal layer that includes a second plate of the capacitor is disclosed. The method may include forming the second plate of the capacitor by creating, in a top surface of the metal layer, the recess having at least one side and a bottom and depositing a conformal dielectric film onto the at least one side and the bottom of the recess. The method may also include forming the first plate of the capacitor by filling a portion of the recess that is not filled by the conformal dielectric film with an electrically conductive material that is electrically insulated, by the conformal dielectric film, from the second plate. | 2016-05-26 |
20160148869 | METHOD AND STRUCTURE TO CONTACT TIGHT PITCH CONDUCTIVE LAYERS WITH GUIDED VIAS - An apparatus including a circuit substrate; a first interconnect layer in a first plane on the substrate and a second interconnect layer in a different second plane on the substrate; and a hardmask layer separating the first interconnect layer and the second interconnect layer, wherein the hardmask layer comprises alternating guide sections comprising different hard mask materials, and a via guide. A method including forming a dielectric layer on an integrated circuit structure; forming a first interconnect layer having interconnect lines in the dielectric layer; forming a hardmask layer on a surface of the dielectric layer, the hardmask layer comprising alternating hardmask materials which form guide sections over the interconnect lines; forming a via guide in one of the guide sections; and forming a second interconnect layer over the hardmask guide layer which is electrically connected to one of the interconnect lines through the via guide. | 2016-05-26 |
20160148870 | LOW-K DIELECTRIC PORE SEALANT AND METAL-DIFFUSION BARRIER FORMED BY DOPING AND METHOD FOR FORMING THE SAME - A diffusion barrier and a method to form the diffusion bather are disclosed. A trench structure is formed in an Inter Layer Dielectric (ILD). The ILD comprises a dielectric matrix having a first density. A dopant material layer is formed on the trench structure in which the dopant material layer comprises atoms of at least one of a rare-earth element. The ILD and the trench structure are annealed to form a dielectric matrix comprising a second density in one or more regions of the ILD on which the dopant material layer was formed that is greater than the first density. After annealing, the dielectric matrix comprising the second density includes increased bond lengths of oxygen-silicon bonds and/or oxygen-semiconductor bonds, increased bond angles of oxygen-silicon bonds and/or oxygen-semiconductor material bonds, and pores in the dielectric matrix are sealed compared to the dielectric matrix comprising the first density. | 2016-05-26 |
20160148871 | ELECTRONIC COMPONENT AND METHOD FOR PRODUCING THE SAME - An aspect of the invention is an electronic component including a semiconductor substrate | 2016-05-26 |
20160148872 | SEMICONDUCTOR DEVICE HAVING REDUCED CONTACT RESISTANCE - A semiconductor device including at least one self-aligned contact has at least one gate electrode on a bulk substrate layer of the semiconductor device. A gate cap encapsulates the at least one gate electrode. The semiconductor device further includes at least one contact separated from the at least one gate electrode via a portion of the gate cap. The at least one contact includes a metal portion that directly contacts the gate cap. | 2016-05-26 |
20160148873 | ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF - A method for fabricating an electronic package is provided, which includes the steps of: providing a substrate having a cavity and a first via hole; disposing an electronic element in the cavity; forming a dielectric layer on the substrate and the electronic element; forming a circuit layer on the dielectric layer and forming a first conductive portion in the first via hole; forming on the substrate a second via hole communicating with the first via hole, the first and second via holes constituting a through hole; and forming a second conductive portion in the second via hole, the first and second conductive portions constituting a conductor. Since the through hole is formed through a two-step process, the invention can reduce the depth of the via holes and therefore perform laser drilling or etching processes with reduced energy, thereby avoiding damage of the conductive portions and improving the product reliability. | 2016-05-26 |
20160148874 | Method for Forming Interconnect Structure that Avoids via Recess - A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features. | 2016-05-26 |
20160148875 | SEMICONDUCTOR ELEMENT SUBSTRATE, AND METHOD FOR PRODUCING SAME - A diffusion time when forming an isolation region is shortened without deteriorating strength against wafer cracks. A plurality of circular holes | 2016-05-26 |
20160148876 | FLAT NO-LEADS PACKAGE WITH IMPROVED CONTACT PINS - According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple. | 2016-05-26 |
20160148877 | QFN PACKAGE WITH IMPROVED CONTACT PINS - According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe, bonding the IC chip to at least some of the plurality of pins, encapsulating the leadframe and bonded IC chip, sawing a step cut into the encapsulated leadframe, plating the exposed portion of the plurality of pins, and cutting the IC package free from the bar. The leadframe may include a plurality of pins extending from the center support structure and a bar connecting the plurality of pins remote from the center support structure. The step cut may be sawn into the encapsulated leadframe along a set of cutting lines using a first saw width without separating the bonded IC package from the bar, thereby exposing at least a portion of the plurality of pins. The IC package may be cut free from the bar by sawing through the encapsulated lead frame at the set of cutting lines using a second saw width less than the first saw width. | 2016-05-26 |
20160148878 | SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR PATTERN STRUCTURE - A semiconductor pattern structure includes a substrate, an input/output (I/O) region defined on the substrate, a core region defined on the substrate, a dummy region defined on the substrate, and a gate electrode formed on the substrate. The dummy region is formed between the I/O region and the core region. The gate electrode crosses the I/O region and covers a portion of the dummy region. | 2016-05-26 |
20160148879 | METHOD FOR FABRICATING AN ELECTRONIC DEVICE AND A STACKED ELECTRONIC DEVICE - A method for fabricating an electronic device, and an electronic device in a stacked configuration, includes a rear face of an integrated-circuit chip that is fixed to a front face of a support wafer. A protective wafer is located facing and at a distance from the front face of the chip, and an infused adhesive is interposed between the chip and the protective wafer and located on a zone of the front face of the chip outside a central region of this front face. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. An obstruction barrier is arranged between the chip and the protective wafer and is disposed outside the central region of the front face of the chip. An encapsulation ring surrounds the chip, the protective wafer and the obstruction barrier. | 2016-05-26 |
20160148880 | ELECTRONIC DEVICE WITH STACKED CHIPS - An electronic device includes a first and a second integrated-circuit chip that are stacked at a distance from one another, and a plurality of electrical connection pillars and at least one protective barrier interposed between the chips. The protective barrier delimits a free space between mutually opposing local regions of the chips, and an encapsulation block extends around the chip that has the smaller mounting face and over the periphery of the mounting face of the other chip. The electrical connection pillars and the protective barrier are made of at least one identical metallic material with a view to simultaneous fabrication. | 2016-05-26 |
20160148881 | Semiconductor Packages - Semiconductor packages are provided. The semiconductor packages may include a base film having a top surface and a bottom surface, a circuit pattern disposed on the top surface of the base film and connected to a ground terminal, a via hole penetrating the base film, a lower shielding layer that is electrically connected to the circuit pattern and fills the whole region of the via hole and cover the bottom surface of the base. | 2016-05-26 |
20160148882 | Semiconductor Device and Method of Forming Holes in Substrate to Interconnect Top Shield and Ground Shield - A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die. | 2016-05-26 |
20160148883 | Bond Pad Having Ruthenium Covering Passivation Sidewall - A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads. | 2016-05-26 |
20160148884 | MEMORY APPARATUS HAVING POWER PAD - A memory apparatus includes a pad, an internal circuit that is connected with the pad, a power connection unit connected with power meshes, and a first switching unit suitable for selectively connecting the pad with the power connection unit based on a package control signal. | 2016-05-26 |
20160148885 | Cu Core Ball - A Cu core ball is provided that prevents any soft errors and decreases any connection failure. The Cu core ball includes a solder plating film formed on the surface of a Cu ball that is a Sn solder plating film or is made of a lead-free solder alloy, a principal ingredient of which is Sn. The solder plating film contains U of 5 ppb or less and Th of 5 ppb or less. The Cu ball has a purity of not less than 99.9% Cu and not more than 99.995% Cu. Pb and/or Bi contents therein are at a total of 1 ppm or more. The sphericity thereof is 0.95 or more. The obtained Cu core ball has an α dose of 0.0200 cph/cm | 2016-05-26 |
20160148886 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate layer, a redistribution layer (RDL) disposed over the substrate layer, a conductive bump disposed over the RDL, and a molding disposed over the RDL and surrounding the conductive bump, wherein the molding includes a protruded portion laterally protruded from a sidewall of the substrate layer and away from the conductive bump. | 2016-05-26 |
20160148887 | Device Package with Reduced Thickness and Method for Forming Same - A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and bonded to the interconnect structure. | 2016-05-26 |
20160148888 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor device may include a semiconductor substrate, a conductive pad on the semiconductor substrate, a passivation layer overlying the semiconductor substrate and exposing the conductive pad, and a bump structure. The bump structure may include a first bump structure on the conductive pad and a second bump structure on the passivation layer. The first bump structure may include a base bump layer, a first pillar bump layer, and a first solder bump layer that are sequentially stacked on the conductive pad. The second bump structure may include a second pillar bump layer and a second solder bump layer that are sequentially stacked on the passivation layer. | 2016-05-26 |
20160148889 | System and Method for an Improved Fine Pitch Joint - Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate. | 2016-05-26 |
20160148890 | Method and Apparatus for Cooling Semiconductor Device Hot Blocks and Large Scale Integrated Circuit (IC) Using Integrated Interposer for IC Packages - A method, system, and apparatus for improved IC device packaging is described. In an aspect, an (IC) device package includes an IC die having at one or more contact pads, each contact pad located at a corresponding hotspot on a surface of th28e IC die. The package also includes a thermally conductive interposer which is thermally coupled to the IC die at the contact pads. In another aspect, an underfill material fills a space between the IC die and the interposer. The interposer may also be electrically coupled to the IC die. In an aspect, the interposer and the IC die are coupled through thermal interconnects or “nodules.” | 2016-05-26 |
20160148891 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8. | 2016-05-26 |
20160148892 | SOLDER IN CAVITY INTERCONNECTION STRUCTURES - The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate. | 2016-05-26 |
20160148893 | WAFER LEVEL PACKAGING USING A CATALYTIC ADHESIVE - Wafer level packaging includes a first layer of a catalytic adhesive on a wafer surface. The catalytic adhesive includes catalytic particles that will reduce electroless copper (Cu) from Cu | 2016-05-26 |
20160148894 | CONDUCTIVE DIE ATTACH FILM FOR LARGE DIE SEMICONDUCTOR PACKAGES AND COMPOSITIONS USEFUL FOR THE PREPARATION THEREOF - Provided herein are conductive die attach films having advantageous properties for use in a variety of applications, e.g., for the preparation of large die semiconductor packages. Also provided are formulations useful for the preparation of such films, as well as methods for making such formulations. In additional aspects of the present invention, there are provided conductive networks prepared from compositions according to the present invention. In additional aspects, the invention further relates to articles comprising such conductive die attach films adhered to a suitable substrate therefor. | 2016-05-26 |
20160148895 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device, includes providing a wiring substrate having a first surface and a second surface, the first surface being provided with a plurality of leads, after the providing of the wiring substrate, arranging a semiconductor chip with a main surface, a plurality of electrode pads formed at the main surface, and a back surface opposite to the main surface, over the first surface of the wiring substrate such that the back surface of the semiconductor chip is opposed to the first surface of the wiring substrate, after the arranging of the semiconductor chip, electrically coupling the electrode pads formed along three out of four sides of the main surface of the semiconductor chip to the leads disposed at the first surface of the wiring substrate via a plurality of metal wires, and after the electrically coupling of the electrode pads, forming a seal body over the first surface of the wiring substrate. | 2016-05-26 |
20160148896 | SEMICONDUCTOR DEVICE WITH A WIRE BONDING AND A SINTERED REGION, AND MANUFACTURING PROCESS THEREOF - An electronic device includes: a semiconductor body; a front metallization region; a top buffer region, arranged between the front metallization region and the semiconductor body; and a conductive wire, electrically connected to the front metallization region. The top buffer region is at least partially sintered. | 2016-05-26 |
20160148897 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a corner constituted by a first side and a second side being perpendicular to the first side; and a plurality of pads including a first pad, arranged along the second side and formed over a semiconductor substrate. The first pad is arranged nearer the corner than other pads of the plurality of pads. The first pad includes a third side, a fourth side being perpendicular to the third side, a fifth side being parallel to the third side and a sixth side being perpendicular to a fifth side. The third side and the fourth side are nearer to the corner than the fifth side and sixth side. A first dummy wiring is formed along the first side. A second dummy wiring is formed along the second side. The first dummy wiring and the second dummy wiring are formed integrally with each other. | 2016-05-26 |
20160148898 | WIRE SPOOL SYSTEM FOR A WIRE BONDING APPARATUS - Disclosed is a wire spool system for a wire bonding apparatus, comprising: a wire reel arranged to receive a wire; a wire guide for feeding a free end of the wire to a bond head of the wire bonding apparatus; and a tensioning mechanism for tensioning the wire to define a wire path between the wire reel and the wire guide. The wire spool system comprises an imaging module comprising a camera having an image sensor. The imaging module also comprises an image processing unit. The camera is positioned to image, by said image sensor, at least a portion of the wire path to generate image data. The image processing unit is configured to process the image data to determine a geometry and/or a change in geometry of the at least a portion of the wire path. | 2016-05-26 |
20160148899 | METHOD OF DETERMINING CURING CONDITIONS, METHOD OF PRODUCING CIRCUIT DEVICE, AND CIRCUIT DEVICE - A method of determining curing conditions is for determining the curing conditions of a thermosetting resin to seal a conductive part between a substrate and an electronic component. A curing degree curve is created. The curing degree curve indicates, with respect to each of heating temperatures, relationship between heating time and curing degree of the thermosetting resin. On the basis of the created curing degree curve, a void removal time of a void naturally moving upward in the thermosetting resin, at a first heating temperature, is calculated. The first heating temperature is one of the heating temperatures. | 2016-05-26 |
20160148900 | METHOD FOR BONDING WITH A SILVER PASTE - Disclosed is a method for bonding with a silver paste, the method including: coating a silver paste on a semiconductor device or a substrate, the silver paste containing silver and indium; disposing the semiconductor on the substrate; and heating the silver paste to form a bonding layer, wherein the semiconductor device and the substrate are bonded to each other through the bonding layer, and wherein the indium is contained in the silver paste at 40 mole % or less. | 2016-05-26 |
20160148901 | INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES OF A PROCESSOR ARRAY - Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order. | 2016-05-26 |
20160148902 | THERMALLY-ENHANCED THREE DIMENSIONAL SYSTEM-IN-PACKAGES AND METHODS FOR THE FABRICATION THEREOF - Embodiments of three dimensional (3D) System-in-Package (SiPs) and methods for producing 3D SiPs having improved heat dissipation capabilities are provided. In one embodiment, the 3D SiP includes a heat-dissipating structure having a first principal surface and a second principal surface opposite the first principal surface. The backside of a first microelectronic device is disposed adjacent and thermally coupled to the first principal surface of the heat-dissipating structure, while the backside of a second microelectronic device is disposed adjacent and thermally coupled to the second principal surface of the heat-dissipating structure. During operation of the 3D SiP, heat generated by the microelectronic devices is conductively transferred to and dissipated through the heat-dissipating structure. | 2016-05-26 |
20160148903 | Integrated Circuit Packages and Methods of Forming Same - Packages and methods of manufacture thereof are described. A package may include a first package and a die structure disposed over the first package. The first package may include: a first encapsulant; a first via structure within the first encapsulant; a first die within the first encapsulant, at least a portion of the first encapsulant being interposed between a sidewall of the first die and a sidewall of the first via structure; a second die within the first encapsulant, an active side of the second die facing an active side of the first die; and a first via chip within the first encapsulant, the first via chip comprising one or more through vias, wherein the first via chip is disposed at the active side of the first die, and between the second die and the first via structure. | 2016-05-26 |
20160148904 | 3D INTEGRATION OF FANOUT WAFER LEVEL PACKAGES - Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer. | 2016-05-26 |
20160148905 | SEMICONDUCTOR CHIP FOR SENSING TEMPERATURE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - In one example embodiment, a semiconductor system includes a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor. The semiconductor system further includes a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information. | 2016-05-26 |
20160148906 | SEMICONDUCTOR PACKAGES AND FABRICATION METHOD THEREOF - A semiconductor package and a method of fabricating the same are provided. The semiconductor package may include a first semiconductor chip with a first circuit pattern, a second semiconductor chip disposed on the first semiconductor chip and provided with a second circuit pattern, and first and second connection structures penetrating the first and second semiconductor chips. The first connection structure may be electrically connected to the first circuit pattern and may be electrically disconnected from the second circuit pattern. The second connection structure may be electrically disconnected from the first circuit pattern and may be electrically connected to the second circuit pattern. | 2016-05-26 |
20160148907 | SEMICONDUCTOR DEVICE - One semiconductor device includes nine surface micro-bumps laid out in a 3×3 matrix on a semiconductor substrate, a transistor that contains first and second diffusion layers formed on the semiconductor substrate, and power-supply wiring laid out on the semiconductor substrate. The aforementioned first diffusion layer is connected to one of the surface micro-bumps, the second diffusion layer is connected to the power-supply wiring, and the transistor is laid out in the region between the surface micro-bumps located on one edge in an X direction and the surface micro-bumps located on the other edge in said X direction. | 2016-05-26 |
20160148908 | MULTI-CHIP PACKAGE SYSTEM - A multi-chip package system includes a signal transmission line commonly coupled to a plurality of semiconductor chips to transfer data to/from the semiconductor chips from/to outside; and a termination controller suitable for detecting a loading value of the signal transmission line and controlling a termination operation on the signal transmission line based on the loading value. | 2016-05-26 |
20160148909 | SEMICONDUCTOR PACKAGES HAVING THROUGH ELECTRODES AND METHODS OF FABRICATING THE SAME - Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively. | 2016-05-26 |
20160148910 | Semiconductor Device Having Plural Memory Chip - A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions. | 2016-05-26 |
20160148911 | ULTRA-SMALL LED ELECTRODE ASSEMBLY AND METHOD FOR MANUFACTURING SAME - Provided are a nano-scale LED assembly and a method for manufacturing the same. First, a nano-scale LED device that is independently manufactured may be aligned and connected to two electrodes different from each other to solve a limitation in which a nano-scale LED device having a nano unit is coupled to two electrodes different from each other in a stand-up state. Also, since the LED device and the electrodes are disposed on the same plane, light extraction efficiency of the LED device may be improved. Furthermore, the number of nano-scale LED devices may be adjusted. Second, since the nano-scale LED device does not stand up to be three-dimensionally coupled to upper and lower electrodes, but lies to be coupled to two electrodes different from each other on the same plane, the light extraction efficiency may be very improved. Also, since a separate layer is formed on a surface of the LED device to prevent the LED device and the electrode from being electrically short-circuited, defects of the LED electrode assembly may be minimized. Also, in preparation for the occurrence of the very rare defects of the LED device, the plurality of LED devices may be connected to the electrode to maintain the original function of the nano-scale LED electrode assembly. | 2016-05-26 |
20160148912 | SEMICONDUCTOR LIGHT-EMITTING DEVICE HAVING MATRIX-ARRANGED LIGHT-EMITTING ELEMENTS AND TRANSPARENT PLATES - A semiconductor light-emitting device includes a support body multiple, multiple light-emitting elements arranged in a matrix on the support body, a transparent resin layer provided on the light-emitting elements, multiple transparent plates provided on the transparent resin layer, each of the transparent plates being provided over one of the multiple light-emitting elements, and multiple optical shield layers each provided at one of a first side face of a first one of the transparent plates and a second the face of a second one of the transparent plates opposing the first the face of the first transparent plate. | 2016-05-26 |
20160148913 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal. | 2016-05-26 |
20160148914 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing a semiconductor package are provided. The semiconductor package includes a first substrate having electrodes are disposed on both surfaces thereof, one or more first elements mounted on a first surface of the first substrate, a first insulating member comprising an insulating material disposed on a first surface of the first substrate and affixing one or more first elements to the first surface of the first substrate, and one or more second elements mounted on a second surface of the first substrate. At least a portion of the first elements is externally exposed from the first insulating member. | 2016-05-26 |
20160148915 | LOW-IMPEDANCE POWER DELIVERY FOR A PACKAGED DIE - A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system. | 2016-05-26 |
20160148916 | METHOD AND STRUCTURE FOR RECEIVING A MICRO DEVICE - A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material. | 2016-05-26 |