20th week of 2012 patent applcation highlights part 67 |
Patent application number | Title | Published |
20120124313 | MULTI-CHANNEL MEMORY WITH EMBEDDED CHANNEL SELECTION - Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same. | 2012-05-17 |
20120124314 | RECORDING MEDIUM - A recording medium according to an embodiment includes: a storing section including a first area in which a number-of-reproductions limited file is written and a second area in which at least one determination address in an address range of the first area, in which the number-of-reproductions limited file is written, and a number of readable times of the number-of-reproductions limited file are written; and a control section configured not to perform, after the number of readouts of reading out of data in the at least one determination address reaches the number of readable times, output of the number-of-reproductions limited file in response to a readout request for the number-of-reproductions limited file. | 2012-05-17 |
20120124315 | METHOD OF MANAGING DATA ON A NON-VOLATILE MEMORY - Machine-reading media and method for managing data in a non-volatile memory. The method comprises the steps: a plurality of first logical offsets may be assigned to a plurality of first fragments of a first memory block, a first fragment of the plurality of first fragments may store data; a plurality of second logical offsets may be assigned to a plurality of second fragments of a second memory block, a second fragment of the plurality of second fragments may be associated with the first fragment, a second logical offset assigned to the second fragment may be identical to a first logical offset assigned to the first fragment; then, data may be copied from the first fragment to the second fragment. | 2012-05-17 |
20120124316 | LEAKAGE REDUCTION IN STORAGE ELEMENTS VIA OPTIMIZED RESET STATES - Various methods are provided for leakage reduction via optimized reset states and improving performance for storage elements. The methods include selecting a storage element, where the storage element comprises at least one storage element component sized to reduce static current leakage or at least one storage element component adapted to increase at least one of speed or performance of the storage element. The methods also call for determining a preferred reset state for the storage element, wherein the preferred reset state is based at least upon the reduction of static current leakage, the speed or the performance of the storage element. The methods also call for setting the storage element reset state to the preferred reset state. An additional method calls for determining if a storage element spends a predetermined amount of time in a static state, and determining a preferred reset state for the storage element based upon at least the static state in which the storage element spends the at least a predetermined amount of time. The additional method also calls for setting a preferred reset state based at least upon the static state in which the storage element spends the at least a predetermined amount of time. | 2012-05-17 |
20120124317 | CONCURRENT READ AND WRITE MEMORY OPERATIONS IN A SERIAL INTERFACE MEMORY - Subject matter disclosed herein relates to read and write processes of a memory device. | 2012-05-17 |
20120124318 | Method and Apparatus for Optimal Cache Sizing and Configuration for Large Memory Systems - A method for configuring a large hybrid memory subsystem having a large cache size in a computing system where one or more performance metrics of the computing system are expressed as an explicit function of configuration parameters of the memory subsystem and workload parameters of the memory subsystem. The computing system hosts applications that utilize the memory subsystem, and the performance metrics cover the use of the memory subsystem by the applications. A performance goal containing values for the performance metric is identified for the computing system. These values for the performance metrics are used in the explicit function of performance metrics, configuration parameters and workload parameters to calculate values for the configuration parameters that achieve the identified performance goal. The calculated values of the configuration parameters are implemented in the memory subsystem. | 2012-05-17 |
20120124319 | METHODS AND STRUCTURE FOR TUNING STORAGE SYSTEM PERFORMANCE BASED ON DETECTED PATTERNS OF BLOCK LEVEL USAGE - Methods and structure within a storage system for tuning performance of the storage system based on monitored block level access within the storage system. Block level access, either in cache memory or on the storage devices of the storage system, is monitored to detect patterns of access and/or data that correspond to an identified host system program. Based on the identified host system program, a profile of desired storage device configuration information is selected by the storage system. The profile comprises information identifying optimal configuration of a logical volume used by the corresponding host system program. Reconfiguration options are identified from the profile information and used either to automatically reconfigure the logical volume or are presented to a user to permit the user to select desired options from the reconfiguration options. | 2012-05-17 |
20120124320 | MEMORY MANAGEMENT DEVICE, MEMORY MANAGEMENT METHOD, MEMORY MANAGEMENT PROGRAM, COMPUTER-READABLE RECORDING MEDIUM RECORDING MEMORY MANAGEMENT PROGRAM AND INTEGRATED CIRCUIT - Available capacity of a specific memory block is secured as much as possible. A termination candidate process selection unit ( | 2012-05-17 |
20120124321 | COMPUTER SYSTEM AND CONTROL METHOD THEREFOR - A physical storage area that is allocated to an unused area of a virtual volume is removed. A management unit sends a request to a server computer to make every piece of data stored in a first logical volume migrate to a second logical volume. The server reads all the data out of the first logical volume and writes the data in the second logical volume. A storage system that includes the first logical volume and the second logical volume allocates a physical storage area to an area of the second logical volume where the data is to be written, and writes the data in the allocated physical storage area. The storage system then deletes the first logical volume. | 2012-05-17 |
20120124322 | STORAGE DEVICE, NON-TRANSITORY COMPUTER READABLE MEDIUM AND METHOD OF CONTROLLING STORAGE DEVICE - A storage device that stores at least one of video data and audio data comprising: a storage medium having a total storage area divided into multiple divided storage areas; a storage processing unit that selects a divided storage area other than a divided storage area that is most recently subjected to storage processing among the multiple divided storage areas, and stores, in a selected divided area, at least one of the video data and the audio data corresponding to a storage period unit; and a divided storage area control unit that performs initialization processing or defragmentation processing to the divided storage area which stores at least one of the video data and the audio data corresponding to the storage period unit. | 2012-05-17 |
20120124323 | METHOD FOR SETTING MEMORY ADDRESS SPACE - A method for setting a memory address space is provided. A memory access frequency of an application program is obtained under execution of an operating system (OS). And a mapping of a memory region is decided according to the memory access frequency. Next, an interrupt signal is used for executing an interrupt handler routine. The mapping of the memory region is set under execution the interrupt handler routine. And the application program is loaded into the memory region for executing in the OS. | 2012-05-17 |
20120124324 | METHOD AND APPARATUS FOR TRANSLATING MEMORY ACCESS ADDRESS - A memory access address translating apparatus and method may each classify pixels included in an input image into a plurality of tiles, and may generate a new memory for each of the successive tiles to enable the successive tiles, among a plurality of tiles, to be stored in different banks. | 2012-05-17 |
20120124325 | METHOD AND APPARATUS FOR CONTROLLING A TRANSLATION LOOKASIDE BUFFER - A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions within a plurality of instructions to be executed, and placing the identified load instructions in a queue prior to execution. An atomic instruction identified in the queue is prevented from executing until the atomic instruction is the oldest instruction in the queue. The apparatus comprises a queue and a translation lookaside buffer. The queue is adapted to: identify an atomic instruction within a plurality of instructions to be executed; prevent execution of the atomic instruction until it is the oldest instruction in the queue; and send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue. The translation lookaside buffer is adapted for maintaining at least one virtual to physical address translation, and is adapted to force a miss in the translation lookaside buffer in response to receiving the atomic load signal. | 2012-05-17 |
20120124326 | Translation Lookaside Buffer Structure Including a Data Array Sense Amplifier and Fast Compare Unit - A translation lookaside buffer (TLB) includes a data array including a number of memory storage cells arranged to form a plurality of entries. The memory storage cells of each entry may be configured to store the respective bits of a translated physical address. The data array further includes a number of sense amplifiers, each coupled to a respective memory storage cell. In response to a read access to a given entry, the sense amplifiers corresponding to the memory storage cells of the given entry may be configured to output respective bit representations of the translated physical address. The TLB also includes a compare unit coupled to the sense amplifier outputs and configured to perform a bit-wise compare of each bit representation of the translated physical address with a corresponding respective bit of each of a plurality of additional addresses. | 2012-05-17 |
20120124327 | Translation Lookaside Buffer Structure Including a Data Array Storing an Address Selection Signal - A translation lookaside buffer (TLB) includes a data array unit with a data array having a plurality of entries. Each entry may store a respective translated physical address and an address selection indication. The address selection indication may select as an output of the data array unit one of the respective translated physical address stored within a particular entry or another address provided to the data array unit in response to the particular entry being read. | 2012-05-17 |
20120124328 | Translation Lookaside Buffer Structure Including an Output Comparator - A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle. | 2012-05-17 |
20120124329 | Translation Lookaside Buffer Structure Including a Data Array Having an Integrated Multiplexer - A translation lookaside buffer (TLB) includes a data array including memory storage cells arranged to form a number of entries. Each entry may store a translated physical address. The data array also includes an integrated multiplexer that may be coupled to an output of the data array. The integrated multiplexer may include a respective first bit select transistor that may be coupled between an output of each of at least some of the memory storage cells and the output of the data array. In addition, the integrated multiplexer may bit-wise select as the output of the data array, one of the translated physical address or another address provided to the data array from external to the TLB in response to a given entry being accessed. | 2012-05-17 |
20120124330 | MEMORY SYSTEM - A memory system according to an embodiment of the present invention comprises: a data managing unit | 2012-05-17 |
20120124331 | DATA PROCESSING SYSTEM - The system includes first and second storage systems. The first storage system includes a first control unit managing a plurality of logical units (LUs) and a plurality of first storage devices being controlled to store data by the first control unit, the plurality of LUs including a first type LU and a second type LU, the first type LU corresponding to at least one of the plurality of first storage devices of the first storage system so that data to be stored to the first type LU is stored to the at least one of the plurality of first storage devices of the first storage system, the second type LU mapping to an LU which is managed by a second storage system so that data to be stored to the second type LU is transferred to the LU managed by the second storage system. | 2012-05-17 |
20120124332 | VECTOR PROCESSING CIRCUIT, COMMAND ISSUANCE CONTROL METHOD, AND PROCESSOR SYSTEM - A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline arithmetic unit performs arithmetic processing of data stored in the array elements indicated as a source by one command in parts through a plurality of cycles and stores the result in the array elements indicated as a destination by the one command through a plurality of cycles. When data word length of a preceding command is longer than that of a subsequent command, the command issuance control circuit changes data sizes of the array elements in accordance with data word length of the command and determines whether there is register interference between the array element to be processed at a non-head cycle of the preceding command, and the array element to be processed at a head cycle of the subsequent command. | 2012-05-17 |
20120124333 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. | 2012-05-17 |
20120124334 | SIMD PROCESSOR FOR PERFORMING DATA FILTERING AND/OR INTERPOLATION - Data processing circuit containing an instruction execution circuit having an instruction set comprising a SIMD instruction. The instruction execution circuit comprises arithmetic circuits, arranged to perform N respective identical operations in parallel in response to the SIMD instruction. The SIMD instruction selects a first one and a second one of the registers. The SIMD instruction defines a first and second series of N respective SIMD instruction operands of the SIMD instruction from the addressed registers. Each arithmetic circuit receives a respective first operand and a respective second operand from the first and second series respectively. The instruction execution circuit selects the first and second series so they partially overlap. Positioning the operands is under program control. | 2012-05-17 |
20120124335 | System Core for Transferring Data Between an External Device and Memory - Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified. | 2012-05-17 |
20120124336 | SIGNAL PROCESSING SYSTEM AND INTEGRATED CIRCUIT COMPRISING A PREFETCH MODULE AND METHOD THEREFOR - A signal processing system comprising at least one master device at least one memory element and prefetch module arranged to perform prefetching from at least one memory element upon a memory access request to the at least one memory element from the at least one master device. Upon receiving a memory access request from the at least one master device, the prefetch module is arranged to configure the enabling of prefetching of at least one of instruction information and data information in relation to that memory access request based at least partly on an address to which the memory access request relates. | 2012-05-17 |
20120124337 | Size mis-match hazard detection - An out-of-order processor | 2012-05-17 |
20120124338 | MULTI-THREADED DATA PROCESSING SYSTEM - A method and apparatus are provided for executing instructions of a multi-threaded processor having multiple hardware threads ( | 2012-05-17 |
20120124339 | PROCESSOR CORE SELECTION BASED AT LEAST IN PART UPON AT LEAST ONE INTER-DEPENDENCY - An embodiment may include at least one first process to be executed, at least in part, by circuitry. The at least one first process may select, at least in part, from a plurality of processor cores, one or more processor cores to execute, at least in part, at least one second process. The at least one first process may select, at least in part, the one or more processor cores based at least in part upon whether at least one inter-dependency exists, at least in part, between the at least one second process and at least one third process also to be executed by the one or more processor cores. Many alternatives, variations, and modifications are possible. | 2012-05-17 |
20120124340 | Retirement serialisation of status register access operations - A processor | 2012-05-17 |
20120124341 | Methods and Apparatus for Performing Multiple Operand Logical Operations in a Single Instruction - A method for performing multiple-operand logical operations in a single instruction includes the steps of: generating a table defining a correspondence between a plurality of input variables to a multiple-operand logical operation and a plurality of output results of the multiple-operand logical operation; encoding the table to generate a set of values for use by the single instruction, each value being indicative of an output result of the multiple-operand logical operation as a function of a corresponding unique combination of values of the input variables; and at least one processor performing the multiple-operand logical operation in a single instruction as a function of the set of values for a prescribed combination of values of the input variables. | 2012-05-17 |
20120124342 | CONCURRENT CORE AFFINITY FOR WEAK COOPERATIVE MULTITHREADING SYSTEMS - A data structure is stored. Further, a plurality of operations performed on the data structure is modified to be per core instead of per thread so that a subset of the plurality of threads safely share the data structure. In addition, interruption of each of the plurality of threads in the subset is prevented unless one or more of each of the plurality of threads in the subset allows the interruption. | 2012-05-17 |
20120124343 | APPARATUS AND METHOD FOR MODIFYING INSTRUCTION OPERAND - Provided are an apparatus and method for modifying an instruction operand. The apparatus includes a first selector configured to receive first instruction operands and a second selector configured to receive second instruction operands. The apparatus also includes a modification unit configured to select a first instruction operand and a second instruction operand, and to modify the selected first instruction operand and the selected second instruction operand to reduce the operand instructions that are input to the first selector and the second selector. | 2012-05-17 |
20120124344 | LOOP PREDICTOR AND METHOD FOR INSTRUCTION FETCHING USING A LOOP PREDICTOR - A loop predictor and a method for instruction fetching using a loop predictor. A processor may include a loop predictor in addition to a primary branch predictor. A relatively common scenario in program execution is that a set of branches repeat over and over forming a loop. The loop may be detected based on a repeated pattern of access to a data structure used for branch prediction. Once a loop is detected and it may be determined whether the codes would stay in the loop for at least a duration sufficient to disable the branch prediction. On a determination that the detected loop is locked, a sequence of instruction addresses in one iteration of the detected loop may be captured in a buffer and the branch predictor may be turned off and a sequence of fetch instructions may be played from the buffer. | 2012-05-17 |
20120124345 | CUMULATIVE CONFIDENCE FETCH THROTTLING - A method and apparatus to utilize a fetching scheme for instructions in a processor to limit the expenditure of power caused by the speculative execution of branch instructions is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes calculating a cumulative confidence measure based on one or more outstanding conditional branch instructions. The method also includes reducing prefetching operations in response to detecting that the cumulative confidence measure is below a first threshold level. | 2012-05-17 |
20120124346 | Decoding conditional program instructions - A processor | 2012-05-17 |
20120124347 | BRANCH PREDICTION SCHEME UTILIZING PARTIAL-SIZED TARGETS - A method and apparatus to utilize a branch prediction scheme that limits the expenditure of power and the area consumed caused by branch prediction schemes is provided. The method includes accessing a first entry and a second entry of the data structure, wherein each entry stores a portion of a predicted target address, determining the predicted target address using the portion of the predicted target address stored in the first entry and a portion of a branch address of a fetched branch instruction for a fetched branch instruction of a first type, and determining the predicted target address using the portion of the predicted target address stored in the first entry and the portion of the predicted target address stored in the second entry for a fetched branch instruction of a second type. | 2012-05-17 |
20120124348 | BRANCH PREDICTOR ACCURACY BY FORWARDING TABLE UPDATES TO PENDING BRANCH PREDICTIONS - A method and apparatus are provided for increasing the accuracy of a branch predictor. A branch prediction table provides a first instance of a branch prediction value associated with an instruction being speculatively executed a first time; and provides a second instance of the branch prediction value associated with the instruction being speculatively executed a second rime. The first instance of the branch prediction value may be subsequently revised after the instruction associated with the first instance of the branch prediction value is retired. Information regarding whether that branch instruction was accurately predicted may then be used to update the branch prediction table and the second instance of the branch prediction value. | 2012-05-17 |
20120124349 | POWER EFFICIENT PATTERN HISTORY TABLE FETCH IN BRANCH PREDICTOR - A method and apparatus for branch prediction is disclosed. A pattern history table (PHT) is accessed based on at least one global history value to obtain a prediction value. The prediction value and the at least one global history value used to obtain the prediction value are placed in a queue. If a branch prediction is requested, the queue is accessed to obtain a prediction value. The queue may include any number of entries and the queue maintains the oldest prediction value at the head of the queue. The prediction value at the head of the queue is used when a branch prediction is needed. | 2012-05-17 |
20120124350 | TABLE-DRIVEN SOAKER TOOL FOR INFORMATION HANDLING SYSTEMS - A soaker tool for an information handling system (IHS) exercises the IHS to provide a predetermined amount of utilization that a user may specify. The soaker tool schedules wait times following respective utilization times in alternating fashion to achieve a desired utilization value for a predetermined time period. The soaker tool monitors for a dispatch interrupt during the utilization times. Should a dispatch interrupt occur during a utilization time, the soaker tool accounts for the dispatch interrupt by determining a remainder utilization time to maintain utilization accuracy. The soaker tool may employ a parameter table that specifies utilization times, wait times, loop counts and adjustment cycles indexed to the respective utilization values that a user may select. The soaker tool may employ adjustment cycles to compensate for cumulative timing errors that may occur when running the tool for extended time periods. | 2012-05-17 |
20120124351 | APPARATUS AND METHOD FOR DYNAMICALLY DETERMINING EXECUTION MODE OF RECONFIGURABLE ARRAY - An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction word (VLIW) mode or in a coarse grained array (CGA) mode. | 2012-05-17 |
20120124352 | PRE-INSTALLATION ENVIRONMENT USED BY OPERATING SYSTEMS - A pre-installation environment used by an operating system includes a pre-installation kit, a running unit, and a write inhibiting unit. The running unit is used for running the pre-installation kit, and generating an inhibiting signal when running to call the executable files for configuring network environment. The write inhibiting unit is used for inhibiting information generated by running the executable files from being written into a log file in response to the inhibiting signal. | 2012-05-17 |
20120124353 | EVENT PROCESSING FINITE STATE ENGINE AND LANGUAGE - In various embodiments, a method for processing event streams includes receiving a state machine defined in response to a set of processing components, a set of states, and a set of entry points. Event data associated with an event stream is also received. The event data is processed according to the state machine to generate an event. | 2012-05-17 |
20120124354 | DYNAMICALLY SELECT OPERATING SYSTEM (OS) TO BOOT BASED ON HARDWARE STATES - Disclosed is a microprocessor based system with a dynamically selectable Operating System that is capable of providing unique operating systems based upon current hardware states without user intervention. The system will determine the current state of the system and select from a plurality of operating systems the best operating system to load. In normal operating conditions the system will select the most full-featured and robust operating system. If, for example, the system loses alternating-current power, the system will shutdown, reboot, and automatically select an operating system with very limited capabilities and limited power consumption to allow the system to retrieve important data from the cache and store the data to a data storage device. | 2012-05-17 |
20120124355 | SINGLE VOLUME IMAGE FILE EXTRACTION - Disclosed is a method of booting a virtual machine. A file, accessible by a privileged domain that includes an index file image and a plurality of other file images is stored. The index file image is of a predetermined, fixed size and includes a file name and a file size for each of the other images in the file. The privileged domain provides the file to one or more non-privileged virtual machines as a single disk image of the fixed size mounted on the non-privileged virtual machine. The other file images are extracted by the virtual machines based on the file names and file sizes stored in the index file image. | 2012-05-17 |
20120124356 | METHODS AND APPARATUSES FOR RECOVERING USAGE OF TRUSTED PLATFORM MODULE - Methods and systems to perform platform security in conjunction with hardware-base root of trust logic are presented. In one embodiment, a method includes determining whether a status from an authenticated code module is indicative of an error or not. The method further includes determining whether the hardware-based root of trust logic is enabled based on content in a non-volatile memory location. If the hardware-based root of trust is enabled and the status is indicative of an error, the method further includes writing to the non-volatile memory location to disable hardware-based root of trust logic during a next boot sequence. In one embodiment, a platform initializes and uses the trusted platform module in conjunction with the hardware-based root of trust logic or with a platform-based root of trust logic. | 2012-05-17 |
20120124357 | METHOD OF PROVISIONING FIRMWARE IN AN OPERATING SYSTEM (OS) ABSENT SERVICES ENVIRONMENT - Methods and apparatuses for re-instantiating a firmware environment that includes one or more firmware functions available at pre-boot time when transitioning the computing device from a first, higher power consumption state to a second, lower power consumption state. The firmware environment determines whether a cryptographic signature on a firmware volume is verified; whether hardware resources of the computing device requested by a manifest of the firmware volume are available; and whether a firmware module of the firmware volume is compatible with installed firmware of the firmware environment. If so, the firmware environment reserves space in a memory to accommodate resources used by the firmware module, and executes the firmware module with the computing device in the second, lower power consumption state. | 2012-05-17 |
20120124358 | CONFIGURATION INFORMATION RECOVERING SYSTEM AND METHOD - A basic input output system (BIOS) microchip of a card and method recovers configuration information of the BIOS microchip of the card. The BIOS microchip of the card invokes a reading function from a BIOS microchip of a motherboard to read predetermined configuration information from the BIOS microchip of the motherboard. The BIOS microchip of the card replaces the configuration information stored in the BIOS microchip of the card by the predetermined configuration information, in response to a determination that the configuration information stored in the BIOS microchip of the card is different from the predetermined configuration information. | 2012-05-17 |
20120124359 | PROGRAM PROCESSING APPARATUS - A program processing apparatus includes an internal memory An internal memory is arranged to save a first program for activating a target program. A first designator designates the first program in response to a first manipulation in a state that an external memory which saves a second program for updating the internal memory is removed and the first program is saved in the internal memory. A second designator designates the second program in response to a second manipulation in a state that the external memory is attached. An executer executes the program designated by one of the first designator and the second designator. | 2012-05-17 |
20120124360 | Method and Apparatus for Booting a Processing System - Machine-readable media, methods, apparatus and system for booting a processing system are described. In an embodiment, whether to launch an open operating system or a closed operating system to boot a processing system may be determined. A key may be retrieved from a processor register of the processing system and used to decrypt an encrypted version of the closed operating system based at least in part on a determination of booting the processing system with the closed operating system. In another embodiment, the processor register stored with the key may be flushed based at least in part on a determination of booting the processing system with the open operating system. | 2012-05-17 |
20120124361 | PLURALITY OF INTERFACE FILES USABLE FOR ACCESS TO BIOS - A system may comprise a processor ( | 2012-05-17 |
20120124362 | APPARATUS AND METHOD FOR RECORDING REBOOT REASON OF EQUIPMENT - Embodiments of the present invention provide an apparatus and a method for recording a reboot reason of equipment. Besides a first watchdog provided for triggering a global reset of the equipment, the apparatus provided by the present invention further includes a second watchdog. The second watchdog is used to trigger a logic chip to record a value representing the reboot reason of power-down in a storage array after the equipment is powered on. Thus, reboot reason of the equipment could recorded as power-down reboot. | 2012-05-17 |
20120124363 | ANALYZING PERFORMANCE OF COMPUTING DEVICES IN USAGE SCENARIOS - Techniques for conducting an automated analysis of operations carried out during the critical path for a usage scenario and suggesting ways in which the configuration of the computing device could be changed to affect performance of the computing device. Computing devices can be operated in a variety of usage scenarios and users may notice the performance of a computing device in certain usage scenarios more particularly. Critical path analysis of operations conducted in these usage scenarios can be used to identify a critical path of the usage scenario, from which changes that could be made to the computing device to affect performance could be identified. Once the changes that could be made are identified, suggestions can be made to the user, such that a user is able to make changes to the configuration to affect performance when the user has little knowledge about how to improve configurations. | 2012-05-17 |
20120124364 | ELECTRONIC DEVICE AND CONTROL METHOD FOR THE SAME - An electronic device of the present invention includes an input acceptance section that accepts an input of a command that causes any one of a plurality of operation states to be selected; a function section ( | 2012-05-17 |
20120124365 | ACCESSING A SECURE TERMINAL - A method of accessing content on a secure terminal is described. The method comprises: capturing an image of a visual code presented on a display of a secure terminal. The method then involves decoding the visual code to ascertain (i) a set of connection parameters and (ii) a unique identifier. The set of connection parameters are used to establish a connection with the secure terminal. The method also comprises receiving the content from the secure terminal via the established connection in response to transmission of the unique identifier. | 2012-05-17 |
20120124366 | SYSTEM AND METHOD FOR A DERIVATION FUNCTION FOR KEY PER PAGE - Disclosed herein are systems, methods and computer-readable media to perform data encryption and decryption using a derivation function to obtain a key per page of data in a white-box environment. The method includes sharing a master key with the sender and receiver, splitting the input data into blocks and sub-blocks, and utilizing a set of keys and a master key to derive a page key. In another aspect of this disclosure, the key validation and shuffling operations are included. This method allows for the derivation of a key instead of storing a predetermined key, thus maintaining system security in a white-box environment. | 2012-05-17 |
20120124367 | System and Method for Securely Communicating Across Multiple Networks Using a Single Radio - A communications module for facilitating secure communications on a first network and a second network includes: a single transceiver for receiving and transmitting first network messages from and to the first network and at least transmitting second network messages to the second network; at least a first processor connected to the single transceiver for processing one or more first network messages and second network messages; the at least a first processor including first network logic for processing first network messages and second network logic for processing second network messages; and the second network logic including instructions for securing second network messages such that decryption of the second network messages is limited to a particular receiving device on the second network. The second network messages may include commodity pricing and use information. | 2012-05-17 |
20120124368 | Digital Rights Convergence Place Chaser - The present invention is an apparatus and method for the money transactions required in the selling of merchandise or media content on the Internet or other public or private network. It can then track and maintain digital rights to merchandise or media. Methods of access to digitally protected content are disclosed. License metadata and credentials from multiple types of digital rights management systems may be used to grant access through a home based or other end-user custodial digital rights “place-chaser” to content protected by different types of serial copy management systems. Content security using a non-audible or invisible code signal sequence(s) can provide traceability as well as absolute anonymity for the purchaser. This apparatus can be used to conduct transactions off the web so that business can be done on the web. | 2012-05-17 |
20120124369 | SECURE PUBLISHING OF PUBLIC-KEY CERTIFICATES - The current application is directed to methods and systems for secure distribution of public-key certificates using the domain name system with security extensions (“DNSSEC”), a publisher component, and additional client-side functionality. These methods and systems, when combined with public/private-key-based cryptography used for encrypting digitally encoded information, provides a computationally efficient and well-understood method and system for secure communications and digitally-encoded-information verification without current difficulties and inefficiencies attendant with distributing and managing the public keys used for encrypting digitally encoded information. | 2012-05-17 |
20120124370 | PORTABLE INTEGRATED SECURITY STORAGE DEVICE AND SERVICE PROCESSING APPARATUS, AND SERVICE PROCESSING METHOD USING THE SAME - A portable integrated security storage device includes: a password generation module for generating a password; a universal authentication module for storing universal authentication information; a communication interface connected to an external system for transmitting and receiving data with the external system; and a memory for storing the received data received through communication with the external system. The password and universal authentication information are transmitted to the external system for user authentication and device authentication, and encrypted data and a service secret key are received from the external system and stored in the memory. | 2012-05-17 |
20120124371 | SYSTEM AND METHOD FOR AUTHENTICATING STREAMED DATA - One embodiment of a method of authenticating data comprises: receiving, at a device, data in a plurality of indexed packets transmitted by a data server, the data of the indexed packets being at least a portion of a larger data stream; receiving, at the device, from a data authentication server connected to the device by a network, a server-computed authentication value based on a subset of the data transmitted by the data server, the data authentication server having access to the data that was transmitted from the data server to the device; and comparing a device-computed authentication value based on a subset of the received data, corresponding to the subset of the data transmitted by the data server, with the server-computed authentication value in order to determine whether the subset of the data received at the device is authentic. | 2012-05-17 |
20120124372 | Protecting Websites and Website Users By Obscuring URLs - Websites and website users are subject to an increasing array of online threats and attacks. Disclosed herein are, among other things, approaches for protecting websites and website users from online threats. For example, a content server, such as a proxying content delivery network (CDN) server that is delivering content on behalf of an origin server, can modify URLs as they pass through the content server to obscured values that are given to the end-user client browser. The end-user browser can use the obscured URL to obtain content from the content server, but the URL may be valid only for a limited time, and may be invalid for obtaining content from the origin. Hence, information is hidden from the client, making attacks against the website more difficult and frustrating client-end malware that leverages knowledge of browsed URLs. | 2012-05-17 |
20120124373 | METHOD AND APPARATUS FOR AUTHENTICATIING A NETWORK DEVICE - A trust centre ( | 2012-05-17 |
20120124374 | SECURED ACKNOWLEDGE PROTOCOL FOR AUTOMOTIVE REMOTE KEYLESS ENTRY SYSTEMS AND FOR NETWORKED SENSOR DEVICES - A method for generating a secure acknowledgment message that involves constructing a plaintext of the acknowledgment message, computing a cyclic redundancy check (CRC) value for the plaintext of the acknowledgment message, encrypting the plaintext of the acknowledgment message to obtain a ciphertext of the acknowledgment message, computing a secure check (CHK) value from the ciphertext using bits of the cyclic redundancy check value (CRC) and then appending the secure check value (CHK) to the plaintext of the acknowledgment message. | 2012-05-17 |
20120124375 | APPARATUS, SYSTEM AND METHOD FOR VERIFYING SERVER CERTIFICATES - A device and method are provided for a device that authenticates a server over a network. The device and method are operable to contact the server to initiate a handshaking operation. The device receives certificate information and handshaking information from the server. The device completes the handshaking operations to establish the connection with the server. The device downloads the content from the server through the connection before authenticating the server to establish a secure connection. In some aspects, the device may display a portion of the downloaded content before the server is authenticated. | 2012-05-17 |
20120124376 | Information Processing System Using Nucleotide Sequence-Related Information - The present invention provides a highly-safe information processing system that is capable of effectively using nucleotide sequence information differences between individual organisms to offer semantic information useful for each individual organism while properly preventing leakage and illegal use of nucleotide sequence information. | 2012-05-17 |
20120124377 | PROCESS AND STREAMING SERVER FOR ENCRYPTING A DATA STREAM WITH BANDWIDTH BASED VARIATION - There is disclosed a process for encrypting a data stream to secure the data stream for single viewing and to protect copyrights of the data stream. Specifically, there is disclosed a process for protecting streaming multimedia, entertainment and communications in an Internet-type transmission. There is further disclosed a streaming server component operably connected with a streaming server that interacts with a client system to affect the inventive process. | 2012-05-17 |
20120124378 | METHOD FOR PERSONAL IDENTITY AUTHENTICATION UTILIZING A PERSONAL CRYPTOGRAPHIC DEVICE - A method for personal identity authentication utilizing a personal cryptographic device initially provides a personal cryptographic device storing a client key from a host system and a device serial number. Next, the personal cryptographic device is connected to the host system. Thereafter, unique user information is inputted via the personal cryptographic device. Then, the unique user information and the device serial number are encrypted and sent to the host system for authentication and for requesting key information. The personal cryptographic device receives and decrypts encrypted key information with the client key, and changes the client key using the key information. | 2012-05-17 |
20120124379 | ANONYMOUS AUTHENTICATION SIGNATURE SYSTEM, USER DEVICE, VERIFICATION DEVICE, SIGNATURE METHOD, VERIFICATION METHOD, AND PROGRAM THEREFOR - The user device includes: a recording unit which stores system parameters as respective parameters given in advance, a disclosure public key, a user public key, a user private key, a member certificate, and an attribute certificate; an input/output unit which receives input of the document from the user and an attribute the user intends to disclose; a cryptograph generating module which generates a cryptograph based on the inputted document, the attribute to be disclosed, and each of the parameters; a signature text generating module which generates a zero-knowledge signature text from the generated cryptograph; and a signature output module which outputs the cryptograph and the zero-knowledge signature text as the signature data. The user public key and the attribute certificate are generated by using a same power. | 2012-05-17 |
20120124380 | USB COMPOSITE DEVICE AND METHOD THEREFOR - The invention, which relates to information security device, provides a USB composite device and implementing method thereof. The invention provides a solution that integrates the mass storage function and the key device function on a single device. A USB composite device is connected with a host computer and claims its device type; the composite device receives the operating instruction allocated by the host computer and determines whether the instruction is key device operating instruction; if so, performs key device operating; otherwise, performs data reading/writing operating. Providing higher data security and good usability for the user, the solution of the invention is easy to use. | 2012-05-17 |
20120124381 | VALIDATION SYSTEM AND VERIFICATION METHOD INCLUDING SIGNATURE DEVICE AND VERIFICATION DEVICE TO VERIFY CONTENTS - Provided are methods and a validation system that includes a signature device and a verification device for verifying a content. The signature device may generate verification information for each segment of a divided content and may generate signature information to verify the integrity of each segment and whether a corresponding segment is a part of a content. When a segment is received, the verification device may verify integrity of the segment and whether the segment is a part of the content, based on the verification information and the signature value received from the signature device. | 2012-05-17 |
20120124382 | SYSTEM AND METHOD FOR CHECKING DIGITAL CERTIFICATE STATUS - A method for handling digital certificate status requests between a client system and a proxy system is provided. The method includes the steps of receiving at the proxy system digital certificate status request data transmitted from the client system and generating query data for the digital certificate status in response to receiving the digital certificate status request data. The query data is transmitted to a status provider system, and status data from the status provider system in response to the query data is received at the proxy system. Digital certificate status data based on the status data received is generated and transmitting to the client system. | 2012-05-17 |
20120124383 | SYSTEM AND METHOD FOR PROTECTING NETWORK RESOURCES FROM DENIAL OF SERVICE ATTACKS - The present disclosure generally pertains to systems and methods for protecting network resources from denial of service attacks. In one exemplary embodiment, a responder stores an access filter value used to determine whether an incoming message frame has been transmitted from an authorized user. In this regard, a user communication device includes logic for determining the access filter value stored at the responder and, includes the access filter value in a message frame transmitted from the computer to the responder. The responder compares the received access filter value to the stored access filter value. If such values match or otherwise correspond, the responder authenticates the message frame. However, if such values do not match or otherwise correspond, the responder discards the message frame. Thus, the responder processes authenticated message frames and discards unauthenticated message frames thereby preventing denial of service attacks from malicious users. | 2012-05-17 |
20120124384 | HTTP Signing - A system and method for signing data transferred over a computer network is described. In one aspect, the HTTP header of an HTTP response message is extended to include a content identifier, a content expiration time, and a digital signature. The digital signature may be generated from the content identifier, the content expiration time, and the message body of the HTTP response message. | 2012-05-17 |
20120124385 | METHOD, CONTROLLER AND SYSTEM FOR DETECTING INFRINGEMENTS OF THE AUTHENTICITY OF SYSTEM COMPONENTS - In a method for detecting infringements of the authenticity of a system component an authentication request is sent from a controller to an authentication device of the system component. A first authentication code is calculated in the authentication device by applying a shared one-way function to an identification code, stored in the authentication device, for the system component. A second authentication code in the controller is calculated by applying the shared one-way function to an identification code, stored in the controller, for the system component, and an authentication response including the first authentication code is sent from the authentication device to the controller. The first authentication code is compared with the second authentication code in the controller for detecting infringements of the authenticity of the system component. | 2012-05-17 |
20120124386 | Method and System for Refreshing Content in a Storage Device - A method and system for refreshing content in a storage device are disclosed. In one embodiment, a content replication system authenticates to each of a plurality of storage devices in parallel without creating a unique secure channel with each respective storage device. After authenticating to each of the plurality of storage devices, the content replication system is permitted to write content to, but not read content from, each of the plurality of storage devices. The content replication system then writes content to each of the plurality of storage devices in parallel. | 2012-05-17 |
20120124387 | Animal Data Management - Animal data is stored in memory accessible to a server. The server allows users to access the animal data, such as across a communication network. In some embodiments an identifier for an animal is stored with animal information. The identifier can be used to control access to animal records and to quickly locate animal information associated with a particular animal. | 2012-05-17 |
20120124388 | Electronic-device theft-deterring systems - A method and apparatus to deter theft of electronic-devices is disclosed. Electronic-devices have locked and unlocked states that permit deny and permit use of the electronic-device. Electronic-devices are shipped from manufacturers, thorough suppliers, to retailers in the locked state. Unlocking functions are transmitted through computer networks to the retail locations and held in volatile storage. The unlocking of the electronic-device occurs subsequent to purchase. Other methods and apparatus are disclosed related to multiple distribution methods of unlocking schemes, re-locking and return validation and data structures. | 2012-05-17 |
20120124389 | Protecting images, and viewing environments for viewing protected images - A method, apparatus, and system are provided to facilitate protecting media such as images, documents, video streams, and the like, from unauthorized copying or distribution. The method is based on requiring certain conditions to be filled prior to, and during, display of the media on a user display. The conditions for display may require pointing device cursor placement, operating certain keys, and the like. Permissions are granted to users by the media owners and the permissions are checked prior to display. Thus the user is prevented from copying the media and using it illicitly, and the media owner may share media while at the same time maintaining control over the use thereof. The system may also be utilized to provide time-limited access to certain materials. | 2012-05-17 |
20120124390 | Virtual Secure Digital Card - A system (and a method) are disclosed for generating a virtual secure digital (SD) card. One embodiment detects an SD card and reads a media key block and media identification for the SD card. The system stores the media key block and the media identification. The system creates a file system for secure data on a storage device for storage of secure data corresponding to a secure data area of the SD card and creates a file system for user data on the storage device for storage of user data corresponding to a user data area of the SD card. In addition, the system uses the virtual secure digital (SD) card. The system determines if the virtual SD card is provisioned and provisions it if not. The system accesses the data stored in the secure area of the provisioned virtual SD card. The system extracts the data from the secured area of the provisioned virtual SD card. | 2012-05-17 |
20120124391 | STORAGE DEVICE, MEMORY DEVICE, CONTROL DEVICE, AND METHOD FOR CONTROLLING MEMORY DEVICE - A storage device includes a storage unit and a controller that controls the storage unit in accordance with a request provided from an upstream-side device. The storage unit includes a storage medium that stores data, an authentication processing unit that performs an authentication process, and a storage region managing unit that sets either a first region or a second region in a storage region. The first region is accessible and useable to perform data reading and data writing between the upstream-side device and the storage unit when the access authentication is successfully performed on the basis of a first password. The second region may be released when the access authentication is successfully performed on the basis of a second password. When the storage unit needs to be disconnected, the controller sets the second region in the storage region in which the first region has been previously set. | 2012-05-17 |
20120124392 | SYSTEM AND METHOD FOR STREAM/BLOCK CIPHER WITH INTERNAL RANDOM STATES - Disclosed herein are systems, methods, and computer readable-media for performing data encryption and decryption using a stream or block cipher with internal random states. The method includes splitting the input data into a predetermined number of blocks and processing each block. The processing includes creating sub-blocks, permuting the sub-blocks, replacing bytes using a lookup table, rotating bits, performing expansion and combining sets of bits. The element of randomness employed in this process allows for the same input to yield the same output, with differing internal states. | 2012-05-17 |
20120124393 | System and Methods for Silencing Hardware Backdoors - Methods for preventing activation of hardware backdoors installed in a digital circuit, the digital circuit comprising one or more hardware units to be protected. A timer is repeatedly initiated for a period less than a validation epoch, and the hardware units are reset upon expiration of the timer to prevent activation of a time-based backdoor. Data being sent to the hardware unit is encrypted in an encryption element to render it unrecognizable to a single-shot cheat code hardware backdoor present in the hardware unit. The instructions being sent to the hardware unit are reordered randomly or pseudo-randomly, with determined sequential restraints, using an reordering element, to render an activation instruction sequence embedded in the instructions unrecognizable to a sequence cheat code hardware backdoor present in the hardware unit. | 2012-05-17 |
20120124394 | System and Method for Providing a Virtual Secure Element on a Portable Communication Device - A system for providing a virtual secure element on a portable communication device having a secured element. The system comprising memory; a card management module operably associated with the secure element providing an application programming interface to the secure element and controlling writing to and reading from at least a portion of the memory; a virtual encryption key preferably stored within the secured element; and an encryption engine capable of encrypting data before its placed in the memory and decrypting that data using the virtual encryption key. | 2012-05-17 |
20120124395 | COMPUTER POWER SUPPLY - A computer power supply includes a case and a number of power connectors. The power connectors are mounted on the case and operable to receive different kinds of power signals from the case. Each power connector outputs a corresponding power signal through a corresponding power adapter cable. | 2012-05-17 |
20120124396 | COMPUTER SERVER - A server includes a power line assembly, at least one hard disc drive (HDD), at least one fixing base, and a power supply module. Each HDD defines a power interface. Each fixing base defines a slot. The structure of the slot is substantially the same as that of the power interface. The power supply module is used for supplying power to the at least one HDD. The power line includes a main plug and at least two sub-plugs. The main plug is plugged into the power supply module. One of the at least two sub-plugs is plugged into the power interface of one of the at least one HDD, and another one of the at least two sub-plugs is plugged into the slot of one of the at least one fixing base. | 2012-05-17 |
20120124397 | POWER SWITCH CONTROL CIRCUITRY - Electronic circuits and methods are provided for conserving power within computers and other apparatus. A logic circuit performs a logical operation on a plurality of variables thus deriving a corresponding output. The output is used to drive and maintain an open or closed state of an electronic switch, accordingly. The electronic switch is disposed between a source of electrical energy and a system power buss of a computer. The computer can assume very low power, full power and other respective operating modes in accordance with the present state of the electronic switch. | 2012-05-17 |
20120124398 | Measuring and Managing Power Usage and Cooling in a Network - A system for measuring aspects of a network having a plurality of network components, includes a monitor configured to gather operational characteristics of at least one of the plurality of network components and an analyzer. The analyzer is configured to analyze the gathered operational characteristics received from the monitor and estimate characteristics of an unmonitored one of the plurality of network components based on the gathered operational characteristics. | 2012-05-17 |
20120124399 | Method and System of Power Control - A power control method for a computer system is disclosed. The computer system establishes wireless connection with a handheld equipment via a wireless communication interface. The power control method includes receiving a sound signal transmitted from the handheld equipment via the wireless communication interface when the computer system operates in a shut-down state, recognizing the sound signal to generate a recognition result, and starting the computer system when the recognition result indicates that the sound signal conforms to a start command. | 2012-05-17 |
20120124400 | METHOD FOR CONTOLLING CONNECTION BETWEEN TERMINALS USING LOW SPEED NETWORK COMMUNICATION AND DEVICE USING THE SAME - Disclosed is a terminal device for controlling connection between terminals by using low speed network communication. The terminal device includes a first transmission/reception unit for making a request for connection information required for high speed data communication with a connection terminal, to which the terminal device desires to connect, and receiving the connection information from the connection terminal, a network controller for determining a high speed network module to be used for high speed data communication with the connection terminal based on the connection information, and a second transmission/reception unit for performing high speed data communication with the connection terminal by using a high speed network module determined by the network controller. | 2012-05-17 |
20120124401 | DOMESTIC APPLIANCE COMPRISING A COMMUNICATION UNIT, SYSTEM OF APPLIANCES AND METHOD FOR OPERATING A DOMESTIC APPLIANCE - A domestic appliance includes an internal electrical load, a controller for controlling the internal electrical load, and a communication device coupled with the controller. The controller is configured for transmitting via the communication device data to additional domestic appliances, wherein the received data include information about a time of an impending startup of the internal electrical load, and/or for receiving via the communication device data from additional domestic appliances, wherein the received data include information about a time of an impending startup of an electrical load of an additional domestic appliance. The internal electrical load is controlled based on the received information, preventing an overload of the power supply system. | 2012-05-17 |
20120124402 | DETERMINING A POWER SAVING MODE BASED ON A HARDWARE RESOURCE UTILIZATION TREND - Techniques are disclosed for managing the amount of power consumed by server components of a computer system, each server component having multiple power modes. The utilization of each server component is monitored. Based on the monitored utilization, a time period is determined in which to apply a selected power mode to the respective server component. The respective server component is configured to operate in the selected power mode for at least the determined time period. | 2012-05-17 |
20120124403 | POWER CAPPING FEEDBACK NORMALIZATION - A power capping system ( | 2012-05-17 |
20120124404 | COMPUTER HAVING ELECTRICITY SAVING FUNCTION - A computer includes a motherboard, a capacitive sensor antenna, a capacitive approach sensor module, and a micro control unit (MCU). The capacitive sensor antenna is used to sense a capacitive signal generated from people adjacent to the computer. The capacitive approach sensor module is used to receive the capacitive signal sensed by the capacitive sensor antenna. The MCU is used to receive the capacitive signal from the capacitive approach sensor module. The MCU outputs a first control signal to a sleep control pin of the motherboard to control the motherboard to enter a sleep state in response to the capacitive signal being less than a predetermined value. The MCU outputs a second control signal to the sleep control pin to control the motherboard to exit from the sleep state in response to the capacitive signal being greater than or equal to the predetermined value. | 2012-05-17 |
20120124405 | System and Method for Energy Savings on a PHY/MAC Interface for Energy Efficient Ethernet - A system and method for energy savings on a PHY/MAC interface for energy efficient Ethernet. Power savings for a PHY due to low-link utilization can also be realized in the higher layer elements that interface with the PHY. In one embodiment, subrating is implemented on a MAC/PHY interface to match a subrating of the PHY with a remote link partner. This subrating is less than the full capacity rate and can be zero. | 2012-05-17 |
20120124406 | COMPUTER SYSTEM AND POWER MANAGEMENT METHOD THEREOF - A power management method of a computer system is provided. The method includes the following steps. Health states of a plurality of power supplies are detected to generate a detection signal. Output powers provided by the power supplies are received to calculate a total maximum output power of the power supplies. An interrupt is generated by triggering a configuration management program according to the total maximum output power or the detection signal. The interrupt is processed by an interrupt handler to adjust a power consumption of a central processing unit (CPU). | 2012-05-17 |
20120124407 | SEMICONDUCTOR DEVICE AND RESET CONTROL METHOD IN SEMICONDUCTOR DEVICE - Reset request from external are held at a reset request holding unit having holding units connected in series; a reset switching unit performs a logical product operation of all of outputs of the holding units to set it as an asynchronous reset request, setting an output of the holding unit at a final stage of the holding units as a synchronous reset request, performing a logical product operation of the asynchronous reset request and the synchronous reset request, and outputs an operation result; the asynchronous reset request is masked in a synchronous reset mode; and a reset signal is output from a reset output unit based on the operation result at the reset switching unit. | 2012-05-17 |
20120124408 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal. | 2012-05-17 |
20120124409 | SEMICONDUCTOR DEVICE HAVING DLL CIRCUIT - A semiconductor device with a clock control circuit that outputs an internal clock signal configured by delaying external clock signals based on at least a feedback clock signal; a plurality of output buffers that output data in synchronization with the internal clock signal; an output replica that is a replica of the output buffers and that generates the feedback clock signal in synchronization with the internal clock signal and supplies the feedback clock signal to the clock control circuit; and a clock tree that receives the internal clock signal from the clock control circuit and transmits the internal clock signal to the plurality of output buffers and the output replica such that signal line are substantially equal to one another. | 2012-05-17 |
20120124410 | SYSTEM AND METHOD FOR SELF-HEALING - Provided are a system and a method for self-healing in a critical system. The present invention monitors a current situation of the critical system, determines whether a system has an error by analyzing the monitoring result, judges whether to perform self-healing in a current state or drive safety software which provides a minimum basic service according to self-healing of the system error or not when the system error occurs, and evaluates self-healing performance after healing the system error. According to exemplary embodiments of the present invention, it is possible to continuously provide a software service and further improve the reliability of the self-healing system through the evaluation of the self-healing performance. | 2012-05-17 |
20120124411 | SYSTEM ON CHIP FAULT DETECTION - The invention relates to a method for fault identification in a System-on-Chip (SoC) consisting of a number of IP cores, wherein each IP core is a fault containment unit, and where the IP cores communicate with one another by means of messages via a Network-on-Chip, and wherein an excellent IP core provides a TRM (Trusted Resource Monitor), wherein a faulty control message which is sent from one non-privileged IP core to another non-privileged IP core is identified and projected by an (independent) fault container unit, as a result of which this faulty control message cannot cause any failure of the message receiver. | 2012-05-17 |
20120124412 | Systems and Methods of Providing Fast Leader Elections in Distributed Systems of Simple Topologies - Systems and computer-implemented methods of electing a new leader node in distributed systems of simple topologies connecting a plurality of nodes on at least one computer system. The computer-implemented method comprises several steps including at least one node, which detected the absence of a leader, starting a first round for its approval as an Approved Election Initiator. If a quorum accepts the StartElection request during the first round, then the Election Initiator starts a second round to set the leader. If a quorum of all nodes has not been reached during the first round, then the first round fails. The method repeats until a leader is set and is repeated each time a node discovers that the network does not have an active leader. Also provided herein is a computer readable medium having computer executable instructions stored thereon for performing the computer-implemented method. | 2012-05-17 |