20th week of 2012 patent applcation highlights part 31 |
Patent application number | Title | Published |
20120120706 | SEMICONDUCTOR MEMORY DEVICE - A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed. | 2012-05-17 |
20120120707 | SEMICONDUCTOR DEVICE WITH OTP MEMORY CELL - A semiconductor device with an OTP memory cell includes a first MOS transistor having a first gate terminal connected to a first line, and a first terminal connected to a first node, a second MOS transistor having a second gate terminal connected to a second line, and a first terminal connected to the first node, and a third MOS transistor having a gate terminal connected to a three line, and a first terminal of the third MOS transistor connected to the first node. | 2012-05-17 |
20120120708 | METHOD OF SWITCHING OUT-OF-PLANE MAGNETIC TUNNEL JUNCTION CELLS - A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through the out-of-plane magnetic tunnel junction cell, wherein the AC switching current switches the magnetization orientation of the ferromagnetic free layer. | 2012-05-17 |
20120120709 | Transistor Driven 3D Memory - A nonvolatile memory device with a first conductor extending in a first direction and a semiconductor element above the first conductor. The semiconductor element includes a source, a drain and a channel of a field effect transistor (JFET or MOSFET). The nonvolatile memory device also includes a second conductor above the semiconductor element, the second conductor extending in a second direction. The nonvolatile memory device also includes a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element. The JFET or MOSFET includes a gate adjacent to the channel, and the MOSFET gate being self-aligned with the first conductor. | 2012-05-17 |
20120120710 | MEMORY SYSTEM WITH REVERSIBLE RESISTIVITY-SWITCHING USING PULSES OF ALTERNATRIE POLARITY - A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition. | 2012-05-17 |
20120120711 | MEMORY SYSTEM WITH REVERSIBLE RESISTIVITY-SWITCHING USING PULSES OF ALTERNATRIE POLARITY - A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition. | 2012-05-17 |
20120120712 | FORMING METHOD FOR VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT, AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE - An optimum forming method of performing a forming for a variable resistance element to maximize an operation window of the variable resistance element is provided. The forming method is used to initialize a variable resistance element ( | 2012-05-17 |
20120120713 | Asymmetric Write Current Compensation Using Gate Overdrive for Resistive Sense Memory Cells - Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element. | 2012-05-17 |
20120120714 | MEMORY RESISTOR HAVING MULTI-LAYER ELECTRODES - Methods and means related to memory resistors are provided. A memristor includes two multi-layer electrodes and an active material layer. One multi-layer electrode forms an Ohmic contact region with the active material layer. The other multi-layer electrode forms a Schottky barrier layer with the active material layer. The active material layer is subject to oxygen vacancy profile reconfiguration under the influence of an applied electric field. An electrical resistance of the memristor is thus adjustable by way of applied programming voltages and is non-volatile between programming events. | 2012-05-17 |
20120120715 | SEMICONDUCTOR DEVICE - Provided is a memory device in which memory capacity per unit area is increased without making the manufacturing process complicated. The memory device includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells includes a switching element and a capacitor including a first electrode and a second electrode. In at least one of the plurality of memory cells, in accordance with a potential applied to one of the plurality of word lines, the switching element controls a connection between one of the plurality of bit lines and the first electrode, and the second electrode is connected to another one of the plurality of word lines. | 2012-05-17 |
20120120716 | SECURE NON-VOLATILE MEMORY - A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope. | 2012-05-17 |
20120120717 | SRAM CELL - The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor. | 2012-05-17 |
20120120718 | Multi-Bit Magnetic Memory with Independently Programmable Free Layer Domains - An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a magnetic tunnel junction (MTJ) has a ferromagnetic free layer with multiple magnetic domains that are each independently programmable to predetermined magnetizations. Those magnetizations can then be read as different logical states of the MTJ. | 2012-05-17 |
20120120719 | NON-VOLATILE MAGNETIC TUNNEL JUNCTION TRANSISTOR - An example embodiment is an apparatus for controlling a magnetic direction of a magnetic free layer. The apparatus includes a writer with a first magnetic write layer and a second magnetic write layer. Applying a write voltage across first and second magnetic write layers causes a magnetic anisotropy of one of the magnetic write layers to switch from parallel to the plane of the magnetic write layers to orthogonal to the plane of the magnetic write layers. The magnetic write layer with the magnetic anisotropy parallel to the plane of the magnetic write layers induces the magnetic direction in the magnetic free layer. | 2012-05-17 |
20120120720 | MULTILEVEL MAGNETIC ELEMENT - The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line. | 2012-05-17 |
20120120721 | UNIDIRECTIONAL SPIN TORQUE TRANSFER MAGNETIC MEMORY CELL STRUCTURE - Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents. | 2012-05-17 |
20120120722 | PIPELINE ARCHITECTURE FOR SCALABLE PERFORMANCE ON MEMORY - An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times. | 2012-05-17 |
20120120723 | Dynamic Pulse Operation for Phase Change Memory - The control circuit performs a reset operation and a set operation that change the resistance states of phase change memory cells of the array. The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. This change is responsive to an indicator of degraded memory state retention of the array. | 2012-05-17 |
20120120724 | PHASE CHANGE MEMORY DEVICE - A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing. | 2012-05-17 |
20120120725 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device includes a memory array having memory cell strings including a first and a second memory cell groups having memory cells, a first and a second dummy elements, a drain select transistor and a source select transistor, wherein the first memory cell group and the second memory cell group are arranged between the drain select transistor and the source select transistor; connecting electrically the first memory cell group to the second memory cell group during a program operation or a read operation of the first memory cell group or the second memory cell group; and performing separately an erase operation of the first memory cell group and an erase operation of the second memory cell group, selecting simultaneously one of the first dummy element and the second dummy element during the erase operation of the selected memory cell group. | 2012-05-17 |
20120120726 | VARIABLE INITIAL PROGRAM VOLTAGE MAGNITUDE FOR NON-VOLATILE STORAGE - Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional programming passes include the programming of data. In another embodiment, all of the programming process includes programming data. For at least a subset of said programming processes, a program pulse associated with achieving a particular result for a respective programming process is identified. The identified program pulse is used to adjust programming for a subsequent programming process. | 2012-05-17 |
20120120727 | METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE - A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage. | 2012-05-17 |
20120120728 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers. | 2012-05-17 |
20120120729 | WORD LINE KICKING WHEN SENSING NON-VOLATILE STORAGE - Methods and devices for sensing non-volatile storage are disclosed. Technology disclosed herein reduces the time for sensing operations of non-volatile storage such as read and program verify. In one embodiment, a kicking voltage is applied to a selected word line during a sensing operation. The kicking voltage may be applied to one end of a selected word line during a transition from a first reference voltage to a second reference voltage. The kicking voltage may help the other end of the word line reach the second reference voltage quickly. Since the bit lines can be sensed after the selected word line has reached the target reference voltage, the time delay prior to sensing of the bit lines may be reduced. | 2012-05-17 |
20120120730 | METHOD AND APPARATUS FOR ADJUSTING MAXIMUM VERIFY TIME IN NONVOLATILE MEMORY DEVICE - A nonvolatile memory device is programmed by decoding a received address, determining whether the received address is a first type of page address or a second type of page address, adjusting a maximum verify time of a program loop used to verify a program state of page data according to the determined type of page address, and performing a verify operation during the adjusted maximum verify time. | 2012-05-17 |
20120120731 | SEMICONDUCTOR MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges. | 2012-05-17 |
20120120732 | NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF - A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed. | 2012-05-17 |
20120120733 | SEMICONDUCTOR DEVICE INCLUDING FUSE ARRAY AND METHOD OF OPERATION THE SAME - Provided are a semiconductor device including a fuse and a method of operating the same. The semiconductor device includes a fuse array, a first register unit, and a second register unit. The fuse array includes a plurality of rows and columns. The first register unit receives at least one row of fuse data from the fuse array. Fuse data of the at least one row of fuse data is received in parallel by the first register unit. The second register unit receives the fuse data at least one bit at a time from the first register unit. | 2012-05-17 |
20120120734 | DOUBLE LINE ACCESS TO A FIFO - An apparatus comprising a write data buffer circuit, a memory, and a read data buffer circuit. The write data circuit may be configured to present data in a second format in response to data received in a first format. The memory may be configured to (i) receive the data in the second format and (ii) present the data in the second format. The read data buffer circuit may be configured to (i) receive data in the second format and (ii) present data in a third format. The memory may be configured to allow two reads or two writes during a single clock cycle of reference clock without encountering a data overflow condition. | 2012-05-17 |
20120120735 | SEMICONDUCTOR DEVICE HAVING ELECTRICAL FUSE AND CONTROL METHOD THEREOF - To provide a plurality of fuse elements, each of which is either in a programmed state or a non-programmed state, a plurality of fuse determination circuits, each of which outputs a determination result signal that corresponds to a programmed state or a non-programmed state of the fuse element, and a plurality of latch circuits that commonly receive a first timing signal, and each of which latches and outputs the determination result signal synchronously with the first timing signal. | 2012-05-17 |
20120120736 | Self Pre-Charging and Equalizing Bit Line Sense Amplifier - A bit-line sense amplifier includes a latching unit and a control unit. The latching unit has a plurality of field effect transistors coupled between first and second bit lines. The control unit controls application of a bias voltage to a set of the field effect transistors such that respective pre-charge voltages are generated at the first and second bit lines with drain currents flowing in the field effect transistors during a pre-charge time period, without a bit line bias voltage and with a minimized number of transistors. | 2012-05-17 |
20120120737 | REPAIR CIRCUIT AND CONTROL METHOD THEREOF - A semiconductor memory apparatus including a repair circuit may comprise: a fuse set block configured to store a repair address, compare the repair address with an input address, and generate a primary repair signal; and a redundancy control block configured to receive the primary repair signal, determine whether a repair cell in a repair memory designated by the primary repair signal is failed or not, and generate a secondary repair signal which repair the failed repair cell with another repair cell in the repair memory. | 2012-05-17 |
20120120738 | SEMICONDUCTOR DEVICE - The semiconductor device makes a comparison between a word-line timing signal for determining a word-line activation time and a reference signal, applies a back-gate bias for enlarging a read margin when the result of the comparison represents a low condition of the read margin, and applies a back-gate bias for enlarging a write margin when the comparison result represents a low condition of the write margin. The reference signal is selected depending on whether to compensate an operating margin fluctuating according to the word-line activation time (or word-line pulse width), or to compensate an operating margin fluctuating according to the process fluctuation (or variation in threshold voltage). By controlling the back-gate biases according to the word-line pulse width, an operating margin fluctuating according to the word-line pulse width, and an operating margin fluctuating owing to the variation in threshold voltage during its fabrication are improved. | 2012-05-17 |
20120120739 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells. | 2012-05-17 |
20120120740 | Nonvolatile Memory Devices, Erasing Methods Thereof and Memory Systems Including the Same - Disclosed are erase methods for a memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the plurality of cell strings; applying a ground voltage to string selection lines connected with selection transistors of the plurality of cell strings; applying a word line erase voltage to word lines connected with memory cells of the plurality of cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage. | 2012-05-17 |
20120120741 | NONVOLATILE MEMORY DEVICE, READ METHOD FOR NONVOLATILE MEMORY DEVICE, AND MEMORY SYSTEM INCORPORATING NONVOLATILE MEMORY DEVICE - A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times. | 2012-05-17 |
20120120742 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a memory which can efficiently improve a yield by employing a structure which facilitates the use of a spare memory cell. The semiconductor device includes a memory cell array having a memory cell and a spare memory cell, a decoder connected to the memory cell and the spare memory cell, a data holding circuit connected to the decoder, and a battery which supplies electric power to the data holding circuit. The spare memory cell operates in accordance with an output from the data holding circuit. | 2012-05-17 |
20120120743 | SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor memory apparatus includes a shared pad which is configured to output a read operation control signal in a read operation and receive a write operation control signal in a write operation. | 2012-05-17 |
20120120744 | METHOD FOR SYNCHRONIZING SIGNALS AND PROCESSING DATA - A method for synchronizing signals includes the steps of receiving a preamble of a data strobe signal in response to a write preamble command, and synchronizing the data strobe signal with a clock signal through the preamble of the data strobe signal. | 2012-05-17 |
20120120745 | Semiconductor device and information processing system including the same - A semiconductor device includes: an input node supplied with an input signal; an output node provided correspondingly to the input node; first and second input circuits coupled in parallel to each other between the input and output nodes; and a control circuit configured to control the first and second input circuits such that one of the first and second input circuits is switched over from an active state to an inactive state and the other of the first and second input circuits is switched over from an inactive state to an active state during the one of the first and second input circuits being still in the active state. | 2012-05-17 |
20120120746 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus may comprise: an input buffer block configured to receive a write signal and a reference level signal, compare a the write signal with a the reference level signal to generate a first write control signal, and delay the first write control signal by a predetermined time to generate a second write control signal; a first decoder block configured to combine the second write control signal inputted from the input buffer block with externally inputted command signals, and generate a first write command signal; a clock control block configured to generate a clock control signal for determining determine a level of an internal clock signal in response to a level of the first write control signal outputted from the input buffer block; and a write signal control block configured to generate an internal write command signal according to a level of the first write command signal inputted from the first decoder block and the clock control signal inputted from the clock control block. | 2012-05-17 |
20120120747 | SEMICONDUCTOR DEVICE - A first data amplifier connects to a first memory cell identified by an X-address signal and a selection signal obtained by predecoding a Y-address signal. A second data amplifier connects to a second memory cell identified by the X-address signal and a delayed selection signal obtained by delaying the selection signal. A generator generates a delayed operation clock signal by delaying an operation clock signal of the first data amplifier. A timing controller receives a first control signal for controlling an operation of the first data amplifier and a second control signal for controlling an operation of the second data amplifier, outputs the first control signal to the first data amplifier at a timing according to the operation clock signal, and outputs the second control signal to the second data amplifier at a timing according to the delayed operation clock signal. | 2012-05-17 |
20120120748 | TEST APPARATUS AND REPAIR ANALYSIS METHOD - A test apparatus that tests a memory under test, comprising an address fail memory that stores address fail data for each address; a block fail memory that stores block fail data for each block; a reading section that reads the address fail data from the address fail memory for each block; a row fail counter that, for each row address in a group including a plurality of the blocks in the memory under test, counts the fail cells indicated by the address fail data; and a column fail counter that counts the fails cells for each column address. | 2012-05-17 |
20120120749 | JTAG CONTROLLED SELF-REPAIR AFTER PACKAGING - An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the integrated circuit has been packaged. The JTAG controlled self-repair system allows a user to direct circuitry to blow fuses using an externally supplied voltage to electrically couple or isolate components to permanently repair a memory location with JTAG standard TMS and TCK signals. The system may optionally sequentially repair more than one memory location using a repair sequencer. | 2012-05-17 |
20120120750 | SEMICONDUCTOR DEVICE HAVING ELECTRICAL FUSE AND CONTROL METHOD THEREOF - To provide an electrical fuse that is connected to a detection node via a selective transistor, a precharge transistor that precharges the detection node in a state where the selective transistor is off; a bias transistor that passes a bias current to the detection node in a state where the selective transistor is on and the precharge transistor is off, and a detection circuit that detects a potential of the detection node in a state where the bias current is flowing into the detection node, wherein the bias transistor reduces an amount of the bias current in a stepwise manner or a continuous manner. | 2012-05-17 |
20120120751 | SEMICONDUCTOR DEVICE HAVING EQUALIZING CIRCUIT EQUALIZING PAIR OF BIT LINES - A semiconductor device includes: a sense amplifier including an equalizing circuit that equalizes a pair of bit lines; an equalizing control circuit that converts the amplitude of an equalizing signal into a VDD level, and a word driver that controls a sub word line based on a timing signal. The word driver includes a level shift circuit for changing the operation timing of the sub word line in accordance with the VDD level, allowing a timing to complete the equalizing operation and a timing to reset the sub word line to synchronize even when the level of the VDD level is changed. | 2012-05-17 |
20120120752 | Dual-Port Semiconductor Memory and First-In First-Out (FIFO) Memory Having Electrically Floating Body Transistor - Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device. | 2012-05-17 |
20120120753 | Semiconductor device having point-shift type FIFO circuit - For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift register to generate an input pointer signal and a binary counter to generate an output pointer signal. The input selection circuit selects one of the latch circuits on the basis of a value of the input pointer signal. The output selection circuit selects one of the latch circuits on the basis of a value of the output pointer signal. Therefore, it is possible to prevent a hazard from occurring in the input selection circuit, as well as to reduce the number of signal lines that transmit the output pointer signal. | 2012-05-17 |
20120120754 | Semiconductor device including latency counter - For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density. | 2012-05-17 |
20120120755 | Beater attachment for use in commercial food mixers - A scraper attachment used with a food mixer made up of a plurality of elongated segments wherein each of said segments have a different degree of flexibility so that in operation food ingredients located in the mixing bowl is directed to the middle of the bowl | 2012-05-17 |
20120120756 | MODULAR MIXER - The invention relates to modular mixers for applications in modular microprocess technology. | 2012-05-17 |
20120120757 | TO CHEMICAL REACTOR APPARATUS - Support apparatus for a chemical reactor vessel comprises a mounting system comprising a collar device ( | 2012-05-17 |
20120120758 | METHODS FOR READING A FEATURE PATTERN FROM A PACKAGED DIE - Methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification used to fabricate the die and a product chip location for the die on a wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging. | 2012-05-17 |
20120120759 | IMMERSION CONTROL METHOD AND APPARATUS FOR A STATIONARY SEISMIC STREAMER - A seismic streamer incorporates apparatus for controlling its depth of immersion for modifying and maintaining its degree of immersion, wherein, the streamer being designed for stationary use and including a power supply network, the immersion control apparatus comprises a plurality of variable buoyancy ballasts connected to the power supply network of the streamer and installed at regular intervals along the seismic streamer and each associated with a microcontroller for at least controlling buoyancy of the corresponding ballast, a plurality of pressure sensors also installed at regular intervals along the streamer, at least one receiver for one or more desired value instructions, a bus for distributing the one or more desired value instructions to the ballasts, the microcontroller associated with a given ballasts being adapted to receive at least signals originating from at least one pressure sensor located in the proximity of the ballast and instruction signals originating from the receiver for instructions, being adapted to calculate a control signal for modifying the buoyancy of the ballast as a function of at least the signals received and being adapted to send this control signal at least to the corresponding ballast. | 2012-05-17 |
20120120760 | Active Detection of Marine Mammals During Seismic Surveying - An embodiment according to one or more aspects of the present disclosure for conducting a marine survey includes towing a survey spread comprising a plurality of receivers and an energy source along a selected course; emitting a signal from an energy source; receiving backscattered acoustic signals at the receivers; and actively detecting a cetacean from the received data. | 2012-05-17 |
20120120761 | INTEGRATED SYSTEM FOR INVESTIGATING SUB-SURFACE FEATURES OF A ROCK FORMATION - A system for investigating non-linear properties of a rock formation around a borehole is provided. The system includes a first sub-system configured to perform data acquisition, control and recording of data; a second subsystem in communication with the first sub-system and configured to perform non-linearity and velocity preliminary imaging; a third subsystem in communication with the first subsystem and configured to emit controlled acoustic broadcasts and receive acoustic energy; a fourth subsystem in communication with the first subsystem and the third subsystem and configured to generate a source signal directed towards the rock formation; and a fifth subsystem in communication with the third subsystem and the fourth subsystem and configured to perform detection of signals representative of the non-linear properties of the rock formation. | 2012-05-17 |
20120120762 | METHODS AND SYSTEMS FOR SEISMIC SIGNAL DETECTION - Methods and systems utilizing seismic sensors configured or designed for use in seismic signal detection. An electrical current is applied to a seismic sensor such that the moving coil is located at a neutral position relative to the magnetic field in the seismic sensor to compensate for gravitational acceleration. | 2012-05-17 |
20120120763 | SYSTEM AND METHOD FOR INVESTIGATING SUB-SURFACE FEATURES OF A ROCK FORMATION WITH ACOUSTIC SOURCES GENERATING CODED SIGNALS - A system and a method for investigating rock formations includes generating, by a first acoustic source, a first acoustic signal comprising a first plurality of pulses, each pulse including a first modulated signal at a central frequency; and generating, by a second acoustic source, a second acoustic signal comprising a second plurality of pulses. A receiver arranged within the borehole receives a detected signal including a signal being generated by a non-linear mixing process from the first-and-second acoustic signal in a non-linear mixing zone within the intersection volume. The method also includes-processing the received signal to extract the signal generated by the non-linear mixing process over noise or over signals generated by a linear interaction process, or both. | 2012-05-17 |
20120120764 | SYSTEM AND METHOD FOR INVESTIGATING SUB-SURFACE FEATURES AND 3D IMAGING OF NON-LINEAR PROPERTY, COMPRESSIONAL VELOCITY VP, SHEAR VELOCITY VS AND VELOCITY RATIO VP/VS OF A ROCK FORMATION - A system and a method for generating a three-dimensional image of a rock formation, compressional velocity VP, shear velocity VS and velocity ratio VP/VS of a rock formation are provided. A first acoustic signal includes a first plurality of pulses. A second acoustic signal from a second source includes a second plurality of pulses. A detected signal returning to the borehole includes a signal generated by a non-linear mixing process from the first and second acoustic signals in a non-linear mixing zone within an intersection volume. The received signal is processed to extract the signal over noise and/or signals resulting from linear interaction and the three dimensional image of is generated. | 2012-05-17 |
20120120765 | SYSTEM AND METHOD FOR INVESTIGATING SUB-SURFACE FEATURES OF A ROCK FORMATION WITH ACOUSTIC SOURCES GENERATING CONICAL BROADCAST SIGNALS - A method of interrogating a formation includes generating a conical acoustic signal, at a first frequency—a second conical acoustic signal at a second frequency each in the between approximately 500 Hz and 500 kHz such that the signals intersect in a desired intersection volume outside the borehole. The method further includes receiving, a difference signal returning to the borehole resulting from a non-linear mixing of the signals in a mixing zone within the intersection volume. | 2012-05-17 |
20120120766 | SYSTEM AND METHOD FOR INVESTIGATING SUB-SURFACE FEATURES OF A ROCK FORMATION USING COMPRESSIONAL ACOUSTIC SOURCES - A system and method for investigating rock formations outside a borehole are provided. The method includes generating a first compressional acoustic wave at a first frequency by a first acoustic source; and generating a second compressional acoustic wave at a second frequency by a second acoustic source. The first and the second acoustic sources are arranged within a localized area of the borehole. The first and the second acoustic waves intersect in an intersection volume outside the borehole. The method further includes receiving a third shear acoustic wave at a third frequency, the third shear acoustic wave returning to the borehole due to a non-linear mixing process in a non-linear mixing zone within the intersection volume at a receiver arranged in the borehole. The third frequency is equal to a difference between the first frequency and the second frequency. | 2012-05-17 |
20120120767 | DATA ACQUISITION AND PROCESSING SYSTEM AND METHOD FOR INVESTIGATING SUB-SURFACE FEATURES OF A ROCK FORMATION - A system and a method includes generating a first signal at a first frequency; and a second signal at a second frequency. Respective sources are positioned within the borehole and controllable such that the signals intersect in an intersection volume outside the borehole. A receiver detects a difference signal returning to the borehole generated by a non-linear mixing process within the intersection volume, and records the detected signal and stores the detected signal in a storage device and records measurement parameters including a position of the first acoustic source, a position of the second acoustic source, a position of the receiver, elevation angle and azimuth angle of the first acoustic signal and elevation angle and azimuth angle of the second acoustic signal. | 2012-05-17 |
20120120768 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME FOR CORRELATION DETECTION - In an embodiment a semiconductor device correlates a received signal with a known pattern. A correlation output is used as a basis for forming a confidence reference level. The confidence reference level and the correlation output are compared to identify a peak in the received signal indicating that a present signal state of the received signal contains the known pattern. | 2012-05-17 |
20120120769 | Method and System for Monitoring The Incursion of Particulate Material into A Well Casing within Hydrocarbon Bearing Formations Including Gas Hydrates - A method and system for monitoring any incursion of particulate matter from a gas hydrate formation into a well casing used for the production of the gas hydrate and determining the degree of incursion of particulate material within the distal end of the well casing. | 2012-05-17 |
20120120770 | ALARM CLOCK AND ALARM SHUTDOWN METHOD THEREOF - In a face recognition-based method for an alarm clock, an alarm time of an alarm clock and a predetermined time period are received from a user and saved in the alarm clock. Upon detecting that a current time matches the alarm time, the alarm clock executes an alarm and directs a capture unit to capture at least one image of the user. If the least one image captured from the capture unit includes an open-eye image and the open-eye image exists after the predetermined time period, the alarm clock turns off the alarm automatically. | 2012-05-17 |
20120120771 | ATHLETIC EVENT TIMING AND DISPLAY SYSTEMS - Presenting comparative timing data to the audience of a sports or other competition multiple within an event, where timing or scoring data is stored during each heat, compared between heats, and displayed. Timing data includes lap times, split times, or other timing information. Timing data from each heat can also be compared with historical timing records such as Olympic, NCAA, or other records. A computing device coupled to timing equipment, storage, and a display operate to gather and store timing data from each heat, compare the timing data to generate comparative timing data, and present the comparative timing data to attendees. A software application running on the computing device allows a user to select particular timing data to compare with the current event timing data. Video and biographical information about a given competitor in the event can also be presented to the user. | 2012-05-17 |
20120120772 | Electronic Timepiece with Internal Antenna - An electronic timepiece with internal antenna maintains sufficiently high reception performance of circularly polarized waves even when having a metal external case. The timepiece has a cylindrical case; a crystal that covers the opening on the face side of the case; a drive mechanism that arranged inside the case; a metal antenna; and a dielectric. The antenna houses the drive mechanism and has a cylindrical side part, a bottom part that covers the opening on the back side of the side part, and an antenna electrode that contacts the inside of the side part. The back cover covers the back side of the case and is also the bottom part. The dielectric extends circumferentially to the side part, and contacts the antenna electrode in the face-back cover direction. A slot extending circumferentially is formed in the antenna electrode. Part or all of the slot is covered by the dielectric. | 2012-05-17 |
20120120773 | Variable Snooze Alarm - A system, device and method provides a variable snooze alarm allowing a user to set multiple snooze alarm cycles to begin after an initial time alarm has sounded. In one form, before sleeping, the user can pre set or pre program the number of snooze alarm cycles that the device will go through after an initial alarm has sounded. In another form, during sounding of the initial alarm, the user can set multiple snooze alarm cycles that the device will go through. The variable snooze alarm may include a progressive volume feature that increases the alarm volume for each successive snooze alarm cycle. The variable snooze alarm feature may be provided as part of various devices such as alarm clocks, alarm clock radios, and portable electronic devices. As such, the present variable snooze alarm can run on any operating system and/or platform. It can also be a stand-alone electronic device. | 2012-05-17 |
20120120774 | Anchor escapement and mechanical watch having the same - An anchor escapement of a mechanical watch has an escape wheel, a pallet fork engageable with or disengageable from a roller jewel of a pallet shaft having banking pin engaging portions at both sides, and pallet bridges engageable with the banking pin engaging portions at the pallet engaging portions to define the swing range of the pallet fork. One of the pallet shaft and the pallet bridges has elastic arm portions having engaging portions engageable with the engaging portions of the other member of the pallet shaft and the pallet bridge in a state in which the pallet fork fixes the escape wheel at the pallet jewel. | 2012-05-17 |
20120120775 | DRIVING MECHANISM FOR WATCH MOVEMENT - Driving mechanism for watch movement having: a barrel mounted on an arbor so as to be capable of turning around an axis of the arbor when the driving mechanism is wound up. A mainspring unit has a first and second spring coiled up inside the barrel in superimposed fashion and coaxial one relative to the other. The first and second springs are coupled at one of their extremities to the barrel and to the arbor, respectively. The unit has a plate mounted coaxially between the two springs, and mounted rotatively on the axis. The first and second springs are coupled at their other extremity to the centre and to the periphery of the plate, respectively, so that the two springs simultaneously wind up around the axis when the driving mechanism is wound up. | 2012-05-17 |
20120120776 | EXTERIOR ELEMENT FOR A WRISTWATCH - An external element for a wristwatch, containing an electronic device and a power source for powering the electronic device with electric energy, wherein the electronic device and power source are integrated in the exterior element, to form an autonomous electronic module, which is completely independent of the wristwatch movement. | 2012-05-17 |
20120120777 | Timepiece - A wristwatch includes a case formed of a glass and a back lid attached to a case body that has an annular receiving portion on an inner peripheral surface thereof. An inner frame is integrated into the case body by engaging an engaging portion of the inner frame with the annular receiving portion from the side of the back lid. A movement is supported inside the inner frame, and a plurality of resilient bodies are attached to the inner frame and project from the outer peripheral surface of the inner frame. The resilient bodies are clamped between the inner peripheral surface of the case body and the outer peripheral surface of the inner frame, and are resiliently deformed so as to match a gap between the inner peripheral surface and the outer peripheral surface. | 2012-05-17 |
20120120778 | Timepiece - A wristwatch case includes a case body, an edge member, and a mounting ring. The case body has a circular fitting hole, an edge receiving surface, and an engaging surface. The edge member includes a cylindrical portion extending through the fitting hole, a cover portion, a male screw portion, and a receiving portion. The cover portion is provided on an outer periphery of the cylindrical portion that projects out of the case body and overlaps the edge receiving surface. The male screw portion is formed on the outer periphery of the cylindrical portion that is inserted into the case body. The receiving portion is formed on the cylindrical portion and receives a peripheral portion of a dial of the movement. The mounting ring is screwed onto the male screw portion and comes into contact with the engaging surface to fix the edge member to the case body. | 2012-05-17 |
20120120779 | DEVICE FOR LOCKING A TIMEPIECE MOVEMENT - A timepiece including a case including a middle part, which is closed on the top portion thereof by a bezel and on the bottom portion by a back cover, and a timepiece movement mounted against the middle part by a casing ring. The timepiece also includes a locking device for pressing the assembly including the timepiece movement and casing ring against the middle part when the case of the timepiece is closed. | 2012-05-17 |
20120120780 | THERMALLY-ASSISTED MAGNETIC RECORDING HEAD COMPRISING PLASMON GENERATOR - Provided is a thermally-assisted magnetic recording head in which NF-light with sufficiently high light density can be applied to a medium while a write-field generating point and a near-field light (NF-light) generating point are close to each other. The head comprises a plasmon generator provided between a magnetic pole and a waveguide and configured to be coupled with light propagating through the waveguide in a surface plasmon mode to emit NF-light. The plasmon generator comprises: a plasmon propagating part comprising a propagation edge for propagating surface plasmon excited by the light; and a light penetration suppressing part with an extinction coefficient greater than the plasmon propagating part. The light penetration suppressing part is in surface-contact with a surface portion of the plasmon propagating part excluding the propagation edge, and the magnetic pole is in surface-contact with the light penetration suppressing part. This configuration can avoid significant reduction in light use efficiency of an optical system generating NF-light due to partial absorption of electromagnetic field (light) into the magnetic pole. | 2012-05-17 |
20120120781 | Thermally-Assisted Head Including Surface-Plasmon Resonant Optical System - Provided is a surface plasmon resonating optical system emitting near-field light (NF-light) with a higher light density. The system comprises: a waveguide through which a light for exciting surface plasmon propagates; a plasmon generator that couples with the light in a surface plasmon mode and emits NF-light from its NF-light generating end surface; and a resonator mirror that reflects the excited surface plasmon, provided on the side of the plasmon generator opposite to the NF-light generating end surface. In the system, the excited surface plasmon can be amplified by using a resonator structure while reducing the length of the plasmon generator to reduce absorption of surface plasmon and prevent overheating of the plasmon generator. | 2012-05-17 |
20120120782 | CIRCUIT FOR GENERATING TRACKING ERROR SIGNAL - A circuit for generating a tracking error signal is provided. The circuit includes a digitizing circuit, a short signal removing circuit and phase comparator. The digitizing circuit receives first and second pick-up signals outputted from a pick-up head, and respectively compares the first and the second pick-up signals with a reference signal to obtain a first digital signal and a second digital signal. The short signal removing circuit is used for removing pulses in the first and the second digital signals, wherein the pulse width of the removed pulses are shorter than a preset time, and the first and second digital without the removed pulses are respectively served as a first determining signal and a second determining signal. The phase comparator receives the first determining signal and the second determining signal for outputting the tracking error signal according to a phase difference between the first and the second determining signals. | 2012-05-17 |
20120120783 | GUIDE-LAYER SEPARATED OPTICAL DISK, OPTICAL DISK DRIVE APPARATUS, AND TRACKING CONTROL METHOD - A guide-layer separated optical disk which includes a guide layer having a guide structure whose tracking guide tracks are divided into areas by discontinuous portions, the areas each having concentric guide tracks of arc shape at a regular track pitch, the guide tracks in adjoining two of the areas across one of the discontinuous portions deviating from each other in a radial direction of the disk by ¼ the track pitch. An optical disk drive apparatus and a tracking control method in which a servo optical system switches the tracking center of the irradiation spot of a first laser beam between on the guide tracks and in between the guide tracks alternately each time the irradiation spot passes two of the discontinuous portions. | 2012-05-17 |
20120120784 | Systems and Methods for Sync Mark Detection Metric Computation - Various embodiments of the present invention provide systems and methods for data processing. As an example, a pattern detection circuit is discussed that includes a distance calculation circuit and a comparator circuit. The distance calculation circuit is operable to calculate a noise whitened distance between a reference signal and a received input to yield a comparison value. The comparator circuit is operable to compare the comparison value with a threshold value. | 2012-05-17 |
20120120785 | Optical Pickup Device - Provided is an optical pickup device which suppresses the decrease of light amount and performs conversion to circular polarization light, wherein the optical pickup device includes a beam splitter and a raising mirror on each of which a layered member is formed, and the optical pickup device satisfies conditional expressions relating to intensities of S-polarized light and P-polarized light with respect to the beam splitter of a laser beam emitted from a semiconductor laser element, reflecances of S-polarized light and P-polarized light on the beam splitter, a reflection phase difference obtained by subtracting a phase of S-polarized light from a phase of P-polarized light after the reflection, reflectances of S-polarized light and P-polarized light on the raising mirror, and a reflection phase difference obtained by subtracting a phase of S-polarized light from a phase of P-polarized light after the reflection. | 2012-05-17 |
20120120786 | DISC CARTRIDGE - A disc cartridge includes a case body for receiving disc-shaped recording media in an axial direction of a central shaft so that first and second shells respectively having a base surface portion parallel to a recording surface of the disc-shaped recording media are coupled separated by axial engagement/disengagement; and a lock lever supported perpendicular to the axial direction in the case body and locking the shells coupled. The shells are separated to form a disc insertion/extraction hole for the insert or discharge of the disc-shaped recording media into/from the case body. A support shaft serving as a pivoting point of the lock lever is installed to the case body. The lock lever includes a supported portion supported by the support shaft, a lock portion protruding from the supported portion and locking the shells, and a balance portion protruding from the supported portion approximately opposite to protrusion of the lock portion. | 2012-05-17 |
20120120787 | RECTANGULAR POWER SPECTRAL DENSITIES OF ORTHOGONAL FUNCTIONS - In this application, a set of orthogonal functions is introduced whose power spectral densities are all rectangular shape. To find the orthogonal function set, it was considered that their spectrums (Fourier transforms of the functions) are either real-valued or imaginary-valued, which are corresponding to even and odd real-valued time domain signals, respectively. The time domain functions are all considered real-valued because they are actually physical signals. The shape of the power spectral densities of the signals are rectangular thus, the Haar orthogonal function set can be employed in the frequency domain to decompose them to several orthogonal functions. Based on the inverse Fourier transform of the Haar orthogonal functions, the time domain functions with rectangular power spectral densities can be determined. This is equivalent to finding the time-domain functions by taking the inverse Fourier transform of the frequency domain Walsh functions. The obtained functions are sampled and truncated to generate finite-length discrete signals. Truncation destroys the orthogonality of the signals. The Singular Value Decomposition method is used to restore the orthogonality of the truncated discrete signals. | 2012-05-17 |
20120120788 | METHOD, SYSTEM AND DEVICE FOR RECOVERING INVALID DOWNLINK DATA TUNNEL BETWEEN NETWORKS - Described herein is a method for processing an invalidation of a downlink data tunnel between networks. The method includes the following steps: (1) a core network user plane anchor receives an error indication of data tunnel sent from an access network device, (2) after deciding that the user plane corresponding to the error indication uses a One Tunnel technology, the core network user plane anchor notifies a relevant core network control plane to request recovering the downlink data tunnel, (3) the core network control plane recovers the downlink data tunnel and notifies the core network user plane anchor to update information of the user plane. In addition, a communication system and a communication device are also provided. The method, system, and device can improve the speed of recovering data transmission after the downlink data tunnel becomes invalid. | 2012-05-17 |
20120120789 | SYSTEMS AND METHODS FOR IMPROVING CIRCUIT SWITCHED FALLBACK PERFORMANCE - Methods and apparatus for improving Circuit Switched (CS) Fallback performance, such as in an LTE network, are described. In one aspect, a UE may perform a RAU procedure before performing a CS call setup procedure when the UE has camped on a Non-DTM GERAN target after failing to access a redirection target. In another aspect, an MME may determine whether to perform a PS suspension based on an ISR status associated with a user terminal. In another aspect, an eNB may send information associated with a PS suspension to a user terminal. | 2012-05-17 |
20120120790 | Coordinated Fault Protection System - A power distribution protection system and method uses communications to coordinate operation of fault protection devices. Communications may be prioritized wherein messages of a lower priority are held or discarded in favor of messages of a higher priority, for example, messages indicating a fault condition. The devices may use multiple channel access schemes in accordance with a priority of a message to be communicated. | 2012-05-17 |
20120120791 | AUTOMATIC REDUNDANT LOGICAL CONNECTIONS | 2012-05-17 |
20120120792 | MONITOR/CONTROL DEVICE AND MONITOR TARGET DEVICE - A monitor and control device includes a monitor and control unit transmitting to a monitor target device a monitor and control signal (M&CS) through a M&CS path in a case of a malfunction occurred in a main signal path, and transmits to the monitor target device the M&CS through the main signal path in a case of a malfunction occurred in the M&CS path, the monitor target device including: a first path connection unit connected to the main signal path passing either a main signal in which the M&CS for monitoring and controlling the monitor target device is multiplexed or a main signal in which the M&CS is not multiplexed; a second path connection unit connected to the M&CS path passing the M&CS; and a selection unit selecting whether to perform transmission and reception of the M&CS by either one of the main signal path and the M&CS path. | 2012-05-17 |
20120120793 | METHODS AND APPARATUS FOR PROTECTING A COMMUNICATIONS NETWORK - The invention relates in general to a communications network, and more particularly, to methods and apparatus for protecting such a network. The methods and apparatus disclose the providision path protection in a communications network ( | 2012-05-17 |
20120120794 | METHOD AND APPARATUS FOR CONTROLLING TRAFFIC - A method for controlling traffic in a mobile communication network is provided. A traffic control apparatus checks locations of a calling terminal and a receiving terminal, and determines whether to perform terminal-to-terminal direct communication based on the locations of the calling terminal and the receiving terminal. A base station of the calling terminal and a base station of the receiving terminal instruct the calling terminal and the receiving terminal to perform the terminal-to-terminal direct communication when the terminal-to-terminal direct communication is determined to be performed. | 2012-05-17 |
20120120795 | SYSTEM AND METHOD FOR INCREASING GRANULARITY OF PREFIX CONTROL IN A COMPUTER NETWORK - In one embodiment, a routing table of a router is populated with a plurality of prefixes. One or more performance characteristics of the plurality of prefixes are monitored. The router determines that a need exists to split a selected prefix of the plurality of prefixes. The router determines one or more boundaries upon which to split the selected prefix based on the monitored performance characteristics. The router then injects one or more more-specific prefixes into the routing table, each more-specific prefix referring to a smaller subset of nodes than the selected prefix, to split the selected prefix on the one or more boundaries to create a plurality of split prefixes. The split prefixes are controlled to optimize distribution of traffic. | 2012-05-17 |
20120120796 | METHOD AND SYSTEM FOR PROVIDING A PRIORITY-BASED, LOW-COLLISION DISTRIBUTED COORDINATION FUNCTION USING A SUPER-FRAME STRUCTURE - A method for providing a priority-based, low-collision distributed coordination function (DCF) in a wireless network is provided. The network includes an access point and a plurality of stations. The method includes receiving at a first station a super-frame from the access point. The super-frame is operable to define a service period for each of the stations. A priority for the first station is determined based on the super-frame. A back-off time is selected for the first station based on the priority. | 2012-05-17 |
20120120797 | Method and System for Managing Time-Sensitive Packetized Data Streams at a Receiver - According to one embodiment of the invention, a method for managing time-sensitive packetized data streams at a receiver includes receiving a time-sensitive packet of a data stream, analyzing an energy level of a payload signal of the packet, and determining whether to drop the packet based on the energy level of the payload signal. | 2012-05-17 |
20120120798 | POLICING USAGE OF DATA NETWORKS - Methods and systems for policing usage by one or more users ( | 2012-05-17 |
20120120799 | DATA BUNDLING AND FAST DORMANCY BASED UPON INTERACTIVITY - A system and methodology that performs data bundling and controls fast dormancy based on user interaction with a user equipment (UE) is provided. Moreover, the system provides a balance between saving battery power of the UE and reducing signaling and processing load in a radio resource controller (RRC). Specifically, the system observes user inputs and data flow requests to identify “interactive” and “non-interactive” data flows. On receiving a data flow request, the system determines whether the data flow can be bundled together and transmitted over a single connection with disparate data flows, based on the classification of the data flow. Additionally, on completion of a data flow, the system determines whether a fast dormancy timer can be disabled/delayed to transmit a next data flow over the current connection, based on the classification of the data flow. | 2012-05-17 |
20120120800 | Request Modification for Transparent Capacity Management in a Carrier Network - Some embodiments provide a capacity management agent that modifies content requests to adjust bandwidth consumption when streaming requested content from a content provider to a requesting user. The modifications include modifying a URL or header information of the request. The agent performs a process that receives a request for content of a content provider. The process identifies a parameter of the carrier network and modifies the request when the parameter satisfies a threshold. The process passes the request to the content provider and the content provider provides content that consumes a first set of resources in response to an unmodified request and a second set of resources in response to a modified request. When the parameter identifies congestion, the first set of resources is greater than the second set of resources. When the condition parameter identifies underutilization, the first set of resources is less than the second set of resources. | 2012-05-17 |
20120120801 | NETWORK-FRIENDLY TRANSMISSION CONTROL PROTOCOL (TCP) METHODS, APPARATUS AND ARTICLES OF MANUFACTURE - Example methods, apparatus and articles of manufacture to route policy requests are disclosed. A disclosed example method includes sending bandwidth probe packets at a probing rate, receiving a packet containing an indication representative of whether the probe packets triggered congestion, and selecting a transmission rate for sending data packets based on the probing rate and the indication. | 2012-05-17 |
20120120802 | APPARATUS - An apparatus comprising a processor configured to initiate re-selection and/or re-registration procedures and, responsive to a first parameter, delay initiation of re-selection and/or re-registration procedures for a random and/or pseudo-random delay value. | 2012-05-17 |
20120120803 | NODE AND METHOD FOR COMPUTING FORWARDING TREES TO DISTRIBUTE TRAFFIC IN A NETWORK - A node and a method are described herein for computing forwarding trees to distribute traffic in a network. In addition, a network is described herein that has a plurality of nodes interconnected to one another by a plurality of network links, and each node is configured to perform multiple rounds of forwarding tree computations to distribute traffic load on one or more of the network links to the other nodes. | 2012-05-17 |
20120120804 | Load Scheduling in Wideband Code Division Multiple Access - A method for load scheduling in a WCDMA communication system utilizing GRake equalizing radio reception comprises estimating ( | 2012-05-17 |
20120120805 | Client based congestion control mechanism - The invention concerns a method of notifying control information to a congestion control mechanism in charge of controlling data segments sending rate of a server towards a client. The control information includes loss events where a loss event corresponds to one or more data segments lost. The method comprises a step of receiving data segments into a reception buffer at the client, a step of detecting loss events from the received data segments and a step of notifying the congestion control mechanism with a number of loss events that is dependent on the number of detected loss events and a measure of criticality related to the reception of the data segments by the client. The measure of criticality can be derived from the filling level of the reception buffer, the reception of data segments being in a critical state when the reception buffer is experiencing overflow or underflow conditions. | 2012-05-17 |