20th week of 2014 patent applcation highlights part 17 |
Patent application number | Title | Published |
20140131826 | SPATIALLY DISTRIBUTED CdS IN THIN FILM PHOTOVOLTAIC DEVICES AND THEIR METHODS OF MANUFACTURE - Thin film photovoltaic devices are provided. The device includes a transparent substrate; a transparent conductive oxide layer on the transparent substrate; an n-type window layer on the transparent conductive oxide layer, an absorber layer on the n-type window layer, and a back contact layer on the absorber layer. The n-type window layer includes a plurality of nanoparticles spatially distributed within a medium, with the nanoparticles comprising cadmium sulfide. In one embodiment, the medium has an optical bandgap that is greater than about | 2014-05-15 |
20140131827 | AVALANCHE PHOTODIODE AND METHOD OF MANUFACTURE THEREOF - An i-type AlInAs avalanche multiplication layer is grown on an n-type InP substrate. A p-type AlInAs electric field reduction layer is grown on the i-type AlInAs avalanche multiplication layer. Transition layers are grown to cover the top surface of the electric field reduction layer. After the covering of the top surface of the electric field reduction layer by the transition layers, the temperature of the growth process is increased and an n | 2014-05-15 |
20140131828 | SOLID-STATE IMAGING APPARATUS AND METHOD FOR MANUFACTURING SAME - An insulating layer is layered above a substrate, and a plurality of pixel electrodes are formed above the insulating layer in a matrix with intervals therebetween. A photoelectric conversion layer and an opposing electrode are formed in respective order above the pixel electrodes. A dummy layer is formed above the insulating layer in a region that in plan-view is more peripheral than a pixel region in which the pixel electrodes are formed. The dummy layer is formed from the same material as the pixel electrodes. The dummy layer is composed of a plurality of dummy layer portions that are each equal to each of the pixel electrodes in terms of size in plan-view. The dummy layer functions as a support layer for planarization during polishing by chemical mechanical polishing. | 2014-05-15 |
20140131829 | ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME - A method of forming of a semiconductor structure has isolation structures. A substrate having a first region and a second region is provided. The first region and the second region are implanted with neutral dopants to form a first etching stop feature and a second stop feature in the first region and the second region, respectively. The first etching stop feature has a depth D | 2014-05-15 |
20140131830 | SOLID STATE DEVICES HAVING FINE PITCH STRUCTURES - In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded. | 2014-05-15 |
20140131831 | INTEGRATED CIRUIT INCLUDING AN FIN-BASED DIODE AND METHODS OF ITS FABRICATION - A method is provided for forming an integrated circuit having a diode. The method includes forming at least one fin in a shallow trench isolation (STI) oxide layer disposed above a substrate layer. The at least one fin extends from a bottom end adjacent the substrate layer to a top end. The method further includes adding a cathode implant in a first region of the at least one fin and the substrate layer and adding an anode implant in a second region of the at least one fin and the substrate layer such that a junction is formed in the substrate layer below the at least one fin. The method also includes etching away a portion of the STI oxide layer to expose the top end of the at least one fin. | 2014-05-15 |
20140131832 | METHOD FOR MANUFACTURING SEMICONDUCTOR LAYOUT PATTERN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes providing a substrate having a mask layer formed thereon, providing a first photomask having a first layout pattern and a second photomask having a second layout pattern, the first layout pattern including a plurality of active area portions and at least a neck portion connecting two adjacent active area portions, transferring the first layout pattern from the first photomask to the mask layer to form a plurality of active area patterns and at least a neck pattern connecting two adjacent active area patterns in the mask layer, and transferring the second layout pattern from the second photomask to the mask layer to remove the neck pattern to form a patterned mask. The patterned mask includes the active area patterns. A slot is at least formed between the two adjacent active area patterns. | 2014-05-15 |
20140131833 | BODY-BIAS VOLTAGE ROUTING STRUCTURES - Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit. | 2014-05-15 |
20140131834 | DECOUPLING CAPACITORS FOR INTERPOSERS - Embodiments of the invention generally relate to interposers for packaging integrated circuits. The interposers include capacitive devices for reducing signal noise and leakage between adjacent integrated circuits coupled to the interposers. The capacitive devices are formed from doped semiconductor layers. In one embodiment, an interposer includes a substrate having doped regions of opposing conductivities. First and second oxide layers are disposed over the doped regions. A first interconnect disposed in the second oxide layer is electrically coupled to a doped region of a first conductivity, and a second interconnect disposed in the second oxide is electrically coupled to a doped region of a second conductivity. Additional capacitive devices utilizing doped semiconductor layers are also disclosed. | 2014-05-15 |
20140131835 | SEMICONDUCTOR DEVICE WITH RUTILE TITANIUM OXIDE DIELECTRIC FILM - A capacitor structure includes a first electrode on a substrate; a template layer on the first electrode; a titanium oxide (TiO2) dielectric layer on the template layer, wherein the TiO2 dielectric layer has substantially only rutile phase; and a second electrode on the TiO2 dielectric layer. The titanium oxide dielectric layer is an undoped titanium oxide dielectric layer. | 2014-05-15 |
20140131836 | DIELECTRIC TRENCHES, NICKEL/TANTALUM OXIDE STRUCTURES, AND CHEMICAL MECHANICAL POLISHING TECHNIQUES - A portion of a conductive layer ( | 2014-05-15 |
20140131837 | GAN VERTICAL BIPOLAR TRANSISTOR - An embodiment of a semiconductor device includes a III-nitride base structure of a first conductivity type, and a III-nitride emitter structure of a second conductivity type having a first surface and a second surface. The second surface is substantially opposite the first surface. The first surface of the III-nitride emitter structure is coupled to a surface of the III-nitride base structure. The semiconductor also includes a first dielectric layer coupled to the second surface of the III-nitride emitter structure, and a spacer coupled to a sidewall of the III-nitride emitter structure and the surface of the III-nitride base structure. The semiconductor also includes a base contact structure with a III-nitride material coupled to the spacer, the surface of the III-nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the III-nitride emitter structure. | 2014-05-15 |
20140131838 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. Semiconductor units are arranged on a substrate. A material layer is formed on the semiconductor units. A first patterned mask layer is formed on the semiconductor units. The first patterned mask layer has a mask opening corresponding to a portion of the semiconductor units and exposing the material layer. A portion of the material layer exposed by the mask opening is removed to remain a portion of the material layer on a sidewall of each of the semiconductor units exposed by the mask opening to form spacer structures. | 2014-05-15 |
20140131839 | Etching Method Using Block-Copolymers - A method for lithography is disclosed. The method includes obtaining a self-organizing block-copolymer layer on a neutral layer overlying a substrate, the self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, the self-organizing block-copolymer layer furthermore comprising a copolymer pattern structure formed by micro-phase separation of the at least two polymer components. Further, the method includes etching selectively a first polymer component of the self-organizing block-copolymer layer, thereby remaining a second polymer component. Still further, the method includes applying a plasma etching to the neutral layer using the second polymer component as a mask, wherein the plasma etching comprises an inert gas and H | 2014-05-15 |
20140131840 | WAFER AND METHOD OF MANUFACTURING THE SAME - A wafer includes a first die, a second die, and a scribe lane located between the first die and the second die. The scribe lane includes a first doped silicon region, and does not directly contact the first die and the second die. | 2014-05-15 |
20140131841 | METAL PAD STRUCTURE OVER TSV TO REDUCE SHORTING OF UPPER METAL LAYER - Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced. | 2014-05-15 |
20140131842 | AXIAL SEMICONDUCTOR PACKAGE - An axially-mountable device includes a semiconductor chip comprising lower and upper electrical contacts. A lower die pad is electrically and mechanically connected to the lower electrical contact of the chip. An upper die pad is electrically and mechanically connected to the upper electrical contact of the chip. A first axially extending electrical lead is electrically and mechanically connected to the upper die pad and extends in a first axial direction. A second axially extending electrical lead is electrically and mechanically connected to the lower die pad and extends in a second axial direction that is opposite to the first axial direction. Packaging material encapsulates the semiconductor chip, the upper and lower die pads and a portion of the first and second axially extending leads. The first and second leads extend from the packaging material and are adapted to allow the device to be axially-mounted with another electrical component. | 2014-05-15 |
20140131843 | MAGNETICALLY COUPLED GALVANICALLY ISOLATED COMMUNICATION USING LEAD FRAME - An integrated circuit package includes an encapsulation and a lead frame. A portion of the lead frame is disposed within encapsulation. The lead frame includes a first conductor having a first conductive loop disposed substantially within the encapsulation. The lead frame also includes a second conductor that is galvanically isolated from the first conductor. The second conductor includes a second conductive loop that is substantially disposed within the encapsulation proximate to and magnetically coupled to the first conductive loop to provide a communication link between the first and second conductors. | 2014-05-15 |
20140131844 | System and Method for an Electronic Package with a Fail-Open Mechanism - A semiconductor package including a fail open mechanism is disclosed. An embodiment includes a semiconductor package having a chip carrier, a chip disposed on the chip carrier and an encapsulant encapsulating the chip and the chip carrier. The semiconductor package further including a pin protruding from the encapsulant and a fail open mechanism disposed on the encapsulant and connected to the pin, wherein the fail open mechanism is configured to be disconnected from the pin if a temperature exceeds a pre-determined temperature. | 2014-05-15 |
20140131845 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, a capacitor, a first resin, lead frames and a second resin. The first resin forms a resin molding which covers the semiconductor element and the capacitor. The lead frames are attached to two surfaces of the resin molding and are connected to the semiconductor element and the capacitor. The second resin directly covers the capacitor and has a rigidity lower than a rigidity of the first resin. An outside of the second resin is directly covered with the first resin. | 2014-05-15 |
20140131846 | POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - A power semiconductor module has a first frame portion, a power semiconductor element, a second frame portion, a control integrated circuit, a wire, and an insulator portion. The power semiconductor element is mounted on a first surface of the first frame portion. The control integrated circuit is mounted on a third surface of the second frame portion for controlling the power semiconductor element. A wire has one end connected to the power semiconductor element and the other end connected to the control integrated circuit. The first surface of the first frame portion and the third surface of the second frame portion are located at the same height in a direction vertical to the first surface of the first frame portion. | 2014-05-15 |
20140131847 | THERMAL PERFORMANCE OF LOGIC CHIP IN A PACKAGE-ON-PACKAGE STRUCTURE - Embodiments of the invention provides an IC system in which low-power chips can be positioned vertically proximate high-power chips without suffering the effects of overheating. In one embodiment, the IC system includes a first substrate, a high-power chip disposed on a first side of the first substrate, a thermal conductive pad disposed on a second side of the first substrate, one or more thermal conductive features formed in the first substrate, wherein the thermal conductive features thermally connect the high-power chip and the thermal conductive pad, and a heat sink attached to a surface of the thermal conductive pad, wherein the heat sink is in thermal communication with the thermal conductive pad. By having thermal conductive features formed through the first substrate to thermally connect the high-power chip and the thermal conductive pad, heat generated by the high-power chip can be effectively dissipated into the heat sink. | 2014-05-15 |
20140131848 | LAND STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD THEREFOR - In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the adhesion pad and the land structure from each other, to expose a top surface of the resin layer, and to form at least one land having a part with a relatively greater size than the size of a respective lower part. | 2014-05-15 |
20140131849 | STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR - A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. | 2014-05-15 |
20140131850 | MICROCHIP WITH BLOCKING APPARATUS AND METHOD OF FABRICATING MICROCHIP - A microchip has a base die with a conductive interconnect and an isolation trench around at least a portion of the conductive interconnect, and a cap die secured to the base die. A seal, formed from a metal material, is positioned between the base die and the cap die to secure them together. The microchip also has a blocking apparatus, between the isolation trench and the metal seal, that at least in part prevents the metal material from contacting the interconnect. | 2014-05-15 |
20140131851 | STRUCTURE FOR MICROELECTRONIC PACKAGING WITH TERMINALS ON DIELECTRIC MASS - A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element. | 2014-05-15 |
20140131852 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor integrated circuit sandwiched between a pair of a first impact resistance layer and a second impact resistance layer, an impact diffusion layer is provided between the semiconductor integrated circuit and the second impact resistance layer. By provision of the impact resistance layer against the external stress and the impact diffusion layer for diffusing the impact, force applied to the semiconductor integrated circuit per unit area is reduced, so that the semiconductor integrated circuit is protected. The impact diffusion layer preferably has a low modulus of elasticity and high breaking modulus. | 2014-05-15 |
20140131853 | ELECTRONIC COMPONENT, METHOD OF MANUFACTURING SAME, COMPOSITE MODULE INCLUDING ELECTRONIC COMPONENT, AND METHOD OF MANUFACTURING SAME - A method of manufacturing a composite module prevents a connection electrode electrically coupled to a functional element from separating from a first principal surface of an element substrate. A transmission filter element, a reception filter element, connection electrodes electrically coupled to the transmission filter element and the reception filter element, and an insulating layer surrounding the transmission filter element, the reception filter element, and the connection electrodes are disposed on a first principal surface of an element substrate. The insulating layer covers at least a portion of the surface of each of the connection electrodes. Because the portion of the surface of each of the connection electrodes in an exposed state is covered with the insulating layer, the connection electrodes electrically coupled to the transmission filter element and the reception filter element are prevented from separating from the first principal surface of the element substrate. | 2014-05-15 |
20140131854 | MULTI-CHIP MODULE CONNECTION BY WAY OF BRIDGING BLOCKS - One aspect provides an integrated circuit (IC) multi-chip packaging assembly, comprising a first IC chip having packaging substrate contacts and bridging block contacts, a second IC chip having packaging substrate contacts and bridging block contacts, and a bridging block partially overlapping the first and second IC chips and having interconnected electrical contacts on opposing ends thereof that contact the bridging block contacts of the first IC chip and the second IC chip to thereby electrically connect the first IC chip to the second chip. | 2014-05-15 |
20140131855 | THERMOCOMPRESSION FOR SEMICONDUCTOR CHIP ASSEMBLY - A method of assembling a semiconductor chip to a substrate wherein at least one of the semiconductor chip and substrate comprise solder bumps. The method includes aligning the semiconductor chip with the substrate; applying a compression force to the semiconductor chip to cause the solder bumps to deform between the semiconductor chip pads and the substrate pads, the compression force being applied while the semiconductor chip and substrate are held at a temperature above room temperature and below a temperature at which any liquid will form in at least one of the solder bumps; then applying an underfill material to fill the gap between the chip and substrate; and then heating the assembled semiconductor chip and substrate to an elevated temperature to cause the solder bumps to melt and reflow and form a metallurgical bond between the semiconductor chip pads and the substrate pads. | 2014-05-15 |
20140131856 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer. | 2014-05-15 |
20140131857 | BARRIER LAYER ON BUMP AND NON-WETTABLE COATING ON TRACE - Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized. | 2014-05-15 |
20140131858 | Warpage Control of Semiconductor Die Package - Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved. | 2014-05-15 |
20140131859 | SOLDER FATIGUE ARREST FOR WAFER LEVEL PACKAGE - A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 μm) and fifty micrometers (50 μm) from the lead. In some embodiments, the core covers between at least approximately one-third (⅓) and one-half (½) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core. | 2014-05-15 |
20140131860 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC DEVICE - A semiconductor device includes a semiconductor substrate; an active element configured to be formed on the semiconductor substrate; and a multi-layer wiring structure configured to be formed on the semiconductor substrate. A heat dissipation structure is provided in the multi-layer wiring structure. The upper end of the heat dissipation structure forms an external connection pad to be connected with an external wiring board, and the lower end of the heat dissipation structure makes contact with a surface of the semiconductor substrate outside of an element forming region for the active element. | 2014-05-15 |
20140131861 | Plasma Treatment for Semiconductor Devices - A semiconductor device having a polymer layer and a method of fabricating the same is provided. A two-step plasma treatment for a surface of the polymer layer includes a first plasma process to roughen the surface of the polymer layer and loosen contaminants, and a second plasma process to make the polymer layer smoother or make the polymer layer less rough. An etch process may be used between the first plasma process and the second plasma process to remove the contaminants loosened by the first plasma process. In an embodiment, the polymer layer exhibits a surface roughness between about 1% and about 8% as measured by Atomic Force Microscopy (AFM) with the index of surface area difference percentage (SADP) and/or has surface contaminants of less than about 1% of Ti, less than about 1% of F, less than about 1.5% Sn, and less than about 0.4% of Pb. | 2014-05-15 |
20140131862 | SEMICONDUCTOR DEVICE HAVING CONDUCTIVE PADS AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a plurality of conductive pads formed in consecutive conductive layers, and a bump structure. The plurality of conductive pads is aligned and arranged one above another over the substrate. The plurality of conductive pads comprises a first conductive pad and a second conductive pad. The first conductive pad is above the second conductive pad. A redistribution layer extends the second conductive pad. The first conductive pad is not extended by a redistribution layer. The bump structure is formed directly on the first conductive pad and electrically coupled to the plurality of conductive pads. | 2014-05-15 |
20140131863 | Semiconductor Device with Copper-Tin Compound on Copper Connector - An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector. | 2014-05-15 |
20140131864 | Connector Design for Packaging Integrated Circuits - A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar. | 2014-05-15 |
20140131865 | Structure and Method for Bump to Landing Trace Ratio - The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure and coupled to the interconnect structure, wherein the landing metal trace includes a first width T defined in a first direction; and a metal bump post formed on and aligned with the landing metal trace, wherein the metal bump post includes a second width U defined in the first direction, and the second width U is greater than the first width T. | 2014-05-15 |
20140131866 | TRACE ROUTING WITHIN A SEMICONDUCTOR PACKAGE SUBSTRATE - A semiconductor device includes a substrate configured with a plurality of conductive traces. The traces are configured to electrically couple to an integrated circuit (IC) die and at least one of the plurality of conductive traces includes first electrically conductive portions in a first electrically conductive layer of the substrate, second electrically conductive portions in a second electrically conductive layer of the substrate, and first electrically conductive connections between the first electrically conductive portions and the second electrically conductive portions. The first and second electrically conductive portions and the first electrically conductive connections form a continuous path along at least a portion of the at least one of the conductive traces. Time delay of conducting a signal along the at least one of the conductive traces is within a specified amount of time of time delay of conducting a signal along another one of the plurality of conductive traces. | 2014-05-15 |
20140131867 | SYSTEM AND METHOD FOR DESIGNING SEMICONDUCTOR PACKAGE USING COMPUTING SYSTEM, APPARATUS FOR FABRICATING SEMICONDUCTOR PACKAGE INCLUDING THE SYSTEM, AND SEMICONDUCTOR PACKAGE DESIGNED BY THE METHOD - A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts in which the first and second chips are stacked, on the package substrate; a modeling module configured to model operating parameters for the first and second chips and the package substrate in response to the virtual layouts; and a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters. | 2014-05-15 |
20140131868 | Systems and Methods for Producing Low Work Function Electrodes - According to an exemplary embodiment of the invention, systems and methods are provided for producing low work function electrodes. According to an exemplary embodiment, a method is provided for reducing a work function of an electrode. The method includes applying, to at least a portion of the electrode, a solution comprising a Lewis basic oligomer or polymer; and based at least in part on applying the solution, forming an ultra-thin layer on a surface of the electrode, wherein the ultra-thin layer reduces the work function associated with the electrode by greater than 0.5 eV. According to another exemplary embodiment of the invention, a device is provided. The device includes a semiconductor; at least one electrode disposed adjacent to the semiconductor and configured to transport electrons in or out of the semiconductor. | 2014-05-15 |
20140131869 | Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask - A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow. | 2014-05-15 |
20140131870 | Multi-chip package and manufacturing method - Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern. | 2014-05-15 |
20140131871 | INTERCONNECTION STRUCTURE AND FABRICATION THEREOF - A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad. | 2014-05-15 |
20140131872 | COPPER ETCHING INTEGRATION SCHEME - The present disclosure is directed to a method of manufacturing an interconnect structure in which a sacrificial layer is formed over a semiconductor substrate followed by etching of the sacrificial layer to form a first feature. The metal layer is patterned and etched to form a second feature, followed by deposition of a low-k dielectric material. The method allows for formation of an interconnect structure without encountering the various problems presented by porous low-k dielectric damage. | 2014-05-15 |
20140131873 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an insulation film formed above a semiconductor substrate, a conductor containing Cu formed in the insulation film, and a layer film formed between the insulation film and the conductor and formed of a first metal film containing Ti and a second metal film different from the first metal film, a layer containing Ti and Si is formed on the surface of the conductor. | 2014-05-15 |
20140131874 | SEMICONDUCTOR APPARATUS, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS - A semiconductor apparatus, electronic device, and method of manufacturing the semiconductor apparatus are disclosed. In one example, the semiconductor apparatus comprises a first semiconductor part that includes a first wiring, and a second semiconductor part that is adhered to the first semiconductor part and which includes a second wiring electrically connected to the first wiring. A metallic oxide is formed in at least one of the first wiring and the second wiring. | 2014-05-15 |
20140131875 | Z-CONNECTION USING ELECTROLESS PLATING - In one embodiment, an assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor. | 2014-05-15 |
20140131876 | METHOD FOR DICING A SEMICONDUCTOR WAFER HAVING THROUGH SILICON VIAS AND RESULTANT STRUCTURES - The present invention provides a semiconductor device, a semiconductor package and a semiconductor process. The semiconductor process includes the following steps: (a) providing a semiconductor wafer having a first surface, a second surface and a passivation layer; (b) applying a first laser on the passivation layer to remove a part of the passivation layer and expose a part of the semiconductor wafer; (c) applying a second laser, wherein the second laser passes through the exposed semiconductor wafer and focuses at an interior of the semiconductor wafer; and (d) applying a lateral force to the semiconductor wafer. Whereby, the cutting quality is ensured. | 2014-05-15 |
20140131877 | STRESS RELIEF STRUCTURES IN PACKAGE ASSEMBLIES - A semiconductor package structure, comprises a substrate, a die region having one or more dies disposed on the substrate, and at least one stress relief structure disposed at one or more corners of the substrate, the at least one stress relief structure being adjacent to at least one die of the one or more dies. | 2014-05-15 |
20140131878 | SEMICONDUCTOR DEVICES WITH ENHANCED ELECTROMIGRATION PERFORMANCE - Semiconductor devices with enhanced electromigration performance and methods of manufacture are disclosed. The method includes forming at least one metal line in electrical contact with a device. The method further includes forming at least one staple structure in electrical contact with the at least one metal line. The at least one staple structure is formed such that electrical current passing through the at least one metal line also passes through the at least staple structure to reduce electromigration issues. | 2014-05-15 |
20140131879 | DESIGN METHOD OF WIRING LAYOUT, SEMICONDUCTOR DEVICE, PROGRAM FOR SUPPORTING DESIGN OF WIRING LAYOUT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion. | 2014-05-15 |
20140131880 | METHODS FOR FABRICATION OF AN AIR GAP-CONTAINING INTERCONNECT STRUCTURE - Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures. | 2014-05-15 |
20140131881 | INTEGRATED CIRCUITS AND METHODS OF FORMING INTEGRATED CIRCUITS WITH INTERLAYER DIELECTRIC PROTECTION - Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess. | 2014-05-15 |
20140131882 | THROUGH-SILICON VIA STRUCTURE WITH PATTERNED SURFACE, PATTERNED SIDEWALL AND LOCAL ISOLATION - This invention discloses a through-silicon via (TSV) structure for providing an electrical path between a first-side surface and a second-side surface of a silicon chip, and a method for fabricating the structure. In one embodiment, the TSV structure comprises a via penetrated through the chip from the first-side surface to the second-side surface, providing a first end on the first-side surface and a second end on the second-side surface. A local isolation layer is deposited on the via's sidewall and on a portion of the first-side surface surrounding the first end. The TSV structure further comprises a plurality of substantially closely-packed microstructures arranged to form a substantially non-random pattern and fabricated on at least the portion of the first-side surface covered by the local isolation layer for promoting adhesion of the local isolation layer to the chip. A majority of the microstructures has a depth of at least 1 μm. | 2014-05-15 |
20140131883 | SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR FABRICATING PROCESS FOR THE SAME - A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer. | 2014-05-15 |
20140131884 | Through-Substrate via Formation with Improved Topography Control - A device include a substrate and an interconnect structure over the substrate. The interconnect structure comprising an inter-layer dielectric (ILD) and a first inter-metal dielectric (IMD) formed over the ILD. A through-substrate via (TSV) is formed at the IMD extending a first depth through the interconnect structure into the substrate. A metallic pad is formed at the IMD adjoining the TSV and extending a second depth into the interconnect structure, wherein the second depth is less than the first depth. Connections to the TSV are made through the metallic pad. | 2014-05-15 |
20140131885 | HARD MACRO HAVING BLOCKAGE SITES, INTEGRATED CIRCUIT INCLUDING SAME AND METHOD OF ROUTING THROUGH A HARD MACRO - A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro. | 2014-05-15 |
20140131886 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device and a method of manufacturing the same. A carrier is removed after a first semiconductor die and a second semiconductor die are stacked on each other, and then a first encapsulant is formed, so that the carrier may be easily removed when compared to approaches in which a carrier is removed from a wafer having a thin thickness. | 2014-05-15 |
20140131887 | PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A package structure including: a first semiconductor device including a first semiconductor substrate and a first electronic device, the first semiconductor device having a first side and a second side, wherein at least part of the first electronic device being adjacent to the first side, and the first semiconductor device has a via-hole formed through the first semiconductor device, wherein the via-hole has a first opening adjacent to the first side; an interconnection structure disposed in the first semiconductor device, wherein the interconnection structure includes: a via structure disposed in the via-hole without exceeding the first opening; a first pad disposed on the first side of the first semiconductor device and covering the via-hole; and a second semiconductor device vertically integrated with the first semiconductor device. | 2014-05-15 |
20140131888 | Method for producing an electrical feedthrough in a substrate, and substrate having an electrical feedthrough - A method for producing an electrical feedthrough in a substrate having an electrical feedthrough, including: forming an etch stop layer on the front side of the substrate; forming a mask on the back side of the substrate; forming an annular trench in the substrate, which trench extends from the back to the front side, by an etching process that stops at the etch stop layer, using the mask, the trench surrounding a substrate punch; depositing a metal layer over the back side of the substrate using the mask, the metal layer penetrating into the annular trench and being deposited on the substrate punch; forming a metal silicide layer on the substrate punch by at least partially converting the metal layer into the metal silicide layer on the substrate punch; selectively removing a remainder of the metal layer; and closing off the annular trench at the back side of the substrate. | 2014-05-15 |
20140131889 | FLEXIBLE PRINTED CIRCUIT BOARD FOR PACKAGING SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A flexible circuit board, a semiconductor package, and methods of forming the same are provided. The flexible circuit board includes: a base film; an input line pattern, an output line pattern, and a dummy pattern on a first surface of the base film; and a ground pattern on a second surface of the base film and electrically connected with the dummy pattern. | 2014-05-15 |
20140131890 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS - A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode. | 2014-05-15 |
20140131891 | SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME - A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes. | 2014-05-15 |
20140131892 | CHIP ASSEMBLY HAVING VIA INTERCONNECTS JOINED BY PLATING - An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element. | 2014-05-15 |
20140131893 | METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY - Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer. | 2014-05-15 |
20140131894 | POP Structures with Air Gaps and Methods for Forming the Same - A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die. | 2014-05-15 |
20140131895 | MEMORY MODULE AND MEMORY SYSTEM - A memory module is provided which includes a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board, the first semiconductor packages and the second semiconductor packages having semiconductor dies that form ranks. A number of the ranks formed by the first semiconductor packages being different from a number of the ranks formed by the second semiconductor packages. Semiconductor packages forming a same one of the ranks receive a chip selection signal in common and semiconductor packages forming other ranks receive a different chip selection signal. | 2014-05-15 |
20140131896 | Exposing Connectors in Packages Through Selective Treatment - A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed. | 2014-05-15 |
20140131897 | Warpage Control for Flexible Substrates - A flexible substrate may be provided having a first side and a second side. A device may be electrically coupled to the first side of the flexible substrate through one or more electrical connections. A warpage control device may be attached to the second side flexible substrate. The warpage control device may include an adhesive layer and a rigid layer. The warpage control device may be formed in an area of the second side of the flexible substrate that may be opposite the one or more electrical connections on the first side of the flexible substrate. | 2014-05-15 |
20140131898 | SEMICONDUCTOR PACKAGING CONTAINING SINTERING DIE-ATTACH MATERIAL - Sintering die-attach materials provide a lead-free solution for semiconductor packages with superior electrical, thermal and mechanical performance to prior art alternatives. Wafer-applied sintering materials form a metallurgical bond to both semiconductor die and adherends as well as throughout the die-attach joint and do not remelt at the original process temperature. Application to either one or both sides of the wafer, as well as paste a film application are disclosed. | 2014-05-15 |
20140131899 | PACKAGE FOR AN INTEGRATED CIRCUIT - The invention refers to method for packaging an integrated circuit (IC) comprising steps of:
| 2014-05-15 |
20140131900 | MICROELECTRONIC ASSEMBLY WITH THERMALLY AND ELECTRICALLY CONDUCTIVE UNDERFILL - A microelectronic assembly may include a microelectronic element having a surface and a plurality of contacts at the surface; a first element consisting essentially of at least one of semiconductor or dielectric material, the first element having a surface facing the surface of the microelectronic element and a plurality of first element contacts at the surface of the first element; electrically conductive masses each joining a contact of the plurality of contacts of the microelectronic element with a respective first element contact of the plurality of first element contacts; a thermally and electrically conductive material layer between the surface of the microelectronic element and the surface of the first element and adjacent conductive masses of the conductive masses; and an electrically insulating coating electrically insulating the conductive masses and the surfaces of the microelectronic element and the first element from the thermally and electrically conductive material layer | 2014-05-15 |
20140131901 | MISTING FAN - A misting fan includes a body, a nebulizing member, a directing member and a fan member. The body has a motor, a sink and a plurality of channels defined thereon. The channels communicate with the sink. The nebulizing member is assembled on the body, corresponds to one side of the motor, and communicates with the channels. The fan member is assembled to the motor and is defined between the nebulizing member and the motor. The directing member is assembled on the body and is defined between the fan member and the nebulizing member. Under this arrangement, when a volume of water is delivered from the sink to the nebulizing member via the channels so as to eject mists, the gas flows are delivered to each directing portion to forwardly spread the mists outside. | 2014-05-15 |
20140131902 | GAS SEPARATION APPARATUS AND PACKING - Provided is a gas separation apparatus advantageous in suppression of increase in pressure loss and achievement of reduced size and weight, thereby reducing costs. The gas separation apparatus causes an absorbent to flow down along the surface of a packing arranged in a treatment chamber, and supplies to the treatment chamber a gas to be treated which contains a target gas component, and then causes the gas to be treated and the absorbent flowing down along the surface of the packing to come into gas-liquid contact. Thus the target gas component contained in the gas to be treated is absorbed into the absorbent and separated or recovered from the gas to be treated. The packing has at least one packing unit configured by a plurality of expanded metal plates standing vertically and being aligned. | 2014-05-15 |
20140131903 | CONDENSING DEHUMIDIFIER - According to the present invention, a condensing dehumidifier comprises: a main body having a space for receiving an object to be dried, and an inlet and an outlet formed at the top and bottom, respectively, of the receiving space; a drying unit for supplying heated air through the main body inlet to the receiving space; a condensing unit for cooling and condensing the heated air discharged through the main body outlet and separating the air into condensed water and dry air; a first pipe connecting the main body outlet and the condensing unit to each other, and transferring the heated air discharged through the main body outlet to the condensing unit; a second pipe connecting the condensing unit and the drying unit to each other, and transferring the dry air separated by the condensing unit to the drying unit; and an intermediate pipe one end of which is branched from the first pipe, and the other end of which is connected to the second pipe, wherein a portion of the heated air discharged through the main body outlet passes through the intermediate pipe past the drying unit and is supplied to the receiving space. | 2014-05-15 |
20140131904 | HUMIFIER AND LAYERED HEATING ELEMENT - A heating apparatus includes a heating element ( | 2014-05-15 |
20140131905 | PROCESS FOR MANUFACTURING AN INTRAOCULAR LENS - Intraocular implants and methods of making intraocular implants are provided. The intraocular implant can include a mask adapted to increase depth of focus. The method of making the intraocular implant can include suspending the mask along an optical axis of the intraocular implant using a centration tool. | 2014-05-15 |
20140131906 | METHOD FOR THE DENSIFICATION AND SPHEROIDIZATION OF SOLID AND SOLUTION PRECURSOR DROPLETS OF MATERIALS USING MICROWAVE GENERATED PLASMA PROCESSING - A method for processing feed material to produce dense and spheroidal products is described. The feed material is comprised of powder particles from the spray-drying technique or solution precursor droplets from ceramic or metallic materials. The feed material is processed using plasma generated from a microwave. The microwave plasma torch employed is capable of generating laminar flow during processing which allows for the production of spheroidal particles with a homogenous materials distribution. This results in products having improved thermal properties, improved corrosion and wear resistance and a higher tolerance to interface stresses. | 2014-05-15 |
20140131907 | COLLECTOR DEVICE, NON-WOVEN FABRIC MANUFACTURING APPARATUS, AND NON-WOVEN FABRIC MANUFACTURING METHOD - A collector device of a non-woven fabric manufacturing apparatus electrostatically attracts and stacks fibers charged at a first electrical polarity on a front surface of a base sheet. The collector device comprises an electrode disposed to face a back surface of the base sheet at a distance, the electrode is supplied with a voltage having a second electrical polarity opposite to the first electrical polarity or grounded, and a plurality of charge holding members positioned between the base sheet and the electrode. The charge holding members serially come in contact with and get away from the back surface of the base sheet at random. | 2014-05-15 |
20140131908 | THREE-DIMENSIONAL FABRICATING MATERIAL SYSTEMS FOR PRODUCING DENTAL PRODUCTS - This invention relates to printable polymerizable material systems for making dental products such as artificial teeth, dentures, splints, veneers, inlays, onlays, copings, frame patterns, crowns and bridges and the like. A DLP or stereolithography printer is used to cure polymerizable material in a layer-by-layer manner to build-up the object. The resulting three-dimensional object has good dimensional stability. | 2014-05-15 |
20140131909 | BIOLOGIC ARTIFICIAL BONE - A biologic artificial bone includes an artificial fiber material formed from a synthetic polymer with mechanical properties similar to type I collagen. A biocompatible liquid substance is impregnated in the fiber material that hardens and stiffens the fiber material. A bone substitute is impregnated in the hardened and stiffened fiber material forming an artificial bone composite. Vascular channels are formed in the artificial bone composite to facilitate in-growth of vessels and bone forming cells. The construction and methods achieve an artificial composite structure that is similar to natural bone with comparable properties. | 2014-05-15 |
20140131910 | THERMALLY HARDENABLE PREPARATIONS - The subject matter of the present application is thermally-expandable preparations, containing (a) at least one peroxide-crosslinkable polymer, (b) at least one low-molecular, multifunctional acrylate, (c) at least one peroxide and (d) at least two different chemical propellants, the mass ratio of the at least one peroxide to the at least one low-molecular, multifunctional acrylate being at least 1:3. | 2014-05-15 |
20140131911 | Cartridge Reactor for Production of Materials via the Chemical Vapor Deposition Process - The present invention overcomes the limitations of Siemens reactors by providing for the deposition reaction to occur inside of a sealed crucible rather than inside of the overall cavity of a water-cooled reactor. The crucible itself is positioned inside of a cartridge reactor, which can have heat shields between crucible and the reactor walls to significantly reduce radiant energy losses. Additionally, the ratio of deposition surface area to cavity volume in the crucible is much higher than that in the ratio of rod deposition surface area to overall cavity volume in Siemens reactors, which results in a much higher contact percentage of gas molecules with the deposition surfaces. This in turn results in a much higher actual conversion ratio of material in the gas to material on the deposition surfaces. | 2014-05-15 |
20140131912 | SUPPRESSION OF DEWETTING OF POLYMER FILMS VIA INEXPENSIVE SOFT LITHOGRAPY - A method for producing a patterned polymer film on a substrate includes the steps of coating a substrate with a polymer film; placing a patterned mask onto the surface of the polymer film, the patterned mask having at least one pattern section of dimensions less than the capillary wavelength of the polymer film; annealing the polymer film by either solvent annealing or temperature-based annealing, which involves raising the temperature of the polymer film above its glass transition temperature, the step of annealing causing the polymer film to conform to the dimensions of the at least one pattern section of dimensions less than the capillary wavelength of the polymer film, thereby forming a patterned polymer film; and removing the patterned mask from the patterned polymer film. | 2014-05-15 |
20140131913 | AQUEOUS BINDERS FOR GRANULAR AND/OR FIBROUS SUBSTRATES - Binder for granular and/or fibrous substrates. | 2014-05-15 |
20140131914 | DEVICE AND METHOD FOR PRODUCING FIBER PREFORMS - A device for producing fiber preforms including a plurality of unwind stations, a plurality of grippers and at least one first molding tool. Further, a method includes the successive steps of tensioning threads or rovings for a first layer with grippers, draping the first layer over a first molding tool, severing of the threads or rovings of the first layer, tensioning threads or rovings for a second layer with grippers, draping an additional layer over the first forming tool, and severing the threads or rovings of the second layer. | 2014-05-15 |
20140131915 | Methods and Materials for Fabricating Laminate Nanomolds and Nanoparticles Therefrom - A laminate nanomold includes a layer of perfluoropolyether defining a cavity that has a predetermined shape and a support layer coupled with the layer of perfluoropolyether. The laminate can also include a tie-layer coupling the layer of perfluoropolyether with the support layer. The tie-layer can also include a photocurable component and a thermal curable component. The cavity can have a broadest dimension of less than 500 nanometers. | 2014-05-15 |
20140131916 | THERMO-RHEOLOGICAL FLUID VALVE FOR RESIN INFUSION - A resin flow-controlling apparatus for infusing composite reinforcement material with resin. The resin flow-controlling apparatus may have at least one viscosity valve to speed, slow, allow, or deny resin flow through the viscosity valve to the composite reinforcement material depending on the temperature of the viscosity valve. The viscosity valve may fluidly couple a resin reservoir with an enclosed chamber in which the composite reinforcement material resides. The viscosity valve may be thermally coupled with heating and/or cooling elements selectively variable between at least two different temperatures to affect viscosity of the resin and control resin flow from the resin reservoir into the composite reinforcement material. A vacuum port at an opposite end of the composite reinforcement material from the viscosity valve may fluidly couple with the enclosed chamber and a vacuum source may pull atmosphere and/or resin from the enclosed chamber and/or the resin reservoir. | 2014-05-15 |
20140131917 | METHOD AND APPARATUS FOR PRODUCING AN AIRCRAFT STRUCTURAL COMPONENT - A method for producing an aircraft structural component includes the steps of introducing a plurality of semi-finished product layers for producing a component from a fibre-reinforced, thermoplastic plastic material into a compression mould, applying pressure to the stacked semi-finished product layers, the stacked semi-finished product layers being fixed, before pressure is applied, at particular points in their position in the compression mould and/or relative to one another in such a way that, while pressure is being applied to the semi-finished product layers stacked in the compression mould, a sliding movement of the semi-finished product layers relative to one another and/or relative to the compression mould, preventing wrinkling in the semi-finished product layers, takes place, and removing the aircraft structural component from the compression mould. | 2014-05-15 |
20140131918 | METHOD FOR FASTENING AN ACCESSORY IN A PLASTIC FUEL TANK - Method for stake-fastening an accessory ( | 2014-05-15 |
20140131919 | METHOD FOR MANUFACTURING LAMINATED IRON CORE - A method for manufacturing a laminated iron core is provided. A laminated iron core body including a permanent magnet inserted into a magnet-insert hole is arranged between a molding die and a holding die. A cull plate is arranged between the molding die and the laminated iron core body. The cull plate has a groove shaped runner directed toward the magnet-insert hole from a resin reservoir and provided with a gate hole communicating with the magnet-insert hole, and a through hole which vertically passes through the cull plate is formed in the runner of the cull plate at a different position from a position of the gate hole. After the magnet-insert hole is filled with the mold resin a resin residue remaining in the cull plate is pushed off and removed from the gate hole and the through hole. | 2014-05-15 |
20140131920 | TEMPERATURE CONTROL APPARATUS FOR PREFORM, TEMPERATURE CONTROL METHOD FOR PREFORM, RESIN CONTAINER AND METHOD FOR PRODUCING RESIN CONTAINER - The outer circumferential surface of a bottom | 2014-05-15 |
20140131921 | PROCESS FOR SELECTIVE LASER MELTING AND SYSTEM FOR CARRYING OUT SAID PROCESS - A component is manufactured by selective laser melting by a laser having an intensity profile set largely constant by a diffractive optical element, so that the treatment surface which has occurred as a result of this profile is melted uniformly on the surface of the component. Thermal load peaks, such as occur due to an intensity maximum of an unshaped laser, can therefore be advantageously avoided. Moreover, the treatment surface may, for example, have a square shape, so that, in the case of rectangular components, it becomes simpler to produce the corners of the cross section to be manufactured. Overall, as a result, components having improved surface quality can be produced. The system is equipped with suitable optics for generating the intensity profile described. | 2014-05-15 |
20140131922 | METHOD AND DEVICE FOR MACHINING A WORKPIECE, MORE PARTICULARLY FOR PRODUCING CUTTING TOOLS - A method for machining a workpiece by means of a laser beam, in which material of the workpiece is removed layer-by-layer according to predetermined definitions to produce a workpiece by traversing the exposed workpiece surface in lengths across the entire surface with a laser beam in order to vaporize and/or combust workpiece material. In a first material removal phase, the laser beam is guided relative to the workpiece over the workpiece surface by adjustable mirrors inside the laser tool, more particularly without mechanical control axes being moved to adjust the relative position between the laser tool and the workpiece. In a second material removal phase, the laser beam is guided relative to the workpiece over the workpiece surface by means of one or more control axes of the machine, the focal length being variably adjustable by means of a variable optical unit. | 2014-05-15 |
20140131923 | METHOD AND APPARATUS FOR USE IN MANUFACTURING A FILTER ELEMENT - A method of manufacturing a porous fluid treatment element, e.g. a filter element, includes forming a layered structure having at least two layers and subjecting the layered structure to at least a heat treatment. The step of forming a layered structure includes forming a first layer including particulate matter including at least a binder and applying a second layer including particulate matter including at least a binder directly onto the first layer on a first side thereof. The step of forming a layered structure further includes applying at least one of radiation and heat to at least the first side of the first layer prior to applying the second layer. | 2014-05-15 |
20140131924 | METHODS OF FORMING A POLYMERIC COMPONENT - A method of forming a plurality of polymeric components comprises the steps of: providing an array of preforms ( | 2014-05-15 |
20140131925 | ORTHOPEDIC COMPONENT OF LOW STIFFNESS - An orthopedic component having multiple layers that are selected to provide an overall modulus that is substantially lower than the modulus of known orthopedic components to more closely approximate the modulus of the bone into which the orthopedic component is implanted. In one exemplary embodiment, the orthopedic component is an acetabular shell. For example, the acetabular shell may include an outer layer configured for securement to the natural acetabulum of a patient and an inner layer configured to receive an acetabular liner. The head of a femoral prosthesis articulates against the acetabular liner to replicate the function of a natural hip joint. Alternatively, the inner layer of the acetabular shell may act as an integral acetabular liner against which the head of the femoral prosthesis articulates. | 2014-05-15 |