18th week of 2009 patent applcation highlights part 16 |
Patent application number | Title | Published |
20090108375 | SEMICONDUCTOR DEVICE - The present invention proposes a dummy metal fill structure which makes it possible to reduce variations in transistor characteristics as much as possible even if mask misalignment occurs, as well as to ensure the intended planarizing effect of the metal CMP process. The dummy metal fill formed above the gate electrode extends in the gate length direction with both ends thereof protruding from a region corresponding to the gate electrode. Even if a mask for forming a wiring layer is misaligned and the position of the dummy metal fill is misaligned from an intended position, the shape of the dummy metal fill within a region of the gate electrode is kept symmetric with respect to the center of the gate electrode. | 2009-04-30 |
20090108376 | SEMICONDUCTOR DEVICE HAVING MOS TRANSISTORS WHICH ARE SERIALLY CONNECTED VIA CONTACTS AND CONDUCTION LAYER - A semiconductor device includes a plurality of signal lines which are arranged at a predetermined pitch; first and second MOS transistors which are connected to the signal lines, and also serially connected to each other; and a connection device which functions as a connection node between the serially-connected first and second MOS transistors, and connects a source area of one of the first and second MOS transistors to a drain area of the other of the first and second MOS transistors via contact holes, which are formed through an insulating layer, and a conduction layer connected to the contact holes. | 2009-04-30 |
20090108377 | Method for fabricating gate dielectrics of metal-oxide-semiconductor transistors using rapid thermal processing - In a method for fabricating gate dielectrics of metal-oxide-semiconductor transistors, rapid thermal processing (RTP) of a gate dielectric material is performed at a temperature from 1000-1200° C. in a low-concentration oxidizing gas. The method regrows an oxide layer having a thickness of more than 0.05 nm between the gate dielectric layer and the channel region that reduces gate leakage current by 2-5 orders of magnitude and improves hot-electron reliability due to phonon-energy-coupling enhancement (PECE) effect. | 2009-04-30 |
20090108378 | STRUCTURE AND METHOD FOR FABRICATING SELF-ALIGNED METAL CONTACTS - A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer. The stressed layer is self-aligned to the gate conductor. The inventive structure also has a reduced external parasitic S/D resistance as a result of having a metallic contact located atop source/drain regions that include a surface region comprised of a metal semiconductor alloy. The metallic contact is self-aligned to the gate conductor. | 2009-04-30 |
20090108379 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer. | 2009-04-30 |
20090108380 | FET-BASED GAS SENSOR SYSTEM - A sensor system for detection of gas with a modified ion selection FET. The FET may have a gate of low conductivity material for detection of a species in a fluid. A component such as a capacitor may be connected to an electrode of the FET, such as a source, in conjunction with the FET to reduce noise of the detection signal of the species. One or more current sources may provide a current through the FET, and through a resistor to provide a constant source-to-drain voltage. The system may have a bulk voltage selection of either that of a voltage approximately equal to the FET source voltage or greater than the FET source voltage. Also, a guard ring may be implemented in the FET for preventing leakage currents relative to the source or drain. | 2009-04-30 |
20090108381 | Low temperature bi-CMOS compatible process for MEMS RF resonators and filters - A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material. The method of removal of the sacrificial material is by an oxygen plasma or an anneal in an oxygen containing ambient. A method of vacuum encapsulation of the MEMS resonator or filter is provided through means of a cavity containing the MEMS device, filled with additional sacrificial material, and sealed. Access vias are created through the membrane sealing the cavity; the sacrificial material is removed as stated previously, and the vias are re-sealed in a vacuum coating process. | 2009-04-30 |
20090108382 | TRANSDUCER FOR USE IN HARSH ENVIRONMENTS - A pressure sensor for use in a harsh environment including a substrate and a sensor die directly coupled to the substrate by a bond frame positioned between the substrate and the sensor die. The sensor die includes a generally flexible diaphragm configured to flex when exposed to a sufficient differential pressure thereacross. The sensor further includes a piezoelectric or piezoresistive sensing element at least partially located on the diaphragm such that the sensing element provides an electrical signal upon flexure of the diaphragm. The sensor also includes an connecting component electrically coupled to the sensing element at a connection location that is fluidly isolated from the diaphragm by the bond frame. The bond frame is made of materials and the connecting component is electrically coupled to the sensing element by the same materials of the bond frame. | 2009-04-30 |
20090108383 | High performance MTJ element for conventional MRAM and for STT-RAM and a method for making the same - A STT-RAM MTJ that minimizes spin-transfer magnetization switching current (Jc) is disclosed. The MTJ has a MgO tunnel barrier layer formed with a natural oxidation process to achieve a low RA (10 ohm-um | 2009-04-30 |
20090108384 | Optoelectronic Device with Germanium Photodetector - An optoelectronic device comprises a photodetector feature, an interfacial layer disposed above at least a portion of the photodetector feature, and a vertical contact disposed on at least a portion of the interfacial layer. The photodetector feature comprises germanium and is operative to convert a light signal into an electrical signal. The interfacial layer comprises nickel. Finally, the vertical contact is operative to transmit the electrical signal from the photodetector feature. | 2009-04-30 |
20090108385 | METHOD AND APPARATUS FOR IMPROVING CROSSTALK AND SENSITIVITY IN AN IMAGER - A pixel sensor cell includes a substrate of a first conductivity type, and a photoconversion region. The photoconversion region includes a pinning layer of the first conductivity type for receiving incident light of multiple colors, and a diode implant layer of a second conductivity type, disposed below the pinning layer, for accumulating photo-generated charge. Also included is a deep well of the first conductivity type, disposed below the diode implant layer, for rejecting at least one color of the incident light. The deep well includes a doped region, vertically disposed at a predetermined depth below the diode implant layer. The diode implant layer is effective in accumulating photo-generated charge of a blue color, and the deep well is effective in rejecting photo-generated charges of green and red colors from the diode implant layer. By placing the deep well at another predetermined depth below the diode implant layer, the deep well is effective in rejecting photo-generated charge of a red color from the diode implant layer. | 2009-04-30 |
20090108386 | Image Sensor and Method for Manufacturing the Same - Provided is an image sensor and method for manufacturing the same. The image sensor includes a semiconductor substrate including a photodiode for each unit pixel, an interlayer insulating layer including metal lines on the semiconductor substrate, and an optical refractive part in a region of the interlayer insulating layer corresponding to the photodiode for focusing light on the photodiode. The optical refractive part can be formed by implanting impurities into the interlayer insulating layer. | 2009-04-30 |
20090108387 | Semiconductor Device And Method For Strain Controlled Optical Absorption - A semiconductor device which has controlled optical absorption includes a substrate, and a semiconductor layer supported by the substrate. The semiconductor has variable optical absorption at a predetermined optical frequency in relationship to a bandgap of the semiconductor layer. Also included is a strain application structure coupled to the semiconductor layer to create a strain in the semiconductor layer to change the semiconductor bandgap. | 2009-04-30 |
20090108388 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a semiconductor substrate including a light receiving element, a silicon oxide film formed on the semiconductor substrate, a plurality of wiring interlayer films formed on the silicon oxide film, and each including a wiring layer formed as the result of the fact that copper is buried, and a silicon nitride film formed on the wiring interlayer film of the uppermost layer wherein Si—H concentration is smaller than N—H concentration. | 2009-04-30 |
20090108389 | IMAGING DEVICE COMPRISING SHIELDING UNIT WHICH SHIELDS LIGHT INCIDENT FROM IMAGING AREA TO OPTICAL BLACK AREA AND METHOD OF MANUFACTURING THE SAME - An imaging device according to an example of the invention comprises a first photoelectric conversion unit which is formed at an imaging area of a substrate, a second photoelectric conversion unit for black reference observation which is formed at an optical black area between the imaging area of the substrate and a peripheral circuit area where a peripheral circuit is formed, an insulating film which is formed on the imaging area and the optical black area of the substrate, and a shielding unit which is formed by connecting a contact and a interconnect in an accumulating direction of the insulating film from the substrate surface to the insulating film surface. | 2009-04-30 |
20090108390 | Image Sensor and Method for Manufacturing Thereof - An image sensor may include a semiconductor substrate including a device isolating film and a light receiving device; an insulating film on the semiconductor substrate; a barrier; a metal wire layer on the insulating film; a trench between adjacent metal wires having a protective film pattern on sidewalls thereof; and a photosensitive material in the trench. A method for manufacturing an image sensor may comprise forming an insulating film on a semiconductor substrate, the semiconductor substrate having a device isolating film, a barrier and a light receiving device; forming a metal wire layer on the insulating film; forming a trench between adjacent metal wires; forming a protective film pattern on sidewall surfaces of the trench; forming a photosensitive material over the metal wire layer and in the trench; and planarizing the semiconductor substrate to remove portions of the photosensitive material over the metal wire layer. | 2009-04-30 |
20090108391 | SOLID-STATE IMAGING DEVICE AND METHOD FOR FABRICATING THE SAME - A solid-state imaging device comprises an imaging region, a peripheral circuit region formed in an outer peripheral portion of the imaging region, a first conductivity type semiconductor substrate having the imaging region and the peripheral circuit region on a main surface thereof, a second conductivity type first semiconductor layer formed in the semiconductor substrate, a first conductivity type second semiconductor layer formed in first semiconductor layer, a through electrode formed in a through hole penetrating through the semiconductor substrate in a thickness direction of the semiconductor substrate, and a pad portion formed on the semiconductor substrate and connected to the through electrode. The through hole penetrates through a first conductivity type region of the semiconductor substrate. | 2009-04-30 |
20090108392 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a semiconductor device includes a plurality of rectilinear structures, wherein the plurality of rectilinear structures comprise silicon dioxide and extend from a surface of a semiconductor material to a distance of at least about three microns or greater below the surface of the semiconductor material and wherein a first rectilinear structure of the plurality of rectilinear structures is perpendicular to, or substantially perpendicular to, a second rectilinear structure of the plurality of rectilinear structures. Other embodiments are described and claimed. | 2009-04-30 |
20090108393 | Semiconductor Device With a Plurality of Ground Planes - A multi-chip module (MCM) with a plurality of ground planes/layers is provided. Each integrated circuit (IC) chip of the MCM has its own ground plane on a substrate in the MCM. This MCM structure may facilitate separate testing of each IC chip without affecting other chips and without being affected by other chips. This MCM structure also may facilitate testing of interconnects/connections between two or more chips. | 2009-04-30 |
20090108394 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device comprises forming a deposition structure including a first substrate, an insulating layer and a second substrate of a SOI substrate; etching the second substrate located in a boundary of cell and core regions and a peripheral region to form a line-type trench; filling an isolating film in the trench; removing the second substrate and the insulating layer of the peripheral region; performing a selective epitaxial growth (SEG) process using the first substrate exposed in the peripheral region to form an epitaxial layer; and performing a chemical mechanical polishing (CMP) process on the epitaxial layer. As a result, the method has a floating body effect to shorten a developing period and improve a process yield. | 2009-04-30 |
20090108395 | SEMICONDUCTOR DEVICE HAVING INCREASED ACTIVE REGION WIDTH AND METHOD FOR MANUFACTURING THE SAME - The disclosed semiconductor device includes a plurality of active patterns including first active patterns which protrude from a semiconductor substrate and have a first width and second active patterns which are connected to upper ends of the respective first active patterns and have a second width greater than the first width. The semiconductor device further includes isolation patterns respectively located between the active patterns to insulate the active patterns from one another. | 2009-04-30 |
20090108396 | ELECTRICAL FUSE HAVING A FULLY SILICIDED FUSELINK AND ENHANCED FLUX DIVERGENCE - A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys. | 2009-04-30 |
20090108397 | THIN FILM DEVICE WITH LAYER ISOLATION STRUCTURE - This invention provides a thin film device with layer isolation structures. Specifically, a plurality of patterned thin film device layers provide a first rail and a second rail. There is at least one overpass between the first rail and the second rail. The overpass is defined by an array of spaced holes disposed transversely through the continuous material of the first rail on either side of the overpass. The holes are in communication with isolation voids adjacent to the second rail adjacent to the overpass. | 2009-04-30 |
20090108398 | Fuse of Semiconductor Device and Method for Forming the Same - A fuse in a semiconductor device includes: first and second fuse patterns, each being in the shape of a bar, separated from each other in a blowing region; first and second contact plugs respectively coupled to the first and the second fuse patterns; and a third fuse pattern coupled to the first and the second fuse patterns through the first and the second contact plugs. | 2009-04-30 |
20090108399 | APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE INCORPORATING FUSE ELEMENTS - An apparatus and a method for manufacturing semiconductor devices is disclosed for selectively disconnecting a fuse element out of plural fuse elements formed on a semiconductor wafer substrate which is provided with the plural fuse elements and a dielectric layer having at least one opening corresponding to the location for the plural fuse elements. The method includes processing steps implemented onto the wafer substrate, such as (a) forming a layer of etching barrier resin by scanning at least one discharging nozzle for discharging the raw etching barrier resin while suitably discharging droplets of raw etching barrier resin to replenish the opening corresponding to the location of the fuse element not to be disconnected, (b) hardening the raw etching barrier resin to be a layer of etching barrier resin, and (c) the fuse element in the prescribed disconnecting area without overlying portion of the etching barrier resin layer is selectively disconnected by etching using the dielectric layer and the etching barrier resin as a mask. | 2009-04-30 |
20090108400 | ANTI-FUSE STRUCTURE INCLUDING A SENSE PAD CONTACT REGION AND METHODS FOR FABRICATION AND PROGRAMMING THEREOF - An antifuse structure includes a sense pad contact region that is separate from an anode contact region and a cathode contact region. By including the sense pad contact region that is separate from the anode contact region and the cathode contact region, a programming current flow when programming the antifuse structure may travel a different pathway than a sense current flow when sensing the antifuse structure. In particular a sense current flow may avoid a depletion region created within the cathode contact region when programming the antifuse structure. | 2009-04-30 |
20090108401 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides a semiconductor chip. The semiconductor chip includes a first electrode of a capacitor. An insulating layer is arranged on top of the first electrode. A second electrode of the capacitor is applied over the insulating layer, wherein the second electrode is made of a conductive layer arranged over the semiconductor chip. | 2009-04-30 |
20090108402 | Method for Manufacturing Capacitor of Semiconductor Device - A method for manufacturing a capacitor of a semiconductor device may include: forming an interlayer insulating film including a contact plug over a semiconductor substrate; forming a first stack film comprising a capacitor oxide film and a nitride film over the interlayer insulating film; etching the first stack film to form a first stack pattern and a contact hole that exposes the contact plug; forming a lower electrode in the contact hole; forming a capping oxide film continuously over the first stack pattern so as to form a bridge between neighboring the first stack patterns; forming an etching barrier film including cavities over the capping oxide film; performing a blanket etching process onto the etching barrier film including cavities until the capacitor oxide film is exposed to form a nitride film pattern; and removing the exposed capacitor oxide film. | 2009-04-30 |
20090108403 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a capacitor embedded in a dielectric material below the surface of a semiconductor substrate is disclosed. Other embodiments are described and claimed. | 2009-04-30 |
20090108404 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a plurality of capacitance elements. Each capacitance element has a structure obtained by holding a capacitance film made of an insulating material between first and second electrodes made of a metallic material. The first and second electrodes are so arranged as to partially overlap each other while relatively positionally deviating from each other in a direction orthogonal to the opposed direction thereof. The plurality of capacitance elements are stacked in the opposed direction. | 2009-04-30 |
20090108405 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A conductive film embedded in a predetermined region on an upper surface of an insulation film and metallic wirings embedded so as to penetrate through the conductive film and protrudes into the insulation film constitute a lower electrode of an MIM capacitor. | 2009-04-30 |
20090108406 | Semiconductor device having two bipolar transistors constituting electrostatic protective element - A semiconductor device includes a pair of transistors formed in a first conductive type semiconductor substrate. Each of the transistors contains a collector region of a second conductive type, opposite to the first conductive type, formed in the semiconductor substrate, a base region of the first conductive type formed in the collector region, and an emitter region of the second conductive type formed in the base region, the collector region of one transistor of the pair of transistors being separated from that of the other transistor. The semiconductor device further includes a first region of the first conductive type formed between the collector regions of the pair of transistors, and a buried layer of the second conductive type formed in the semiconductor substrate under the collector region of one transistor of the pair of transistors to connect the collector regions of the transistors therethrough. | 2009-04-30 |
20090108407 | Oxygen-doped n-type gallium nitride freestanding single crystal substrate - Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal. | 2009-04-30 |
20090108408 | Method for Trapping Implant Damage in a Semiconductor Substrate - A method for minimizing the effects of defects produced in a implantated area of a crystal lattice during dopant implantation in the lattice. The method begins with the step of implanting a trap layer of trap atoms, the trap atoms having a size less than that of the lattice member atoms. After implantation, the lattice is annealed for a time sufficient for interstitial defect atoms to be emitted from the defect area. In that manner, energetically stable pairs are formed between trap atoms and emitted interstitial atoms. | 2009-04-30 |
20090108409 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an element formed on a substrate, at least one insulating film formed on the substrate, and a seal ring formed in the insulating film so as to surround a region where the element is formed and to extend through the insulating film. The semiconductor device further includes a void region including a void and formed in the insulating film in a region located outside the seal ring when viewed from the element. | 2009-04-30 |
20090108410 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a diffusion layer conductive film formed on the semiconductor substrate, an interlayer insulating film layered on the semiconductor substrate, an interconnect pattern and a via pattern formed in the interlayer insulating film, a plurality of circuit regions formed in the semiconductor substrate, and a scribe region formed around the circuit regions and separating the circuit regions from each other. The diffusion layer conductive film is not formed at least in a region to which laser light is emitted in the scribe region. | 2009-04-30 |
20090108411 | SILICON SUBSTRATE FOR PACKAGE - In a silicon substrate for a package, a through electrode is provided with which a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate is filled. An end part of the through electrode in the bottom surface side of the cavity has a connection part to a wiring that forms an electric circuit including the chip of the electronic device. The silicon substrate for a package is characterized in that (1) a thin film wiring is included as the wiring and the connection part is reinforced by a conductor connected to the thin film wiring and/or (2) a wire bonding part is included as the wiring and the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity. | 2009-04-30 |
20090108412 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE - A semiconductor substrate includes: a silicon support substrate with a first crystal orientation; a silicon functional substrate which is formed on the silicon support substrate and which has a first crystalline region with a crystal orientation different from the first crystal orientation of the silicon support substrate and a second crystalline region with a crystal orientation equal to the first crystal orientation of the silicon support substrate; and a defect creation-preventing region formed at an interface between the first crystalline region and the second crystalline region of the silicon functional substrate so as to be at least elongated to a main surface of the silicon support substrate. | 2009-04-30 |
20090108413 | Interlayer Insulating Film, Interconnection Structure, and Methods of Manufacturing the Same - This invention provides an interlayer insulating film for a semiconductor device, which has low permittivity, is free from the evolution of gas such as CFx and SiF | 2009-04-30 |
20090108414 | WAFER - A wafer has a rare earth oxide layer disposed, typically sprayed, on a substrate. It is useful as a dummy wafer in a plasma etching or deposition system. | 2009-04-30 |
20090108415 | INCREASING ETCH SELECTIVITY DURING THE PATTERNING OF A CONTACT STRUCTURE OF A SEMICONDUCTOR DEVICE - By forming an intermediate etch stop material or by appropriately positioning an additional etch stop material in a spacer structure of a polysilicon line, the probability of exposing a shallow doped region of an active semiconductor region during a critical contact etch step for forming rectangular contacts may be significantly reduced. Thus, leakage current, which may conventionally be created by etching into shallow doped regions during the contact etch step, may be reduced. | 2009-04-30 |
20090108416 | DIRECT-CONNECT SIGNALING SYSTEM - A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board. | 2009-04-30 |
20090108417 | Method and System for Providing a Continuous Impedance Along a Signal Trace in an IC Package - A multi-layered integrated circuit chip package comprises a void layer that includes at least one void. The multi-layered integrated circuit chip package also includes an insulation layer that electrically insulates the void layer from a trace layer. At least one trace resides in the trace layer. The trace having a length in which a first section thereof is located an overlying relation to the at least one void, wherein the first section overlying the void has a width different from an adjacent section of the trace located on at least one opposing side of the void such that impedance mismatches and signal reflections along the trace are mitigated. | 2009-04-30 |
20090108418 | Non-leaded semiconductor package structure - A non-leaded semiconductor package structure is proposed, in which the structure of a lead frame is improved to let the lower surface of a die paddle of the lead frame be used to carry a die and the upper surface thereof be exposed out of the package structure. Moreover, a plurality of leads of the lead frame is located at the periphery of the lower surface of the die paddle. Each lead has an inner lead and an outer lead, and the outer lead is exposed out of the package structure. The package structure thus formed has a good heat-radiating effect and a reduced chance of leakage current. | 2009-04-30 |
20090108419 | LEADFRAME FOR LEADLESS PACKAGE - A leadframe for a leadless package comprises a plurality of package areas, a plurality of slots, a plurality of connection portions, a plurality of openings, and a tape (film). Each package area comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of slots are disposed around each of the package units. The plurality of connection portions connect the plurality of package areas. The plurality of openings are disposed on the plurality of connection portions, and are aligned with some of the plurality of slots. The tape (film) fixes the plurality of package areas, the plurality of connection portions, the plurality of die pads, and the plurality of leads in place. | 2009-04-30 |
20090108420 | SEMICONDUCTOR DEVICE AND ITS FABRICATION PROCESS - A technique capable of preventing whiskers which are generated in a plating film formed on the surface of each of leads of a semiconductor device is provided. Particularly, a technique capable of preventing generation of whiskers in a plating film containing tin as a primary material and not containing lead is provided. The plating film formed on the surface of the lead is formed so that a particular plane orientation among plane orientations of tin constituting the plating film is parallel to the surface of the lead. Specifically, the plating film is formed so that the (001) plane of tin is parallel to the surface of the lead. Thus, the coefficient of thermal expansion of tin constituting the plating film can be made to be lower than a coefficient of thermal expansion of the copper constituting the lead. | 2009-04-30 |
20090108421 | APPARATUS AND METHOD CONFIGURED TO LOWER THERMAL STRESSES - An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range. | 2009-04-30 |
20090108422 | SEMICONDUCTOR DEVICE - The present invention can supply power for each circuit section by separating and connecting bus-bar ( | 2009-04-30 |
20090108423 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a leadframe defining a die pad, a chip electrically coupled to the die pad, encapsulation material covering the chip and the die pad, and a plurality of lead ends exposed relative to the encapsulation material and configured for electrical communication with the chip, and a nitrogen-containing hydrocarbon coating disposed over at least the lead ends of the leadframe, where the hydrocarbon coating is free of metal particles. | 2009-04-30 |
20090108424 | LEADFRAME FOR LEADLESS PACKAGE - A leadframe for a leadless package comprises a plurality of package areas, a plurality of first slots, a plurality of first side rails, a plurality of second side rails, and tape. Each of the package areas comprises a plurality of package units, each of which comprises a die pad and a plurality of leads surrounding the die pad. The plurality of first side rails and the plurality of second side rails are connected and surround the plurality of the package areas. The tape fixes the plurality of package areas, the plurality of first side rails, the plurality of second side rails, the die pads, and the plurality of leads in place. | 2009-04-30 |
20090108425 | Stacked package and method of manufacturing the same - In one embodiment, the stacked package includes a first chip disposed over a package substrate. The first chip has at least one first chip dummy pad, and the first chip dummy pad is not electrically connected to circuits of the first chip. A first dummy bonding wire is connected to the first chip dummy pad and the package substrate. A second chip is disposed over at least a portion of the first chip, and the second chip has at least one second chip bonding pad. A first bonding wire is electrically connected to the second chip bonding pad and the first dummy bonding wire. | 2009-04-30 |
20090108426 | OPTICAL DEVICE AND METHOD OF MANUFACTURING THE SAME - An optical device includes a semiconductor substrate ( | 2009-04-30 |
20090108427 | Techniques for Modular Chip Fabrication - Techniques for modular chip fabrication are provided. In one aspect, a modular chip structure is provided. The modular chip structure comprises a substrate; a carrier platform attached to the substrate, the carrier platform comprising a plurality of conductive vias extending through the carrier platform; and a wiring layer on the carrier platform in contact with one or more of the conductive vias, wherein the wiring layer comprises one or more wiring levels and is configured to divide the carrier platform into a plurality of voltage islands; and chips, chip macros or at least one chip in combination with at least one chip macro assembled on the carrier platform. | 2009-04-30 |
20090108428 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUBSTRATE HAVING A CONDUCTOR-FREE RECESS - A mountable integrated circuit package system includes: providing a carrier; mounting a first integrated circuit device over the carrier; mounting a substrate over the first integrated circuit device with the substrate having a conductor-free recess; connecting a first electrical interconnect under the conductor-free recess electrically connecting the carrier and the first integrated circuit device; and forming a package encapsulation over the carrier, the first integrated circuit device, the first electrical interconnect, the conductor-free recess, and partially exposing the substrate. | 2009-04-30 |
20090108429 | Flip Chip Packages with Spacers Separating Heat Sinks and Substrates - A package structure includes a substrate; a die over and flip bonded on the substrate; a heat sink over the die; and one or more spacer separating the heat sink from the substrate. | 2009-04-30 |
20090108430 | STACKED SEMICONDUCTOR PACKAGE IN WHICH SEMICONDUCTOR PACKAGES ARE CONNECTED USING A CONNECTOR - A stacked semiconductor package includes a semiconductor package module in which a plurality of semiconductor packages, which include a substrate and a semiconductor chip mounted over the substrate, are stacked. The stacked semiconductor package includes connectors for electrically connecting pairs of adjacent semiconductor packages so as to provide sequentially a signal from a lower semiconductor package of the semiconductor package module toward an upper semiconductor package. The stacked semiconductor package gives the semiconductor packages in the stacked semiconductor package the ability to cooperate with one another | 2009-04-30 |
20090108431 | Inverted package-on-package (POP) assemblies and packaging methods for integrated circuits - Integrated circuit package assemblies and packaging methods are provided. An integrated circuit package assembly includes a first circuit package including a first substrate having a top surface and a bottom surface, a first circuit die containing a programmable processor mounted to and electrically connected to the bottom surface of the first substrate, a bottom connector on the bottom surface of the first substrate and top circuit connections on the top surface of the first substrate, and a second circuit package mounted on the top surface of the first substrate and electrically connected to the top circuit connections of the first circuit package. | 2009-04-30 |
20090108432 | STACK PACKAGE MADE OF CHIP SCALE PACKAGES - A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages. | 2009-04-30 |
20090108433 | MULTILAYER SEMICONDUCTOR DEVICE PACKAGE ASSEMBLY AND METHOD - Methods for assembling multilayer semiconductor device packages are disclosed. A base substrate having device mounting sites is provided. A number of semiconductor devices are connected to the device mounting sites. Upper boards are attached to the base substrate and over each of the coupled devices. The method includes steps of testing one or more of the base substrate, semiconductor device, or upper board, prior to operably connecting one to another. | 2009-04-30 |
20090108434 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, PDP DRIVER, AND PLASMA DISPLAY PANEL - In a semiconductor integrated circuit device of the present invention, temperature increase of a bonding wire can be suppressed even when conductive leads are short-circuited with each other, and reliability of the semiconductor integrated circuit device is improved. The conductive leads of a resin package for supplying a power supply section of a semiconductor integrated circuit chip with power from an external power supply are connected with bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires. Furthermore, the conductive leads connected to a GND for supplying the power supply section of the semiconductor integrated circuit chip with a grounding potential are connected with the bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires. | 2009-04-30 |
20090108435 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. | 2009-04-30 |
20090108436 | SEMICONDUCTOR PACKAGE - In a semiconductor package, a semiconductor chip is adhered with an adhesive member, with a circuit face of the semiconductor chip facing upward, onto a circuit board including a plurality of interconnections, a plurality of through holes, wire bonding pads and a solder resist for protecting the interconnections and the through holes. A plurality of electrodes of the semiconductor chip are electrically connected to the plural wire bonding pads of the circuit board through wires. A concave is formed in the solder resist of the circuit board correspondingly to every through hole of the circuit board, and concaves present in a region opposing a rim portion of the semiconductor chip and a region surrounding the semiconductor chip are buried with a resin so as to attain a flat top face. | 2009-04-30 |
20090108437 | WAFER SCALE INTEGRATED THERMAL HEAT SPREADER - Various embodiments are directed to providing an electronic device with an integrated thermal heat spreader. In one embodiment, an electronic device may comprise an integrated circuit fabricated on a substrate and a heat spreader integrated with the electronic device after fabrication of the integrated circuit. The heat spreader may comprise one or more layers of composite plating material including solid particles incorporated into a metal plating material. The composite plating material may be patterned to the substrate to define the heat spreader. Other embodiments are described and claimed. | 2009-04-30 |
20090108438 | Semiconductor device and method of manufacturing the same - Through heat discharge only by wiring connected to a conventional semiconductor chip, sufficient heat discharge performance may not be achieved in a recent semiconductor device. A semiconductor device according to an aspect of the present invention includes: a flexible substrate including a first main surface and a second main surface; a semiconductor chip; a first heat conductive layer formed on the first main surface of the flexible substrate and electrically connected to the semiconductor chip; and a second heat conductive layer formed on the second main surface of the flexible substrate and electrically insulated from the semiconductor chip. | 2009-04-30 |
20090108439 | Fluid cooled encapsulated microelectronic package - An encapsulated microelectronic package includes a fluid conducting cooling tube directly coupled to one or more semiconductor chips, with the encapsulant being molded over the semiconductor chips and portions of the cooling tube in proximity to the semiconductor chips. The encapsulant immobilizes the cooling tube with respect to the semiconductor chips, and the cooling tube and encapsulant are designed to minimize differences in their coefficients of thermal expansion relative to the semiconductor chips. | 2009-04-30 |
20090108440 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material. | 2009-04-30 |
20090108441 | SEMICONDUCTOR CLAMP SYSTEM - A system for clamping a plurality of semiconductors that includes: 1) a first endplate and a second endplate that are substantially parallel and oppose each other across a predetermine distance (the predetermined distance being fixed by one or more tension members that extend between the first endplate and the second endplate); and 2) a screw jack that includes a threaded cylinder that moves through a threaded opening in the first endplate upon being rotated such that the threaded cylinder moves toward the second endplate if rotated one direction and away from the second endplate if rotated the opposite direction. | 2009-04-30 |
20090108442 | SELF-ASSEMBLED STRESS RELIEF INTERFACE - A method of forming an interconnect assembly is provided in which contacts exposed at a face of a first element such as, for example, a microelectronic element are aligned and joined with corresponding contacts of an interconnect element confronting the face of the first element. At least one of the i) the contacts of the first element, ii) the corresponding contacts of the interconnect element, iii) a joining metal between the contacts and the corresponding contacts includes a catalyst metal. Subsequently, a material including an organic component contacting the catalyst metal reacts to form volume expansion accommodation elements in the presence of the catalyst metal, the reaction being limited by proximity with the catalyst metal, such that the interconnect assembly includes volume expansion accommodation elements adjacent to the joined contacts. | 2009-04-30 |
20090108443 | Flip-Chip Interconnect Structure - Various aspects can be implemented for providing flip-chip interconnect structures for connecting or mounting semiconductor chips to supporting substrates, such as cards, circuit boards, carriers, lead frames, and the like. In general, one aspect can be a method of providing a flip-chip interconnect structure that includes providing a semiconductor work piece that includes one or more bond pads. The method also includes depositing a first non-reflowable layer that has a first melting temperature higher than a predetermined first reflow temperature. The method further includes depositing a reflowable stress relief layer that reflows at the predetermined first reflow temperature. The method additionally includes depositing a second non-reflowable layer that has a second melting temperature higher than the predetermined first reflow temperature such that the deposited reflowable stress relief layer is between the first and the second non-reflowable layers. | 2009-04-30 |
20090108444 | CHIP PACKAGE STRUCTURE AND ITS FABRICATION METHOD - A chip package structure and its fabrication method are disclosed. Method of electrically connecting a chip with plural different metal layers is utilized to replace the conventional method of connecting identical metal layer merely. Besides, the method of a protective layer directly set on the metal layer to cover the chip and the conductive connecting structure is different from the general method of coating the solder mask on the metal layer. Moreover, a carrier utilized for support makes lighter and thinner substrate be fabricated. The fabrication method is utilized to manufacture by using the fabrication process of present package manufacturing. No additional equipments and fabrication processes are needed so that the PCB production flow may be simplified to reduce the package cost. | 2009-04-30 |
20090108445 | SUBSTRATE STRUCTURE AND SEMICONDUCTOR PACKAGE USING THE SAME - A substrate structure is provided. The substrate structure includes a substrate and a patterned wiring layer formed on the substrate. The patterned wiring layer includes a plurality of conductive traces. An isolation layer covers the patterned wiring layer and has an opening to expose a portion of at least one of the conductive traces therefrom. A plurality of conductive coatings covers the exposed portions of the conductive traces. The present invention further provides a semiconductor package with the above substrate structure. | 2009-04-30 |
20090108446 | ELECTRODE STRUCTURE FOR SEMICONDUCTOR CHIP - The bump electrode | 2009-04-30 |
20090108447 | SEMICONDUCTOR DEVICE HAVING A FINE PITCH BONDPAD - A semiconductor device is provided, including a semiconductor chip having fine pitch bond pads, dummy bond pads, and ball bonds formed on the semiconductor chip, and electrically connected to circuits of the semiconductor chip, where the width of each fine pitch bond pad is less than the diameter of each ball bond. The dummy bond pads are formed between adjacent bond pads and have a plurality of lands not connected to each other. The ball bonds may be connected to the bond pads in a zigzag configuration and are partially connected to the dummy bond pads. Accordingly, the pitch between bond pads is reduced while preventing short circuits between adjacent ball bonds. | 2009-04-30 |
20090108448 | METAL PAD OF SEMICONDUCTOR DEVICE - A metal pad of a semiconductor device that prevents cracking during a ball bonding process in a metal pad applied to a wafer level package (WLP). The metal pad includes a main metal pad formed on and/or over a semiconductor substrate and electrically connected to a contact plug, and a dummy metal pad electrically isolated from the main metal pad and formed at a peripheral portion of the main metal pad to surround the main metal pad. | 2009-04-30 |
20090108449 | Microelectronic device - A microelectronic device includes a non-polymeric substrate, an organic interlayer, and a indium tin oxide layer formed on the organic interlayer. | 2009-04-30 |
20090108450 | INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME - An interconnect structure and method of fabricating the same is provided. The interconnect structure is a highly reliable copper interconnect structure. The interconnect structure includes a planarized lower dielectric layer and a lower cap layer on the planarized lower dielectric layer. A copper material is formed in a trench of the planarized lower dielectric layer, below the lower cap layer. A lower liner extends into a pattern of the lower cap layer and contacts the copper layer. An upper dielectric layer is on the lower cap layer and a copper layer contacts the lower liner and is formed in a via of at least the lower cap layer. An upper liner is formed over the copper layer, sandwiching the copper layer between the lower liner and the upper liner. An upper copper layer is formed over the upper liner. | 2009-04-30 |
20090108451 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a pattern layer formed on and/or over a semiconductor substrate, a fluorine-diffusion barrier layer containing a silicon-doped silicon oxide formed on and/or over the pattern layer, and an interlayer dielectric layer containing fluorine formed on and/or over the fluorine-diffusion barrier layer. | 2009-04-30 |
20090108452 | Semiconductor device and method for manufacturing the same - A method of manufacturing a semiconductor device including a sputtering process for forming a barrier film mainly having tantalum or tantalum nitride on an interlayer insulator formed by sputtering using a xenon gas. The sputtering process may include a step of forming one barrier film mainly composed of tantalum nitride on a substrate by sputtering using a xenon gas by applying a RF bias, and a step for forming another barrier film mainly composed of tantalum on the first barrier film by sputtering using a xenon gas without applying the RF bias. The barrier film may be formed by changing the RF bias continuously, and forming the interlayer insulator side by applying the RF bias, and forming the wiring side without applying the RF bias. | 2009-04-30 |
20090108453 | CHIP STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a metallization structure comprises depositing a first metal layer; depositing a first pattern-defining layer over said first metal layer, a first opening in said first pattern-defining layer exposes said first metal layer; depositing a second metal layer over said first metal layer exposed by said first opening; depositing a second pattern-defining layer over said second metal layer, a second opening in said second pattern-defining layer exposes said second metal layer; depositing a third metal layer over said second metal layer exposed by said second opening; removing said second pattern-defining layer; removing said first pattern-defining layer; and removing said first metal layer not under said second metal layer. | 2009-04-30 |
20090108454 | METAL LINE IN SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A metal line in a semiconductor device and fabricating method thereof includes a first contact plug on a substrate, a first insulating interlayer over the substrate including the first contact plug, a first etch stop layer formed over the first insulating interlayer; a trench in the first insulating interlayer and the first etch stopper layer, a metal line in the trench, the metal line including a second contact plug projecting from the trench, wherein the metal line and the trench are formed as a single body, and a second insulating interlayer over the substrate including the metal line and the second contact plug. | 2009-04-30 |
20090108455 | INTEGRATED CIRCUIT AND PROCESS FOR FABRICATING THEREOF - A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further comprises forming a plurality of longitudinal trenches in the substrate and depositing a layer of a first conductive material on at least one longitudinal trench of the plurality of longitudinal trenches. A first layer of a second conductive material is deposited on the layer of the first conductive material. Thereafter, the process includes depositing a second layer of the second conductive material on the first layer of the second conductive material. The second layer of the second conductive material at least partially fills the at least one longitudinal trench. The first conductive material is selected such that a reduction potential of the first conductive material is less than a reduction potential of the second conductive material. | 2009-04-30 |
20090108456 | Solder-top Enhanced Semiconductor Device and Method for Low Parasitic Impedance Packaging - A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes:
| 2009-04-30 |
20090108457 | Apparatus for Improved Power Distribution in a Three Dimensional Vertical Integrated Circuit - A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path. | 2009-04-30 |
20090108458 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE - In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, an electrical bus embedded in a dielectric material below a surface of a semiconductor substrate is disclosed. Other embodiments are described and claimed. | 2009-04-30 |
20090108459 | SEMICONDUCTOR DEVICE - A semiconductor device includes first underlying lines in an underlying wiring layer electrically connected to and shaped like a first semiconductor region, second underlying lines in the underlying wiring layer electrically connected to and shaped like a second semiconductor region, a first intermediate line in an intermediate wiring layer electrically connected to the first underlying lines, the first intermediate line including finger regions shaped like the first underlying lines, a coupling section to electrically interconnect the finger regions, a second intermediate line in the intermediate wiring layer electrically connected to the second underlying lines, the second intermediate line including finger regions shaped like the second underlying lines, and a coupling section to electrically connect the finger regions, a first overlying line in an overlying wiring layer electrically connected to the first intermediate line, and a second overlying line in the overlying wiring layer electrically connected to the second intermediate line. | 2009-04-30 |
20090108460 | DEVICE INCLUDING A SEMICONDUCTOR CHIP HAVING A PLURALITY OF ELECTRODES - A device, including a semiconductor chip having a plurality of first electrodes is disclosed. A plurality of second electrodes is arranged on a first surface of the semiconductor chip. A first electrically conductive layer is applied over a first section of the first surface and electrically coupled to the first electrodes arranged within the first section. A second electrically conductive layer is applied over the first electrically conductive layer and electrically coupled to the second electrodes arranged within the first section. | 2009-04-30 |
20090108461 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes providing a semiconductor substrate including a first landing plug and a second landing plug. A bit line is formed over the semiconductor substrate. The bit line is electrically coupled to the first landing plug. A stacked structure of an etch stop film and an interlayer insulating film is deposited over the semiconductor substrate including the bit line. The stacked structure is selectively etched using a contact mask to form a contact hole having an upper part that is wider than a lower part of the contact hole. The contact hole exposes the second landing plug. A contact plug is formed over the contact hole. The contact plug is electrically coupled to the second landing plug. | 2009-04-30 |
20090108462 | DUAL INTEGRATION SCHEME FOR LOW RESISTANCE METAL LAYERS - By forming a metal line extending through the entire interlayer dielectric material in resistance sensitive metallization layers, enhanced uniformity of these metallization layers may be obtained. The patterning of respective via openings may be accomplished on the basis of a recess formed in a cap layer, which additionally acts as an efficient etch stop layer during the patterning of the trenches, which extend through the entire interlayer dielectric material. Consequently, for a given design width of metal lines in resistance sensitive metallization layers, a maximum cross-sectional area may be obtained for the metal line with a high degree of process uniformity irrespective of a variation of the via density. | 2009-04-30 |
20090108463 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a wiring layer over a substrate, forming a first film over the wiring layer, forming a second film over the first film, selectively etching the first and second films to form an first end of the first and second films over the wiring layer, forming a third film over the second film, selectively etching the third film to form a second end of the third film tapered off over the first end of the first and second films, forming an interlayer insulating film over the second and third films, forming a contact hole by selectively etching the interlayer insulating film, the first film, the second film and the third film, and forming a contact plug connected to the wiring layer in the contact holes. | 2009-04-30 |
20090108464 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first insulating layer including a first contact pad made of conductive polysilicon and a second insulating layer including a second contact pad are formed over a semiconductor silicon layer. After this, a via hole for a through-hole electrode is formed until the via hole penetrates through at least the semiconductor silicon layer and the first contact pad and reaches to the second contact pad. | 2009-04-30 |
20090108465 | CERAMIC SUBSTRATE GRID STRUCTURE FOR THE CREATION OF VIRTUAL COAX ARRANGEMENT - Signal line conductors passing through vertical vias in an insulative substrate for supporting and interconnecting integrated circuit chips are provided with shielding conductors in adjacent vias that link respective power and ground planes. The shielding conductors' presence in positions around a signal via is made possible through the employment of power plane and ground plane conductive grids that are laid out in rhomboid patterns. The power plane and ground plane grids possess a left-right mirror relation to one another and are displaced to place the rhomboid's corners to avoid overlapping any of the grid lines. | 2009-04-30 |
20090108466 | SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS - Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance. | 2009-04-30 |
20090108467 | DEVICE WITH A PLURALITY OF SEMICONDUCTOR CHIPS - A device with a plurality of semiconductor chips is disclosed. One embodiment provides a substrate. A first semiconductor chip is mounted over the substrate. A second semiconductor chip is mounted over the first semiconductor chip. A first electrically conducting element electrically couples the second semiconductor chip to the substrate and a mold material covers the first electrically conducting element only partially. | 2009-04-30 |
20090108468 | STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips, each semiconductor chip having a first face, a second face opposite to the first face, and a circuit part. A thorough portion passes through the first and second faces of the semiconductor chip. A recess part is formed in a portion of the second face where the second face and the through portion meets. A through electrode is electrically connected to the circuit part and is disposed inside of the through portion. A connection member is disposed int he recess part to electrically connect the through electrodes of adjacent stacked semiconductor chips. And the semiconductor chip module is mounted to a substrate. The stacked semiconductor package prevents both gaps between semiconductor chips and misalignment of the through electrode. | 2009-04-30 |
20090108469 | CHIP STACK PACKAGE - A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities. | 2009-04-30 |
20090108470 | SEMICONDUCTOR DEVICE - A element group includes a plurality of semiconductor elements stacked in a step-like shape on a wiring board. The semiconductor elements are electrically connect to connection pads of the wiring board through metal wires. Among the plural semiconductor elements stacked in a step-like shape, the uppermost semiconductor element has a thickness larger than that of the semiconductor element immediately below it. | 2009-04-30 |
20090108471 | Wiring board of semiconductor device, semiconductor device, electronic apparatus, mother board, method of manufacturing wiring board of semiconductor device, method of manufacturing mother board and method of manufacturing electronic apparatus - In a wiring board of a semiconductor device according to the present invention, a land | 2009-04-30 |
20090108472 | WAFER-LEVEL UNDERFILL PROCESS USING OVER-BUMP-APPLIED RESIN - A process of fabricating wafer-level underfilled microelectronic packages using over-bump application of a self-fluxing resin to a wafer, b-staging of the resin, dicing of the coated wafer, and joining the diced chips to substrates producing wafer-level underfilled microelectronic flip-chip packages. Moreover, provided are microelectronic packages, which are produced in accordance with the inventive process. | 2009-04-30 |
20090108473 | DIE-ATTACH MATERIAL OVERFLOW CONTROL FOR DIE PROTECTION IN INTEGRATED CIRCUIT PACKAGES - Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package includes a metal layer, an integrated circuit die, and an adhesive material. The metal layer has a first surface that has a die-attach region. The metal layer further has one or more recessed regions formed in the first surface of the metal layer adjacent to the die-attach region. The adhesive material attaches a first surface of the die to the die-attach region and at least partially fills the recessed region(s). Excess adhesive material flows into the recessed region(s) during application of the die to the die-attach region, so that the side surfaces of the die remain substantially uncovered by the adhesive material. By preventing the excess adhesive material from covering the side surfaces of the die, the adhesive material is prevented from penetrating the side surfaces of the die, which could damage the die. | 2009-04-30 |
20090108474 | JUNCTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A junction structure and a method of manufacturing the same are provided which can achieve stable wire bonding between a Poly-Si film bonding pad and an Al wire. The junction structure is made up of a SiO | 2009-04-30 |