17th week of 2014 patent applcation highlights part 42 |
Patent application number | Title | Published |
20140113386 | SYSTEMS AND DEVICES FOR MOLEUCLE SENSING AND METHOD OF MANUFACTURING THEREOF - Embodiments of the disclosure are directed to a device for molecule sensing. In some embodiments, the device includes a first electrode separated from a second electrode by a dielectric layer. The first electrode comprises a large area electrode and the second electrode comprises a small area electrode. At least one opening (e.g., trench) cut or otherwise created into the dielectric layer exposes a tunnel junction therebetween whereby target molecules in solution can bind across the tunnel junction. | 2014-04-24 |
20140113387 | METHOD OF INHIBITING NONSPECIFIC REACTION IN PIVKA-II ASSAY REAGENT - A problem to be solved by the present invention is to inhibit a nonspecific agglutination reaction in an agglutination test using a monoclonal antibody having a property of specifically biding to PIVKA-II and a monoclonal antibody having a property of specifically biding to prothrombin as well as two types of carrier particles carrying these monoclonal antibodies. The nonspecific agglutination reaction can be inhibited by adding certain divalent metal ions to a reaction solution containing the monoclonal antibody having a property of specifically biding to PIVKA-II and the monoclonal antibody having a property of specifically biding to prothrombin as well as the two types of carrier particles carrying these monoclonal antibodies. | 2014-04-24 |
20140113388 | TREATMENT PLANNING BASED ON POLYPEPTIDE RADIOTOXICITY SERUM MARKERS - A method includes at least one of creating or adapting a treatment plan for a patient based on a set of serum polypeptides of the patient that are indicative of a radiotoxicity of the patient at least one of before or after at least one of a plurality of radiotherapy treatments of the treatment plan, wherein the radiotoxicity is induced by radiation exposure from the radiotherapy treatment. A system includes a treatment planning device ( | 2014-04-24 |
20140113389 | Multi-Wafer Reactor - A solution for manufacturing semiconductors is provided. An embodiment provides a chemical vapor deposition reactor, which includes a chemical vapor deposition chamber. A substrate holder located in the chemical vapor deposition chamber can be rotated about its own axis at a first angular speed, and a gas injection component located in the chemical vapor deposition chamber can be rotated about an axis of the gas injection component at a second angular speed. The angular speeds are independently selectable and can be configured to cause each point on a surface of a substrate wafer to travel in an epicyclical trajectory within a gas flow injected by the gas injection component. An angle between the substrate holder axis and the gas injection component axis and/or a distance between the substrate holder axis and the gas injection component axis can be controlled variables. | 2014-04-24 |
20140113390 | Method for Producing Singulated Semiconductor Devices - A method for producing singulated semiconductor components includes providing a starting substrate. An etching process is carried out to form depressions at a side of the starting substrate. The depressions are arranged in the region of the semiconductor components to be produced. Walls present between the depressions are arranged in the region of separating regions provided for severing the starting substrate. The method furthermore comprises forming a metallic layer on the side of the starting substrate with the depressions and walls and carrying out a further etching process for severing the starting substrate in the separating regions and forming the singulated semiconductor components. | 2014-04-24 |
20140113391 | APPARATUS FOR MOUNTING OPTICAL MEMBER AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE - There is provided a method of manufacturing a light emitting device including preparing a light source including a wavelength conversion unit and an optical member applied to the light source. Light is irradiated to the wavelength conversion unit to excite the wavelength conversion unit and positional information regarding the light source is obtained from light emitted from the wavelength conversion unit. A mounting position of the optical member is determined based on the obtained positional information regarding the light source. The method of manufacturing a light emitting device having excellent light characteristics can be obtained. | 2014-04-24 |
20140113392 | PACKAGE SUBSTRATE FOR OPTICAL ELEMENT AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a method of manufacturing a package substrate for optical elements. The method includes the steps of providing a conductive substrate including an insulation layer formed thereon, and forming a circuit layer and electrode pads on the conductive substrate using a plating process. The method further includes selectively plating the circuit layer, in which the optical element is to be mounted, with a conductor to such a thickness that the optical element is buried, forming a cavity space including a lower part and a side wall in the circuit layer, and mounting an optical element in the cavity space and then applying a fluorescent resin layer thereon. | 2014-04-24 |
20140113393 | PACKAGE SUBSTRATE FOR OPTICAL ELEMENT AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a method of manufacturing a package substrate for optical elements. The method includes the steps of providing a conductive substrate, forming a cavity space in the conductive substrate, and forming an insulation layer on the conductive substrate. The method further includes the steps of forming a circuit layer and electrode pads on the conductive substrate using a plating process, forming a cavity space including a lower part and a side wall in the circuit layer, and mounting an optical element in the cavity space and then applying a fluorescent resin layer thereon. | 2014-04-24 |
20140113394 | FILM LAMINATION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS USING THE FILM LAMINATION APPARATUS - A film lamination apparatus for laminating a film on a flat display panel including a display unit on one surface of a substrate, the film lamination apparatus including: a work table configured to support the flat display panel such that the display unit is below the substrate; and a transfer robot configured to support the flat display panel such that the display unit faces upward and then transfer the flat display panel to the work table while the flat display panel is turned over such that the display unit faces downward. | 2014-04-24 |
20140113395 | VAPOR DEPOSITION APPARATUS, METHOD OF FORMING THIN FILM BY USING VAPOR DEPOSITION APPARATUS, AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY APPARATUS - A vapor deposition apparatus for depositing a thin film on a substrate includes a cover having an accommodation portion and a communicated portion, which communicated portion is connected to the accommodation portion and faces a direction of the substrate, and includes a body in the accommodation portion, which body includes a first portion and a second portion. The first portion is disposed at a first location of the body and connected to a first injection portion for injecting a first material onto the substrate, the second portion is disposed at a second location of the body and connected to a second injection portion for injecting a second material onto the substrate, and the body rotates in at least one direction so that the first portion and the second portion are alternately connected to each other with respect to the communicated portion. | 2014-04-24 |
20140113396 | ESD PROTECTION FOR MEMS RESONATOR DEVICES - Disclosed herein are MEMS resonator device designs and fabrication techniques that provide protection against electrostatic charge imbalances. In one aspect, a MEMS resonator device includes a substrate, an electrode including a first microstructure supported by the substrate, a resonant element including a second microstructure spaced from the first microstructure by a gap for resonant displacement of the second microstructure within the gap during operation, and a disabled shunt coupled to the electrode or the resonant element. The disabled shunt is disabled to enable the resonant displacement but otherwise configured to protect against damage from an electrostatic charge imbalance before the operation of the MEMS resonator device. | 2014-04-24 |
20140113397 | Enhancing planarization uniformity in optical devices - An optical device is formed from a device precursor having a layer of a light-transmitting medium on a base. A first feature is formed on the device precursor. The device precursor is then processed such that a stop layer protects the first feature and a portion of the device precursor is above the top of the stop layer. The first feature is between the base and the stop layer. The device precursor is planarized such that the portion of the device precursor located above the top of the stop layer becomes flush with the top of the portion of the stop layer that is present on the device precursor after the planarization. During the planarization, the stop layer acts as a planarization stop that slows or stops the rate of planarization. | 2014-04-24 |
20140113398 | Apparatus for Vertically Integrated Backside Illuminated Image Sensors - A backside illuminated image sensor comprises a photodiode and a first transistor located in a first chip, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a second transistor formed in a second chip and a plurality of logic circuits formed in a third chip, wherein the second chip is stacked on the first chip and the third chip is stacked on the second chip. The logic circuit, the second transistor and the first transistor are coupled to each other through a plurality of boding pads and through vias. | 2014-04-24 |
20140113399 | MANUFACTURING METHOD OF SOLID-STATE IMAGING APPARATUS, SOLID-STATE IMAGING APPARATUS, AND ELECTRONIC IMAGING APPARATUS - A manufacturing method of a solid-state imaging apparatus includes the steps of: preparing a solid-state imaging device having a light receiving region at a main surface thereof; preparing a light transmitting member having an extending portion extending from the solid-state imaging device; preparing a holding member having a space for holding the solid-state imaging device therein, and having a positioning portion for positioning the solid-state imaging device; fixing the light transmitting member to the main surface of the solid-state imaging device in parallel to each other to keep a constant interval therebetween; bringing a side of the solid-state imaging device to meet the positioning portion of the holding member; and fixing the extending portion of the light transmitting member to the holding member. | 2014-04-24 |
20140113400 | SOLAR BATTERY MODULE AND SOLAR BATTERY ARRAY - A solar battery module ( | 2014-04-24 |
20140113401 | Image Sensor Device and Method for Making Same - The present invention discloses an image sensor device and a method for making an image sensor device. The image sensor device comprises an optical pixel and an electronic circuit, wherein the optical pixel includes: a substrate; an image sensor area formed in the substrate; a masking layer formed above the image sensor area, wherein the masking layer is formed during a process for forming the electronic circuit; and a light passage above the masking layer for increasing light sensing ability of the image sensor area. | 2014-04-24 |
20140113402 | High Efficiency Flexible Solar Cells For Consumer Electronics - A method comprises providing a base substrate having a surface; disposing layers of III-V semiconductor material on the surface of the base substrate using a chemical vapor deposition technique or a molecular beam epitaxy technique; disposing a stressor layer on the layer of III-V semiconductor material; operatively associating a flexible handle substrate with the stressor layer; and using controlled spalling to separate the layer of III-V semiconductor material from the base substrate to expose a surface of the layer of III-V semiconductor material. | 2014-04-24 |
20140113403 | High efficiency CZTSe by a two-step approach - Methods of forming CZTS absorber layers in a TFPV device with a graded bandgap with or without a graded concentration are provided. In general, a Cu—Zn—Sn—(S, Se) precursor film is formed by sputtering. The Cu—Zn—Sn—(S, Se) precursor film can be formed as a single layer or as a multilayer stack. The composition may be uniform or graded throughout the thickness of the film. In some embodiments, the sputtering is performed in a reactive atmosphere including a chalcogen source (e.g. H | 2014-04-24 |
20140113404 | METHOD FOR MANUFACTURING AN OPTO-MICROELECTRONIC DEVICE - Method for manufacturing a microelectronic device from a first substrate ( | 2014-04-24 |
20140113405 | METHOD FOR FORMING MULTILAYER FILM INCLUDING OXIDE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To form an oxide semiconductor film with a low density of localized levels. To improve electric characteristics of a semiconductor device including the oxide semiconductor. After oxygen is added to an oxide film containing In or Ga in contact with an oxide semiconductor film functioning as a channel, heat treatment is performed to make oxygen in the oxide film containing In or Ga transfer to the oxide semiconductor film functioning as a channel, so that the amount of oxygen vacancies in the oxide semiconductor film is reduced. Further, an oxide film containing In or Ga is formed, oxygen is added to the oxide film, an oxide semiconductor film is formed over the oxide film, and then heat treatment is performed. | 2014-04-24 |
20140113406 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith. | 2014-04-24 |
20140113407 | SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME - An object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H | 2014-04-24 |
20140113408 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer. | 2014-04-24 |
20140113409 | PACKAGE SUBSTRATE DYNAMIC PRESSURE STRUCTURE - Devices and methods for their formation, including electronic assemblies having a shape memory material structure, are described. In one embodiment, a device includes a package substrate and an electronic component coupled to the package substrate. The device also includes a shape memory material structure coupled to the package substrate. In one aspect of certain embodiments, the shape memory material structure is formed from a material selected to have a martensite to austenite transition temperature in the range of 50-300 degrees Celsius. In another aspect of certain embodiments, the shape memory material structure is positioned to extend around a periphery of the electronic component. Other embodiments are described and claimed. | 2014-04-24 |
20140113410 | SYSTEM IN PACKAGE MANUFACTURING METHOD USING WAFER-TO-WAFER BONDING - Embodiments of the present disclosure are related to manufacturing system-in-packages at wafer-level. In particular, various embodiments are directed to adhering a first wafer to a second wafer and adhering solder balls to contact pads of the first wafer. In one embodiment, a first wafer having first and second surfaces is provided. The first wafer includes bond pads located on the first surface that are coupled to a respective semiconductor device located in the first wafer. A second wafer having an electrical component located therein is provided. A conductive adhesive is provided on at least one of the first wafer and the second wafer. Conductive balls are provided on the bond pads on the first surface of the first wafer. The conductive balls and the conductive adhesive are heated to cause the conductive balls to adhere to the bond pad and the conductive adhesive to adhere the first wafer to the second wafer. | 2014-04-24 |
20140113411 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device which includes a first semiconductor chip | 2014-04-24 |
20140113412 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes. | 2014-04-24 |
20140113413 | SEMICONDUCTOR WAFER MOUNTING METHOD AND SEMICONDUCTOR WAFER MOUNTING APPARATUS - A resin sealing sheet is cut into an adhesive sheet piece having an outer shape smaller than that of a wafer. The adhesive sheet piece is joined to a supporting adhesive tape together with a ring frame. The adhesive tape between the ring frame and the adhesive sheet piece is sandwiched by upper and lower housings to form a chamber. The wafer with a support board placed on a wafer holding table within the chamber faces to the adhesive sheet piece closely. The chamber is divided into two spaces by the adhesive tape. Differential pressure generated within the two spaces causes the adhesive tape and the adhesive sheet piece to cave and bend toward the wafer, whereby the adhesive sheet piece is joined to the wafer. | 2014-04-24 |
20140113414 | SEMICONDUCTOR MOUNTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MOUNTING DEVICE - A semiconductor mounting device including a first substrate having first insulation layers, first conductor layers formed on the first insulation layers and via conductors connecting the first conductor layers, a second substrate having a core substrate, second conductor layers, through-hole conductors and buildup layers having second insulation layers and third conductor layers, first bumps connecting the first and second substrates and formed on the outermost first conductor layer on the outermost first insulation layer, and second bumps positioned to connect a semiconductor element and formed on the outermost third conductor layer on the outermost second insulation layer. The second substrate has greater thickness than the first substrate, the second conductor layers are formed on surfaces of the core substrate, respectively, the through-hole conductors are formed through the core substrate and connecting the second conductor layers, and the buildup layers are formed on the core substrate and second conductor layers, respectively. | 2014-04-24 |
20140113415 | METHOD OF MANUFACTURING CIRCUIT BOARD AND CHIP PACKAGE AND CIRCUIT BOARD MANUFACTURED BY USING THE METHOD - Provided is a method of manufacturing a circuit board. The method includes: preparing a base substrate including a core layer and a first conductive layer that is formed on at least one surface of the core layer and includes an internal circuit pattern; forming a build-up material to cover the first conductive layer; forming in the build-up material at least one cavity through which the core layer and the first conductive layer are exposed; forming a laminated body by curing the build-up material in which the at least one cavity is formed; and forming a second conductive layer including an external circuit pattern on an outer surface of the laminated body. | 2014-04-24 |
20140113416 | DIELECTRIC FOR CARBON-BASED NANO-DEVICES - A method for fabricating a carbon-based semiconductor device. A substrate is provided and source/drain contacts are formed on the substrate. A graphene channel is formed on the substrate connecting the source contact and the drain contact. A dielectric layer is formed on the graphene channel with a molecular beam deposition process. A gate contact is formed over the graphene channel and on the dielectric. The gate contact is in a non-overlapping position with the source and drain contacts leaving exposed sections of the graphene channel between the gate contact and the source and drain contacts. | 2014-04-24 |
20140113417 | CROSS-COUPLING OF GATE CONDUCTOR LINE AND ACTIVE REGION IN SEMICONDUCTOR DEVICES - Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme. | 2014-04-24 |
20140113418 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE - A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate ( | 2014-04-24 |
20140113419 | METHODS OF REDUCING MATERIAL LOSS IN ISOLATION STRUCTURES BY INTRODUCING INERT ATOMS INTO OXIDE HARD MASK LAYER USED IN GROWING CHANNEL SEMICONDUCTOR MATERIAL - In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process. | 2014-04-24 |
20140113420 | METHODS OF AVOIDING SHADOWING WHEN FORMING SOURCE/DRAIN IMPLANT REGIONS ON 3D SEMICONDUCTOR DEVICES - One illustrative method disclosed herein includes forming a patterned photoresist implant mask that has an opening that is defined, at least partially, by a plurality of non-vertical sidewalls, wherein the implant mask covers one of an N-type FinFET or P-type FinFET device, while the other of the N-type FinFET or P-type FinFET device is exposed by the opening in the patterned photoresist implant mask, and performing at least one source/drain implant process through the opening in the patterned photoresist implant mask to form a doped source/drain implant region in at least one fin of the FinFET device exposed by the opening in the patterned photoresist implant mask. | 2014-04-24 |
20140113421 | SILICON CARBIDE SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SAME - A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage is provided. For this, a first deposition film ( | 2014-04-24 |
20140113422 | SEMICONDUCTOR DEVICE WITH POCKET REGIONS AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth. | 2014-04-24 |
20140113423 | METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE - In various embodiments, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device may include forming a first source/drain region, forming a second source/drain region, forming an active region electrically coupled between the first source/drain region and the second source/drain region, forming a trench disposed between the second source/drain region and at least a portion of the active region, forming a first isolation layer disposed over the bottom and the sidewalls of the trench, forming electrically conductive material disposed over the isolation layer in the trench, forming a second isolation layer disposed over the active region, and forming a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact. | 2014-04-24 |
20140113424 | Source/Drain Stressor Having Enhanced Carrier Mobility and Method for Manufacturing Same - Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer. | 2014-04-24 |
20140113425 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes the following steps. At first, at least a gate structure is formed on a substrate. Subsequently, a first material layer and a second material layer sequentially formed on the substrate conformally cover the gate structure. Subsequently, an implantation process is performed on the second material layer, and a wet etching process is further performed to remove a part of the second material layer to form a remaining second material layer. Furthermore, a dry etching process is performed to remove a part of the remaining second material layer to form a partial spacer. | 2014-04-24 |
20140113426 | TRANSISTOR AND METHOD OF FORMING THE TRANSISTOR SO AS TO HAVE REDUCED BASE RESISTANCE - Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance R | 2014-04-24 |
20140113427 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory (PCRAM) device includes a semiconductor substrate; switching elements formed on the semiconductor substrate; a plurality of phase-change structures formed on the switching elements; and heat absorption layers buried between the plurality of phase-change structures, wherein the plurality of phase-change structures are insulated from the heat absorption layers. | 2014-04-24 |
20140113428 | Method for Integrating MnOz Based Resistive Memory with Copper Interconnection Back-End Process - The present invention pertains to the technical field of semiconductor memory. More particularly, the invention relates to a method for integrating MnO | 2014-04-24 |
20140113429 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane. | 2014-04-24 |
20140113430 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor device according to the present invention includes: forming a lower electrode above a substrate; forming, above the lower electrode, a first variable resistance layer comprising a first metal oxide; forming a step region in the first variable resistance layer by collision of ions excited by plasma; removing residue of the first variable resistance layer created in the forming of the step region; forming a second variable resistance layer which covers the step region of the first variable resistance layer, comprises a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide, and has a bend on a step formed along an edge of the step region; and forming an upper electrode above the second variable resistance layer. | 2014-04-24 |
20140113431 | METHODS OF FABRICATING A STORAGE NODE IN A SEMICONDUCTOR DEVICE AND METHODS OF FABRICATING A CAPACITOR USING THE SAME - Methods of forming a storage node in a semiconductor device are provided. The method includes forming an interlayer insulation layer on a substrate, forming an etch stop layer and a first sacrificial layer on the interlayer insulation layer, patterning the first sacrificial layer and the etch stop layer to form a first sacrificial layer pattern and an etch stop layer pattern that define a storage node contact hole, forming a recessed first storage node conductive pattern that conformally covers a lower sidewall and a bottom surface of the storage node contact hole, forming a second storage node conductive pattern that includes a first portion surrounded by the recessed first storage node conductive pattern and a second portion conformally covering an upper sidewall of the storage node contact hole, and removing the first sacrificial layer pattern. The recessed first storage node conductive pattern and the second storage node conductive pattern constitute a storage node. | 2014-04-24 |
20140113432 | Semiconductor Fins with Reduced Widths and Methods for Forming the Same - A method includes forming Shallow Trench Isolation (STI) regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and after the forming the STI regions, oxidizing an upper portion of a semiconductor strip between the STI regions. A width of the upper portion of the semiconductor strip is reduced by the oxidizing. The STI regions are recessed, until a portion of the upper portion of the semiconductor strip is higher than a top surface of remaining portions of the STI regions to form a semiconductor fin. | 2014-04-24 |
20140113433 | WAFER BONDING FOR 3D DEVICE PACKAGING FABRICATION - An apparatus and method bond a first wafer to a second wafer. The apparatus includes a first pressure application device configured to apply pressure at a central region of the first wafer in a direction toward the second wafer to initiate a bonding process between the first wafer and the second wafer. The apparatus also includes one or more second pressure application devices configured to apply pressure between the central region and an outer edge of the first wafer to complete the bonding process. The one or more second pressure application devices apply pressure on the first wafer after the first pressure application device has initiated the bonding process and while the first pressure application device continues to apply pressure at the central region. A controller controls the first pressure application device and the one or more second pressure application devices. | 2014-04-24 |
20140113434 | PROCESS FOR FORMING A CRACK IN A MATERIAL - A process for forming a layer ( | 2014-04-24 |
20140113435 | USE OF REPELLENT MATERIAL TO PROTECT FABRICATION REGIONS IN SEMI CONDUCTOR ASSEMBLY - A method of preparing semiconductor dies from a semiconductor wafer having a plurality of fabrication regions separated by dicing lines on the top side of the wafer, and an adhesive coating on the back side of the wafer, comprises applying a repellent material to the fabrication regions and dicing lines where the adhesive coating is not intended to be printed; applying the adhesive coating to the back side of the wafer; removing the repellent material; and separating the wafer along the dicing lines into individual dies. | 2014-04-24 |
20140113436 | METHOD OF DEPOSITING A FILM AND FILM DEPOSITION APPARATUS - A disclosed method of depositing a silicon film on a substrate mounted on a turntable and can pass by rotation through a first process area and a second process area, which are separately arranged along a peripheral direction in a cylindrical chamber set to have a first temperature capable of cutting a Si—H bond includes a molecular layer deposition step of supplying a Si | 2014-04-24 |
20140113437 | SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions. | 2014-04-24 |
20140113438 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device in which a via hole and a trench are formed in a low dielectric constant film using a hard mask film having at least three layers. In a process of forming the hard mask film having at least three layers, the hard mask film formed of an insulating material and the hard mask film formed of a metal material, amorphous silicon or polycrystalline silicon are alternately laminated. | 2014-04-24 |
20140113439 | METHOD OF DEPOSITING AN AMORPHOUS SILICON FILM - A method is for depositing in a chamber an amorphous silicon layer on a surface of a semiconducting or insulating substrate. In the method, the surface is pretreated with a NH | 2014-04-24 |
20140113440 | LASER IRRADIATION METHOD AND LASER IRRADIATION DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention is characterized in that by laser beam being slantly incident to the convex lens, an aberration such as astigmatism or the like is occurred, and the shape of the laser beam is made linear on the irradiation surface or in its neighborhood. Since the present invention has a very simple configuration, the optical adjustment is easier, and the device becomes compact in size. Furthermore, since the beam is slantly incident with respect to the irradiated body, the return beam can be prevented. | 2014-04-24 |
20140113441 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film. | 2014-04-24 |
20140113442 | DUAL GATE PROCESS - The control of gate widths is improved for system-on-a-chip (SoC) devices which require multiple gate dielectric “gate” thicknesses, e.g., for analog and digital processing on the same chip. A hard mask is formed to protect a thick gate while the thin gate region is etched to remove oxide (sometimes referred to as a preclean step). The patterned substrate is then processed to selectively deposit a second thickness of gate material. The thin gate may be silicon oxide and the physical thickness of the thin gate may be less than that of the thick gate. In a preferred embodiment, the substrate is not exposed to air or atmosphere after the hardmask is removed. | 2014-04-24 |
20140113443 | FABRICATING METHOD OF A SEMICONDUCTOR DEVICE - A fabricating method of a semiconductor device includes stacking a high-k dielectric film not containing silicon (Si) and an insulating film containing silicon (Si) on a substrate, and diffusing Si contained in the insulating film into the high-k dielectric film by annealing the substrate having the high-k dielectric film and the insulating film stacked thereon. | 2014-04-24 |
20140113444 | ACTIVE AREA BONDING COMPATIBLE HIGH CURRENT STRUCTURES - A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer. | 2014-04-24 |
20140113445 | AL BOND PAD CLEAN METHOD - Embodiments of the present disclosure provide a method for controlling moisture from substrate being processed. Particularly, embodiments of the present disclosure provide methods for removing moisture from polymer materials adjacent bond pad areas. One embodiment of the present includes providing a moisture sensitive precursor and forming a compound from a reaction between the moisture to be controlled and the moisture sensitive precursor. | 2014-04-24 |
20140113446 | Semiconductor Device and Method of Confining Conductive Bump Material with Solder Mask Patch - A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate. | 2014-04-24 |
20140113447 | Electrical Connection for Chip Scale Packaging - A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion. | 2014-04-24 |
20140113448 | POSITIVE PHOTOSENSITIVE RESIN COMPOSITION FOR SPRAY COATING AND METHOD FOR PRODUCING THROUGH ELECTRODE USING THE SAME - A method for producing a through electrode includes providing a semiconductor wafer having an integrated circuit provided on a surface of the semiconductor wafer and a hole provided in the semiconductor wafer along a thickness direction of the semiconductor wafer. At least a portion of a back surface of an electrode of the integrated circuit is exposed through the hole. A positive photosensitive resin composition is sprayed to form a coating film so that the coating film covers an inner surface of the hole. The positive photosensitive resin composition has a viscosity of 0.5 to 200 cP and includes an alkali-soluble resin, a compound which generates an acid when exposed to light, and a solvent. At least a portion of the coating film is exposed and developed to form a coating film pattern. | 2014-04-24 |
20140113449 | Nanoelectromechanical Logic Devices - Nanoelectromechanical logic devices can include a plurality of flexible bridges having control and logic electrodes. Voltages applied to control electrodes can be used to control flexing of the bridges. The logic electrodes can provide logical functions of the applied voltages. | 2014-04-24 |
20140113450 | PLASMA ETCHING METHOD - A plasma etching method includes supplying an etching gas containing an oxygen gas and a sulfur fluoride gas at a predetermined flow rate into a processing chamber that accommodates a processing substrate including a silicon layer and a resist layer, and etching the silicon layer with plasma generated from the etching gas using the resist layer as a mask. The plasma etching method further includes a first step of etching the silicon layer while a flow ratio of the oxygen gas to the sulfur fluoride gas is adjusted to a first flow ratio; a second step of etching the silicon layer while decreasing a flow rate of the oxygen gas to decrease the flow ratio to a second flow ratio, which is lower than the first flow ratio; and a third step of etching the silicon layer while the flow ratio is adjusted to the second flow ratio. | 2014-04-24 |
20140113451 | METHOD FOR FORMING A PATTERN - One aspect of the present invention is directed to a method of forming a pattern. A first layer which comprises a polymerization initiator is selectively formed on a second layer of a substrate. A polymer layer is selectively formed on the first layer by subjecting an organic monomer to living radical polymerization using the polymerization initiator. The second layer is selectively etched using the polymer layer as a mask. | 2014-04-24 |
20140113452 | WAFER EDGE TRIMMING METHOD - A wafer edge trimming method comprises steps as follows: Firstly, an etch-resistant layer is formed on a surface of a wafer. A wet treatment process is then performed to remove a portion of the etch-resistant layer, so as to expose a portion of the surface adjacent to an edge of the wafer. Subsequently, an etching process is performed to remove a portion of the wafer that is not covered by the remained etch-resistant layer. | 2014-04-24 |
20140113453 | TUNGSTEN CARBIDE COATED METAL COMPONENT OF A PLASMA REACTOR CHAMBER AND METHOD OF COATING - A tungsten carbide coated chamber component of semiconductor processing equipment includes a metal surface, optional intermediate nickel coating, and outer tungsten carbide coating. The component is manufactured by optionally depositing a nickel coating on a metal surface of the component and depositing a tungsten carbide coating on the metal surface or nickel coating to form an outermost surface. | 2014-04-24 |
20140113454 | LOW PROFILE MAGNETIC FILTER - A plasma processing apparatus includes a processing chamber having a plasma processing space therein and a substrate support in the processing chamber at a first end for supporting a substrate. A plasma source is coupled into the processing space and configured to form a plasma at a second end of the processing chamber opposite said first end. The apparatus further includes a magnetic grid having an intensity of a magnetic flux therein, a plurality of passageways penetrating from a first side to a second side, a thickness, a transparency, a passageway aspect ratio, and a position within the processing chamber between the second end and the substrate. The intensity, the thickness, the transparency, the passageway aspect ratio, and the position are configured to cause electrons having energies above an acceptable maximum level to divert from the direction. A method of obtaining low average electron energy flux onto the substrate is also provided. | 2014-04-24 |
20140113455 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A WET ETCH PROCESS FOR REMOVING SILICON NITRIDE - A method disclosed herein includes providing a semiconductor structure comprising a transistor, the transistor comprising a gate electrode and a silicon nitride sidewall spacer formed at the gate electrode. A wet etch process is performed. The wet etch process removes at least a portion of the silicon nitride sidewall spacer. The wet etch process comprises applying an etchant comprising at least one of hydrofluoric acid and phosphoric acid. | 2014-04-24 |
20140113456 | PREPARATION OF CERIUM-CONTAINING PRECURSORS AND DEPOSITION OF CERIUM-CONTAINING FILMS - Methods and compositions for depositing rare earth metal-containing layers are described herein. In general, the disclosed methods deposit the precursor compounds comprising rare earth-containing compounds using deposition methods such as chemical vapor deposition or atomic layer deposition. The disclosed precursor compounds include a cyclopentadienyl ligand having at least one aliphatic group as a substituent and an amidine ligand. | 2014-04-24 |
20140113457 | PLASMA ENHANCED ATOMIC LAYER DEPOSITION WITH PULSED PLASMA EXPOSURE - The embodiments herein focus on plasma enhanced atomic layer deposition (PEALD) processes using pulsed plasmas. While conventional PEALD processes use continuous wave plasmas during the plasma exposure/conversion operation, the embodiments herein utilize a pulsed plasma during this operation to achieve a film with high quality sidewalls. Because conventional PEALD techniques result in films having high quality at the bottom and top of a feature, but low quality on the sidewalls, this increased sidewall quality in the disclosed methods corresponds to a film that is overall more uniform in quality compared to that achieved with conventional continuous wave plasma techniques. | 2014-04-24 |
20140113458 | MINIMAL CONTACT EDGE RING FOR RAPID THERMAL PROCESSING - Embodiments of the disclosure generally relate to a support ring that supports a substrate in a process chamber. In one embodiment, the support ring comprises an inner ring, an outer ring connecting to an outer perimeter of the inner ring through a flat portion, an edge lip extending radially inwardly from an inner perimeter of the inner ring to form a supporting ledge, and a substrate support extending upwardly from a top surface of the edge lip. The substrate support may be a continuous ring-shaped body disposed around a circumference of the edge lip. The substrate support supports a substrate about its entire periphery from the back side with minimized contact surface to thermally disconnect the substrate from the edge lip. Particularly, the substrate support provides a substantial line contact with the back surface of the substrate. | 2014-04-24 |
20140113459 | METHOD FOR IN-SITU DRY CLEANING, PASSIVATION AND FUNCTIONALIZATION OF GE SEMICONDUCTOR SURFACES - A method for in-situ dry cleaning of a Ge containing semiconductor surface, other than SiGe. The method is conducted in a vacuum chamber. An oxygen monolayer(s) is formed and promotes removal of essentially all carbon from the surface, and serves to both clean and functionalize the surface. The Ge semiconductor surface is then annealed at a temperature below that which would induce dopant diffusion. | 2014-04-24 |
20140113460 | MEMORY CARD AND MEMORY CARD ADAPTOR - A memory card includes a card body, an interface terminal and an attachment mechanism for detachably mounting the card to an adaptor of an electronic device. The interface terminal is disposed at a central portion of a major surface of the card body. The attachment mechanism is located at an outer peripheral portion of the card body that surrounds the central portion. The adaptor has a recess whose shape complements that of the major surface of the card body, and socket exposed at a central portion of the bottom of the recess. Thus, the memory card may be inserted face down into the adaptor. | 2014-04-24 |
20140113461 | CONNECTION DEVICE FOR PORTABLE TERMINAL - A connection device of a portable terminal is provided. The connection device includes one or more coupling slots provided on a lateral side of the portable terminal, one or more metal pads mounted on a bottom of the one or more coupling slots, and a plug including one or more magnets corresponding to the one or more pads. The one or more magnets are arranged to protrude toward a predetermined side of the plug, and inserted into the one or more coupling slots by an attractive force produced between the one or more metal pads and the one or more magnets, thereby coupling the plug to the lateral side of the portable terminal. | 2014-04-24 |
20140113462 | CONNECTOR - A connector includes a housing having an insertion section into which a connection end of a sheet-shaped connection target is inserted, and a plurality of contacts held by the housing so as to extend in an insertion direction of the connection target and be aligned along a direction across the insertion direction of the connection target, wherein each contact to be mounted by soldering on the top surface of the mounting board on a side of insertion of the connection target has at its end on the side of insertion of the connection target a surface of flat shape to be mounted on the top surface of the mounting board, and a sloping surface which is inclined at a predetermined angle of less than 90 degrees with respect to the surface to be mounted for guiding the connection end of the connection target to the insertion section. | 2014-04-24 |
20140113463 | Structures for Securing Printed Circuit Connectors - Printed circuit substrates may be formed from rigid printed circuit material or flexible sheets of polymer. Printed circuit substrates may have conductive traces. Integrated circuits, touch sensor electrode structure, sensors, and other components may be mounted to the conductive traces. Connectors such as board-to-board connectors may be used to couple printed circuit substrates together. To hold the connectors together and to provide electromagnetic shielding, printed circuits and connectors may be surrounded by printed circuit connector securing structures. The printed circuit connector securing structures may have one or more strips of conductive fabric tape wrapped around the connectors. Metal stiffening members may be attached to opposing ends of the strip of conductive tape to facilitate removal of the tape for rework or repair. An additional strip of tape may be used to help secure the wrapped conductive tape. The additional strip of tapc may have a tab to facilitate removal. | 2014-04-24 |
20140113464 | FLEXIBLE PACKAGE-TO-SOCKET INTERPOSER - A flexible interposer for the attachment of a microelectronic package to a microelectronic socket, wherein a first portion of the flexible substrate may be positioned between the microelectronic package and the microelectronic socket, and a second portion of the flexible interposer may extend from between the microelectronic package and the microelectronic socket to electrically contact an external component. In one embodiment, the external component may be a microelectronic substrate and the microelectronic socket may be attached to the microelectronic substrate. | 2014-04-24 |
20140113465 | ELECTRICAL CONNECTOR AND ELECTRICAL CONNECTOR COMBINATION - An electrical connector includes a plastic body, a first terminal and a second terminal. The first terminal includes a first connecting part, a first contact part and a first mating part extending from two ends of the first connecting part. The first contact part and the first mating part are located at two sides of the first connecting part respectively. An extending direction of the first contact part deviates from a straight line of an extending direction of the first mating part. The first terminal and the second terminal pass through through holes of the plastic body respectively. The first contact part and the first mating part of the first terminal respectively protrude out of the through hole that the first terminal passes through; a second contact part and a second mating part of the second terminal respectively protrude out of the through hole that the second terminal passes through. | 2014-04-24 |
20140113466 | EURO POWER PLUG - Power plugs that provide reliable functionality, may be reliably manufactured, and have a pleasant appearance. One example may provide a power plug that functions in a reliable manner by providing a ground connection that may maintain its shape over several insertions and removals from a wall socket. A relatively large ground block may act as a heat sink to help reduce plug temperature during operation. Another example may provide a power plug that may be reliably manufactured by forming the ground block as a solid piece to prevent buckling and bending during plug manufacturing that may otherwise result. Another example may provide a power plug that has an attractive appearance by employing a bridge having a flat surface such that after an overmold is formed over the bridge, a face of the plug has a resulting flat, smooth appearance. | 2014-04-24 |
20140113467 | CONNECTOR DOOR FOR AN ELECTRONIC DEVICE - An electronic device includes a housing, a system connector accessible at an external surface of the housing, and a hinged door to selectively expose or cover the system connector. The electronic device may also include a mechanism coupled to the hinged door that pivotally biases the door from an open position, in which the system connector can receive an external connector, to a partially closed position in which the hinged door at least partially covers said system connector. The hinged door is to slide along the housing if the hinged door is moved from the partially closed position to a fully closed position. | 2014-04-24 |
20140113468 | Electrical Cover Receptacle With Integrated Safety Device - An outlet cover safety device with an integrated safety device having an electrical with at least one aperture. The electrical cover mounting on an electrical outlet. The matching up with electrical gangs of the electrical outlet. The safety device having a at least one strap, with at least one prong disposed on the strap. The strap being biased to remain in an open position away from the plug accepting outlet when not in use. When wishing to engage the safety device, the strap is bent in a direction such that the prong is gets inserted into an aperture of a plug receiving outlet. The safety device may be incorporated with an outlet cover or may be a separate mechanism. | 2014-04-24 |
20140113469 | LEVER-TYPE CONNECTOR - A lever-type connector ( | 2014-04-24 |
20140113470 | LEVER CONNECTOR - A lever connector includes a first connector, a second connector and a lever. The lever includes a locking portion provided to be bendable inward and outward with respect to a rotation direction of the lever. The first connector is provided with a locked portion to be locked with the locking portion. The rotation of the lever causes the locking portion to be bent outward with respect to the rotation direction of the lever, and then causes the locking portion to be bent inward with respect to the rotation direction of the lever such that the locked portion is locked with the locking portion. The locking portion is provided with an abutment portion that abuts on an edge part of an attachment hole of a panel when the first connector and the second connector are attached to the attachment hole in the middle of the rotation of the lever. | 2014-04-24 |
20140113471 | LEVER-OPERATIVE CONNECTOR - A lever-operative connector which can be downsized includes a frame and a lever rotatably coupled to the frame. The frame has a circumferential wall having one opening and the other opening at both ends. The frame has a notch formed in the circumferential wall and communicating with the one opening. When the lever is rotated toward the one opening side, a part of a lever side wall is exposed from an interior of the circumferential wall so as to compensate the notch of the circumferential wall, thereby forming, together with the frame, a hood having the housing-receiving width. When the lever is rotated toward the other opening side, the part of the lever side wall is received inside the circumferential wall so as to open the notch of the circumferential wall, thereby eliminating the housing-receiving width and the hood. | 2014-04-24 |
20140113472 | BUSS BAR ASSEMBLY - A buss bar assembly for electrically interconnecting phase leads of first, second, and third phase coil winding assemblies arranged about a stator central axis. A substantially annular dielectric body defines a buss bar central axis, and has an inner face. Substantially annular first, second, and third phase bars at least partially disposed within the body have first, second, and third pluralities, respectively, of phase bar contacts angularly spaced from each other at locations about the buss bar central axis and electrically engagable from outside of the body. The buss bar assembly is adapted for installation such that the stator central axis is substantially surrounded by the body, the coil winding assemblies and inner face interface, and phase leads of the first, second, and third phase coil winding assemblies are electrically engaged with the first, second, and third pluralities of phase bar contacts, respectively. | 2014-04-24 |
20140113473 | FLOATING BUS BAR AND CONNECTOR WITHIN CHASSIS - A chassis includes floating bus bars providing power and a sliding tray included in the chassis includes a power terminal and connecting fingers contacting the floating bus bars. As the sliding tray moves in a direction of motion, the connecting fingers remain in contact with the floating bus bars, providing power to components included on the sliding tray while it is repositioned. The floating bus bars are mounted inside the chassis in a direction parallel to the sliding direction of the sliding tray, and may be positioned within the chassis in a location that does not significantly impede airflow within the chassis. | 2014-04-24 |
20140113474 | Connector, In Particular An Electrical Connector - A connector is provided having an outer housing, an inner housing and a seal. The seal includes a first sealing device that positioned between the outer housing and the inner housing such that a mating connector receiving gap is provided between an inner side of the outer housing and the first sealing device. | 2014-04-24 |
20140113475 | RETENTION KEY LOCK FOR BOARD-TO-BOARD CONNECTORS - Board-to-board connectors that consume a minimal amount of board area, are simple to assemble, and provide a clear indication that a proper connection has been made. One example may consume minimal area, since only a retention key and slots in boards and connectors are needed. The connector may be simple to assemble since it may be as simple as stacking components, pushing down, and turning a retention key. Further, a first and a first line on a key and a cowling may be aligned after assembly to provide a clear indication that the connector has been properly assembled. | 2014-04-24 |
20140113476 | LEVER-FITTING-TYPE CONNECTOR - A boss drawing-in groove of a lever includes: a lever inversion groove portion configured to cause the lever drawing-in boss to rotate the lever in an opposite direction opposite to a fitting rotation direction, in response to an insertion of a male connector into a hood with the lever being positioned at an initial rotation position; a drawing-in groove portion configured to guide the lever drawing-in boss by a rotating operation of the lever in the fitting rotation direction and cause the male connector to be fitted into a female connector; and a lever inertial rotation portion configured to rotate in the fitting rotation direction due to an inertial force of the lever after rotation of the lever in the opposite direction and cause the lever drawing-in boss to move to the drawing-in groove portion. | 2014-04-24 |
20140113477 | ASSEMBLY OF PLUG CONNECTOR AND CIRCUIT BOARD - The invention relates to an assembly of a plug connector and a circuit board ( | 2014-04-24 |
20140113478 | SPEAKER INTERCONNECT - An interconnect for an internal device, such as a speaker, coupling power from a flexible connector to the speaker at two or more terminals. The interconnect includes a flexible element, such as a “minus” terminal, and a second element, such as a “plus” terminal, which are coupled to corresponding terminals on the flexible connector. A screw can be threaded through a hole in the flexible element, the corresponding terminals, and can be terminated at the second element. The screw presses the “minus” terminal and the “plus” terminal into their corresponding terminals, making an electrical connection and a physical connection. | 2014-04-24 |
20140113479 | CONNECTOR OF ELECTRIC VEHICLE CHARGER - There is disclosed a connector of an electric vehicle charger, more particularly, to a connector of an electric vehicle charger which can be assembled and dissembled easily, with an easy maintenance, a simple structure and a less number of parts. | 2014-04-24 |
20140113480 | LEVER MECHANISM FOR CONNECTOR FITTING, AND CONNECTOR - A lever mechanism for connector fitting | 2014-04-24 |
20140113481 | ELECTRICAL CONNECTOR WITH IMPROVED MATING MEMBER HAVING ANTI-MISMATING PORTION FOR PREVENTING INCORRECT INSERTION - An electrical connector includes a first insulative housing defining a base member and a mating member extending forwardly from the base member in a mating direction, and a plurality of first contacts retained in the first housing. The mating member defines opposite first and second mating faces in a vertical direction perpendicular to said mating direction, and a receiving portion recessed towards the first mating face from the second mating face thereof. The receiving portion cooperates with a corresponding portion of a mating connector for preventing incorrect insertion of the electrical connector. | 2014-04-24 |
20140113482 | PINS FOR CONNECTOR ALIGNMENT - Connector receptacles that may help maintain registration or alignment between a printed circuit board, a connector receptacle, and an opening in a device enclosure. One example may provide a connector receptacle having a housing including a passage. A pin may be placed in the passage such that a first portion extends away from a front of the housing and a rear portion extends away from a rear of the housing. The front portion may be arranged to fit in a cavity or opening in an inside surface of a device enclosure, while the rear portion may be arranged to fit in a cavity or opening in a top surface of a printed circuit board. | 2014-04-24 |
20140113483 | DUAL CONDUCTOR CABLE CONNECTOR - A connector assembly for use with dual conductor cable is disclosed. The connector assembly includes a first connector, a second connector, first and second fixture wires, and first and second connector terminals. The first and second connectors are removably attachable. The first connector includes a first connector base, two prongs extending from the first connector base, and a first connector slot for accepting the first connector terminal. The second connector includes a second connector base, two wings extending from the second connector base, and a second connector slot for accepting the second connector terminal. The wings are sized and configured to accept the two prongs when the first and second connectors are joined. The first and second connector terminals include a spike extending generally away from the base of the connector into which the terminal has been secured. The first connector terminal is secured in the first connector in electrical communication with the first fixture wire, and the second connector terminal is secured in the second connector in electrical communication with second fixture wire. The first and second connectors, when joined by the insertion of the prongs between the wings, define a central portion sized to allow the passage of the dual conductor cable to which the first and second connectors are connected. When the first and second connectors are joined with the dual connector cable located in the central portion, the spikes of the first and second terminals penetrate into the dual conductor cable, whereby the dual conductor cable is placed into electrical communication with the first and second fixture wire. | 2014-04-24 |
20140113484 | Flexible Flat Cable Connector Fixing Structure - The present invention discloses a flexible flat cable connector fixing structure. The fixing structure includes a flexible flat cable, a first connector, and a hold-down strip. The first connector includes a plurality of contacts, a first slot and a first circuit board. The first slot includes a plurality of passageways, for placing the contacts, and a back-end seam. The first circuit board is fixed with a back of the first slot and includes a plurality of conducting portions, for being conductively fixed with the contacts, and a plurality of conducting parts, positioned on a front of the first circuit board, for being electrically connected to the flexible flat cable. The flexible flat cable is conductively fixed with the conducting parts, stretches through the seam, and further stretches through the hold-down strip to be positioned by the hold-down strip. | 2014-04-24 |
20140113485 | HDMI, VGA, Component, & Coax recessed receptacles - Low voltage TV input receptacles, that can be single or ganged together in numerous configuration, with a recessed device. It eliminates the need to locate a specific electrical box or plaster ring, because each piece is cut into, and clips onto the wallboard. The clips can be removed, for new construction, and the devices can be used with a electrical box or plaster ring. It easily accommodates future expansion. In addition, it allows flush mounting of television, and flush placement of furniture. | 2014-04-24 |