16th week of 2010 patent applcation highlights part 42 |
Patent application number | Title | Published |
20100097089 | Test Handler and Loading Method Thereof - When a test handler loads semiconductor devices of user trays onto a test tray, the test handler adjusts a front/rear pitch or a right/left pitch between the semiconductor devices, adjusts the right/left pitch or the front/rear pitch, and loads the semiconductor devices. The test handler can sequentially adjust individually the front/rear pitch and the right/left pitch between the semiconductor devices, thereby reducing the apparatus weight and the loading time. | 2010-04-22 |
20100097090 | PUSHER ASSEMBLIES FOR USE IN MICROFEATURE DEVICE TESTING, SYSTEMS WITH PUSHER ASSEMBLIES, AND METHODS FOR USING SUCH PUSHER ASSEMBLIES - Pusher assemblies for use in microelectronic device testing systems and methods for using such pusher assemblies are disclosed herein. One particular embodiment of such a pusher assembly comprises a plate having a first side and a second side opposite the first side. An engagement assembly is removably coupled to the second side of the plate and positioned to contact a microfeature device being tested. The pusher assembly can include an urging member proximate the first side of the plate and configured to move the engagement assembly toward the device being tested. The pusher assembly can also include a heat transfer unit carried by the first side of the plate. In several embodiments, the pusher assembly can further include a plurality of pins carried by the engagement assembly such that the pins extend through the plate and engage the urging member to restrict axial movement of the urging member toward the device being tested. | 2010-04-22 |
20100097091 | Methodology for Bias Temperature Instability Test - A method for performing a bias temperature instability test on a device includes performing a first stress on the device. After the first stress, a first measurement is performed to determine a first parameter of the device. After the first measurement, a second stress is performed on the device, wherein only the first parameter is measured between the first stress and the second stress. The method further includes performing a second measurement to determine a second parameter of the device after the second stress. The second parameter is different from the first parameter. | 2010-04-22 |
20100097092 | CLOSED LOOP FEEDBACK CONTROL OF INTEGRATED CIRCUITS - Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior. | 2010-04-22 |
20100097093 | INPUT/OUTPUT CIRCUITRY WITH COMPENSATION BLOCK - Circuitry including an output circuit having a first variable resistance block coupled between a first supply voltage and an output node, the first variable resistance block having a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the output node, the output circuit having an output impedance determined by the resistance of the first variable resistance block; and a compensation circuit for regulating the impedance of the first variable resistance block of the output circuit, the compensation circuit having a second variable resistance block coupled between the first supply voltage and the first node of an external resistor, the second node of the external resistor being coupled to a second supply voltage, wherein the second variable resistance block comprises a plurality of selectable resistive elements coupled in series with at least one resistor between the first supply voltage and the first node of the external resistor, and wherein the plurality of selectable resistive elements of the first and second variable resistance blocks are selected based on a voltage level at the first node of the external resistor. | 2010-04-22 |
20100097094 | Output circuit having variable output voltage swing level - An output circuit having a variable swing level of a terminated output data signal is disclosed. The output circuit includes a control circuit configured to generate a first control signal and a second control signal in response to a voltage swing level selection signal and an output enable signal. The output circuit further includes an output driving circuit configured to, in response to the first and second control signals, perform on-die termination in an input mode and configured to control swing level of a signal output from the output circuit in an output mode. | 2010-04-22 |
20100097095 | ON-DIE SYSTEM AND METHOD FOR CONTROLLING TERMINATION IMPEDANCE OF MEMORY DEVICE DATA BUS TERMINALS - A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a termination resistor connected to each data bus terminal, which is connected in parallel with several transistors that are selectively turned on to adjust the termination impedance. The transistors are controlled by a circuit that determines the resistance of the termination resistor and turns on the correct number of transistor to properly set the termination impedance. In one example, the resistance of the termination resistor is determined by directly measuring a resistor of the same type as the termination resistor. In another example, the resistance of the termination resistor is determined indirectly by measuring parameters that affect the resistance of the termination resistor. In either case, the system can maintain the termination impedance of the data bus terminals constant despite changes in the termination resistor. | 2010-04-22 |
20100097096 | Calibration circuit, semiconductor device including the same, and data processing system - A semiconductor device adjusting an impedance level of an output buffer, includes a replica buffer circuit including a circuit configuration substantially identical to the output buffer, a counter circuit changing an impedance code to vary an impedance level of the replica buffer, a latch circuit temporarily holding the impedance code in response to a control signal, and an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level. | 2010-04-22 |
20100097097 | SEMICONDUCTOR DEVICE USING POWER GATING - A semiconductor device using power gating includes a circuit unit and a current blocking unit. The circuit unit is connected between a first voltage node and a virtual voltage node. The current blocking unit is connected between the virtual voltage node and a second voltage node, and can block a leakage current of the circuit unit in a standby mode. Also, the current blocking unit controls whether or not to connect the virtual voltage node and the second voltage node in response to a plurality of random signals whose logic states are randomly transited when the standby mode is switched to an active mode. The semiconductor device can minimize ground bounce noise and can stably apply a voltage to a circuit storing data in a data retention mode. | 2010-04-22 |
20100097098 | CONFIGURABLE LOGIC DEVICE - The configurable logic device comprises a plurality of configurable logic cells ( | 2010-04-22 |
20100097099 | FPGA Having a Direct Routing Structure - A FPGA comprising, a direct interconnect structure for providing selective data routing without stressing the general-purpose routing resources and enabling high rate of data exchange within the FPGA. At least two IP cores are connected to each other through said direct interconnect structure for enabling simultaneous data interaction among the ports of said IP cores and for providing configurable bus width routing between said IP cores, and a plurality of logic blocks connected to said IP cores through said direct interconnect structure for enabling simultaneous data routing among said IP cores and said plurality of logic blocks. | 2010-04-22 |
20100097100 | INTEGRATED CIRCUITS - An integrated circuit comprises a processor, a controller and plural terminals. Each terminal constitutes a connection between the integrated circuit and a peripheral device. Each terminal is connected to a logic circuit on the integrated circuit by a respective IO cell in series connection with a respective IO isolation circuit and wherein the controller is operable on power up of the integrated circuit to activate a reset state and to release the reset state prior to releasing IO isolation by one or more of the IO isolation circuits. Each IO isolation circuit may be arranged so that a default state of the IO isolation circuit is a state in which the IO cell is isolated from the logic circuit. The IO isolation circuits may be controllable by software, for instance a driver for a peripheral device connected to the terminal associated with the IO isolation circuit. Plural IO isolation circuits may be connected so as to be commonly controllable by a single control signal from the controller. | 2010-04-22 |
20100097101 | DISTRIBUTED SUPPLY CURRENT SWITCH CIRCUITS FOR ENABLING INDIVIDUAL POWER DOMAINS - An integrated circuit includes multiple power domains. Supply current switch circuits (SCSCs) are distributed across each power domain. When a signal is present on a control node within a SCSC, the SCSC couples a local supply bus of the power domain to a global supply bus. An enable signal path extends through the SCSCs so that an enable signal can be propagated down a chain of SCSCs from control node to control node, thereby turning the SCSCs on one by one. When the domain is to be powered up, a control circuit asserts an enable signal that propagates down a first chain of SCSCs. After a programmable amount of time, the control circuit asserts a second enable signal that propagates down a second chain. By spreading the turning on of SCSCs over time, large currents that would otherwise be associated with coupling the local and global buses together are avoided. | 2010-04-22 |
20100097102 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a clock generator for generating a second clock signal having a frequency that varies over time by using a first clock signal having a fixed frequency, a test circuit for generating a digital signal according to a difference between a first frequency corresponding to the first clock signal and a second frequency corresponding to the second clock signal by a digital logic operation based on the first clock signal and the second clock signal, and a signal path for outputting the digital signal generated by the test circuit. | 2010-04-22 |
20100097103 | Receiving circuit, electronic apparatus and method for controlling receiving circuit - A receiving circuit includes a comparing circuit, a first storage circuit, a second storage circuit, and a voltage controlling circuit. The comparing circuit compares an input signal with a reference voltage and outputs a signal with either a first level when the input signal is larger than the reference voltage or a second level when the input signal is smaller than the reference voltage as a comparison result. The first storage circuit stores an output level of the comparing circuit for a next one cycle. The second storage circuit stores an output level of the first storage circuit for a next one cycle. The voltage controlling circuit controls a level of the reference voltage in each cycle on the basis of output levels of the first storage circuit and the second storage circuit. | 2010-04-22 |
20100097104 | CONTROL CIRCUIT HAVING OFF-TIME MODULATION TO OPERATE POWER CONVERTER AT QUASI-RESONANCE AND IN CONTINUOUS CURRENT MODE - A control circuit is developed to adaptively operate a power converter at quasi-resonance (QR) and in a continuous current mode (CCM) to achieve high efficiency. The control circuit includes a PWM circuit generating a switching signal coupled to switch a transformer. A signal generation circuit generates a ramp signal and a pulse signal. The pulse signal is generated in response to the ramp signal for switching on the switching signal. A feedback circuit produces a feedback signal according to an output load of the power converter. The feedback signal is coupled to switch off the switching signal. A detection circuit is coupled to the transformer for generating a valley signal in response to the waveform of the transformer. The valley signal is further coupled to generate the pulse signal when the ramp signal is lower than a threshold. The level of the threshold is correlated to the feedback signal. | 2010-04-22 |
20100097105 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device includes a semiconductor layer stack | 2010-04-22 |
20100097106 | Novel double-feedback flexible non-integer frequency division circuit - An embodiment of this invention combines feed-forward and feedback frequency division circuits in a such a way, to provide greater flexibility in choosing the non-integer division ratios at the output, with little added complexity. Alternate embodiments include additional divider(s) in signal or feedback paths providing additional flexibility and design simplification. An embodiment uses in-phase/quadrature signals to select the desired modes at feedback-path and signal-path mixers. Various alternatives are also described. | 2010-04-22 |
20100097107 | TWO-PHASE CLOCK-STALLING TECHNIQUE FOR ERROR DETECTION AND ERROR CORRECTION - One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a set of blocks that are clocked by an independent clock source, and integrates an error signal propagation circuit between the set of blocks. For a respective block, the system determines a set of internal registers that are to be implemented as double data sampling registers, and replaces the determined set of internal registers with double data sampling registers, wherein a given double data sampling register is configured to generate an error signal when it detects a timing error. Then, the system integrates a two-phase error correction circuit into the respective block, wherein when notified of a timing error by a double data sampling register, the two-phase error correction circuit is configured to stall registers in the respective block. | 2010-04-22 |
20100097108 | SEMICONDUCTOR DEVICE - A semiconductor device having a nonvolatile variable resistor, includes: a resistance value conversion circuit unit configured to convert a resistance value of the nonvolatile variable resistor into a potential or a current and which outputs the converted potential or current; a comparison circuit unit configured to compare the output from the resistance value conversion circuit unit and a potential or current at a node of a portion within the semiconductor device; and a resistance value changing circuit unit configured to change the resistance value of the nonvolatile variable resistor based on the comparison results from the comparison circuit unit. | 2010-04-22 |
20100097109 | RESET CIRCUIT AND SYSTEM HAVING RESET CIRCUIT - In a power-on detection circuit, a first connection node at which a first divided voltage is generated is connected to a second power supply line during activation of a power-down detection signal. Inactivation timing of the power-down detection signal is set earlier than an activation timing of a power-on detection signal. Therefore, the first transistor whose gate is connected to the first connection node is certainly turned off in the first half of a power-on period, which prevents the power-on detection signal from being activated during the power-on period. Further, a leak current flowing through the first transistor is reduced. In the second half of the power-on period, the power-on detection signal is certainly generated using the first divided voltage generated by the first dividing circuit. Thus, operating a reset circuit without malfunction and normally outputting a reset signal is possible disregarding behavior of a power supply voltage at power-on. | 2010-04-22 |
20100097110 | WIRELESS COMMUNICATION UNIT, INTEGRATED CIRCUIT COMPRISING A VOLTAGE CONTROLLED OSCILLATOR AND METHOD OF OPERATION THEREFOR - A wireless communication unit comprises a frequency generation circuit employing a phase locked loop (PLL) circuit comprising a voltage controlled oscillator having a modulation port for directly modulating a signal output from the voltage controlled oscillator. The voltage controlled oscillator is operably coupled to at least one switch and a capacitor bank comprising one or more varactors. A controller is arranged to switch in one or more varactors associated with the modulation port of the phase locked loop circuit to provide an inverse cubic relationship to the direct modulated signal. | 2010-04-22 |
20100097111 | Semiconductor device including delay locked loop having periodically activated replica path - A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal. | 2010-04-22 |
20100097112 | DUTY CYCLE CORRECTION CIRCUITS HAVING SHORT LOCKING TIMES THAT ARE RELATIVELY INSENSITIVE TO TEMPERATURE CHANGES - A duty cycle correction circuit includes a duty cycle correction portion that is configured to output a correction signal that is obtained by correcting a duty cycle of an input signal and to output a delayed signal that is obtained by delaying the correction signal, a complementary portion that is configured to output a complementary signal that is the complement of the delayed signal, and a phase interpolator that is configured to phase interpolate the complementary signal and the correction signal. | 2010-04-22 |
20100097113 | PULSE GENERATING CIRCUIT AND PULSE WIDTH MODULATOR - A pulse generating unit receives a clock at a predetermined frequency, and generates a pulse signal which transits synchronously with the positive edge of the clock. A flip-flop acquires the pulse signal every time a positive edge occurs in an inverted clock output from the inverter. A logic gate multiplexes the pulse signal and the output of the flip-flop. A selector selects either the output of the logic gate or the pulse signal. | 2010-04-22 |
20100097114 | PULSE WIDTH MODULATION CIRCUIT AND LIQUID JET PRINTING APPARATUS - A pulse width modulation circuit includes: a reference signal generator which generates a plurality of mutually differing reference signals; a comparator which compares the reference signals and an input signal with respect to magnitude, and outputs results of the comparison as a plurality of comparison signals with mutually differing phases; and a synthesizer which, using a logical operation, outputs the plurality of comparison signals output from the comparator as a pulse width modulated signal configured of one or more binary signals. | 2010-04-22 |
20100097115 | DEVICE AND SYSTEM FOR REDUCING NOISE INDUCED ERRORS - A method and a device for reducing noise induced errors. The device includes: a latch that includes a latch input node; a voltage limiting transfer circuit connected between a first input node and between the latch; wherein the voltage limiting transfer circuit is adapted to selectively transfer an input signal from the first input node to the latch during transfer mode; and to prevent a transfer of an input signal from the first input node to the latch by limiting voltage levels developed in the voltage limiting transfer circuit to a predefined range. | 2010-04-22 |
20100097116 | HIGH SIDE DRIVER WITH SHORT TO GROUND PROTECTION - A protection circuit for a high side driver includes an exclusive-OR gate adapted to receive a first input and a second input, analyze each of the inputs and transmit an output in response to the analysis of the inputs, wherein the first input represents an electric power output of the high side driver and the second input represents a control signal for operating the high side driver, and a switching device adapted to control an electrical output of the high side driver in response to the output of the exclusive-OR gate. | 2010-04-22 |
20100097117 | Mixed-voltage I/O buffer - A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current. | 2010-04-22 |
20100097118 | Activating an Information Handling System Battery From a Ship Mode - In some embodiments, a method for activating an information handling system battery without using AC power is provided. One or more switches associated with a battery are maintained in a ship mode state during shipping of the information handling system such that the battery remains disconnected from particular information handling system components during shipping. In response to a user input, a power-on device generates and communicates a power-on signal to a battery management unit (BMU) of the battery. In response to receiving the power-on signal, the BMU activates the one or more switches from the ship mode state, which connects the battery to the particular information handling system components. The power-on device generates and communicates the power-on signal to the BMU, and the BMU activates the one or more switches from the ship mode state, while the information handling system is not connected to any AC power source. | 2010-04-22 |
20100097119 | GALLIUM NITRIDE SWITCH METHODOLOGY - Devices and systems for using a Gallium Nitride-based (GaN-based) transistor for selectively switching signals are provided. A first transmission line is configured to connect a common connection and a first connection. A first Gallium-Nitride-based (GaN-based) transistor has a first terminal coupled to the first transmission line at a first point, a second terminal coupled to a relative ground, and a third terminal configured to be coupled to a first control connection. A second GaN-based transistor has a first terminal coupled to the first transmission line at a second point, a second terminal configured to be coupled to the relative ground, and a third terminal configured to be coupled to the first control connection. | 2010-04-22 |
20100097120 | Electronic Switching Device for High-Frequency Signals - The invention relates to an electronic switching device for high-frequency signals. The invention is of particular use in the connection between a microwave frequency antenna and an electronic circuit. This circuit comprises one or two access points designed to be connected to the antenna forming a third access point. In the case of a switch between one access point and the antenna (called an SPST switch), it comprises two switching diodes, one, called a serial diode, being connected in series between the access points and the other, called a shunt diode, between one of the access points and an earth of the device. According to the invention, a first transmission line is placed in series with the shunt diode, a second transmission line is placed in series with the serial diode, a third transmission line is placed at the common point of the first transmission line and of the shunt diode, a fourth transmission line is placed at the first access point, and a fifth transmission line is placed at the second access point. For a switch with three access points, two other diodes and four other transmission lines are added in a symmetrical manner relative to those already described. It is possible to obtain adapted lines having lengths much shorter than λ/4, which makes it possible to improve the compactness of the device while increasing its bandwidth. | 2010-04-22 |
20100097121 | METHOD AND ARRANGEMENT FOR CONTROLLING SEMICONDUCTOR COMPONENT - A method is disclosed for controlling a semiconductor component which includes a voltage controlled gate. The method includes determining and storing, prior to use of the semiconductor component, reference values of a gate voltage to be given to the gate of the semiconductor component during a change of operating states. The method also includes providing a pulse width modulated voltage from a driver circuit to a resistor connected to the gate of the semiconductor component according to the stored reference values of the gate voltage when a change in operating states of the semiconductor component is desired. | 2010-04-22 |
20100097122 | Photosensor Circuits Including a Switch Mode Power Converter - Photosensor circuits include a relay coil configured to control application of an alternating current (AC) power source to a load. The circuit includes a pulse width modulator circuit configured to generate a pulse width modulated signal having a pulse width that varies responsive to an average voltage across the relay coil. A drive transistor is coupled between the relay coil and a neutral bus that controls the average voltage across the relay coil responsive to the pulse width modulated signal. A photo control circuit is configured to control application of the pulse width modulated signal to the drive transistor responsive to a detected light level. A power circuit includes a half-wave rectifier coupled to the power source that is configured to provide a power signal to the pulse width modulator circuit and a regulated power signal to the photo control circuit. The power signal is a square wave and the power circuit further includes a rectifier circuit and a voltage divider circuit configured to generate the regulated power signal from the power signal. The photo control circuit includes a phototransistor. The phototransistor has a first terminal coupled to the regulated power signal through a first resistor and a second terminal that outputs a current responsive to a level of light detected by the phototransistor. A low pass filter circuit is coupled to the first terminal of the phototransistor that filters the output current of the phototransistor to provide a light level signal voltage and a select transistor couples the pulse width modulated signal to the drive transistor responsive to the light level signal voltage having a selected level. | 2010-04-22 |
20100097123 | Keep-alive for power stage with multiple switch nodes - A keep alive circuit for recharging bootstrap capacitors in multiple totem-pole switching power stages using N-channel field effect transistor or NPN bipolar junction transistor switching devices during 100% or substantially 100% duty cycle operation of one of the totem pole pairs. | 2010-04-22 |
20100097124 | Method of operating semiconductor device - Provided is a method of operating a semiconductor device, wherein an operating mode is set by adjusting timing of a voltage pulse or by adjusting a voltage level of the voltage pulse. | 2010-04-22 |
20100097125 | HVNMOS/HVPMOS switched capacitor charge pump having ideal charge transfer - An integrated circuit for a charge pump with a charge stage and a pump stage and a single High-Voltage PMOS (HVPMOS) transistor as the main switch for each stage and two times two minimum HVPMOS transistors in series as a bulk switch with fixed bulk connections, where the minimum HVPMOS transistors are smaller sized transistors than the transistors of the main switch. The bulk of the main switch is switched synchronously to the voltage node of the HVPMOS transistor of the main switch to force the bulk voltage (V | 2010-04-22 |
20100097126 | CHARGE PUMPING CIRCUIT AND CLOCK GENERATOR - A charge pumping circuit comprises: a charging pump capacitance; a charging unit; a discharging unit; a detection resistor having one terminal and the other terminal, the one terminal being connected between a first node and a second node in a second mode; a voltage source for supplying a reference voltage to the other terminal of the detection resistor; a correction unit for correcting a charging current output from the charging unit and a discharging current that is to be sunk by the discharging unit to equalize the charging current and the discharging current in the second mode, based on a difference between a voltage of the one terminal of the detection resistor and the reference voltage when the charging unit outputs the charging current to the one terminal of the detection resistor and the discharging unit sinks the discharging current from the one terminal of the detection resistor. | 2010-04-22 |
20100097127 | BOOSTER CIRCUIT AND VOLTAGE SUPPLY CIRCUIT - A voltage supply circuit includes a booster circuit and a ripple filter circuit. The ripple filter circuit has a first resistor connected to a first output terminal at one end thereof. The ripple filter circuit also has a first switch circuit connected between the other end of the first resistor and a second output terminal. In addition, the ripple filter circuit has a second switch circuit connected between the first output terminal of the booster circuit and the first switch circuit. | 2010-04-22 |
20100097128 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit ( | 2010-04-22 |
20100097129 | CMOS Circuit and Semiconductor Device - There is provided an output stage circuit including such MOSTs (M) that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, wherein upon its deactivation, a voltage is applied to the gate of each of the MOSTs (M) in such a manner than a reverse bias is applied between the gate and source of the MOST (M). That is, when the MOST (M) is of a p channel type, a voltage higher than that of a p type source is applied to its gate. When the MOST (M) is of an n channel type, a voltage lower than that of an n type source is applied to its gate. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage. A CMOS circuit and a semiconductor device can be realized each of which is small in leakage current even though its threshold voltage is low and which is operated at high speed and with a small voltage amplitude. | 2010-04-22 |
20100097130 | DEVICE HAVING CIRCUIT CAPABLE OF INTERMITTENT OPERATION - A circuit unit is provided. The circuit unit has an intermittent operation circuit. The intermittent operation circuit is set in an operation state and in a stand-by state periodically. An operation mode control unit generates a test mode control signal to designate either an operation test mode or an intermittent operation test mode of the intermittent operation circuit. The operation test mode corresponds to one of a continuous operation or a predetermined time period operation of the intermittent operation circuit. An operation timing generation unit receives the test mode control signal. The operation timing generation unit produces an operation control signal based on the test mode control signal. The operation control signal is outputted to the intermittent operation circuit to operate or wait the intermittent operation circuit. | 2010-04-22 |
20100097131 | HARDENING OF SELF-TIMED CIRCUITS AGAINST GLITCHES - Multiple techniques are disclosed for hardening a self-clocking circuit against glitches. Glitch filters are placed in some portions of a digital design. In some embodiments the glitch filter is dynamically tunable. In one embodiment the inputs are locked out by the outputs. Methods for evaluating code symbols are presented, as is a circuit for differential signaling. | 2010-04-22 |
20100097132 | Systems and Methods for Filtering Signals Corresponding to Sensed Parameters - Systems and methods for filtering analog signals corresponding to sensed parameters are provided. In this regard, a representative method includes: sampling the analog signal to acquire a sequential series of data points; determining a first cumulative change in value with respect to a first of the data points relative to at least two subsequent data points in the series, the subsequent data points including a second of the data points; determining a second cumulative change in value with respect to the second of the data points relative to at least two data points adjacent to the second of the data points in the series, the at least two adjacent data points including an immediately preceding and an immediately succeeding one of the data points relative to the second of the data points; comparing the first cumulative change and the second cumulative change to respective data thresholds; and outputting a filtered analog signal based, at least in part, on results of the comparing. | 2010-04-22 |
20100097133 | Signal Processing - An iterative method for generating a series of output signal values from a series of input signal values is described. Iterations of the method comprise the steps of obtaining a current input signal value for the current iteration, comparing the current input signal value with an output signal value determined in a previous iteration, updating a counter value determined in the previous iteration based on the result of the comparison between the current input signal value and the previous output signal value such that the updated counter value replaces the counter value determined in the previous iteration, determining a slew value based on the counter value; and adding the slew value to the previously determined output signal value to generate a new current output signal value. Thus different slew values may be added to the previous output signal to obtain a new output signal. The counter value is updated so that its value reflects recent trends in the input signals. E.g. if the input signal is on an upward trend, the counter value may achieve a relative high value, for example because it is incremented each time an input signal exceeds a previously determined output signal. The magnitude of the slew values may increase as the counter value increases, thereby allowing the output signals to more rapidly track changes in the input signals. | 2010-04-22 |
20100097134 | APPARATUS FOR GENERATING A CORRECTION SIGNAL - An apparatus for generating a correction signal for linearizing an output signal of a non-linear element includes a correction signal generator. The correction signal generator is configured to generate a correction signal on the basis of a superposition of a digital reference signal and a superposed output signal. The superposed output signal is based on a superposition of the output signal and an analog reference signal. | 2010-04-22 |
20100097135 | TUNNEL FIELD EFFECT TRANSISTOR - A tunnel transistor includes source diffusion ( | 2010-04-22 |
20100097136 | A/D CONVERTER AND A/D CONVERSION METHOD - In an A/D converter provided with an A/D converter circuit | 2010-04-22 |
20100097137 | LOOKUP TABLE GENERATION METHOD AND RELATED DEVICE FOR A PREDISTORTER - A lookup table generation method for a predistorter comprises sending a first single tone signal with a maximum expected amplitude to a channel simulation device including the power amplifier, estimating a closed loop gain and a closed loop phase of the power amplifier according to the first single tone signal and a first simulation output signal generated outputted by the channel simulation device, sending a plurality of single tone signals to the channel simulation device, each single tone signal having an amplitude different from all others of the plurality of single tone signals and lower than the maximum expected amplitude, generating a plurality of predistortion parameters according to the closed loop gain, the closed loop phase, the plurality of single tone signals and a plurality of simulation output signals outputted by the channel simulation device, and storing the plurality of predistortion parameters in a lookup table of the predistorter. | 2010-04-22 |
20100097138 | RF Power Transmission, Modulation, and Amplification Embodiments - Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion. | 2010-04-22 |
20100097139 | ERROR CORRECTION SYSTEM FOR A CLASS-D POWER STAGE - The present invention relates to a method for correcting for a source of non-linearity and noise introduced in a switching power amplification stage during power amplification of a pulse-modulated reference signal from a pulse modulator, where the method comprises the following steps: —providing an output stage embedded in an analogue self-oscillating control loop able to receive a pulse-referenced input signal; —generating a feedback signal from the switching power amplification stage or after a demodulation filter; —deriving an error signal by comparing the feedback signal with the reference signal; —filtering the error signal by a low pass filter for reducing the higher harmonics of the carrier; —adding a compensator for generating high loop gain in the audio band; —feeding the compensator output to a zero cross detector or comparator, thus providing a carrier for re-modulation or re-timing by feeding the filtered signal to a zero cross detector or comparator, which controls the output stage. The invention furthermore relates to various systems for implementing the above method. | 2010-04-22 |
20100097140 | AMPLIFICATION APPARATUS - An amplification apparatus comprising first amplification circuitry having first shunt-peak circuitry and second amplification circuitry having second shunt-peak circuitry, wherein the amplification apparatus is arranged to provide an operational bandwidth over which the first and second amplification circuitry amplify signals, and wherein the second shunt-peak circuitry is arranged to use at least part of the first shunt-peak circuitry. | 2010-04-22 |
20100097141 | Current Mirror With Low Headroom And Linear Response - A current mirror circuit provided in an emitter follower configuration achieves linear output currents over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node. | 2010-04-22 |
20100097142 | DRIVING CIRCUIT SYSTEM AND METHOD OF ELEVATING SLEW RATE OF OPERATIONAL AMPLIFIER - The invention discloses a driving circuit system and a method of elevating a slew rate of an operational amplifier. The driving circuit system comprises an operational amplifier, a judging module and a bias enhancing module. The operational amplifier has an input stage driven by a bias current. The bias enhancing module is electrically connected to the judging module and the input stage of the operational amplifier respectively. The judging module is used to generate a bias enhancing signal according to an edge-trigger of a control signal. When the bias enhancing module receives the bias enhancing signal, the bias enhancing module provides an additional current, which cooperates with the bias current, for driving the input stage of the operational amplifier, so as to elevating a slew rate of the operational amplifier. | 2010-04-22 |
20100097143 | RF DETECTOR WITH CREST FACTOR MEASUREMENT - An RF detector configured to provide two outputs, one being a function of the true RMS power level of an RF input signal, and the other being a function of the instantaneous/peak power of the RF input signal, normalized to the average power level. The RF detector includes a variable gain detection subsystem including a single detector or detector array that provides a representation of the power level of the RF input signal. The detector or detector array is common to both the RMS power detection channel and the instantaneous/peak power detection channel of the RF detector. A method of RF detection includes providing representations of the RF input signal at different gain levels, selecting one or more of the representations, and averaging the selected signals. The gain levels of the selected representations is adjusted to provide information about the average power level of the RF input signal. | 2010-04-22 |
20100097144 | METHOD AND SYSTEM FOR POLAR MODULATING OFDM SIGNALS WITH DISCONTINUOUS PHASE - Aspects of a method and system for polar modulating OFDM signals with discontinuous phase may include amplifying a normalized OFDM signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain and an amplitude offset gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain, and a gain of one or more remaining ones of the plurality of amplifiers may be adjusted to set the amplitude offset gain adaptively and/or dynamically. The setting of the coarse amplitude gain and/or the amplitude offset gain may be adjusted dynamically and/or adaptively via an amplitude control. | 2010-04-22 |
20100097145 | FEEDBACK CONTROLLED POWER LIMITING FOR SIGNAL AMPLIFIERS - An apparatus is provided. The apparatus includes an amplifier, differential amplifiers, and FETs. The amplifier has an intermediate node and an output node, and the amplifier is adapted to receive an audio signal. Each differential amplifier amplifies the difference between an output voltage from the output node with a reference voltages. The FETs are coupled in series with one another between a first and a second voltage, and each FET receives an output from at least one of the differential amplifiers. Additionally, the intermediate node is coupled to a node between at least two FETs. | 2010-04-22 |
20100097146 | Signal amplification circuit - This invention provides a low-current consumption type signal amplification circuit, which limits the output voltage to fix a lower-limit (upper-limit) saturation voltage of the amplification circuit at a predetermined lower-limit (upper-limit) limiting voltage. The signal amplification circuit comprises a negative feedback amplification circuit, a lower-limit voltage limiting circuit and an upper-limit voltage limiting circuit. The lower-limit voltage limiting circuit increases a resistance between an output terminal of the negative feedback amplification circuit and a ground terminal when the output voltage of the negative feedback amplification circuit falls below the lower-limit limiting voltage. The upper-limit voltage limiting circuit increases a resistance between the output terminal of the negative feedback amplification circuit and a high-potential side of a power supply when the output voltage of the negative feedback amplification circuit rises above the upper-limit limiting voltage. | 2010-04-22 |
20100097147 | GATE BIAS CIRCUIT - Multiple unit transistors each having the same gate length are arranged in a gate-lengthwise direction to form a group of unit transistors. At least one unit transistor included in the group of unit transistors is used as a part of a gate bias circuit and acts as unit transistor ( | 2010-04-22 |
20100097148 | Headphone Amplifier Circuit - A class G headphone amplifier circuit with improved power efficiency and low EMI. It may use an automatic signal level detector to detect the signal level of incoming signals and determine positive and negative power supplies for headphone amplifiers accordingly. A voltage generator may generate pairs of differential output voltages at a plurality of amplitude steps, and supply to headphone amplifiers the pair with the amplitude determined by the automatic signal level detector. As a result, headphone amplifiers are biased according to the input signal level, and the multiple voltage rails may improve power efficiency and avoid clipping. | 2010-04-22 |
20100097149 | Methods, Algorithms, Circuits, and Systems for Determining a Reference Clock Frequency and/or Locking a Loop Oscillator - Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count, where the sleep clock has a known frequency and a predetermined accuracy; a frequency estimator configured to estimate the reference clock frequency from the reference clock cycle count and the known frequency of the sleep clock; and a frequency selector configured to select a closest frequency to the estimated reference clock frequency from a plurality of allowed frequencies. | 2010-04-22 |
20100097150 | PLL CIRCUIT - A technique for suppressing quantization noise generated due to digitizing an analog circuit in a PLL circuit is provided. The PLL circuit comprises: a digital phase frequency detector which detects (compares) phases and frequencies of a reference signal and a frequency-divided signal and converts the same to a digital value; a digital loop filter which eliminates high-frequency noise components from an output of the digital phase frequency comparator; a digital-analog converter which converts a digital value of an output of the digital loop filter to an analog value; an analog filter which eliminates a high-frequency noise component from an output of the digital-analog converter; a voltage controlled oscillator whose frequency is controlled based on an output of the analog filter; and a frequency divider which divides the frequency of the voltage controlled oscillator and outputs the frequency-divided signal. | 2010-04-22 |
20100097151 | PHASE NOISE CORRECTION DEVICE AND ITS METHOD - A phase noise correction device having a function for accurately detecting a phase noise component and capable of reducing a load on a reception device is provided. A phase noise correction device for correcting a phase noise generated in a local oscillator includes: a division section that divides a signal generated in the local oscillator; a reference signal generation section that generates a signal of the same frequency as that of the divided signal; a phase difference detection section that detects a phase difference between the divided signal and the generated reference signal; and a phase noise correction section that gives a phase rotation to a baseband signal in the direction that cancels the phase noise according to the detected phase difference as a phase noise component. | 2010-04-22 |
20100097152 | TUNABLE FILTER WITH GAIN CONTROL CIRCUIT - An apparatus includes a filter and a gain control circuit. The filter receives and filters an input signal and provides an output signal in a first mode and operates as part of an oscillator in a second mode. The gain control circuit varies the amplitude of an oscillator signal from the oscillator in the second mode, e.g., by adjusting at least one variable gain element within the oscillator to obtain a target amplitude and/or non rail-to-rail signal swing for the oscillator signal. The apparatus may further include a bandwidth control circuit to adjust the bandwidth of the filter in the second mode. The bandwidth control circuit receives the oscillator signal, determines a target oscillation frequency corresponding to a selected bandwidth for the filter, and adjusts at least one circuit element within the filter to obtain the target oscillation frequency. | 2010-04-22 |
20100097153 | Switched Modulation of a Radio-Frequency Amplifier - Switch-modulation of a radio-frequency power amplifier by-representing the input signal by the I-signal ( | 2010-04-22 |
20100097154 | Broadband Active Balun - A broadband active balun configuration is provided. According to embodiments, the subject active balun can include a cascade and cascade transistor pair using a shared input transistor. In a further implementation, a low-pass bias-feedback mechanism for maintaining stable bias conditions can be provided. | 2010-04-22 |
20100097155 | Stripline Balun - According to one embodiment, a balun includes one or more transformers configured to block DC power between a line and a device at microwave frequencies. The one or more transformers block DC power between the line and the device by electromagnetically coupling the device to the line. | 2010-04-22 |
20100097156 | Semiconductor device and manufacturing the same - A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film. | 2010-04-22 |
20100097157 | SEMICONDUCTOR DEVICE AND MANUFACTURING THE SAME - A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film. | 2010-04-22 |
20100097158 | Radio Frequency Coaxial Transition - A coaxial transition includes a first conductor aligned along a first axis. The transition also includes a ground shield surrounding the first conductor such that a first gap exists between the first conductor and the ground shield. An electric field radiates between the first conductor and the ground shield through the first gap. The transition further includes a second conductor aligned along a second axis and coupled to the first conductor. The second conductor forms a second gap between the second conductor and a portion of the ground shield. A first portion of the electric field radiates between the second conductor and the ground shield through the second gap. The transition also includes a top ground plane aligned substantially parallel to the second conductor. A third gap exists between the top ground plane and the second conductor. The second gap and the third gap are substantially parallel with the second conductor therebetween. | 2010-04-22 |
20100097159 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - There are provided a semiconductor device and a semiconductor chip, in which the interconnection is made to be highly reliable by stacking three or more layers of chips without contact therebetween. A semiconductor chip of the present invention comprises a first signal transmission circuit, a silicon substrate on which a first changeover switch is formed, and an interconnection layer on which a first capacitive-coupling upper electrode is formed, wherein a first capacitive-coupling lower electrode is additionally formed on the rear surface of the silicon substrate through a first via hole that penetrates the silicon substrate and, whereas the first capacitive-coupling upper electrode is directly connected to the first signal transmission circuit, the first capacitive-coupling lower electrode is connected to the first signal transmission circuit through the first via hole and through the first changeover switch. | 2010-04-22 |
20100097160 | DIRECTIONAL COUPLER - A directional coupler capable of improving a directionality of a directional coupler body including four terminals. The directional coupler includes a directional coupler body including the four terminals of an input port, an output port, a coupling port, and an isolation port; and a combiner for combining powers of an output signal of the coupling port and an output signal of the isolation port of the directional coupler body; and a directionality improving circuit for amplifying or attenuating at least one of the output signal of the coupling port and the output signal of the isolation port before outputting the same, and the combiner combines powers of the output signals amplified or attenuated by the directionality improving circuit. | 2010-04-22 |
20100097161 | SURFACE ACOUSTIC WAVE FILTER, ANTENNA DUPLEXER AND METHOD FOR MANUFACTURING THEM - A surface acoustic wave filter comprised of a plurality of surface acoustic wave resonators having different resonance frequencies, the filter comprising a substrate made of a lithium niobate, comb electrodes ( | 2010-04-22 |
20100097162 | APPARATUS FOR COUPLING COMBLINE AND CERAMIC RESONATORS - An apparatus for coupling a combline resonator and a ceramic resonator, including one or more of the following: a housing; a combline resonator in the housing; a ceramic resonator in the housing, the ceramic resonator having a stem portion and a mushroom portion; a ridge extending between the combline resonator and the ceramic resonator, the ridge passing between the mushroom portion of the ceramic resonator and the housing, wherein a coupling is obtained between an electrical field of the combline resonator and an electrical field of the ceramic resonator. | 2010-04-22 |
20100097163 | RESONATOR HAVING A THREE DIMENSIONAL DEFECTED GROUND STRUCTURE IN TRANSMISSION LINE - A resonator having a three dimensional Defected Ground Structure (DGS) in the transmission line includes a substrate installed at the center of the resonator floating in the air through supporting members installed on both ends of the substrate; a transmission line for transmitting signals installed on the upper surface of the substrate; an upper ground plane member installed on the upper surface of the substrate with predetermined interval from the surface of the substrate, wherein a DGS pattern with a predetermined shape is formed on each portion of the body of the ground plane member symmetrically with respect to the transmission line to form a resonator; a lower ground plane member installed on the lower surface of the substrate with predetermined interval from the surface of the substrate, wherein a DGS pattern with a predetermined shape is formed on each portion of the body of the ground plane member symmetrically with respect to the transmission line to form a resonator; an upper cover installed closely contacting the upper surface of the upper ground plane member to seal the upper opening of the DGS pattern formed on the upper ground plane member and to protect the upper ground plane member at the same time; and a lower cover installed closely contacting the lower surface of the lower ground plane member to seal the lower opening of the DGS pattern formed on the lower ground plane member and to protect the lower ground plane member at the same time. | 2010-04-22 |
20100097164 | TUNED CIRCUIT AND DOUBLE TUNED CIRCUIT - A double tuned circuit includes: a primary tuning circuit connected to an input terminal; and a secondary tuning circuit connected to an output terminal. The primary tuning circuit has a primary capacitor connected between the input terminal and a ground and a primary inductor connected between the input terminal and the ground and formed of a first coupling line having a spiral shape. The secondary tuning circuit has a secondary capacitor connected between the output terminal and the ground and a secondary inductor connected between the output terminal and the ground and formed of a second coupling line having the same spiral shape as the first coupling line, arranged alternately with the first coupling line, and having an M-coupling with the first coupling line. A length of the first coupling line in the range from a connection point between the first coupling line and the input terminal to a ground point and a length of the second coupling line in the range from a connection point between the second coupling line and the output terminal to the ground point can be changed by a tuning frequency, and the lengths of those are substantially equal to each other. | 2010-04-22 |
20100097165 | Solenoid Assembly with Shock Absorbing Feature - A solenoid assembly includes a solenoid having a coil provided with a passageway and a plunger movable within the passageway upon application of electrical power to the coil. A frame holds the solenoid and includes a backstop movably mounted in the frame extending into the coil passageway. The backstop is selectively engaged by the plunger such that the backstop and the plunger are subjected to an impact therebetween. A resilient dampening element is positioned between the frame and the backstop for cushioning the impact between the backstop and the plunger. | 2010-04-22 |
20100097166 | Solenoid and actuating element with solenoid - The invention refers to a solenoid with a coil which can be current-fed, the resulting magnetic field moving an armature. The armature acts, if necessary, on an actuator. Furthermore, the solenoid has at least one pyrotechnic actuation for the armature or the actuator. | 2010-04-22 |
20100097167 | VEGETABLE OIL BASED DIELECTRIC COOLANT - In one aspect, the present invention provides a dielectric fluid for use in electrical equipment comprising a vegetable oil or vegetable oil blend. In another aspect the invention provides devices for generating and distributing electrical energy that incorporate a dielectric fluid comprising a vegetable oil or vegetable oil blend. Methods of retrofilling electrical equipment with vegetable oil based dielectric fluids also are provided. | 2010-04-22 |
20100097168 | CLADDING ELEMENT WITH AN INTEGRATED RECEPTION UNIT FOR THE CONTACTLESS TRANSFER OF ELECTRICAL ENERGY AND METHOD FOR THE PRODUCTION THEREOF - A cladding (cover) element ( | 2010-04-22 |
20100097169 | MULTIPHASE INDUCTOR AND FILTER ASSEMBLIES USING BUNDLED BUS BARS WITH MAGNETIC CORE MATERIAL RINGS - A multiphase inductor assembly includes an elongate conductor assembly including a plurality of bus bars that are arranged in parallel. A plurality of magnetic core material rings (e.g., ferrite or mu metal rings) surround the conductor assembly and are distributed along a length thereof. Terminals are electrically coupled to the bus bars and disposed between spaced apart ones of the magnetic core material rings. | 2010-04-22 |
20100097170 | LINEAR MOTOR COIL - A linear motor coil includes a first coil portion, a second coil portion, the first coil portion and the second coil portion being arranged across a partition wall, a first connecting portion provided between the first coil portion and the second coil portion and by means of which the conductive wire crosses to the first coil portion from the second coil portion while a winding direction of the conductive wire is reversed, and a second connecting portion by means of which the conductive wire crosses to the second coil portion from the first coil portion while the winding direction of the conductive wire is reversed. The conductive wire is formed by a single wire and of which a winding start point and a winding end point are provided at an end portion of the first coil portion at a side opposite from a side where the partition wall is provided. | 2010-04-22 |
20100097171 | SOFT MAGNETIC ALLOY, MAGNETIC COMPONENT USING THE SAME, AND THIER PRODUCTION METHODS - A soft magnetic alloy contains P, B, and Cu as essential components. As a preferred example, an Fe-based alloy contains Fe of 70 atomic % or more, B of 5 atomic % to 25 atomic %, Cu of 1.5 atomic % or less (excluding zero), and P of 10 atomic or less (excluding zero). | 2010-04-22 |
20100097172 | LAMINATED BODY AND MANUFACTURING METHOD THEREOF - A laminated body and fabrication method thereof, which allow space saving and control of variation in internal layer resistance, are provided. When forming an internal-layer resistive element | 2010-04-22 |
20100097173 | Entry/Exit Managing Device and Information Communication Terminal - An entry/exit managing device for controlling entry and exit of a user, who carries a portable memory and an information communication terminal, to and from a predetermined place includes: a portable memory communication unit which reads and writes data from and to the portable memory; a user managing unit which executes user authentication on the basis of user information stored in the portable memory; and a network device use information managing unit which manages network device use information used to set a network device use setting parameter in the information communication terminal. The portable memory communication unit reads the user information from the portable memory when the user enters the predetermined place. The user managing unit executes the user authentication on the basis of the user information. The portable memory communication unit writes the network device use information in the portable memory, when the user authentication succeeds. | 2010-04-22 |
20100097174 | Providing Parcel Procurement With Acknowledgement Of Receipt In An Intelligent Mailbox - A method for providing a procuration to a user on behalf of a letter or parcel recipient for authorizing this user to retrieve this letter or parcel with acknowledgement of receipt in an intelligent mailbox. Exemplary embodiments include a method to forward delegation between the original recipient and the delegated user through an exchange supported by any electronic or physical protocol of a delegation information made of the recipient unique identifier, a validity period and a hashcode, signed with the recipient private key and the mailbox public key. | 2010-04-22 |
20100097175 | VEHICLE AUTHENTICATION DEVICE - A vehicle authentication device has an in-vehicle device mounted on a vehicle, an authentication unit disposed in the in-vehicle device, for matching an ID returned from a portable device in response to a request from the in-vehicle device and performing an authentication of the vehicle, and an operation switch for instructing a power supply transition of the vehicle. The in-vehicle device has a measurement unit for measuring a duration of an active state of the operation switch, a determination unit for determining whether the duration exceeds a predetermined time, and a control unit for executing a power supply transition control of the vehicle based on the determination that the duration time of the active state of the operation switch exceeds the predetermined time made by the determination unit and an authentication result of the authentication unit. | 2010-04-22 |
20100097176 | INPUT DEVICE AND USER AUTHENTICATION METHOD - An input device having a given input screen includes a first unit that generates data indicating any one of a touch position, a touch area, and a touching time, the touch position being a position touched by an object, the touch area being an area touched by the object, and the touching time being a period touched by the object, a second unit that generates password codes based on any one of the touch position, the touch area, and the touching time, and a third unit that judges whether a user is an authorized user based on the password code. It is possible to generate password codes including data of any one of the touch position, the touch area, and the touching time. Accordingly, the password cannot be stolen by others, and the input device with which impersonation or spoofing is difficult and the password need not be input. | 2010-04-22 |
20100097177 | ELECTRONIC DEVICE AND ACCESS CONTROLLING METHOD THEREOF - An electronic device and method for controlling access to an electronic device includes acquiring a login iris image of a user, and computing iris characteristic values according to iris characteristic points in the login iris image. The electronic device and method further includes obtaining original iris characteristic values of one or more authorized users of the electronic device, and determining an identification of the user by determining if the computed iris characteristic values match the original iris characteristic values of the one or more authorized users. | 2010-04-22 |
20100097178 | VEHICLE BIOMETRIC SYSTEMS AND METHODS - A vehicle biometric system includes an in-vehicle telematics unit having a receiver configured to receive authentication data from a wireless communication device, a memory configured to store computer program instructions, and a processor configured to access and execute the computer program instructions. The authentication data can include voice data based on a vocal input received at the wireless communication device from a requesting user. The executed computer program instructions can cause the processor to analyze the received authentication data to make a determination as to whether the vocal input is that of an authorized user of the vehicle, and based on a positive determination that the vocal input is that of the authorized user, to initiate a vehicle function in response to the vocal input. | 2010-04-22 |
20100097179 | USER AUTHENTICATION DEVICE AND USER AUTHENTICATION METHOD - Biometric information registered for each user is held, user information being a plurality types of attribute information associated with each user is held, a possibility that the user requests authentication is predicted and a predicted value is calculated for each user by using the plurality types of attribute information contained in the held user information. When biometric information for an authentication request is accepted, the accepted biometric information is matched against the biometric information for a plurality of users determined based on calculated predicted values, and it is determined based on the result of the matching whether a person having entered the accepted biometric information is authenticated as the user. | 2010-04-22 |
20100097180 | SYSTEM AND METHOD FOR CREDIT CARD USER IDENTIFICATION VERIFICATION - A system for verifying a credit card user's identification includes a scanner, a comparator and a control unit. The scanner is configured to scan a holographic fingerprint image on a credit card and a credit card user's fingerprint and output first fingerprint image data representing the holographic fingerprint image and second fingerprint image data representing the credit card user's fingerprint. The comparator configured to compare the first fingerprint image data and the second fingerprint image data and determine whether the first fingerprint image data matches the second fingerprint image data. A control unit configured to issue a verification message based on the first fingerprint image data and the second fingerprint image data. | 2010-04-22 |
20100097181 | Patient Lifting System Using RFID Technology - An arrangement for a patient lifting system, wherein the patient lifting system comprises a lifting device and a sling adapted to be coupled to the lifting device. The lifting device is during use of the lifting system adapted to lift the patient from a lowered to a raised position and said sling is adapted to be at least partly wrapped around the patient to be lifted. The arrangement of the present invention comprises at least one RFID-chip ( | 2010-04-22 |
20100097182 | Signal Power Mapping For Detection Of Buried Objects And Other Changes To The RF Environment - In one embodiment, an RF disturbance detection system is provided that includes: an RF interrogator configured to transmit an RF interrogation signal; and a plurality of RF transceiver modules configured to respond to the RF interrogation signal by transmitting unique RF response signals, wherein the RF interrogator is further configured to periodically interrogate the RF transceiver modules to detect the power of the corresponding response signals so as to detect any changes in the response signal powers over time. | 2010-04-22 |
20100097183 | System and Method for Coupling a Component to a Vehicle - An alignment system for coupling a component to a vehicle includes at least one sensor target coupled to the component, and a controller assembly configured to transmit a signal towards the sensor target and receive a reflected signal from the sensor target, wherein the controller assembly is configured to output an orientation dataset for the component relative to the vehicle using the reflected signal. The system also includes a processing device communicatively coupled to the controller assembly, wherein the processing device is programmed to translate the orientation dataset and cause a set of component positioning signals based on the orientation dataset to be displayed at a user interface. | 2010-04-22 |
20100097184 | METHOD AND APPARATUS FOR READING SHORT DISTANCE EMISSION RFID TAGS TO LOCATE ITEMS IN A CONTAINER - The present invention is directed to a method and apparatus for reading short distance emission RFID tags to locate items in a container. A method in accordance with an embodiment of the present invention includes: initiating a reading sequence of a plurality of first RFID tags, wherein each first RFID tag is associated with a respective item located in the container, and wherein each first RFID tag emits an identification (ID); capturing the ID emitted by each first RFID tag using a plurality of second RFID tags located in a vicinity of the first RFID tag; interrogating the plurality of second RFID tags to obtain the captured IDs; and determining a physical location of an item in the container based on the captured IDs. | 2010-04-22 |
20100097185 | RFID TAG POSITIONAL ADDRESSING - The present invention is directed to a method and apparatus for radio frequency identification (RFID) tag positional addressing. A method in accordance with an embodiment of the present invention includes: activating a plurality of first RFID tags, wherein each first RFID tag emits an identification (ID) and a position; capturing the IDs and positions emitted by the first RFID tags using a plurality of second RFID tags, wherein each second RFID tag captures the IDs and positions emitted by the first RFID tags located in a vicinity of the second RFID tag, and wherein each second RFID tag determines its physical location based on the captured IDs and positions; and sending a read command including a position of a targeted one of the second RFID tags that is to be read, wherein only the targeted second RFID tag located at the position in the read command responds to the read command. | 2010-04-22 |
20100097186 | USER INTERFACE DEVICES FOR CONTROL OF MACHINE SYSTEMS - What is disclosed is a system for controlling a process, where the process is implemented by a machine system. The system includes a user interface device and a first transceiver coupled to the user interface device. The first transceiver is configured to receive communications from the user interface device and transfer the communications. The system also includes a second transceiver in communication with the first transceiver and configured to transfer power to the first transceiver, receive the communications from the first transceiver, and transfer the communications to control the process implemented by the machine system. | 2010-04-22 |
20100097187 | RFID TAGS - We describe RFID tags that incorporate a nonlinear resonator that self-adapts to the driving frequency of a reader. More particularly we describe an RF tag for sending data to a tag reader by modulating energy drawn from an RF field of said tag reader, the tag comprising: an antenna; a resonant circuit coupled to said antenna to resonate at a frequency of said RF field; a local power store to store power extracted from said RF field; a modulation system to modulate one or both of the resonance amplitude and a relative phase of a signal in said resonant circuit with respect to said RF field; and a feedback circuit coupled to said resonant circuit and to said local power store to control one or both of said resonance amplitude and said relative phase to control transients in said resonance amplitude caused by said modulation. | 2010-04-22 |
20100097188 | Radio Frequency Identification System and Method - An identification system and method is disclosed to identify an identity and a position of a radio frequency (RF) device. The RF device generates a response signal when receiving an RF signal. The identification system includes a plurality of antenna units, a switching unit, an RF module and a microcontroller. Each antenna unit has a corresponding identifying area. The switching unit is coupled to the antenna units. The microcontroller controls the switching unit to select at least one antenna unit for transmitting the RF signal generated by the RF module, and determines whether the RF device positions in the corresponding identifying area of the select antenna unit according to whether the selected antenna unit receives the response signal. The microcontroller also identifies the identity of the RF device when the select antenna unit receives the response signal. | 2010-04-22 |