15th week of 2010 patent applcation highlights part 28 |
Patent application number | Title | Published |
20100091497 | LIGHT-EMITTING DIODE LIGHTING DEVICE WITH MULTIPLE-LAYERED SOURCE - A lighting device includes a cover, a cap, a central post having opposite ends coupled to the cover and the cap respectively, and a plurality of first and second frames. The cover and the cap both form a plurality of circumferentially distributed slots opposite to each other. The first and second frames have ends respectively fit into the slots of the cover and the cap and each frame carries at least one light-emitting diode. As such, a light-emitting diode lighting device that is hollow, light-weighted, and exhibiting excellent heat dissipation is formed. | 2010-04-15 |
20100091498 | LOW PROFILE SIDE EMISSION TIR LENS FOR LED - A low profile side-emitting lens for an LED die has two tiers of different waveguides radially extending out from a center side-emitting lens. An LED emits light into the center side-emitting lens, which has a curved surface that internally reflects the LED light outward approximately parallel to the top surface of the LED die. The center lens has a height of 2 mm, required for reflecting the LED light outward. Radially extending from the periphery of the bottom half of the center lens is a bottom tier of waveguides, each having a height of 1 mm, and radially extending from the periphery of the top half of the center lens is a top tier of waveguides, each having a height of 1 mm. The light output areas of the top and bottom tiers of waveguides are parallel with each other so that the 2 mm high side emission is reduced to a 1 mm side emission without reducing the emission area. | 2010-04-15 |
20100091499 | Total Internal Reflection Lens and Mechanical Retention and Locating Device - A lens assembly includes a total internal reflection lens and a lens holder. The lens includes a body member having an outer surface shaped to provide total internal reflection and an interior open channel extending longitudinally through the body member. The body member has a first end region for accommodating a light source and a second end region that includes a plurality of refractive surface regions positioned around the open channel. The lens holder has a concave interior surface shaped to accommodate the optical body member of the lens and a convex exterior surface. The holder has multiple clips for securing the lens. The holder also has three or more support members extending from the exterior surface toward the first end. The support members are adapted for centering the optical body member with respect to the light source and maintaining the light source in the specified position in relation to the optical body member. | 2010-04-15 |
20100091500 | MULTI-FUNCTION LIGHT AND AIR FILTRATION UNIT - The subject invention relates to combination lighting and air filtration units that provide illumination and filter air in a particular area. A lighting unit includes an illumination element and a housing with a rounded profile that encloses the illumination element. A conduit is adjacent to the housing wherein a filter is mounted within the conduit. An input fan draws air through the filter to produce filtered air and an output fan expels the filtered air. | 2010-04-15 |
20100091501 | Light emitting diode apparatus and optical engine using the same - A light emitting diode (LED) apparatus includes a heat dissipating component, a flexible circuit board, a slug, a light emitting diode die, and a package material. The flexible circuit board has a hollow-out portion disposed on the heat dissipating component. The slug is thermal conductively connected to the heat dissipating component through the hollow-out portion of the flexible circuit board. The light emitting diode die is disposed on the slug, and electrically connected to the flexible circuit board. The package material covers the light emitting diode die and the slug, and the bottom thereof is connected to the flexible circuit board. The light emitting diode apparatus is applied to an optical engine having a chassis and a top cover. The flexible circuit board of the light emitting diode apparatus is assembled on the chassis, and the heat dissipating component thereof is assembled on the top cover. | 2010-04-15 |
20100091502 | LIGHT POLE BASE COVER - Housings are described that include snap fittings or connections hat can be placed on portions of the housing to allow assembly of the housing in the field, without the need for assembly tools or welding. Reduced assembly time and cost, as well as the reduction/elimination of tooling costs for assembly tools and/or associated hardware can therefore be realized Exemplary embodiments of the present disclosure can include a snap fitting with first and second portions, e.g., male and female portions, including a portion having a tab or clip punched out of a sheet and including a holding protrusion or portion, and another portion having an aperture or depression configured and arranged to receive and be held by the holding portion. Preferred embodiments can be utilized as light pole base covers. | 2010-04-15 |
20100091503 | LAMP DEVICE - A lamp device includes a base plate adapted to be fixed onto a mounting wall, a swivelable carrier having a carrier body swivelably mounted on the base plate about a central axis and retained at a retaining position with respect to the base plate by means of a first slidably engaging unit, and an angularly positionable mounting frame disposed to be swiveled with the carrier body, and having a rim body for mounting a lighting module. The mounting frame has a hinge shaft hingedly mounted on a joint lug of the carrier such that the rim body, together with the lighting module, is turnable relative to the carrier body and is retained at a tilted position by means of a second slidably engaging unit. With simple swiveling and turning operations, the angle and direction of the lighting module can be changed. | 2010-04-15 |
20100091504 | HEAT CONDUCTING SLUG HAVING MULTI-STEP STRUCTURE AND THE LIGHT EMITTING DIODE PACKAGE USING THE SAME - The present invention provides a heat conducting slug having a multi-step structure, which is installed to an LED package to dissipate heat generated from a light emitting chip to the outside. The heat conducting slug includes a first slug, a second slug formed on the first slug, and a third slug formed on the second slug, wherein the light emitting chip is mounted to the third slug, and the second and third slugs respectively shaped to have edges are arranged to cross each other. In this configuration, heat generated from a light emitting chip follows a heat dissipation path, in which the heat is gathered at edges of one slug and dissipated therefrom and then gathered toward edges of another slug, arranged to cross the one slug. Accordingly, the entire heat dissipation path is not concentrated at a specific region but generally distributed widely, thereby improving a heat dissipation effect of the heat conducting slug. | 2010-04-15 |
20100091505 | AUTOMATIC LEVELING DEVICE AND AUTOMATIC LEVELING METHOD - An automatic leveling device and automatic leveling method for being able to reduce an error caused by a hysteresis characteristic of an actuator are provided. A control ECU obtains vehicle height values from a front height sensor and a rear height sensor, computes a vehicle height difference from the vehicle height values, and a stroke amount to be corrected of an actuator | 2010-04-15 |
20100091506 | ILLUMINATION DEVICE FOR AN AIRCRAFT - An illumination device for an aircraft, comprising a combination of two-dimensional background illumination with a reflection of incident light on a face pointing towards the viewer in order to achieve a particular depth effect, as a result of which the illumination body appears to the viewer in greater visual depth than is actually the case. This is, in particular, of importance in aircraft, in which not only is the available space small, but also the weight aspect that is inevitably associated with large bodies plays an important role. | 2010-04-15 |
20100091507 | Directed LED Light With Reflector - A high intensity light is disclosed. A first circular lighting array having a plurality of reflectors and light emitting diodes is provided. A second circular lighting array is mounted on the first circular lighting array. The second circular lighting array has a second plurality of reflectors and light emitting diodes. Each reflector includes a tulip-shaped reflective surface having a symmetrical vertical cross section and a different symmetrical horizontal cross section. The reflective surface creates a uniform beam reflecting from a corresponding LED at horizontal angles relative to the reflective surface and a narrow beam in vertical angles relative to the reflective surface. | 2010-04-15 |
20100091508 | VEHICLE LAMP - A vehicle lamp includes a long solid-core shaped light guide; a first light source that irradiates an end portion of the long solid-core shaped light guide in a longitudinal direction such that light is radiated long from an end side of the vehicle lamp toward another end side of the vehicle lamp; and a second light source that irradiates the another end side of the vehicle lamp to a lateral outer side. | 2010-04-15 |
20100091509 | INTERIOR REARVIEW MIRROR SYSTEM FOR A VEHICLE - A vehicular interior rearview mirror system includes an interior rearview mirror assembly having one of (a) a variable reflectance reflective element and (b) a prismatic reflective element. The interior rearview mirror assembly includes an information display disposed behind and viewable through the reflective element. The interior rearview mirror assembly includes a video camera having, when the interior rearview mirror assembly is normally mounted in the vehicle, a field of view that encompasses one of (i) the windshield of the vehicle and (ii) the driver of the vehicle. The interior rearview mirror assembly may include other electrical accessories such as, for example, a light, a rolling code garage door opener, and a microphone. | 2010-04-15 |
20100091510 | HEADLIGHT FOR A MOTOR VEHICLE - The invention relates to a headlight for a motor vehicle with a sealing disk, which as a component of a housing seals an interior enclosed by the housing from the environment, wherein a layer system, comprising a lower layer, followed by a metal layer and an upper layer, is deposited on the side of the sealing disk directed towards the interior by means of a vacuum method, wherein the lower layer and/or the upper layer is deposited either as a nitride of the elements Al or Si or as an oxide or a mixed oxide of the elements Si, Ti Al, Zn, Sn, In, Nb, Zr, or Ta. | 2010-04-15 |
20100091511 | PRODUCTION METHOD FOR A HEADLIGHT LENS AND HEADLIGHT LENS FOR A MOTOR VEHICLE HEADLIGHT - The invention relates to a headlight lens for a vehicle headlight, particularly for a motor vehicle headlight, wherein the headlight lens comprises a bright-molded lens body made of a transparent material, having a substantially plane optically effective surface and a convexly curved optically effective surface, wherein the headlight lens comprises a lens edge on the outside of the convexly curved optically effective surface, wherein the substantially plane optically effective surface, protrudes over the lends edge, or over part of the lens edge, in a stepped manner in the direction of an optical axis of the headlight lens. | 2010-04-15 |
20100091512 | HEAD LAMP LEVELING DEVICE FOR VEHICLE - A vehicle headlamp of the present invention is provided with a lamp housing and a leveling device. The lamp housing has: a mount portion in which a circular through hole is provided; and an abutment protrusive portion which is provided at the mount portion. The leveling device has: a housing for providing a cylinder portion which is inserted into the circular through hole, and is mounted at a rim of the circular through hole; and an abutment face protrusive portion which is provided partly of the housing and allows the abutment protrusive portion to be in abutment against. As a result, the vehicle headlamp of the present invention allows the abutment protrusive portion to be in abutment against the abutment face protrusive portion, making it possible to ensure a stable distance between the lamp housing and the leveling device. | 2010-04-15 |
20100091513 | Vehicle detection apparatus, vehicle detection program and light control apparatus - A vehicle detection apparatus detects oncoming vehicles, and the illumination angle of the headlight is changed downwardly when oncoming vehicles are detected. When detecting the oncoming vehicles, the vehicle detection apparatus detects brightness or area for the every light source in an acquired image repeatedly, and detects as a variable light source any light source of which brightness or area changes within a reference time beyond a predetermined variation reference value. Then, when a variable light source is detected, it is determined that vehicles exist in the acquired image. | 2010-04-15 |
20100091514 | Optical module for a motor vehicle capable of selectively lighting a zone - A headlamp for a motor vehicle, this headlamp comprising at least one optical module capable of emitting a plurality of light beams, including a low beam and at least one additional light beam. The optical module is equipped with a cover plate which can be moved between at least two positions, this movable cover plate being configured along a shaft mounted so as to rotate in the optical module and driven in rotation at least by a motor. The shaft comprises at least one first cut-off member configured as a double-edged cover plate providing an oblique cut-off for emission of the low beam, and at least one second cut-off member configured as a wall of substantially constant height, angularly offset relative to the first cut-off member and providing at least one substantially vertical cut-off line for emission of a high beam. | 2010-04-15 |
20100091515 | LIGHT PIPE ASSEMBLY HAVING OPTICAL CONCENTRATOR - A light pipe assembly includes a light pipe and an optical concentrator. The light pipe is elongated between opposite ends along a longitudinal axis. The light pipe is formed from a light transmissive material. The optical concentrator is joined to the first end of the light pipe and includes an end section and an opposite coupling end connected to the first end of the light pipe. The end section is configured to receive light generated by a light source. The optical concentrator is formed from a light transmissive material that conveys light through the optical concentrator. The optical concentrator focuses the light generated by the light source into the first end of the light pipe. | 2010-04-15 |
20100091516 | Arrangement Comprising a Fiber-Optic Waveguide - An arrangement comprising a fiber-optic waveguide ( | 2010-04-15 |
20100091517 | ACTIVATED LOW-POWER LIGHTING - The present invention provides a lighting unit comprising a diffusion optic fibre, a light emitting diode (LED) coupled to the optic fibre; and an actuator connected to the LED for selectively activating the LED so that light is sent through the optic fibre and provides lighting. The lighting unit is structured and arranged for at least one of path lighting, staircase lighting, outdoor mats, mailbox lighting; curb address lights, driveway lighting, plant lighting, boat dock lighting, exterior house lighting, furniture patios, specialty home products, airplane lighting, motorcycle lighting, boat lighting; and auto lighting. The lighting unit may also be structured and arranged to be combined with at least one of a net, a ball, a glove, an out-of-bounds lighting, a bicycle, a tricycle, a big-wheels, and golf equipment. The fiber may be wound into thread and woven into at least one of clothing, coats, hats, gloves, bracelets, necklaces, running vests, backpacks, strollers, carriages, and pet collars. The lighting unit may be structured and arranged for at least one of hospital/nursing home lighting, schools and school facilities, movie theatres, industrial signage for property, buildings or vehicles, streets and highways, road signs; and fencing. | 2010-04-15 |
20100091518 | Anti-Glare LED Planar Light Source Adapted For Reading Lamp - An anti-glare LED light source adapted for a reading lamp includes a housing having a good thermal conductivity, a light guide plate, at least one LED module, and an optical film stack. The light guide plate, the at least one LED module, and the optical film stack are disposed in the housing. The optical film stack is configured on a first surface of the light guide plate facing toward an opening of the housing. An optical structure adapted for fetching light thereby is configured at a second surface of the light guide plate. The second surface of the light guide plate faces toward an inside bottom of the housing. The inside bottom of the housing is further provided with a light reflective material. The LED module is disposed at a lateral side of the light guide plate, for projecting light into the light guide plate. | 2010-04-15 |
20100091519 | ILLUMINATION SYSTEM AND DISPLAY DEVICE - The invention relates to an illumination system ( | 2010-04-15 |
20100091520 | Light Guide Plate and Backlight Module using the same - A light guide plate has a light incident surface, a light emitting surface and a bottom surface. The bottom surface or the light emitting surface has a plurality of light guide units disposed thereon. Each of the light guide units has a first curved surface and a second curved surface connected with the first curved surface. Both of the first curved surface and the second curved surface are concave surfaces or convex surfaces. In a cross section perpendicular to the light incident surface and passing through the first curved surface and the second curved surface, the first curved surface and the cross section intersect in a first curved line, and the second curved surface and the cross section intersect in a second curved line. A curvature radius of the first curved line is greater than that of the second curved line. | 2010-04-15 |
20100091521 | DUAL ISOLATED INPUT SINGLE POWER SUPPLY TOPOLOGY - An electric power supply system includes a transformer having two primary windings for receiving input power and a secondary winding for delivering output power, in which the primary windings are galvanically isolated from each other. A method for supplying electrical power to a load includes magnetically coupling a first primary voltage to a secondary power output; and magnetically coupling a second primary voltage to the secondary power output so that the second primary voltage is kept galvanically isolated from the first primary voltage. | 2010-04-15 |
20100091522 | Extended E Matrix Integrated Magnetics (MIM) Core - A matrix integrated magnetics (MIM) “Extended E” core in which a plurality of outer legs are disposed on a base and separated along a first outer edge to define windows therebetween. A center leg is disposed on the top region of the base and separated from the outer legs to define a center window. The center leg is suitably positioned along a second outer edge opposite the first or between outer legs positioned along opposing outer edges. A plate is disposed on the outer legs opposite the base. | 2010-04-15 |
20100091523 | SWITCHING POWER SUPPLY APPARATUS - A digital signal processing circuit which performs average current control is disposed on a secondary side of a transformer of an isolated DC-DC converter, and a switching control signal output from the digital signal processing circuit is transmitted to a switching element included in a power factor correction converter through an isolated drive circuit. The digital signal processing circuit obtains an average value of currents supplied to an inductor in accordance with a voltage output from a bias winding of the inductor or an output from a secondary side of a current transformer which detects a drain current of the switching element. Furthermore, the average value of the currents corresponds to a waveform (full-wave rectification sine wave) of an input voltage Vi. | 2010-04-15 |
20100091524 | Electronic Power Protection Circuit And Applications Thereof - An electric power protection circuit connected in series to a secondary side circuit of a transformer in a switch mode power supply includes a voltage/current limiting device to get an electric power signal output from the secondary side circuit of the transformer that goes through current and voltage limitation before being output and a constant current/voltage controller to get the electric power signal which has the current and voltage limited by the voltage/current limiting device. The electric power signal further is undergone constant voltage/current control to achieve voltage overshoot protection. | 2010-04-15 |
20100091525 | POWER CONVERTERS - We describe a resonant discontinuous power converter including a magnetic energy storage device, and a bipolar junction transistor (BJT) switch having a collector terminal coupled to repetitively switch power from the input on and off to said magnetic energy storage device such that power is transferred from the input to the output. During an off-period of said BJT switch a voltage on said magnetic energy storage device and on said collector terminal of said BJT is at least partially resonant. The power converter includes a voltage clamping circuit to clamp a base voltage on a base terminal of said BJT during a resonant portion of said off-period to limit an excursion of a collector voltage on said collector terminal of said BJT towards or beyond an emitter voltage of said BJT during said resonant portion of said off-period, in particular to inhibit reverse bias of a base emitter junction of the transistor. | 2010-04-15 |
20100091526 | HIGH EFFICIENCY POWER CONVERTER - A power converter nearly losslessly delivers energy and recovers energy from capacitors associated with controlled rectifiers in a secondary winding circuit, each controlled rectifier having a parallel uncontrolled rectifier. First and second primary switches in series with first and second primary windings, respectively, are turned on for a fixed duty cycle, each for approximately one half of the switching cycle. Switched transition times are short relative to the on-state and off-state times of the controlled rectifiers. The control inputs to the controlled rectifiers are cross-coupled from opposite secondary transformer windings. | 2010-04-15 |
20100091527 | TAPPING POWER FROM A HVDC TRANSMISSION SYSTEM - An apparatus for tapping electric energy from an HVDC power transmission system includes at least one voltage source converter. The apparatus includes an intermediate ac network containing the voltage source converter, and a switching arrangement for disconnecting the intermediate ac network in dependence on the transmission direction of the HVDC power transmission system. | 2010-04-15 |
20100091528 | METHOD AND ARRANGEMENT TO REVERSE THE POWER FLOW OF A DIRECT CURRENT POWER TRANSMISSION SYSTEM - A direct current power transmission system includes a first and a second converter station that are coupled to each other via a direct current link. Each converter station includes a first or second line commutated converter, respectively. Before power reversal the first converter is operated as a rectifier and the direct current is controlled in the first station, while the second converter is operated as an inverter and in the second station the extinction angle of the second converter or the direct voltage is controlled. After power reversal, the first converter is operated as an inverter and the second converter as a rectifier. During power reversal a change is carried out in the first station from control of the direct current to control of the extinction angle of the first converter or to control of the direct voltage, which is performed in synchronization with a change in the second station from control of the extinction angle of the second converter or from control of the direct voltage to control of the direct current. | 2010-04-15 |
20100091529 | ELECTRICAL ENERGY CONVERTER - An electrical energy converter ( | 2010-04-15 |
20100091530 | DC/DC CONVERTER - A DC-DC converter includes a control circuit which can change the target voltage of the reference voltage source. At the start-up of the DC-DC converter, the PWM control circuit controls so that the first switching element gradually increases the on-off ratio from a minimum on-off ratio; that the second switching element is placed in the OFF state, and that the target voltage is set higher than the normal operating voltage. When the start-up operation is completed, the PWM control circuit controls so that the second switching element starts to turn on and off, and that the target voltage is returned to the normal operating voltage. | 2010-04-15 |
20100091531 | METHODS AND SYSTEMS FOR REDUCING POWER CONSUMPTION - Methods and systems for managing power are described. In one embodiment of a method, a DC input voltage from an AC mains to DC converter, inputted to a DC to DC converter, is adjusted lower while maintaining substantially constant DC output voltage from the DC to DC converter in order to improve power efficiency. | 2010-04-15 |
20100091532 | METHOD AND APPARATUS FOR IMPROVED BURST MODE DURING POWER CONVERSION - A method and apparatus for converting DC input power to AC output power. The apparatus comprises an input capacitor, a DC-AC inverter, a burst mode controller for causing energy to be stored in the input capacitor during at least one storage period and the energy to be drawn from the input capacitor during at least one burst period, wherein the AC output power is greater than the DC input power during the at least one burst period; a first feedback loop for determining a maximum power point (MPP) and operating the DC-AC inverter proximate the MPP; and a second feedback loop for determining a difference in a first power measurement and a second power measurement, producing an error signal indicative of the difference, and coupling the error signal to the first feedback loop to adjust at least one operating parameter of the DC-AC inverter to drive toward the MPP. | 2010-04-15 |
20100091533 | MEMBER FOR A SYNCHRONOUS RECTIFIER BRIDGE, RELATED SYNCHRONOUS RECTIFIER BRIDGE AND USE THEREOF - The member for a synchronous rectifier bridge ( | 2010-04-15 |
20100091534 | MATRIX CONVERTER SPACE VECTOR MODULATION METHOD - [Object] The present invention provides a space vector modulation method for an AC-AC direct conversion device, which can convert input and output waveforms into sine waves and reduce the number of times of switching at an inter-sector shift. | 2010-04-15 |
20100091535 | ADAPTIVE ESTIMATION OF MEMORY CELL READ THRESHOLDS - A method for operating a memory ( | 2010-04-15 |
20100091536 | COMPOSITE MEMORY HAVING A BRIDGING DEVICE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM - A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto. | 2010-04-15 |
20100091537 | MULTI-DIE MEMORY DEVICE - An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to the memory access commands. The storage die has a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission. | 2010-04-15 |
20100091538 | BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM - Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface connected to the at least one discrete memory device, and a global input/output interface interposed between the local control interface and the local input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device. | 2010-04-15 |
20100091539 | SOLID STATE DEVICE PRODUCTS, INTERMEDIATE SOLID STATE DEVICES, AND METHODS OF MANUFACTURING AND TESTING THE SAME - Example embodiments of the inventive concept are directed to solid state device products, intermediate solid state devices, and methods of manufacturing and testing the same, with removable test terminals, which may permit in situ testing of one or more components of the solid state device products. | 2010-04-15 |
20100091540 | MEMORY MODULE DECODER - A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The plurality of memory devices has a first number of memory devices. The circuit comprises a logic element configurable to receive a set of input signals from the computer system. The circuit further comprising a register and a phase-lock loop circuit, the phase-lock loop circuit configurable to be operatively coupled to the plurality of memory devices, the logic element, and the register. The set of input signals corresponds to a second number of memory devices smaller than the first number of memory devices. | 2010-04-15 |
20100091541 | Stacked memory device and method thereof - A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit. | 2010-04-15 |
20100091542 | Memory Module Having a Memory Device Configurable to Different Data Pin Configurations - A memory module includes a memory device having a plurality of data pins and conductive lines electrically connected to the plurality of data pins. The memory device is configurable, using at least one input to the memory device, to a data pin configuration selected from among a plurality of different data pin configurations. The plurality of different data pin configurations include a first data pin configuration that uses a first number of data pins of the memory device, and a second data pin configuration that uses a second, different number of data pins. | 2010-04-15 |
20100091543 | SEMICONDUCTOR MEMORY APPARATUS INCLUDING A COUPLING CONTROL SECTION - A semiconductor memory apparatus is disclosed having a dual open bit line structure In the dual open bit line structure, bit lines or bit line bars are each arranged side by side in adjoining cell mats. The semiconductor memory apparatus includes a coupling control section connected between at least one pair of adjoining bit lines or at least one pair of adjoining bit line bars and is driven by a bit line equalize signal. The coupling control section prevents a coupling phenomenon from occurring between pairs of bit lines and bit line bars. | 2010-04-15 |
20100091544 | COUPLINGS WITHIN MEMORY DEVICES - A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed. | 2010-04-15 |
20100091545 | ELECTICALLY PROGRAMMABLE FUSE BIT - One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged. | 2010-04-15 |
20100091546 | HIGH DENSITY RECONFIGURABLE SPIN TORQUE NON-VOLATILE MEMORY - One time programmable memory units include a magnetic tunnel junction cell electrically coupled to a bit line and a word line. The magnetic tunnel junction cell is pre-programmed to a first resistance state, and is configured to switch only from the first resistance state to a second resistance state by passing a voltage across the magnetic tunnel junction cell. In some embodiments, a transistor is electrically coupled between the magnetic tunnel junction cell and the word line or the bit line. In other embodiments, a device having a rectifying switching characteristic, such as a diode or other non-ohmic device, is electrically coupled between the magnetic tunnel junction cell and the word line or the bit line. Methods of pre-programming the one time programmable memory units and reading and writing to the units are also disclosed. | 2010-04-15 |
20100091547 | SEMICONDUCTOR MEMORY DEVICE - A memory includes a memory cell array including destructive read-out type memory cells; a decoder selecting a cell; a sense amplifier configured to detect the data; and a read and write controller controlling a read operation and a write operation, wherein the read and write controller outputs a logical value of a write enable signal at the start of the read operation in a first period and makes the write enable signal invalid after the read operation starts during the first period, on the basis of the write enable signal and a restore signal keeping an activated state during the first period, the write enable signal being a signal allowing the write operation, the first period being a period from when the read operation starts to when a restore operation for writing the data back to the memory cell is completed. | 2010-04-15 |
20100091548 | Non-Volatile Memory Array with Resistive Sense Element Block Erase and Uni-Directional Write - A non-volatile memory cell and associated method of use are disclosed. In accordance with various embodiments, the memory cell includes a switching device and a resistive sense element (RSE) connected in series between first and second control lines. The first control line is supplied with a variable voltage and the second control line is maintained at a fixed reference voltage. A first resistive state of the RSE is programmed by lowering the variable voltage of the first control line below the fixed reference voltage of the second control line to flow a body-drain current through the switching device. A different, second resistive state of the RSE is programmed by raising the variable voltage of the first control line above the fixed reference voltage to flow a drain-source current through the switching device. | 2010-04-15 |
20100091549 | Non-Volatile Memory Cell with Complementary Resistive Memory Elements - A non-volatile memory cell and method of writing data thereto. In accordance with some embodiments, the memory cell includes first and second resistive memory elements (RMEs) configured to concurrently store complementary programmed resistive states. The first RME is programmed to a first resistive state and the second RME is concurrently programmed to a second resistive state by application of a common write current in a selected direction through the memory cell. | 2010-04-15 |
20100091550 | Voltage Reference Generation with Selectable Dummy Regions - Various embodiments of the present invention are generally directed to an apparatus and associated method for generating a reference voltage with dummy resistive sense element regions. A first resistance distribution is obtained for a first dummy region of resistance sense elements and a second resistance distribution is obtained for a second dummy region of resistive sense elements. A user resistive sense element from a user region is assigned to a selected resistive sense element of one of the first or second dummy regions in relation to the first and second resistance distributions. | 2010-04-15 |
20100091551 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory cell array having memory cells; and a control circuit configured to apply a first voltage to a selected one of first wirings as well as a second voltage to a selected one of second wirings. The control circuit includes: a signal output circuit configured to output a first signal based on a first current flowing through a selected memory cell and a reference current; and a current retaining circuit configured to retain a second current flowing through the first wirings or a wiring electrically connected to the first wirings during a certain period of time. The signal output circuit is configured to determine the first current based on the second current retained by the current retaining circuit. The control circuit is configured to stop application of the first voltage to the first wirings based on the first signal. | 2010-04-15 |
20100091552 | NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT - A nonvolatile memory device, using a resistance material, includes a memory cell array having nonvolatile memory cells arranged in a matrix, multiple bit lines, a column selection circuit and column drivers. The bit lines are coupled to columns of the nonvolatile memory cells in the memory cell array. The column selection circuit selects at least one bit line in response to column selection signals. Each column driver supplies a column selection signal, and includes a first charge unit that charges an output port of the column driver to a first voltage level in response to a first charge signal, a second charge unit that charges the output port of the column driver to a second voltage level from the first voltage level in response to a second charge signal, and a current controller that controls a current path from the second charge unit to the first charge unit. | 2010-04-15 |
20100091553 | SEMICONDUCTOR DEVICE HAVING RESISTANCE BASED MEMORY ARRAY AND METHOD OF OPERATION ASSOCIATED THEREWITH - In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write circuit configured to write to the non-volatile memory cell array, and a control circuit. The control circuit is configured to store at least one erase indicator. The erase indicator is associated with at least a portion of the non-volatile memory cell array and indicates a logic state. The control circuit is configured to control the write circuit to write the logic state indicated by the erase indicator in the non-volatile memory cell array during an erase operation of the associated portion of the non-volatile memory cell array. | 2010-04-15 |
20100091554 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THEREOF - A semiconductor device includes: a memory cell; a precharge circuit; a negative potential applying circuit; and a sense amplifier. The memory cell is connected to a first bit line and store data. The precharge circuit is connected to the first and second bit lines and precharges the first and second bit lines to a ground potential. The negative potential applying circuit is connected to the first bit line and applies a negative potential to the first bit line. The sense amplifier is connected to the first and second bit lines and read data based on a difference between a first potential of the first bit line and a second potential of the second bit line. An absolute value of the negative potential is smaller than the difference between the first potential and the second potential. | 2010-04-15 |
20100091555 | MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory has a laminating structure including: a magnetization free layer; an insulating layer; and a magnetization fixed layer. The magnetization free layer includes: a sense layer; a first bonding layer being adjacent to the sense layer; and a storage layer being adjacent to the first bonding layer on an opposite side to the sense layer. At least a part of the sense layer and the storage layer is magnetically coupled to one another through the first bonding layer. A magnetic anisotropy of the storage layer is larger than that of the sense layer. A product of a saturation magnetization and a volume of the sense layer is larger than that of the storage layer. According to such a structure, a magnetic random access memory can be provided in which a current for writing is reduced while enough thermal stability is maintained. | 2010-04-15 |
20100091556 | MAGNETO-RESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY - It is possible to reduce a current required for spin injection writing. A magneto-resistance effect element includes: a first magnetization pinned layer; a magnetization free layer; a tunnel barrier layer; a second magnetization pinned layer whose direction of magnetization is pinned to be substantially anti-parallel to the direction of magnetization of the first magnetization pinned layer, and; a non-magnetic layer. When the second magnetization pinned layer is made of ferromagnetic material including Co, material for the non-magnetic layer is metal including at least one element selected from the group consisting of Zr, Hf, Rh, Ag, and Au; when the second magnetization pinned layer is made of ferromagnetic material including Fe, material for the non-magnetic layer is metal including at least one element selected from the group consisting of Rh, Pt, Ir, Al, Ag, and Au; and when the second magnetization pinned layer is made of ferromagnetic material including Ni, material for the non-magnetic layer is metal including at least one element selected from the group consisting of Zr, Hf, Au, and Ag. | 2010-04-15 |
20100091557 | MAGNETIC RANDOM ACCESS MEMORY HAVING IMPROVED READ DISTURB SUPPRESSION AND THERMAL DISTURBANCE RESISTANCE - Between the value of an electric current and the supply duration for which the electric current is supplied that cause magnetization reversal, there is the relation of monotonous decrease. This means that, as the supply duration is shortened, the threshold current value for causing the magnetization reversal is larger. Therefore, in terms of suppressing occurrence of read disturb, the read current supply duration may be shortened to increase the threshold value of the current causing the magnetization reversal and thereby ensure a sufficient read disturb margin. Therefore, the read current supply duration may be shortened relative to the write current supply duration ensure the read disturb margin and suppress occurrence of read disturb. | 2010-04-15 |
20100091558 | Dielectric-Sandwiched Pillar Memory Device - A memory device includes bottom and top electrode structures and a memory cell therebetween. The memory cell comprises bottom and top memory elements and a dielectric element therebetween. A lower resistance conduction path is formed through the dielectric element. The dielectric element may have an outer edge and a central portion, the outer edge being thicker than the central portion. To make a memory device, an electrical pulse is applied through the memory cell to form a conduction path through the dielectric element. A passivation element may be formed by oxidizing the outer surface of the memory cell which may also enlarge the outer edge of the dielectric element. | 2010-04-15 |
20100091559 | Programmable resistance memory with feedback control - A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory cell. | 2010-04-15 |
20100091560 | Multi-terminal phase change devices - Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device. | 2010-04-15 |
20100091561 | Programmable Matrix Array with Chalcogenide Material - A memory element, a threshold switching element, or the series combination of a memory element and a threshold switching element may be used for coupling conductive lines in an electrically programmable matrix array. Leakage may be reduced by optionally placing a breakdown layer in series with the phase-change material and/or threshold switching material between the conductive lines. The matrix array may be used in a programmable logic device. | 2010-04-15 |
20100091562 | TEMPERATURE DEPENDENT SYSTEM FOR READING ST-RAM - A memory device that includes at least one memory cell, the memory cell includes: a magnetic tunnel junction (MTJ); and a transistor, wherein the transistor is operatively coupled to the MTJ; a bit line; a source line; and a word line, wherein the memory cell is operatively coupled between the bit line and the source line, and the word line is operatively coupled to the transistor; a temperature sensor; and control circuitry, wherein the temperature sensor is operatively coupled to the control circuitry and the control circuitry and temperature sensor are configured to control a current across the memory cell. | 2010-04-15 |
20100091563 | MAGNETIC MEMORY WITH PHONON GLASS ELECTRON CRYSTAL MATERIAL - A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron crystal layer also be disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element to provide a Peltier effect on the free magnetic element and the reference magnetic element. | 2010-04-15 |
20100091564 | MAGNETIC STACK HAVING REDUCED SWITCHING CURRENT - A magnetic stack having a ferromagnetic free layer, a ferromagnetic pinned reference layer, a non-magnetic spacer layer between the free layer and the reference layer, and a variable layer proximate the free layer. The variable layer is antiferromagnetic at a first temperature and paramagnetic at a second temperature higher than the first temperature. During a writing process, the variable layer is paramagnetic. For magnetic memory cells, such as magnetic tunnel junction cells, the variable layer provides reduced switching currents. | 2010-04-15 |
20100091565 | M+N BIT PROGRAMMING AND M+L BIT READ FOR M BIT MEMORY CELLS - A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory. | 2010-04-15 |
20100091566 | NAND FLASH MEMORY - In a state in which a first and second selection gate transistors are turned off and a first voltage is applied to a control gate of a second memory cell transistor which is connected to a source line side of a first memory cell transistor selected from among the memory cell transistors and which is to be cut off, a second voltage which is higher than the first voltage and which causes a plurality of third memory cell transistors remaining unselected in the memory cell transistors to conduct is applied to control gates of the third memory cell transistors, and thereafter a threshold voltage of the first memory cell transistor is changed to a threshold voltage higher than the first threshold voltage corresponding to the erase state by applying a third voltage which is higher than the second voltage to a control gate of the first memory cell transistor. | 2010-04-15 |
20100091567 | Test Circuit and Method for Multilevel Cell Flash Memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 2010-04-15 |
20100091568 | Nonvolatile Memory and Method With Reduced Program Verify by Ignoring Fastest and/or Slowest Programming Bits - A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code. | 2010-04-15 |
20100091569 | METHODS OF FORMING FLASH DEVICE WITH SHARED WORD LINES - Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates. | 2010-04-15 |
20100091570 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF INCREASING WRITING SPEED - A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage≧the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation. | 2010-04-15 |
20100091571 | NONVOLATILE MEMORY DEVICE WITH NAND CELL STRINGS - A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage. | 2010-04-15 |
20100091572 | 2T NOR-TYPE NON-VOLATILE MEMORYT CELL ARRAY AND METHOD OF PROCESSING DATA OF 2T NOR-TYPE NON-VOLATILE MEMORY - Provided are a 2-transistor (2T) NOR cell array which includes at least a cell, and a cell comprising a selection transistor and a storage transistor including a charge storage floating gate or a charge storage dielectric, and a method of processing data of a 2T NOR flash memory cell which is used to store data in a 2T NOR cell array, read the stored data, and erase the stored data. The 2T NOR cell array includes a selection transistor and a storage transistor. The selection transistor includes a terminal connected to a bit line and a gate terminal applied with a selection signal. The storage transistor includes a terminal connected to the other terminal of the selection transistor, the other terminal connected to a common source line, and a gate applied with a control voltage. A back bias voltage is applied to bulk regions of the selection transistor and the storage transistor when a programming operation is performed, and a floating gate or a charge storage dielectric is provided between the gate and the bulk region of the storage transistor. | 2010-04-15 |
20100091573 | Nonvolatile Memory And Method With Reduced Program Verify By Ignoring Fastest And/Or Slowest Programming Bits - A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code. | 2010-04-15 |
20100091574 | ONE-TRANSISTOR COMPOSITE-GATE MEMORY - One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies. | 2010-04-15 |
20100091575 | PROGRAMMING METHOD AND INITIAL CHARGING METHOD OF NONVOLATILE MEMORY DEVICE - A programming method of a nonvolatile memory device includes precharging bit lines of the nonvolatile memory device based on loaded data, boosting channels corresponding to the respective precharged bit lines, after supplying word lines adjacent to a selected word line of the nonvolatile memory device with an initializing voltage, the selected word line is a word line selected for programming, and supplying a word line voltage for programming to the channels, after the channels are boosted. | 2010-04-15 |
20100091576 | Nonvolatile memory device, program method and precharge voltage boosting method thereof, and memory system including the nonvolatile memory device - A method of programming a nonvolatile memory device according to the present invention includes precharging bit lines according to data loaded in page buffers; electrically connecting the precharged bit lines to channels corresponding to the bit lines, respectively, to charge the channels; and applying a word line voltage for a program after charging the channels. A channel voltage boosting of each of the channels is determined according to data loaded in adjacent page buffers. | 2010-04-15 |
20100091577 | MEMORY CELL STORAGE NODE LENGTH - Methods, devices, and systems for a memory cell are provided. One embodiment includes a memory cell with a storage node separated from a body region by a first dielectric, wherein the body region includes a channel separating a source and a drain region, and wherein a length of the storage node is less than a length of the channel. The embodiment further includes a memory cell with a gate separated from the storage node by a second dielectric, wherein a length of the gate is greater than a length of the storage node. | 2010-04-15 |
20100091578 | Nonvolatile Memory Devices Having Built-in Memory Cell Recovery During Block Erase and Methods of Operating Same - Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased. | 2010-04-15 |
20100091579 | NON-VOLATILE SEMICONDUCTOR MEMORY APPARATUS - A non-volatile semiconductor memory apparatus includes a first memory area configured to include a plurality of non-volatile memory cells, a second memory area configured to include a plurality of memory cells whose write speed is faster than the plurality of non-volatile memory cells, and a host interface configured to control the first and second memory areas, wherein the first and second memory areas are configured to be provided with the same address signal and command signal from the host interface. | 2010-04-15 |
20100091580 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes data transmission devices for transmit data in synchronization with each other. The semiconductor memory device includes a plurality of data transferring unit, a first control unit, a multiplexing unit, and a second control unit. The plurality of data transferring unit transfers data to a plurality of global lines. The first control unit controls the plurality of data transferring unit in response to a column select signal to select a column of a memory cell. The multiplexing unit multiplexes the data transferred to the plurality of global lines. The second control unit controls the multiplexing unit, wherein the second control unit synchronizes the column select signal with a column address signal having a column address information of the memory cell. | 2010-04-15 |
20100091581 | Memory device and method of operating such a memory device - A memory device, and method of operation of such a device, are provided. The memory device comprises an array of memory cells arranged in a plurality of rows and a plurality of columns, at least one bit line being associated with each column. Column multiplexer circuitry is coupled to the plurality of columns, for inputting write data into a selected column during a write operation and for outputting an indication of read data sensed from a selected column during a read operation. The column multiplexer circuitry comprises a single pass gate transistor per bit line, and latch circuitry is then used to detect the read data from the indication of read data output by the column multiplexer circuitry during the read operation, and to store that detected read data. Such an approach provides a particularly area efficient construction for the column multiplexer circuitry whilst enabling correct evaluation of the read data held in the addressed memory cell. | 2010-04-15 |
20100091582 | ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING - Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line. | 2010-04-15 |
20100091583 | MEMORY DEVICE HAVING LATCH FOR CHARGING OR DISCHARGING DATA INPUT/OUTPUT LINE - A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit. | 2010-04-15 |
20100091584 | MEMORY DEVICE AND METHODS THEREOF - A memory device is disclosed that includes multiple bit cells, whereby each bit cell is capable of being programmed to more than two states. A value stored at the memory device is determined by comparing the information stored at three or more of the bit cells. In an embodiment, the bit cell includes a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (FET) device, and the information stored at the bit cell can be represented by a corresponding level of charge stored in the body of the device. | 2010-04-15 |
20100091585 | STATIC RANDOM ACCESS MEMORIES AND ACCESS METHODS THEREOF - A static random access memory device capable of preventing stability issues during a write operation is provided, in which a memory cell is coupled to a read word line, a write word line, a read bit line, a write bit line and a complementary write bit line, and a multiplexing unit is coupled to the read bit line, the write bit line and the complementary write bit line. The multiplexing unit applies first and second logic voltages representing a logic state stored in the memory cell to the write bit line and the complementary write bit line, respectively, when the memory cell is not selected to be written by an input signal from a data driver and the read word line is activated, in which the first and second logic voltages are opposite to each other. | 2010-04-15 |
20100091586 | TECHNIQUES FOR SIMULTANEOUSLY DRIVING A PLURALITY OF SOURCE LINES - Techniques for simultaneously driving a plurality of source lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for simultaneously driving a plurality of source lines. The apparatus may include a plurality of source lines coupled to a single source line driver. The apparatus may also include a plurality of dynamic random access memory cells arranged in an array of rows and columns, each dynamic random access memory cell including one or more memory transistors. Each of the one or more memory transistors may include a first region coupled to a first source line of the plurality of source lines, a second region coupled to a bit line, a body region disposed between the first region and the second region, wherein the body region may be electrically floating, and a gate coupled to a word line and spaced apart from, and capacitively coupled to, the body region. | 2010-04-15 |
20100091587 | Device selection circuit and method - Embodiments of the invention take advantage of an unused state of an interface protocol (or specification), such as the ONFI specification, to control a selector circuit to assert one of a plurality of relatively localized device selection signals (e.g., chip enable signals). | 2010-04-15 |
20100091588 | MEMORY DEVICE AND MEMORY SYSTEM COMPRISING A MEMORY DEVICE AND A MEMORY CONTROL DEVICE - In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal. | 2010-04-15 |
20100091589 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory block having first and second word lines extending in a first direction and bit lines extending in a perpendicular second direction; a first driver region at a side of the memory block in the first direction driving the first word lines; a second driver region at another side of the memory block in the first direction driving the second word lines; a sensing region at a side of the memory block in the second direction controlling the bit lines responsive to signals from drive lines; a first conjunction region at an intersection of the first driver and sensing regions including a first driver driving the drive lines responsive to signals from control lines; and a second conjunction region at an intersection of the second driver and sensing regions, including a second driver driving the drive lines responsive to signals from the control lines. | 2010-04-15 |
20100091590 | Semiconductor memory apparatus - A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal for selecting one of the first SRAM cells to be read/written the data and a second control signal for selecting one of the second SRAM cells to be read/written the potential difference, a sense amplifier circuit that amplifies a potential difference of a read signal output from a bit line pair of the second SRAM cell selected according to the second control signal, and a write driver circuit that outputs a write signal to the bit line pair of the second SRAM cell selected according to the second control signal, and the write signal has a potential difference between bit lines larger than the read signal. | 2010-04-15 |
20100091591 | DATA STROBE SIGNAL GENERATING DEVICE AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A data strobe signal generating device includes a preamble controller configured to generate a preamble signal enabled in synchronization with a first clock signal and disabled in synchronization with a second clock signal after an output enable signal is enabled, and a data strobe signal output unit configured to generate a data strobe signal in response to the preamble signal. | 2010-04-15 |
20100091592 | CLOCK BUFFER AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A clock buffer includes a reference enable signal generator configured to generate a reference enable signal enabled in synchronization with a rising edge of a first period of a second clock after a clock enable signal is enabled, a delay enable signal generator configured to generate a delayed enable signal enabled in synchronization with a rising edge of a second period of a first clock after the reference enable signal is enabled, a first output unit configured to receive the reference enable signal and the first clock to generate a first internal clock, and a second output unit configured to receive the delayed enable signal and the second clock to generate a second internal clock. | 2010-04-15 |
20100091593 | SEMICONDUCTOR MEMORY DEVICE INCLUDING SIGNAL CONTROLLER CONNECTED BETWEEN MEMORY BLOCKS - A semiconductor memory device includes a first memory block, a second memory block, and a signal controller. The first memory block is configured to generate a first blocking signal, a second blocking signal, and a first enable signal in response to a row address, and to block and enable wordlines of the memory block in response to the first blocking signal and the first enable signal, respectively. The second memory block is configured to generate a third blocking signal, a fourth blocking signal, and a second enable signal in response to the row address, and to block and enable wordlines of the second memory block in response to the third blocking signal and the second enable signal, respectively. The signal controller is connected between the first memory block and the second memory block and is configured to enable the third blocking signal when the second blocking signal is enabled, and to enable the first blocking signal when the fourth blocking signal is enabled. | 2010-04-15 |
20100091594 | SEMICONDUCTOR MEMORY FOR DISCONNECTING A BIT LINE FROM SENSE AMPLIFIER IN A STANDBY PERIOD AND MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY - Each memory block has a plurality of memory cells, and word lines and bit lines connected to the memory cells. Precharge switches connect the bit lines to a precharge line. A switch control circuit controls an operation of the precharge switches and sets a cutoff function that turns off connection switches in a standby period in which no access operation of the memory cells is performed. Since connections of the bit lines and the precharge switch and those of the bit lines and the sense amplifier are cut off in the standby period, if a short circuit failure is present between a word line and a bit line, a leak current can be prevented from flowing from the word line to a precharge voltage line and so on. | 2010-04-15 |
20100091595 | INTEGRATED CIRCUIT WITH CONTROL CIRCUIT FOR PERFORMING RETENTION TEST - An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of memory cells based on the clock signal. A period of the clock signal defines a retention period for the retention test. | 2010-04-15 |
20100091596 | SOLID STATE DRIVE SYSTEMS AND METHODS OF REDUCING TEST TIMES OF THE SAME - Example embodiments of the inventive concept are directed to solid state device systems and methods of reducing test times of the same. | 2010-04-15 |