13th week of 2014 patent applcation highlights part 69 |
Patent application number | Title | Published |
20140089625 | Method for Heap Management - A bitmask array is implemented as a two dimensional bit array where each bit represents an allocated/free cell of the heap. Groups of bits of the bitmask array are assigned to implement commonly sized memory cell allocation requests. The heap manager keeps track of allocations by keeping separate lists of which groups are being used to implement commonly sized memory cell allocations requests by maintaining linked lists according to the number of cells allocated per request. Each list contains a list of the bit groups that have been used to provide allocations for particularly sized requests. By maintaining lists based on allocation size, the heap manager is able to cause new allocation requests to be matched up with previously retired allocations of the same size. Memory may be dynamically allocated between lists of differently sized memory requests. | 2014-03-27 |
20140089626 | TECHNIQUES FOR DYNAMIC PHYSICAL MEMORY PARTITIONING - Various embodiments are presented herein that reallocate partitions of a shared physical memory between processing units. An apparatus and a computer-implemented method may determine an amount of memory space in the physical memory allocated to a first processing unit during system initialization. The determined amount of the memory space may be consolidated. The consolidated memory space may be allocated to the second processing unit during runtime. Other embodiments are described and claimed. | 2014-03-27 |
20140089627 | METHOD FOR TRACKING MEMORY USAGES OF A DATA PROCESSING SYSTEM - Techniques for tracking memory usages of a data processing system are described herein. According to one embodiment, a memory manager is to perform a first lookup operation in a memory allocation table to identify an allocation entry based on a handle representing a memory address of a memory block allocated to a client and to retrieve a trace entry pointer from the allocation entry. The memory manager is then to perform a second lookup operation in a memory trace table to identify a trace entry based on the trace entry pointer and to increment a memory allocation count of the trace entry. The memory allocation count is utilized to indicate a likelihood of the client causing a memory leak. | 2014-03-27 |
20140089628 | DATA STORAGE SPACE RECOVERY SYSTEM AND METHOD - A process of determining explicitly free data space in computer data storage systems with implicitly allocated data space through the use of information provided by a hosting computer system with knowledge of what space allocated is currently being used at the time of a query, is provided. In one embodiment, a File System (“FS”) is asked to identify clusters no longer in use which is then mapped to physical disks as visible to an Operating System (“OS”). The physical disks are mapped to simulated/virtualized volumes presented by a storage subsystem. By using server information regarding the FS, for those pages that are no longer in use, point in time copy (“PITC”) pages are marked for future PITC and will not be coalesced forward, thereby saving significant storage. | 2014-03-27 |
20140089629 | SOLID STATE MEMORY DEVICE LOGICAL AND PHYSICAL PARTITIONING - Embodiments relate to solid state memory device including a storage array having a plurality of physical storage devices and the storage array includes a plurality of partitions. The solid state memory device also includes a controller comprising a plurality of mapping tables, wherein each of the plurality of mapping tables corresponds to one of the plurality of partitions. Each of the plurality of mapping tables is configured to store a physical location and a logical location of data stored in its corresponding partition. | 2014-03-27 |
20140089630 | VIRTUAL ADDRESSING - A method of relating the user logical block address (LBA) of a page of user data to the physical block address (PBA) where the data is stored in a RAIDed architecture reduces to size of the tables by constraining the location to which data of a plurality of LBAs may be written. Chunks of data from a plurality of LBAs may be stored in a common page of memory and the common memory pages is described by a virtual block address (VBA) referencing the PBA, and each of the LBAs uses the same VBA to read the data. | 2014-03-27 |
20140089631 | POWER SAVINGS VIA DYNAMIC PAGE TYPE SELECTION - An operating system monitors a performance metric of a direct memory access (DMA) engine on an I/O adapter to update a translation table used during DMA operations. The translation table is used during a DMA operation to map a virtual address provided by the I/O adapter to a physical address of a data page in the memory modules. If the DMA engine is being underutilized, the operating system updates the translation table such that a virtual address maps to physical address corresponding to a memory location in a more energy efficient memory module. However, if the DMA engine is over-utilized, the operating system may update the translation table such that the data used in the DMA engine is stored in memory modules that provide quicker access times—e.g., the operating system may map virtual addresses to physical addresses in DRAM rather than phase change memory. | 2014-03-27 |
20140089632 | DIVISION OF NUMERICAL VALUES BASED ON SUMMATIONS AND MEMORY MAPPING IN COMPUTING SYSTEMS - Divisions by numbers that are not divisible by two (2) can be performed in a computing system based on a summation that estimates and/or approximates the reciprocal of the dividing number or denominator value. By way of example, dividing by three (3) can be calculated based on a summation that approximates or estimates one third (⅓) represented as the sum of a selected group of the inverses of the powers of two (2) in a pattern, namely the sum of: ¼, 1/16, 1/64, 1/256, . . . ). Applications of the division techniques are virtually unlimited and include memory mapping of global memory addresses to memory channel addresses by dividing a global memory address into the number of memory channels, allowing memory mapping to be performed in an efficient manner even for large memory spaces using a number of memory channels that are not divisible by two, including prime numbers. | 2014-03-27 |
20140089633 | METHOD AND APPARATUS FOR ENCODING DATA ADDRESS - The present invention relates to the field of communication technologies and discloses a method and an apparatus for encoding a data address, so that attacks can be effectively prevented and resources and costs required to handle a bank conflict are reduced. In solutions provided by embodiments of the present invention, an exclusive-OR operation is performed on one or more bits of a received uncoded address by using multiple preset transform polynomials; and an encoded address is obtained according to a result of the exclusive-OR operation. The solutions provided by the embodiments of the present invention are applicable to designs that require a large-capacity DRAM, high performance and high reliability, and have an anti-attack demand. | 2014-03-27 |
20140089634 | APPARATUS AND METHOD FOR DETECTING IDENTICAL ELEMENTS WITHIN A VECTOR REGISTER - An apparatus, system and method are described for identifying identical elements in a vector register. For example, a computer implemented method according to one embodiment comprises the operations of: reading each active element from a first vector register, each active element having a defined bit position within the first vector register; reading each element from a second vector register, each element having a defined bit position within the second vector register corresponding to a bit position of a current active element in the first vector register; reading an input mask register, the input mask register identifying active bit positions in the second vector register for which comparisons are to be made with values in the first vector register, the comparison operations comprising: comparing each active element in the second vector register with elements in the first vector register having bit positions preceding the bit position of the current active element in the second vector register; and setting a bit position in an output mask register equal to a true value if all of the preceding bit positions in the first vector register are equal to the bit in the current active bit position in the second vector register. | 2014-03-27 |
20140089635 | PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND SHARED CORE EXTENSION UTILIZATION INSTRUCTIONS - An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension logic has shared data processing logic that is shared by each of the plurality of cores. Instruction execution logic, for each of the cores, in response to a shared core extension call instruction, is to call the shared core extension logic. The call is to have data processing performed by the shared data processing logic on behalf of a corresponding core. Other apparatus, methods, and systems are also disclosed. | 2014-03-27 |
20140089636 | CACHING OPTIMIZED INTERNAL INSTRUCTIONS IN LOOP BUFFER - Embodiments of the invention relate to a computer system for storing an internal instruction loop in a loop buffer. The computer system includes a loop buffer and a processor. The computer system is configured to perform a method including fetching instructions from memory to generate an internal instruction to be executed, detecting a beginning of a first instruction loop in the instructions, determining that a first internal instruction loop corresponding to the first instruction loop is not stored in the loop buffer, fetching the first instruction loop, optimizing one or more instructions corresponding to the first instruction loop to generate a first optimized internal instruction loop, and storing the first optimized internal instruction loop in the loop buffer based on the determination that the first internal instruction loop is not stored in the loop buffer. | 2014-03-27 |
20140089637 | Optimizing System Throughput By Automatically Altering Thread Co-Execution Based On Operating System Directives - A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads. | 2014-03-27 |
20140089638 | Multi-Destination Instruction Handling - Various techniques for processing instructions that specify multiple destinations. A first portion of a processor pipeline is configured to split a multi-destination instruction into a plurality of single-destination operations. A second portion of the pipeline is configured to process the plurality of single-destination operations. A third portion of the pipeline is configured to merge the plurality of single-destination operations into one or more multi-destination operations. The one or more multi-destination operations may be performed. The first portion of the pipeline may include a decode unit. The second portion of the pipeline may include a map unit, which may in turn include circuitry configured to maintain a list of free architectural registers and a mapping table that maps physical registers to architectural registers. The third portion of the pipeline may comprise a dispatch unit. In some embodiments, this may provide certain advantages such as reduced area and/or power consumption. | 2014-03-27 |
20140089639 | PROCESSOR WITH INSTRUCTION CONCATENATION - A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a number of additional instructions to execute in conjunction with the first instruction and prior to execution of the first instruction. | 2014-03-27 |
20140089640 | PROCESSOR WITH VARIABLE INSTRUCTION ATOMICITY - A processor includes a plurality of execution units. At least one of the execution units is configured to execute a complex instruction that requires multiple instruction cycles to execute, and to enforce atomic execution of the complex instruction during a first-portion of the multiple instruction cycles required to execute the complex instruction. The at least one of the execution units is further configured to enable execution of the complex instruction to be interrupted for execution of a different instruction by the at least one execution unit during execution of a second portion of the multiple instruction cycles. The first portion and the second portion are non-overlapping. | 2014-03-27 |
20140089641 | PROCESSOR WITH INSTRUCTION ITERATION - A processor includes a plurality of execution units. At least one of the execution units is configured to repeatedly execute a first instruction based on a first field of the first instruction indicating that the first instruction is to be iteratively executed. | 2014-03-27 |
20140089642 | METHODS AND SYSTEMS FOR PERFORMING A REPLAY EXECUTION - One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction. | 2014-03-27 |
20140089643 | INFORMATION PROCESSING APPARATUS AND INSTRUCTION OFFLOADING METHOD - In general, according to one embodiment, an information processing apparatus includes an issuer and a communicator. The issuer issues an offload instruction corresponding to a first process executed in company with a first identifier capable of uniquely specifying a resource of a first arithmetic operation device. The communicator transmits the offload instruction to a second arithmetic operation device and receives a result of execution of the offload instruction from the second arithmetic operation device. In the second arithmetic operation device, the first identifier contained in the offload instruction is converted into a second identifier capable of uniquely specifying a resource of the second arithmetic operation device, and processing specified by the offload instruction is executed. | 2014-03-27 |
20140089644 | CIRCUIT AND METHOD FOR IDENTIFYING EXCEPTION CASES IN A FLOATING-POINT UNIT AND GRAPHICS PROCESSING UNIT EMPLOYING THE SAME - A floating-point unit and a method of identifying exception cases in a floating-point unit. In one embodiment, the floating-point unit includes: (1) a floating-point computation circuit having a normal path and an exception path and operable to execute an operation on an operand and (2) a decision circuit associated with the normal path and the exception path and configured to employ a flush-to-zero mode of the floating-point unit to determine which one of the normal path and the exception path is appropriate for carrying out the operation on the operand. | 2014-03-27 |
20140089645 | PROCESSOR WITH EXECUTION UNIT INTEROPERATION - A processor includes a plurality of execution units. Each of the execution units includes processing logic configured to process data, and registers accessible by the processing logic. At least one of the execution units is configured to execute a first instruction that causes the at least one execution unit to: route a value from a first register of the registers of one of the execution units to the processing logic of one of the execution units, to process the value in the processing logic to generate a result, and to store the result in a second register of the registers of one of the execution units. At least one of the first register, the second register, and the processing logic are located in a different one of the execution units from the at least one of the execution units. | 2014-03-27 |
20140089646 | PROCESSOR WITH INTERRUPTABLE INSTRUCTION EXECUTION - A processor includes a plurality of execution units. Each of the execution units includes a status register configured to store a value indicative of state of the execution unit. At least one of the execution units is configured to execute a complex instruction that requires multiple instruction cycles to execute. The at least one of the execution units is also configured to interrupt execution of the complex instruction to execute a different instruction, and resume, based on the value stored in the status register, execution of the complex instruction at the point interrupted after execution of the different instruction. | 2014-03-27 |
20140089647 | Branch Predictor for Wide Issue, Arbitrarily Aligned Fetch - In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, a branch direction predictor may be updated responsive to a misprediction and also responsive to the branch prediction being within a threshold of transitioning between predictions. To avoid a lookup to determine if the threshold update is to be performed, the branch predictor may detect the threshold update during prediction, and may transmit an indication with the branch. | 2014-03-27 |
20140089648 | BIFURCATED PROCESSOR CHIP RESET ARCHITECTURES - Systems and techniques for processor reset hold control are described. A described system includes a controller to detect a hold request based on an external reset signal and an external debug signal, and generate a hold signal based on a detection of the hold request, where the hold signal continues after the external reset signal has been discontinued; a system component that is responsive to the external reset signal; a processor that is responsive to the hold signal, where the hold signal causes the processor to enter a reset state and to maintain the reset state after the external reset signal has been discontinued; and a system manager configured to permit external access to the system component while the processor is in the reset state. The controller can be configured to discontinue the hold signal in response to a clear request. | 2014-03-27 |
20140089649 | System and Method of Server Re-provisioning via a Service Processor and Virtual Initiators - A method includes determining, by a management controller of a first server in a storage network, if a first virtual initiator is used by a second server in the storage network, wherein the first virtual initiator includes first boot information for allocating a first storage resource of the storage network, aborting a boot up of the first server in response to determining that the first virtual initiator is being used by the second server, and proceeding with the boot up of the first server in response to determining that the first virtual initiator is not used by the second server, wherein the boot up proceeds using the first boot information to allocate the first storage resource to the first server. | 2014-03-27 |
20140089650 | Security Enclave Processor Boot Control - An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory. | 2014-03-27 |
20140089651 | COMPUTING DEVICE BOOT SOFTWARE AUTHENTICATION - Various embodiments are generally directed to authenticating a chain of components of boot software of a computing device. An apparatus comprises a processor circuit and storage storing an initial boot software component comprising instructions operative on the processor circuit to select a first set of boot software components of multiple sets of boot software components, each set of boot software components defines a pathway that branches from the initial boot software component and that rejoins at a latter boot software component; authenticate a first boot software component of the first set of boot software components; and execute a sequence of instructions of the first boot software component to authenticate a second boot software component of the first set of boot software components to form a chain of authentication through a first pathway defined by the first set of boot software components. Other embodiments are described and claimed herein. | 2014-03-27 |
20140089652 | CUSTOMIZING PROGRAM LOGIC FOR BOOTING A SYSTEM - A method and system are provided for generating customized program logic operable to control hardware devices of a target system and to boot said target system. The system is connected to one or more target systems via a network, the server system being adapted for: receiving a first list of device identifiers from one of the target systems; automatically selecting, for each of the device identifiers in the received first list, at least one driver operable to control the identified device from a set of drivers, thereby generating a sub-set of said set of drivers; providing a core program logic to the target system; and providing the sub-set of drivers to the target system, wherein a combination of the sub-set of drivers and the core program logic constitutes a customized program logic operable to control the devices of said target system. | 2014-03-27 |
20140089653 | ELECTRONIC APPARATUS, METHOD OF RESTORING GUID PARTITION TABLE (GPT) AND COMPUTER-READABLE RECORDING MEDIUM - An electronic apparatus comprising a storage unit to store a first (primary) GPT, a second (secondary) GPT, and an OS, a controller boots the electronic apparatus using the first GPT and the OS, an effectiveness determination unit determines effectiveness of the first GPT if a predetermined event occurs, and a restoration unit restores the first GPT using the second GPT if the first GPT is not effective. | 2014-03-27 |
20140089654 | NETWORK STORAGE TARGET BOOT AND NETWORK CONNECTIVITY THROUGH A COMMON NETWORK DEVICE - The present disclosure includes systems and techniques relating to booting to a network storage target. In general, in one implementation, a bus-to-network device driver is loaded during a machine boot, where the bus-to-network device driver is capable of sending machine bus commands over a network, providing access to the network for a network device driver, and distinguishing between received responses to the machine bus commands and other network traffic corresponding to the network device driver. Loading of the bus-to-network device driver can occur in response to an operating system load of bus drivers. For example, the bus-to-network device driver can be an iSCSI driver, and the operating system load of bus drivers can be the operating system load of SCSI drivers. | 2014-03-27 |
20140089655 | SYSTEM AND METHOD FOR AUTO-FAILOVER AND VERSION MATCHING OF BOOTLOADER IN AN ACCESS CONTROLLER - In accordance with embodiments of the present disclosure, an information handling system may include a processor and an access controller communicatively coupled to the processor. The access controller may include a memory having a bootloader portion including a first memory address and a second memory address a second processor communicatively coupled to the memory. The second processor may be configured to: (i) attempt to execute the a first copy of a bootloader stored at the first memory address; (ii) in the event of a failure to execute the first copy of the bootloader, copy a second copy of the bootloader stored at the second memory address to the first memory address; and (iii) subsequent to copying the second copy to the first memory address, attempt to execute the second copy of the bootloader stored at the first memory address. | 2014-03-27 |
20140089656 | DATA PROCESSING APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM - Disclosed is a data processing apparatus providing a predetermined function by executing a program for the data processing apparatus, including a first storage unit that stores encoded execution starting data for starting execution of the program; a first decode key storage unit that stores a first decode key capable of decoding the encoded execution starting data; a start up unit that obtains the first decode key from the first decode key storage unit when turning on the power is accepted and decodes the encoded execution starting data by the first decode key to start executing the program; and an authentication confirmation unit that sends a request for authentication to an external apparatus after the start up unit starts executing the program and starts providing the predetermined function when obtaining an authentication result indicating the apparatus is authenticated from the external apparatus. | 2014-03-27 |
20140089657 | RECORDING MEDIUM STORING DATA PROCESSING PROGRAM, DATA PROCESSING APPARATUS AND DATA PROCESSING SYSTEM - A computer-readable storage medium stores a data processing program for causing a computer to execute a process. The process includes: identifying a first combination of first data and second data based on a predetermined condition from a storage in which the first data and first ciphered data obtained by ciphering the first data are correspondently stored, and the second data and second ciphered data obtained by ciphering the second data are correspondently stored; extracting a second combination of the first ciphered data and the second ciphered data stored respectively and correspondently to the first data and the second data identified by the identifying; and transmitting the second combination of the first ciphered data and the second ciphered data extracted by the extracting to an external device. | 2014-03-27 |
20140089658 | METHOD AND SYSTEM TO SECURELY MIGRATE AND PROVISION VIRTUAL MACHINE IMAGES AND CONTENT - A method, device, and system for securely migrating and provisioning a virtual machine image to a host device of a cloud service provider environment (CSPE) is disclosed. A customer device encrypts a virtual machine image (VMI) and stores the VMI in the CSPE. The host device retrieves the encrypted VMI from the object store and sends host trust data (including a symmetric key extracted from the encrypted VMI, the symmetric key being encrypted with the customer public key) to a key management server for trust attestation. If the key management server successfully attests the host device, the key management server decrypts the encrypted symmetric key using the customer private key and re-encrypts the symmetric key using the host public key. The host device receives the re-encrypted symmetric key from the key management server, decrypts it using the host private key, and decrypts the encrypted VMI using the symmetric key. | 2014-03-27 |
20140089659 | Method and apparatus for key provisioning of hardware devices - Keying materials used for providing security in a platform are securely provisioned both online and offline to devices in a remote platform. The secure provisioning of the keying materials is based on a revision of firmware installed in the platform. | 2014-03-27 |
20140089660 | ENHANCED PRIVACY ID BASED PLATFORM ATTESTATION - As opposed to utilizing a manufacturer provisioned EK Certificate for AIK processes, embodiments of the invention utilize EPID based data. EPID mitigates the privacy issues of common RSA PKI security implementations where every individual is uniquely identified by their private keys. Instead, EPID provides the capability of remote attestation but only identifies the client computing system as having a component (such as a chipset) from a particular technology generation. EPID is a group signature scheme, where one group's public key corresponds to multiple private keys, and private keys generate a group signature which is verified by the group public key. EPID provides the security property of being anonymous and unlinkable—given two signatures, one cannot determine whether the signatures are generated from one or two private keys. EPID also provides the security property of being unforgeable—without a private key, one cannot create a valid signature. | 2014-03-27 |
20140089661 | SYSTEM AND METHOD FOR SECURING NETWORK TRAFFIC - One variation of a method for selectively filtering internet traffic includes: receiving DNS queries; determining resource access levels for the DNS queries based on an internet resource database, wherein the resource access levels comprise a first level, a second level, and a third level returning an unmodified IP address for the first level DNS queries; returning a replacement resource IP address for the second level DNS queries; returning a web proxy server IP address for the third level DNS queries; and regulating HTTP traffic directed to the web proxy server IP address. | 2014-03-27 |
20140089662 | SYSTEMS AND METHODS FOR SHARING FILES AMONG MULTIPLE TERMINALS - Embodiments of the disclosure provide a method and apparatus for sharing data. The method includes: initiating the data sharing application on a first terminal; inserting the file to be shared in a webpage of the data sharing application on the first terminal, and generating an URL for the file in the data sharing application; the data-sharing application of the first terminal broadcasts the URL to other terminal, so that other terminals can share the file via the URL. The present disclosure can reduce the cost of data sharing while improve on the real-timeliness. | 2014-03-27 |
20140089663 | COMMUNICATION METHOD, APPLICATION DEVICE, PROGRAM, AND COMMUNICATION SYSTEM - According to one embodiment, a communication method including acquiring an application key from a key-sharing network, determining a key use of the application key, and performing encryption communication by using the application key according to the determined key use. | 2014-03-27 |
20140089664 | TRUSTED AND CONFIDENTIAL REMOTE TPM INITIALIZATION - Techniques are provided to allow remote initialization of a Trusted Platform Module. The results may be trusted and confidential even if the target device has malicious operating system or other software running. | 2014-03-27 |
20140089665 | SYSTEM AND METHOD FOR USING A STREAMING PROTOCOL - An initialization vector (IV) is employed to decrypt a block of a stream that has been encrypted with Cypher Block Chaining (CBC) encryption, without requiring decryption of previous blocks within the stream. For example, a listener who accesses a distribution point to retrieve encrypted content authenticates himself to an application server that regulates access to encrypted content on the distribution point, and responsively receives a key. The listener then requests access to a reference point within the encrypted content stream somewhere after its beginning (e.g., using preview clips). The distribution point relates the reference point to a corresponding block of the encrypted stream, and identifies an IV previously used for encryption of that block. The distribution point provides the associated encrypted block of content and the IV to the listener to enable mid-stream rendering of the encrypted content, without requiring the listener to decrypt previous blocks within the encrypted stream. | 2014-03-27 |
20140089666 | TIME SYNCHRONIZATION IN A MACHINE TO MACHINE COMMUNICATION - The present disclosure is related to performing a time synchronization between entities in a machine to machine (M2M) communication. | 2014-03-27 |
20140089667 | SECURE DEBUG TRACE MESSAGES FOR PRODUCTION AUTHENTICATED CODE MODULES - Methods of extending capabilities of authenticated code modules (ACM) with minimal increase in code size comprises defining an authenticated code module (ACM) extension module using an entry of a Firmware Interface Table (FIT). The FIT contains a starting address of the ACM extension module that is located outside of a protected boot block. Based on the ACM extension module having been authenticated, the ACM and the ACM extension module may be processed together. | 2014-03-27 |
20140089668 | TRANSMITTING DEVICE, RECEIVING DEVICE, TRANSMITTING METHOD, RECEIVING METHOD, AND PROGRAM - There is provided a transmitting device including a public key information adder that adds information on a public key corresponding to an electronic signature to a sender address in an email with the electronic signature attached, and a transmitter that transmits the email. | 2014-03-27 |
20140089669 | CONFIDENTIAL PROVISIONING OF SECRET KEYS OVER THE AIR - A method and apparatus for personalizing a smart card coupled with a communication device of a user who is a subscriber of a first telecommunication network and wishes to become a subscriber of a second telecommunication network is disclosed. A first authentication key is stored in both the smart card and in an first application server included in the first telecommunication network. A secure session is established with a second application server included in the second telecommunication network via the first telecommunication network by negotiating with the first application server and the second application server in order that the smart card and the second application server agree on an second authentication key. Shared values and shared functions according to a secure multiparty computation protocol are used to compute a second authentication key which replaces the first authentication key in the smart card. | 2014-03-27 |
20140089670 | UNIQUE CODE IN MESSAGE FOR SIGNATURE GENERATION IN ASYMMETRIC CRYPTOGRAPHIC DEVICE - Methods and systems are disclosed for verifying the use of a client device by a host device in a secure system. In one aspect, a method for authenticating a client device includes receiving, by the client device, a message from a host device, accessing, by the client device, a private key and a unique code stored on the client device, where the unique code is different than the private key, generating, by the client device, a digital signature for the message using the private key and the unique code, and providing, by the client device, the digital signature to the host device for verification of the use of the client device by the host device. | 2014-03-27 |
20140089671 | Multi-Tiered Authentication Methods For Facilitating Communications Amongst Smart Home Devices and Cloud-Based Servers - Apparatus, systems, methods, and related computer program products for synchronizing distributed states amongst a plurality of entities and authenticating devices to access information and/or services provided by a remote server. Synchronization techniques include client devices and remote servers storing buckets of information. The client device sends a subscription request to the remote serve identifying a bucket of information and, when that bucket changes, the remote server sends the change to the client device. Authentication techniques include client devices including unique default credentials that, when presented to a remote server, provide limited access to the server. The client device may obtain assigned credentials that, when presented to the remote server, provide less limited access to the server. | 2014-03-27 |
20140089672 | WEARABLE DEVICE AND METHOD TO GENERATE BIOMETRIC IDENTIFIER FOR AUTHENTICATION USING NEAR-FIELD COMMUNICATIONS - Techniques associated with a wearable device and method to generate biometric identifier for authentication using near-field communications are described, including capturing data associated with a habitual activity, a physiological characteristic, and a motion pattern using a wearable device, generating a biometric identifier using the data, storing the biometric identifier on the wearable device, and authenticating a user using the biometric identifier. | 2014-03-27 |
20140089673 | BIOMETRIC IDENTIFICATION METHOD AND APPARATUS TO AUTHENTICATE IDENTITY OF A USER OF A WEARABLE DEVICE THAT INCLUDES SENSORS - Embodiments relate generally to electrical and electronic hardware, computer software, wired and wireless network communications, and wearable computing devices for facilitating health and wellness-related information, and more particularly, to an apparatus or method for using a wearable device (or carried device) having sensors to identify a wearer and/or generate a biometric identifier for security and authentication purposes (e.g., using the generated biometric identifier similar to a passcode). In one embodiment, a method includes determining a pattern of activity based on a first activity and a second activity, comparing data representing the pattern of activity against match data associated with a habitual activity, and authenticating an identity of a user associated with a wearable device. | 2014-03-27 |
20140089674 | ENCRYPTION IN THE CLOUD WITH CUSTOMER CONTROLLED KEYS - A system and method for encryption in a cloud computing platform with customer controlled keys is disclosed. A cloud-based encryption key is uploaded from a customer computing platform to a key store of the cloud computing platform, based on a customer-based encryption key. The cloud-based encryption key and customer-based encryption key is able to encrypt or decrypt customer data used by an application server running on the cloud computing platform. Next, the cloud-based encryption key is unlocked from the key store, and then stored in a secure store of a main memory associated with the customer computing platform. Then, according to encryption or decryption mechanism, the unlocked cloud-based encryption key is accessed to encrypt or decrypt customer data stored on a database of the main memory and used by the application server. | 2014-03-27 |
20140089675 | AUTHENTICATOR, AUTHENTICATEE AND AUTHENTICATION METHOD - According to one embodiment, an authenticator which authenticates an authenticatee, which stores first key information (NKey) that is hidden, includes a memory configured to store second key information (HKey) which is hidden, a random number generation module configured to generate random number information, and a data generation module configured to generate a session key (SKey) by using the second key information (HKey) and the random number information. The authenticator is configured such that the second key information (HKey) is generated from the first key information (NKey) but the first key information (NKey) is not generated from the second key information (HKey). | 2014-03-27 |
20140089676 | SECURE PROCESSOR AND A PROGRAM FOR A SECURE PROCESSOR - The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside. | 2014-03-27 |
20140089677 | METHOD AND APPARATUS FOR SECURING PROGRAMMING DATA OF A PROGRAMMABLE DEVICE - Configuration data for a programmable integrated circuit device is at least partially encrypted according to at least one encryption scheme. A plurality of key stores store a plurality of decryption keys for the at least one encryption scheme. Control circuitry identifies a required key from the at least partially encrypted configuration data and generates a key selection signal. Key selection circuitry responsive to the key selection signal reads the plurality of key stores and provides the required key to the control circuitry. The control circuitry may include decryption circuitry that decrypts the at least partially encrypted configuration data using the required key. In some embodiments, different portions of the configuration data, which may represent separate partial reconfigurations of the device, require different decryption keys. Keys may be generated from combinations of the contents of the key stores. | 2014-03-27 |
20140089678 | ORDER-PRESERVING ENCRYPTION SYSTEM, DEVICE, METHOD, AND PROGRAM - An order-preserving encryption system has an encryption means which generates a ciphertext as a sum of data which complies with a distribution X determined in advance, and the encryption means generates the ciphertext using the distribution X represented in a format that data of a bit length determined at random is selected at random according to a distribution matching the bit length. | 2014-03-27 |
20140089679 | SECURE EXECUTION OF A COMPUTER PROGRAM USING BINARY TRANSLATORS - Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein to provide a computing device with cooperative first and second binary translators in first and second execution environments having first and second security levels, respectively. The second security level may be more secure than the first security level. Encrypted instructions of the computer program may be loaded into the first execution environment, and the first binary translator may provide, to the second binary translator, an execution context of the computer program for use by the secondary binary translator to decrypt and execute a first portion of the computer program in the second execution environment. The second binary translator may provide, to the first binary translator, another execution context of the computer program for emulation, by the first binary translator, of execution of a second portion of the computer program in the first execution environment. | 2014-03-27 |
20140089680 | SECURE PROCESSOR AND A PROGRAM FOR A SECURE PROCESSOR - The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside. | 2014-03-27 |
20140089681 | SECURE PROCESSOR AND A PROGRAM FOR A SECURE PROCESSOR - The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside. | 2014-03-27 |
20140089682 | Security Enclave Processor for a System on a Chip - An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory. | 2014-03-27 |
20140089683 | MULTI-DRIVE COOPERATION TO GENERATE AN ENCRYPTION KEY - A system, method, and computer-readable storage medium for protecting a set of storage devices using a secret sharing scheme. The data of each storage device is encrypted with a key, and the key is encrypted based on a shared secret and a device-specific value. Each storage device stores a share and its encrypted key, and if a number of storage devices above a threshold are available, then the shared secret can be reconstructed from the shares and used to decrypt the encrypted keys. Otherwise, the secret cannot be reconstructed if less than the threshold number of storage devices are accessible, and then data on the storage devices will be unreadable. | 2014-03-27 |
20140089684 | METHOD AND APPARATUS FOR PROTECTING FILE - Embodiments of the present invention provide a method and a system for protecting a file, which belong to the field of information security. The method includes: replacing a secure file header of a file to be protected with its original file header to convert the file to be protected to a secure file; and preventing, by the secure file header of the secure file acquired by the conversion, another peripheral from performing an access operation on content of the secure file. By using this method, in a terminal device such as an Android mobile phone or a computer, without affecting normal use by a subscriber, the protection of files such as multimedia files can be realized and content of a protected secure file in a mobile phone is not allowed to be opened on another device to achieve a purpose of avoiding private information leakage and protecting personal privacy. | 2014-03-27 |
20140089685 | KEY INFORMATION GENERATION DEVICE AND KEY INFORMATION GENERATION METHOD - In initial generation (for example, shipping from the factory), a security device generates an identifier w specific to the security device, with the PUF technology, generates key information k (k=HF(k)) from the identifier w, generates encrypted confidential information x by encrypting (x=Enc(mk, k)) confidential information mk with the key information k, and stores the encrypted confidential information x and an authentication code h (h=HF′(k)) of the key information k, in a nonvolatile memory. In operation, the security device generates the identifier w with the PUF technology, generates the key information k from the identifier w, and decrypts the encrypted confidential information x with the key information k. At a timing where the identifier w is generated in the operation, the security device checks whether the current operating environment has largely changed from the initial generation (S | 2014-03-27 |
20140089686 | BUS PIN REDUCTION AND POWER MANAGEMENT - A reduced-pin bus system includes a bus having one or more signal lines that are coupled to a bus power supply through a current limiting device. A master unit is coupled to the bus and is arranged to transmit communications across the bus during an active period of the bus and to initiate communications during (and/or at the end of) a quiescent period of the bus. A slave unit is coupled to the bus and is arranged to couple power from the one or more signal lines to a capacitor during the quiescent period of the bus and to consume power from the capacitor during the active period of the bus. | 2014-03-27 |
20140089687 | POWER MANAGEMENT INTEGRATED CIRCUIT - An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout. | 2014-03-27 |
20140089688 | Sharing Power Between Domains In A Processor Package - In an embodiment, the present invention includes a processor having a first domain with at least one core to execute instructions, a second domain coupled to the first domain and having at least one non-core circuit, and a power control unit (PCU) coupled to the first and second domains. The PCU may include a power sharing logic to receive encoded power consumption information from the second domain and to calculate an available power budget for the first domain based at least in part on the encoded power consumption information. Other embodiments are described and claimed. | 2014-03-27 |
20140089689 | COMPUTER WITH FORCE SENSING RESISTOR - A computer includes a motherboard with a signal receiving port and a switch circuit. The switch circuit includes a force sensing module and a transistor. The transistor includes a first terminal connected to the force sensing module, a second terminal connected to a power source, and a third terminal connected to the signal receiving port. When there is a pressure applied to the force sensing module, the force sensing module outputs a first driving signal to turn on the transistor and enables the computer to maintain its current power on or off state. When there is no pressure applied to the force sensing module, the force sensing module outputs a second driving signal to turn off the transistor and switches on or off the computer. | 2014-03-27 |
20140089690 | CONTROLLING POWER SUPPLY IN ARITHMETIC PROCESSING CIRCUIT - An arithmetic processing circuit includes a plurality of arithmetic processing units, a plurality of selector circuits each configured to select one of a plurality of power supplies that are fewer than the arithmetic processing units and to connect the selected power supply to a corresponding one of the arithmetic processing units, and a power supply control circuit configured to variably control an output voltage of at least one of the plurality of power supplies. | 2014-03-27 |
20140089691 | SUPPLY MARGINING METHOD AND APPARATUS - In accordance with some embodiments, margining routines to determine acceptable voltage command values for specific CPU implementations at one or more different operating levels may be provided. | 2014-03-27 |
20140089692 | STORAGE BATTERY MONITORING METHOD, STORAGE BATTERY MONITORING SYSTEM, AND STORAGE BATTERY SYSTEM - A storage battery monitoring method including: receiving, via a communication network, identification information indicating a storage battery system and characteristic data indicating a state of at least one storage battery; determining, based on the received characteristic data, a deterioration model corresponding to the at least one storage battery from among deterioration models managed in a database and indicating deterioration tendencies of other storage batteries; generating, via the communication network, control data for ameliorating a deterioration state of the at least one storage battery at a predetermined point in time according to the corresponding deterioration model; transmitting the generated control data to the storage battery system; and controlling, in the storage battery system, the at least one storage battery based on the transmitted control data. | 2014-03-27 |
20140089693 | EFFICIENT LOW POWER EXIT SEQUENCE FOR PERIPHERAL DEVICES - Embodiments of the invention describe methods, apparatuses and systems for providing an efficient low power exit sequence for peripheral devices. In embodiments of the invention, a signal from a host device is transmitted to a SATA peripheral device for exiting a low-power state. An initialization time for OOB transmission and reception logic of the SATA peripheral device is tracked, and a reference time value based on the tracked initialization time is stored. In subsequent transitions from said low-power state, the reference time value for waking a host physical layer is utilized, thereby improving the efficiency of the management and use of said low power state. In some embodiments, the above described tracked initialization comprises a time from a transmission of an OOB signal (from the host to the peripheral device) to receiving an OOB response at the host device from the SATA peripheral device. | 2014-03-27 |
20140089694 | DYNAMICALLY CONTROLLING POWER BASED ON WORK-LOOP PERFORMANCE - The present embodiments provide a system that dynamically controls power consumption in a computing device. During operation, the system measures the performance of the computing device while executing a work-loop. Next, the system determines a derived completion time for the work-loop based on the measured performance. (For example, the derived completion time can be an expected completion time, a maximum completion time, or more generally a completion time distribution.) The system then determines a deadline-proximity for the work-loop based on a comparison between the derived completion time and a deadline for the work-loop. (For example, the deadline-proximity can be an expected deadline-proximity, a minimum deadline-proximity, or more generally a deadline-proximity distribution.) Finally, the system controls the power consumption of the computing device based on the determined deadline-proximity for the work-loop. | 2014-03-27 |
20140089695 | ENERGY-SAVING DEVICE - The present invention discloses an energy-saving device with multiple voltage levels which is applied to a motherboard. The energy-saving device includes an energy-saving driving module electrically connected to a CPU on the motherboard for generating an energy-saving signal with multiple voltage levels to the CPU, so as to switch the CPU to a corresponding operational frequency according to a voltage level of the energy-saving signal after the CPU receives the energy-saving signal. The energy-saving device with multiple voltage levels implements 256 voltage levels instead of the conventional two voltage levels, so as to achieve multiple power consumption of the motherboard. | 2014-03-27 |
20140089696 | METHOD FOR CONTROLLING POWER MODE SWITCHING - A method for controlling power mode switching, applied to a computer device, is provided. The computer device includes a power source supplying electrical power to the computer device for operation and is operated in a first power mode. In the method, firstly, a request for switching the computer to a second power mode is received. A power consumption amount corresponding to the second power mode is calculated. A remaining capacity of the power source is obtained. Then, whether the power consumption amount is larger than the remaining capacity is determined. If the power consumption amount is larger than the remaining capacity, a warning indicating that the remaining capacity is not sufficient is sent to an operating system of the computer device and the computer device is not switched to the second power mode. | 2014-03-27 |
20140089697 | SYSTEM-ON-CHIP WITH CAPABILITY FOR CONTROLLING POWER SUPPLY ACCORDING TO DATA TRANSACTION AND METHOD OF OPERATING THE SAME - A system-on-chip (SoC) which includes a plurality of intellectual properties (IP cores) which communicate data with a memory device operates by monitoring whether a data transaction occurs between at least one of the IP cores and the memory device, determining an operation state of the IP core according to the result of the monitoring, and supplying the IP core with power corresponding to the operation state of the IP core. | 2014-03-27 |
20140089698 | SENSING CURRENT TO PROTECT A FUSE - The speed of a processor is adjusted based on the current sensed by a current sensor in order to protect a fuse from being damaged. | 2014-03-27 |
20140089699 | POWER MANAGEMENT SYSTEM AND METHOD FOR A PROCESSOR - The present disclosure relates to a method and apparatus for dynamically controlling power consumption by at least one processor. A power management method includes monitoring, by power control logic of the at least one processor, performance data associated with each of a plurality of executions of a repetitive workload by the at least one processor. The method includes adjusting, by the power control logic following an execution of the repetitive workload, an operating frequency of at least one of a compute unit and a memory controller upon a determination that the at least one processor is at least one of compute-bound and memory-bound based on monitored performance data associated with the execution of the repetitive workload. | 2014-03-27 |
20140089700 | PERFORMANCE MANAGEMENT METHODS FOR ELECTRONIC DEVICES WITH MUTIPLE CENTRAL PROCESSING UNITS - Performance management methods for an electronic device with multiple central processing units (CPUs) are provided. First, thread loading rearrangement and CPU frequency evaluation are performed to obtain a plurality of evaluated performance values for different amounts of CPUs, wherein the plurality of evaluated performance values are relevant to power consumption values of the multiple CPUs. It is then determined whether to adjust an amount of used CPUs based on the plurality of evaluated performance values corresponding to the different amounts of CPUs. | 2014-03-27 |
20140089701 | METHOD FOR CONTROLLING SCHEDULE OF EXECUTING APPLICATION IN TERMINAL DEVICE AND TERMINAL DEVICE IMPLEMENTING THE METHOD - A method may include associating, with a timer-B, a second application in a terminal device; setting the terminal device in a standby mode; and executing the second application when a processor in the terminal device wakes up after the timer-B measures a second amount of elapsed time. The timer-B may not initiate wake-up of the processor. The method may further include determining whether the second application is associated with the timer-B or a timer-A when the terminal device receives a command of setting the terminal device in the standby mode; and when the second application is determined as being associated with the timer-A, unassociating the second application with the timer-A. The timer-A may initiate wake-up of the processor when the timer-A measures another second amount of elapsed time while the terminal device is the standby mode. A timer associated with a first application may initiate wakeup of the processor. | 2014-03-27 |
20140089702 | ENERGY-EFFICIENT CONTENT UPDATE - Embodiments of methods, systems, and storage medium associated with are disclosed herein. In one instance, the method may include: first determining whether the computing device is connected to a network, based on a result of the first determining, monitoring data traffic between the computing device and the network, wherein the data traffic is associated with at least one application residing on the computing device, based on the monitoring, second determining whether the at least one application has been updated, and initiating a transition of the computing device to a sleep mode upon a result of the second determining that indicates that the at least one application has been updated. Other embodiments may be described and/or claimed. | 2014-03-27 |
20140089703 | LOW POWER EVENT PROCESSING FOR SENSOR CONTROLLERS - A controller includes a low power processor to couple to a sensor, the low power processor configured to receive data from the sensor and apply rules to the received data and provide an interrupt in accordance with the applied rules. A high power processor is coupled to receive interrupts from the low power processor in a sleep mode, to wake upon receipt of the interrupt, and to receive and process the data to determine actions to take based on the data, wherein the high power processor initiates the actions. | 2014-03-27 |
20140089704 | SYSTEM POWER CONTROL - A power control unit | 2014-03-27 |
20140089705 | POWER GATING FOR TERMINATION POWER SUPPLIES - Power gating control architectures. A memory device having at least a memory array and input/output (I/O) lines terminated on the memory device with termination circuitry coupled to receive a termination supply voltage (V | 2014-03-27 |
20140089706 | DELAYING RESET SIGNALS IN A MICROCONTROLLER SYSTEM - A microcontroller system includes a reset delaying module that is configured to, during a power saving mode, receive and delay a reset signal from a reset source. The reset delaying module waits for a regulator ready signal from a voltage regulator because, prior to the reset signal, the voltage regulator is in a power saving mode. In response to receiving the regulator ready signal, the reset delaying module releases the reset, e.g., to a reset controller. | 2014-03-27 |
20140089707 | CHANGING POWER MODES OF A MICROCONTROLLER SYSTEM - A microcontroller system can operate in a number of power modes. In response to changing from a previous mode to a present mode, the microcontroller system reads a present calibration value correspond to the present mode from system configuration storage and write the present calibration value to a configuration register for a component. A logic block for the component reads the present calibration value and calibrates the component. | 2014-03-27 |
20140089708 | DELAYING INTERRUPTS IN A MICROCONTROLLER SYSTEM - A microcontroller system includes a power manager that is configured to, during a power saving mode, configure an interrupt delaying module to receive and hold an interrupt from an interrupt source. In response to receiving the interrupt from the interrupt source, the power manager causes the microcontroller system to exit the power saving mode. Upon exiting the power saving mode, the power manager configures the interrupt delaying module to release the interrupt. | 2014-03-27 |
20140089709 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - According to one embodiment, an information processing apparatus includes an operation control module, a calculator, and a display processor. The operation control module is configured to set the information processing apparatus in a power-saving state, based on a power-saving setup value corresponding to at least one power-saving setup item. The power-saving setup value is set by a user. The calculator is configured to calculate a total score indicative of a degree by which the power-saving state contributes to power saving during a period from a score calculation start time point to a reference time point. The display processor is configured to display an image associated with the total score. | 2014-03-27 |
20140089710 | INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND OPERATION METHOD THEREOF - An embodiment of the invention provides an electronic device. The electronic device includes a first wireless module, a second wireless module and a controller. The first wireless module is controlled by a chipset to communicate with a portable device. The second wireless module communicates with the portable device. The controller is coupled to the second wireless module. When the first wireless module and the chipset are disabled, the electronic device receives a signal from the portable device via the second wireless module. | 2014-03-27 |
20140089711 | INCREASING THE BATTERY LIFE OF A MOBILE COMPUTING SYSTEM IN A REDUCED POWER STATE THROUGH MEMORY COMPRESSION - Embodiments of the invention are generally directed to systems, methods, and apparatuses for increasing the battery life of a mobile computing system through memory compression. In some embodiments, an integrated circuit includes compression logic to compress at least a portion of the data in volatile memory independent of an operating system. The compression logic may compress the data responsive to an indication to transition to a reduced power state. | 2014-03-27 |
20140089712 | Security Enclave Processor Power Control - An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory. | 2014-03-27 |
20140089713 | COMPUTER SYSTEM, POWER SUPPLY DEVICE AND METHOD THEREOF - A computer system includes a first electronic device configured to be operated by utilizing a regular voltage, a second electronic device configured to be operated by utilizing the regular voltage, and a power supply device for providing the regular voltage. The power supply device includes a voltage regulator coupled to the first electronic device for transforming a supply voltage to output the regular voltage to the first electronic device, a control logic circuit for generating an enable signal according to a control signal, and a load switch circuit coupled to the control logic circuit, the voltage regulator and the second electronic device for outputting the regular voltage to the second electronic device according to the enable signal. | 2014-03-27 |
20140089714 | CONFIGURING POWER DOMAINS OF A MICROCONTROLLER SYSTEM - A microcontroller system is organized into power domains. A power manager of the microcontroller system can change the power configuration of a power domain in response to event from an event generating module without activating a processor of the microcontroller system. | 2014-03-27 |
20140089715 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, an information processing apparatus is powered by a power source including a power generation unit and a power storage device that stores power generated by the power generation unit. The information processing apparatus includes a first obtaining, a second obtaining unit, and a first control unit. The first obtaining unit is configured to obtain first information indicating a value of power generated by the power generation unit. The second obtaining unit is configured to obtain second information indicating an value of stored energy in the power storage device. The first control unit is configured to start a process that is set in advance when the value of power indicated by the first information is greater than zero and the value of stored energy indicated by the second information is equal to or greater than a first threshold value. | 2014-03-27 |
20140089716 | PROCESSING DEVICE AND METHOD FOR REDUCING NOISE - A processing device includes: a channel adaptor connected to an external device; a first resistor provided parallel to the channel adaptor, and has a variable resistance value; a processor to control the resistance value of the first resistor; a power supply device to provide power; a second resistor provided between the power supply device and the channel adaptor; a switch to control continuity of a current from the power supply device to the channel adaptor and the first resistor; and a controller to monitor a voltage of the second resistor, and turn off the switch when the voltage is larger than a threshold. The processor calculates a resistance value to be set in the first resistor based on a current of the second resistor, the threshold, and a resistance value of the second resistor, and sets the calculated resistance value as the resistance value of the first resistor. | 2014-03-27 |
20140089717 | AD-HOC SYNCHRONIZATION OF INDUSTRIAL CONTROL NETWORKS - A method and apparatus are disclosed to provide ad-hoc synchronization in industrial networks between a programmable logic controller and each I/O device without any specific protocol extensions or distributed clock scheme. An embodiment of an industrial control network comprising a Programmable Logic Controller (PLC), a network coupled to the PLC, and a plurality of networked input/output (I/O) devices coupled to the network is provided. Each I/O device comprises: inputs coupled to the network to receive data from the PLC as device input data; and outputs coupled to the network to transmit output data from the I/O device to the PLC. The embodiment further comprises a programmable timer initiating an I/O cycle for the device on a periodic basis. The I/O device is operable to determine a first time period starting at the time at which specific output data arrives from the PLC and ending when the period of the timer ends. The first time period is compared to a predetermined time period. The I/O device is operable to adjust the period of the timer such that the first period approaches the predetermined time period and ad-hoc synchronization is provided between production time of the PLC and timing of the I/O device. | 2014-03-27 |
20140089718 | CLOCK DOMAIN BOUNDARY CROSSING USING AN ASYNCHRONOUS BUFFER - An apparatus includes a plurality of channels, where each of the channels includes an asynchronous buffer, a latency determination block, a tap selection circuit, and a variable delay. A latency locator is configured to identify a longest latency from among the channels and is coupled to provide the longest latency to the tap selection circuit of each of the channels. For each of the channels: the latency determination block is coupled to the asynchronous buffer to determine a latency value for the asynchronous buffer; the tap selection circuit is coupled to receive the latency value and the longest latency; the tap selection circuit is coupled to the variable delay; and the tap selection circuit is configured to select a tap of taps of the variable delay responsive to the latency value and the longest latency. | 2014-03-27 |
20140089719 | PLANNING UNAMBIGUOUSLY ACROSS MULTIPLE TIME ZONES - A time slot of regular time length and capacity is defined in time local to a time zone. The slot is defined by a local time start timestamp and a local time end timestamp. In one aspect, upon determining that the local time end timestamp of the slot overlaps with the transition period, the time slot is prolonged beyond the transition period. The prolonged time slot is correspondingly defined by an international standard time start timestamp and an international standard time end timestamp. The prolonged time slot is generated based on the international standard time start timestamp and the international standard time end timestamp. | 2014-03-27 |
20140089720 | APPARATUS AND METHODS FOR DETERMINING LATENCY OF A NETWORK PORT - One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed. | 2014-03-27 |
20140089721 | BACKPLANE COMMUNICATION SYSTEM - The invention relates to an improved backplane communication system. In one embodiment this is accomplished by a central data processing card including at least one master central card and a plurality of slave central card, wherein each master central card and the slave central card having a first SerDes (serializer-deserializer), a first clock and a first faster local clock, a line card including a second SerDes (serializer-deserializer), a clock selection module and a second faster local clock and a serial communication channel coupling the central data processing card and the line card, wherein the master central card uses the first faster local clock to transmits the data at a rate higher than actually required, wherein the transmitted data includes a stuff data to adjust to the link data rate between the central data processing card and line card. | 2014-03-27 |
20140089722 | Single Wire Serial Interface - A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin. | 2014-03-27 |
20140089723 | SEMICONDUCTOR DEVICE, CONTROL METHOD FOR THE SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side. | 2014-03-27 |
20140089724 | SECURING CRASH DUMP FILES - In a computer storage system, crash dump files are secured without power fencing in a cluster of a plurality of nodes connected to a storage system. Upon an occurrence of a panic of a crashing node and prior to receiving a panic message of the crashing node by a surviving node loading, in the cluster, a capturing node to become active, prior to a totem token being declared lost by the surviving node, for capturing the crash dump files of the crashing node, while manipulating the surviving node to continue to operate under the assumption the power fencing was performed on the crashing node. | 2014-03-27 |