13th week of 2015 patent applcation highlights part 17 |
Patent application number | Title | Published |
20150084104 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE - Characteristics of a high electron mobility transistor are improved. A stack having an n-type contact layer (n-type AlGaN layer), an electron supply layer (undoped AlGaN layer), and a channel layer (undoped GaN layer) is formed in a growth mode over a Ga plane parallel with a [0001] crystal axis direction. Then, after turning the stack upside down so that the n-type contact layer (n-type AlGaN layer) is situated to the upper surface and forming a trench, a gate electrode is formed by way of a gate insulation film. By stacking the channel layer (undoped GaN layer) and the electron supply layer (undoped AlGaN layer) successively in a [000-1] direction, (1) normally off operation and (2) increase of withstanding voltage can easily be compatible with each other. | 2015-03-26 |
20150084105 | METHOD FOR MANUFACTURING INSULATED GATE FIELD EFFECT TRANSISTOR - An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer configured to be formed on the first interlayer insulating layer. | 2015-03-26 |
20150084106 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE DEVICE - A solid-state imaging device includes unit pixels formed on a semiconductor substrate. Each of the unit pixels includes a photoelectric converter, a floating diffusion, a pinning layer, and a pixel transistor. The pixel transistor includes a gate electrode formed on the semiconductor substrate, a source diffusion layer, and a drain diffusion layer. At least one of the source diffusion layer or the drain diffusion layer functions as the floating diffusion. The pinning layer is covered by the floating diffusion at a bottom and a side at a channel of the pixel transistor. A conductivity type of the floating diffusion is opposite to that of the pinning layer. | 2015-03-26 |
20150084107 | CAPACITOR DEVICE - In some embodiments, a capacitor device includes a metal-oxide-metal (MOM) capacitor array and a varactor array configured overlapping with the MOM capacitor array. The MOM capacitor array includes a first MOM capacitor unit. The first MOM capacitor unit includes a first electrode pattern and a second electrode pattern in a first metallization layer. The first electrode pattern includes a plurality of first fingers and a first bus interconnecting the plurality of first fingers. The second electrode pattern includes a plurality of second fingers and a second bus interconnecting the plurality of second fingers. The varactor array includes a first varactor unit. The first varactor unit includes a first electrode contacting region and a second electrode contacting region. The first electrode pattern contacts the first electrode contacting region. The second electrode pattern contacts the second electrode contacting region. | 2015-03-26 |
20150084108 | TRANSISTOR STRUCTURE AND METHOD WITH AN EPITAXIAL LAYER OVER MULTIPLE HALO IMPLANTS - A transistor structure having an epitaxial layer deposited over an implanted substrate in order to reduce process variability. The epitaxial layer is able to be deposited doped, un-doped or lightly doped via up-diffusion from the implanted substrate, and used to form the channel for the transistor structure. As a result, this use of un-doped epitaxial layer provides the benefit of reducing process variability (e.g. random dopant fluctuation) and thus the transistor performance variability despite the small physical size of the transistors. | 2015-03-26 |
20150084109 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern. | 2015-03-26 |
20150084110 | FLASH MEMORY AND FABRICATION METHOD THEREOF - A method is provided for forming a flash memory. The method includes providing a semiconductor substrate; and forming a first dielectric layer. The method also includes forming a first semiconductor layer on a surface of the first dielectric layer; and performing an ion implantation onto a portion of the first semiconductor layer corresponding to a position of a subsequently formed floating gate. Further, the method includes performing an oxygen ion implantation process onto a portion of the first semiconductor layer between the position of the subsequently formed floating gate and the position of a subsequently formed first select gate to form an oxide layer; and forming a second dielectric layer having an opening exposing the position of the first select gate. Further, the method also includes forming a second semiconductor layer on the second dielectric layer; and forming a flash cell and a select gate structure. | 2015-03-26 |
20150084111 | GUARD RING FOR MEMORY ARRAY - A device and a method for forming a device are presented. The method includes providing a substrate having an array region in which memory cells are to be formed. Storage gates of the memory cells are formed in the array region. A guard ring surrounding the array region is formed. A gate electrode layer is formed on the substrate. The gate electrode layer fills gaps between the storage gates and guard ring. The gate electrode layer is planarized to produce a planar surface between the gate electrode layer, storage gates and guard ring. The guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the storage gates across center and edge regions of the array region is uniform. | 2015-03-26 |
20150084112 | SPLIT GATE FLASH CELL SEMICONDUCTOR DEVICE - A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors. | 2015-03-26 |
20150084113 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto. | 2015-03-26 |
20150084114 | NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS - A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed. | 2015-03-26 |
20150084115 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a plurality of pillar columns, each of the plurality of pillar columns including a plurality of pillars arranged in one direction to be offset from each other, wherein an mth pillar and an (m+1)th pillar, among the plurality of pillars included in each pillar column, are aligned with each other (m is an integer of 0 or more). | 2015-03-26 |
20150084116 | DEVICES INCLUDING ULTRA-SHORT GATES AND METHODS OF FORMING SAME - Provided are devices including ultra-short gates and methods of forming same. Methods include forming a first gate pattern on a semiconductor that includes a first recess having a first width, A dielectric spacer is formed on a sidewall of the first recess to define a second recess in the first recess that has a second width that is smaller than the first width. A gate having the second width is formed in the second recess. | 2015-03-26 |
20150084117 | BOTTOM SOURCE NMOS TRIGGERED ZENER CLAMP FOR CONFIGURING AN ULTRA-LOW VOLTAGE TRANSIENT VOLTAGE SUPPRESSOR (TVS) - A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer to form a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) that comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate. The drain region interfaces with the body region constituting a junction diode. The drain region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode. The body regions further comprises a surface body contact region electrically connected to a body-to-source short-connection thus connecting the body region to the bottom electrode functioning as the source/emitter terminal. | 2015-03-26 |
20150084118 | SEMICONDUCTOR DEVICE INCLUDING A POWER TRANSISTOR DEVICE AND BYPASS DIODE - A semiconductor device includes a vertical FET device and a Schottky bypass diode. The vertical FET device includes a gate contact, a source contact, and a drain contact. The gate contact and the source contact are separated from the drain contact by at least a drift layer. The Schottky bypass diode is coupled between the source contact and the drain contact and monolithically integrated adjacent to the vertical FET device such that a voltage placed between the source contact and the drain contact is distributed throughout the drift layer by the Schottky bypass diode in such a way that a voltage across each one of a plurality of P-N junctions formed between the source contact and the drain contact within the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction. | 2015-03-26 |
20150084119 | LAYOUT CONFIGURATIONS FOR INTEGRATING SCHOTTKY CONTACTS INTO A POWER TRANSISTOR DEVICE - A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed over the substrate, a gate contact and a plurality of source contacts located on a first surface of the drift layer opposite the substrate, a drain contact located on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the one or more bypass diodes are formed by placing a Schottky metal contact on the first surface of the drift layer, such that each Schottky metal contact runs between two of the plurality of junction implants. | 2015-03-26 |
20150084120 | Charge-Compensation Semiconductor Device - An active area of a semiconductor body includes a first charge-compensation structure having spaced apart n-type pillar regions, and an n-type first field-stop region of a semiconductor material in Ohmic contact with a drain metallization and the n-type pillar regions and having a doping charge per area higher than a breakdown charge per area of the semiconductor material. A punch-through area of the semiconductor body includes a p-type semiconductor region in Ohmic contact with a source metallization, a floating p-type body region and an n-type second field-stop region. The floating p-type body region extends into the active area. The second field-stop region is in Ohmic contact with the first field-stop region, forms a pn-junction with the floating p-type body region, is arranged between the p-type semiconductor region and floating p-type body region, and has a doping charge per area lower than the breakdown charge per area of the semiconductor material. | 2015-03-26 |
20150084121 | Transistor Device with a Field Electrode - A transistor device includes a source region, a drift region, and a body region arranged between the source region and the drift region. A gate electrode is adjacent to the body region, and dielectrically insulated from the body region by a gate dielectric. A field electrode arrangement is adjacent to the drift region and the body region, spaced apart from the gate electrode in a first direction that is perpendicular to a vertical direction in which the source region and the drift region are spaced apart, and includes a field electrode and a field electrode dielectric. The field electrode dielectric dielectrically insulates the field electrode at least from the drift region. The field electrode arrangement has a first width adjacent the drift region, and a second width adjacent the body region and the first width is larger than the second width. | 2015-03-26 |
20150084122 | Semiconductor Device - A semiconductor device has an active region defined by a device isolation region arranged on a surface of a semiconductor substrate, a plurality of transistor pillars arranged along a first direction within the active region, and a first dummy pillar disposed in the device isolation region. The first dummy pillar is arranged on a line extending along the first direction from the transistor pillars. The semiconductor device also has a second dummy pillar disposed between the transistor pillars and the first dummy pillar, a gate electrode continuously extending so as to surround each of side surfaces of the transistor pillars, a first power supply gate electrode surrounding a side surface of the first dummy pillar, and a second power supply gate electrode surrounding a side surface of the second dummy pillar. The second power supply gate electrode is connected to the gate electrode and the first power supply gate electrode. | 2015-03-26 |
20150084123 | Semiconductor Device - A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess extending from an upper surface to the second semiconductor region; a control electrode, which is arranged on a region of the insulation film on a side surface of the recess; a first main electrode connected to the first semiconductor region; a second main electrode connected to the fourth semiconductor region; and a bottom electrode, which is arranged on the insulation film and is electrically connected to the second main electrode, and a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses. | 2015-03-26 |
20150084124 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having an element region and a termination region. The element region includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and first floating regions having the first conductivity type. The termination region includes FLR regions, a second drift region and second floating regions. The FLR regions have the first conductivity type and surrounds the element region. The second drift region has the second conductivity type, makes contact with and surrounds the FLR regions. The second floating regions have the first conductivity type and is surrounded by the second drift region. The second floating regions surround the element region. At least one of the second floating regions is placed at an element region side relative to the closest one of the FLR regions to the element region. | 2015-03-26 |
20150084125 | MONOLITHICALLY INTEGRATED VERTICAL POWER TRANSISTOR AND BYPASS DIODE - A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer. | 2015-03-26 |
20150084126 | LDMOS DEVICE WITH SHORT CHANNEL AND ASSOCIATED FABRICATION METHOD - A method of fabricating an LDMOS device includes: forming a gate of the LDMOS device on a semiconductor substrate; performing tilt body implantation by implanting dopants of a first conductivity type in the semiconductor substrate using a mask, wherein the tilt body implantation is implanted at an angle from a vertical direction; performing zero tilt body implantation by implanting dopants of the first conductivity type using the same mask, wherein the zero tilt body implantation is implanted with zero tilt from the vertical direction, and wherein the tilt body implantation and the zero tilt body implantation are configured to form a body region of the LDMOS device; and forming a source region and a drain contact region of the LDMOS device, wherein the source region and the drain contact region are of a second conductivity type. | 2015-03-26 |
20150084127 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - High integrity, lower power consuming semiconductor devices and methods for manufacturing the same. The semiconductor device includes: semiconductor substrate; a well region in the semiconductor substrate; an interlayer structure over the well region, the interlayer structure including a back gate conductor, semiconductor fins at both sides of the back gate conductor and respective back gate dielectric isolating the back gate conductor from the semiconductor fins, respectively, wherein the well region functions as one portion of a conductive path of the back gate conductor; a punch-through stop layer at a lower portion of the semiconductor fin; a front gate stack intersecting the semiconductor fin, the front gate stack including a front gate dielectric and a front gate conductor and the front gate dielectric isolating the front gate conductor from the semiconductor fin; and a source region and a drain region connected to a channel region provided by the semiconductor fin. | 2015-03-26 |
20150084128 | SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES WITH LOCAL HEAT DISSIPATER(S) AND METHODS - Disclosed are semiconductor-on-insulator (SOI) structures comprising an SOI device (e.g., an SOI metal oxide semiconductor field effect transistor (MOSFET)) with local heat dissipater(s). Each heat dissipater comprises an opening, which is adjacent an active region of the SOI device, which extends through the insulator layer on which the SOI device sits to the semiconductor substrate below, and which is at least partially filled with a fill material. This fill material is a thermal conductor so as to dissipate heat generated by the SOI device and is also an electrical isolator so as to minimize current leakage. In the case of MOSFET, the local heat dissipater(s) can be aligned below the source/drain extension(s) or the source/drain(s). Alternatively, the local heat dissipater(s) can be aligned below the channel or parallel and adjacent to opposing sides of the channel. Also disclosed herein are methods of forming these SOI structures. | 2015-03-26 |
20150084129 | DUMMY CELL ARRAY FOR FIN FIELD-EFFECT TRANSISTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE DUMMY CELL ARRAY - A semiconductor device includes a substrate; a device area of the substrate, the device area including a plurality of device unit cells; and a dummy cell array arranged around the device area. The dummy cell array includes a plurality of dummy unit cells repeatedly arranged in a first direction and a second direction perpendicular to the first direction, each of the dummy cell unit having a structure corresponding to a device unit cell. The device unit cell includes at least a first transistor in the device area. The structure of the dummy unit cell includes an active area and a gate line. For each dummy unit cell, the active area and the gate line extend beyond a cell boundary that defines the dummy unit cell. | 2015-03-26 |
20150084130 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing an SOI substrate, onto which a heavily doped buried layer and a surface active layer are formed; forming a gate stack and sidewall spacers on the substrate; forming an opening at one side of the gate stack, wherein the opening penetrates through the surface active layer, the heavily doped buried layer and reaches into a silicon film located on an insulating buried layer of the SOI substrate; filling the opening to form a plug; forming source/drain regions, wherein the source region overlaps with the heavily doped buried layer, and a part of the drain region is located in the plug. Accordingly, the present invention further provides a semiconductor structure. In the present invention, the heavily doped buried layer is favorable for reducing width of depletion layers at source/drain regions and suppressing short-channel effects. The heavily doped buried layer overlaps with the source region, which thence forms a heavily doped pn junction favorable for suppressing floating body effects of SOI MOS devices, thereby improving performance of semiconductor devices. Besides, no body contact is needed in the present invention, thus device area and manufacturing cost are saved. | 2015-03-26 |
20150084131 | GATE HEIGHT UNIFORMITY IN SEMICONDUCTOR DEVICES - Methods of facilitating gate height uniformity by controlling recessing of dielectric material and semiconductor devices formed from the methods are provided. The methods include, for instance, forming a transistor of the semiconductor device with an n-type transistor and a p-type transistor, the n-type transistor and the p-type transistor including plurality of sacrificial gate structures and protective masks at upper surfaces of the plurality of sacrificial gate structures; providing a dielectric material over and between the plurality of sacrificial gate structures; partially densifying the dielectric material to form a partially densified dielectric material; further densifying the partially densified dielectric material to create a modified dielectric material; and creating substantially planar surface on the modified dielectric material, to control dielectric material recess and gate height. | 2015-03-26 |
20150084132 | Silicon Nitride Layer Deposited at Low Temperature to Prevent Gate Dielectric Regrowth High-K Metal Gate Field Effect Transistors - Standard High-K metal gate (HKMG) CMOS technologies fabricated using the replacement metal gate (RMG), also known as gate-last, integration flow, are susceptible to oxygen ingress into the high-K gate dielectric layer and oxygen diffusion into the gate dielectric and semiconductor channel region. The oxygen at the gate dielectric and semiconductor channel interface induces unwanted oxide regrowth that results in an effective oxide thickness increase, and transistor threshold voltage shifts, both of which are highly variable and degrade semiconductor chip performance. By introducing silicon nitride deposited at low temperature, after the metal gate formation, the oxygen ingress and gate dielectric regrowth can be avoided, and a high semiconductor chip performance is maintained. | 2015-03-26 |
20150084133 | TUNNELING FIELD EFFECT TRANSISTOR DEVICE AND RELATED MANUFACTURING METHOD - A transistor device may include a first source portion including a first InSb material set and a first first-type dopant set. The transistor device may include a first drain portion including a second InSb material set and a first second-type dopant set. The transistor device may include a first gate and a corresponding first channel portion disposed between the first source portion and the first drain portion and including a third InSb material set. The transistor device may include a second drain portion including a first GaSb material set and a second first-type dopant set. The transistor device may include a second source portion including a second GaSb material set and a second second-type dopant set. The transistor device may include a second gate and a corresponding second channel portion disposed between the second source portion and the second drain portion and including a third GaSb material set. | 2015-03-26 |
20150084134 | FinFET-Based ESD Devices and Methods for Forming the Same - A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region. | 2015-03-26 |
20150084135 | SEMICONDUCTOR DEVICE - A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points. | 2015-03-26 |
20150084136 | MOS P-N JUNCTION DIODE WITH ENHANCED RESPONSE SPEED AND MANUFACTURING METHOD THEREOF - A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a polysilicon oxide layer, a central conductive layer, ion implantation layer, a channel region, and a metallic sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer, and a polysilicon oxide layer formed on the polysilicon structure. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. An ion implantation layer is formed within the guard ring and the central conductive layer. Afterwards, a metallic sputtering layer is formed, and the mask layer is partially exposed. | 2015-03-26 |
20150084137 | MECHANISM FOR FORMING METAL GATE STRUCTURE - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode. | 2015-03-26 |
20150084138 | INTEGRATED CIRCUIT HAVING VARYING SUBSTRATE DEPTH AND METHOD OF FORMING SAME - A semiconductor device is formed such that a semiconductor substrate of the device has a non-uniform thickness. A cavity is etched at a selected side of the semiconductor substrate, and the selected side is then fusion bonded to another substrate, such as a carrier substrate. After fusion bonding, the side of the semiconductor substrate opposite the selected side is ground to a defined thickness. Accordingly, the semiconductor substrate has a uniform thickness except in the area of the cavity, where the substrate is thinner. Devices that benefit from a thinner substrate, such as an accelerometer, can be formed over the cavity. | 2015-03-26 |
20150084139 | DEVICE, SYSTEM AND METHOD FOR PROVIDING MEMS STRUCTURES OF A SEMICONDUCTOR PACKAGE - Techniques and mechanisms for providing precisely fabricated structures of a semiconductor package. In an embodiment, a build-up carrier of the semiconductor package includes a layer of porous dielectric material. Seed copper and plated copper is disposed on the layer of porous dielectric material. Subsequent etching is performed to remove copper adjacent to the layer of porous dielectric material, forming a gap separating a suspended portion of a MEMS structure from the layer of porous dielectric material. In another embodiment, the semiconductor package includes a copper structure disposed between portions of an insulating layer or portions of a layer of silicon nitride material. The layer of silicon nitride material couples the insulating layer to another insulating layer. One or both of the insulating layers are each protected from desmear processing with a respective release layer structure. | 2015-03-26 |
20150084140 | LANDING PAD IN PERIPHERAL CIRCUIT FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) - The present invention is directed to a memory device having a via landing pad in the peripheral circuit that minimizes the memory cell size. A device having features of the present invention comprises a peripheral circuit region and a magnetic memory cell region including at least a magnetic tunnel junction (MTJ) element. The peripheral circuit region comprises a substrate and a bottom contact formed therein; a landing pad including a first magnetic layer structure formed on top of the bottom contact and a second magnetic layer structure separated from the first magnetic layer structure by an insulating tunnel junction layer, wherein each of the insulating tunnel junction layer and the second magnetic layer structure has an opening aligned to each other; and a via partly embedded in the landing pad and directly coupled to the first magnetic layer structure through the openings. | 2015-03-26 |
20150084141 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a MRAM chip including a semiconductor substrate and a memory cell array area includes magnetoresistive elements which are provided on the semiconductor substrate, and a magnetic shield layer surrounding the memory cell array area in a circumferential direction of the MRAM chip, and having a closed magnetic path. | 2015-03-26 |
20150084142 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY USING THE SAME - According to one embodiment, a magnetoresistive element includes first and second magnetic layers and a first nonmagnetic layer. The first magnetic layer has an axis of easy magnetization perpendicular to a film plane, and a variable magnetization. The second magnetic layer has an axis of easy magnetization perpendicular to a film plane, and an invariable magnetization. The first nonmagnetic layer is provided between the first and second magnetic layers. The second magnetic layer includes third and fourth magnetic layers, and a second nonmagnetic layer formed between the third and fourth magnetic layers. The third magnetic layer is in contact with the first nonmagnetic layer and includes Co and at least one of Zr, Nb, Mo, Hf, Ta, and W. | 2015-03-26 |
20150084143 | WAVEGUIDE-COUPLED MSM-TYPE PHOTODIODE - A waveguide-coupled MSM-type photodiode of the present invention comprises a structure in which a semiconductor light-absorbing layer and an optical waveguide core layer are adjacent and optically coupled to each other, has formed metal-semiconductor-metal (MSM) junctions which are arranged at an interval on the semiconductor light-absorbing layer, and is characterized in that of the MSM electrodes arranged at the interval, a voltage is set so that a reverse bias is applied to those MSM electrodes that are arranged on a light incidence side. | 2015-03-26 |
20150084144 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING A SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - Disclosed is a solid-state imaging device including a plurality of pixels and a plurality of on-chip lenses. The plurality of pixels are arranged in a matrix pattern. Each of the pixels has a photoelectric conversion portion configured to photoelectrically convert light incident from a rear surface side of a semiconductor substrate. The plurality of on-chip lenses are arranged for every other pixel. The on-chip lenses are larger in size than the pixels. Each of color filters at the pixels where the on-chip lenses are present has a cross-sectional shape whose upper side close to the on-chip lens is the same in width as the on-chip lens and whose lower side close to the photoelectric conversion portion is shorter than the upper side. | 2015-03-26 |
20150084145 | OPTICAL SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING THE SAME - A disclosed optical semiconductor element includes: a semiconductor substrate having a first main surface and a second main surface in which a plurality of first grooves are formed; a first optical waveguide defined by portions of the semiconductor substrate between the first grooves and having side faces defined by the first grooves; and a photoelectric converter configured to transmit or receive an optical signal propagating through the first optical waveguide. Moreover, the first grooves define part of a guide hole. | 2015-03-26 |
20150084146 | BACKSIDE ILLUMINATION IMAGE SENSOR AND IMAGE-CAPTURING DEVICE - A backside illumination image sensor that includes a semiconductor substrate with a plurality of photoelectric conversion elements and a read circuit formed on a front surface side of the semiconductor substrate, and captures an image by outputting, via the read circuit, electrical signals generated as incident light having reached a back surface side of the semiconductor substrate is received at the photoelectric conversion elements includes: a light shielding film formed on a side where incident light enters the photoelectric conversion elements, with an opening formed therein in correspondence to each photoelectric conversion element; and an on-chip lens formed at a position set apart from the light shielding film by a predetermined distance in correspondence to each photoelectric conversion element. The light shielding film and an exit pupil plane of the image forming optical system achieve a conjugate relation to each other with regard to the on-chip lens. | 2015-03-26 |
20150084147 | IMAGE PICKUP MODULE AND METHOD FOR MANUFACTURING IMAGE PICKUP MODULE - The present invention achieves reduction in size and thickness while removing the cause of defective image and the like. According to an image pickup module ( | 2015-03-26 |
20150084148 | Low Profile Sensor Package With Cooling Feature And Method Of Making Same - A sensor device and method of making same that includes a silicon substrate with opposing first and second surfaces, a sensor formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the sensor, and a plurality of cooling channels formed as first trenches extending into the second surface but not reaching the first surface. The cooling channels instead can be formed on one or more separate substrates that are attached to the silicon substrate for cooling the silicon substrate. | 2015-03-26 |
20150084149 | RADIATION DETECTOR AND RADIATION DETECTION APPARATUS - A radiation detector according to an embodiment includes: a semiconductor substrate; a light detecting unit provided on a side of a first surface of the semiconductor substrate; a first insulating film provided covering the light detecting unit; a second insulating film covering the first insulating film; a scintillator provided on the second insulating film; an interconnection provided between the first and second insulating films, and connected to the light detecting unit; a first electrode connected to the interconnection through a bottom portion of the first opening; a second electrode provided on a region in the second surface of the semiconductor substrate, the region opposing at least a part of the light detecting unit; a second opening provided in a region surrounding the first electrode and not surrounding the second electrode; and an insulating resin layer covering the first and second electrodes and the first and second openings. | 2015-03-26 |
20150084150 | BALL GRID ARRAY PACKAGED CAMERA DEVICE SOLDERED TO A SUBSTRATE - An assembly that attaches a ball grid array (BGA) packaged camera device to a printed circuit board (PCB) substrate is provided. The assembly includes a spacer between the device and the substrate. The spacer is configured to prevent excessive collapse of solder balls located between the device and the substrate during reflow of the solder balls. The spacer includes one of solder mask, tape, and/or legend ink. | 2015-03-26 |
20150084151 | PHOTOELECTRIC CONVERSION ELEMENT AND METHOD OF MANUFACTURING THE SAME - A photoelectric conversion element includes a first electrode, a ferroelectric layer provided on the first electrode, and a second electrode provided on the ferroelectric layer, the second electrode being a transparent electrode, and a pn junction being formed between the ferroelectric layer and the first electrode or the second electrode. | 2015-03-26 |
20150084152 | PHOTODIODE - A photodiode includes a first-type substrate. A second-type doped well and a second-type doped region are formed in the first-type substrate. An isolation region is formed to enclose the peripheral side of the second-type doped well, and separated from the second-type doped well. The second-type doped region is formed in the second-type doped well and extends from the surface of the second-type doped well. A protective layer covers the first-type substrate. A contact conductor including a contact layer and a conductive strip penetrates through the protective layer. The contact layer is formed on the bottom end of the conductive strip and in contact with the second-type doped region to make an electrical connection. | 2015-03-26 |
20150084153 | SCHOTTKY DEVICE AND METHOD OF MANUFACTURE - A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalk and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed in at least one trench, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the dope region with the multi-concentration impurity profile. | 2015-03-26 |
20150084154 | Methods and Apparatus for ESD Structures - Methods and apparatus for ESD structures. A semiconductor device includes a first active area containing an ESD cell coupled to a first terminal and disposed in a well; a second active area in the semiconductor substrate, the second active area comprising a first diffusion of the first conductivity type for making a bulk contact to the well; and a third active area in the semiconductor substrate, separated from the first and second active areas by another isolation region, a portion of the third active area comprising an implant diffusion of the first conductivity type within a first diffusion of the second conductivity type and adjacent a boundary with the well of the first conductivity type; wherein the third active area comprises a diode coupled to the terminal and reverse biased with respect to the well of the first conductivity type. | 2015-03-26 |
20150084155 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for fabricating a semiconductor device includes defining a curved active region by forming a plurality of trenches over a semiconductor substrate, forming an insulating layer to fill the plurality of trenches, and forming a pair of gate lines crossing the curved active region, so that it is possible to prevent leaning of an active region by forming a curved active region. | 2015-03-26 |
20150084156 | MEMORY CELL WITH INDEPENDENTLY-SIZED ELECTRODE - Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode. | 2015-03-26 |
20150084157 | ELECTRONIC STRUCTURE, A BATTERY STRUCTURE, AND A METHOD FOR MANUFACTURING AN ELECTRONIC STRUCTURE - According to various embodiments, an electronic structure may be provided, the electronic structure may include: a semiconductor carrier, and a battery structure monolithically integrated with the semiconductor carrier, the battery structure including a plurality of thin film batteries. | 2015-03-26 |
20150084158 | THREE DIMENSIONAL CIRCUIT INCLUDING SHIELDED INDUCTOR AND METHOD OF FORMING SAME - The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier. | 2015-03-26 |
20150084159 | Semiconductor Device and Manufacturing Method Thereof - The present invention is capable of suppressing a variation in the characteristics of a semiconductor device. In a conductor pattern CPA and a conductor pattern CPB arranged so as to run side by side with each other, the conductor pattern CPA is divided into a first portion P | 2015-03-26 |
20150084160 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A ferroelectric capacitor formed above a semiconductor substrate includes a lower electrode, a dielectric film (ferroelectric film) having ferroelectric characteristics, and an upper electrode. The upper electrode includes a conductive oxide film made of a ferroelectric material to which conductivity is provided by adding a conductive material such as Ir, and the conductive oxide film is in contact with the dielectric film. | 2015-03-26 |
20150084161 | MIXED MODE RC CLAMPS - A system interconnect includes a first resistor-capacitor (RC) clamp having a first RC time constant. The system interconnect also includes second RC clamps having a second RC time constant. The first and second RC clamps are arranged along the system interconnect. In addition, the first RC time constant is different from the second RC time constant. | 2015-03-26 |
20150084162 | ELECTRONIC DEVICE INCLUDING A DIODE AND A PROCESS OF FORMING THE SAME - An electronic device can include a substrate, lower and upper semiconductor layers over the substrate, and a doped region at the interface between the lower and upper semiconductor layers. The doped region can have a conductivity type opposite that of a dopant within the lower semiconductor layer. Within the lower semiconductor layer, the dopant can have a dopant concentration profile that has a relatively steeper portion adjacent to the substrate, another relatively steeper portion adjacent to an interface between the first and second semiconductor layers, and a relatively flatter portion between the relative steeper portions. A diode lies at a pn junction where a second dopant concentration profile of the first doped region intersects the relatively flatter portion of the first dopant concentration profile. The electronic device can be formed using different processes described herein. | 2015-03-26 |
20150084163 | EPITAXIAL SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides an epitaxial substrate including a silicon substrate containing oxygen atoms in concentrations of 4×10 | 2015-03-26 |
20150084164 | SEMICONDUCTOR DEVICE - The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented. | 2015-03-26 |
20150084165 | STACKED MICROELECTRONIC DICE EMBEDDED IN A MICROELECTRONIC SUBSTRATE - Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material. | 2015-03-26 |
20150084166 | Semiconductor Device Having Plural Memory Chip - A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions. | 2015-03-26 |
20150084167 | EBG STRUCTURE, SEMICONDUCTOR DEVICE, AND CIRCUIT BOARD - An EBG structure of an embodiment includes an electrode plane, a first insulating layer provided on the electrode plane, a first metal patch provided on the first insulating layer, a second metal patch provided on the first insulating layer, a second insulating layer provided on the first and second metal patches, an interconnect layer provided on the second insulating layer, a third insulating layer provided on the interconnect layer, a first via connected to the electrode plane and the first metal patch, and a second via connected to the electrode plane and the second metal patch. The second metal patch is separately adjacent to the first metal patch. The interconnect layer has a first opening and a second opening. The first via penetrates through the first opening. The second via penetrates through the second opening. | 2015-03-26 |
20150084168 | PACKAGE ENCAPSULANT RELIEF FEATURE - A microelectronic device package including a package substrate, microelectronic component disposed on a first surface of a first portion of the substrate, and encapsulant material surrounding the microelectronic electronic component. An exposed surface of the first portion of the substrate is exposed through an opening in a first major surface of the encapsulant material. The exposed surface of the first portion has an edge. Encapsulant material is adjacent to the edge at the first major surface. The exposed surface is opposite the first surface. A stress relief feature located in one of the first major surface or a second major surface of the encapsulant material. The second major surface is opposite the first major surface. The stress relief feature reduces an amount of the encapsulant material and is 1 mm or less of a plane of the edge of the exposed surface. The plane is generally perpendicular to the exposed surface. | 2015-03-26 |
20150084169 | SEMICONDUCTOR PACKAGE WITH STRESS RELIEF AND HEAT SPREADER - A semiconductor device has a die mounted on a die paddle that is elevated above and thermally connected via tie bars to a heat sink structure. Heat generated by the die flows from the die to the die paddle to the tie bars to the heat sink structure and then to either the external environment or to an external heat sink. By elevating the die/paddle sub-assembly above the heat sink structure, the packaged device is less susceptible to delamination between the die and die attach adhesive and/or the die attach adhesive and the die paddle. An optional heat sink ring can surround the die paddle. | 2015-03-26 |
20150084170 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package including a lower package, an interposer on the lower package, and an upper package on the interposer. The lower package may include a lower package substrate, a lower semiconductor chip on the lower package substrate, and a lower heat-transfer layer on the lower semiconductor chip. The interposer may include an interposer substrate, first and second heat-transfer openings defined by recessed bottom and top surfaces, respectively, of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad. The upper package may include an upper package substrate, an upper package heat-transfer pad, which may be disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate. | 2015-03-26 |
20150084171 | NO-LEAD SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A non-lead (QFN) semiconductor package is disclosed. The package includes a die attach pad and a semiconductor die supported by the die attached pad. The semiconductor die includes a plurality of pads on an active surface thereof. The package further includes a plurality of terminal leads, an encapsulant that encapsulates the semiconductor die, and a redistribution layer including a plurality of interconnections electrically connecting the pads to the terminal leads. A method of making the package is also disclosed. | 2015-03-26 |
20150084172 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SIDE SOLDERABLE LEADS AND METHOD OF MANUFACTURE THEREOF - A system and method of manufacture of an integrated circuit packaging system includes: a leadframe having a side solderable lead with a half-etched lead portion and a lead top side; a mold body directly on the leadframe and the side solderable lead, the lead top side of the side solderable lead exposed from the mold body; a mold groove in the mold body and in a portion of the side solderable lead for exposing a lead protrusion of the side solderable lead on an upper perimeter side of the mold body; and the half-etched lead portion exposed from a lower perimeter side of the mold body. | 2015-03-26 |
20150084173 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device having a converter circuit, a brake circuit and an inverter circuit and manufacturable by a simplified manufacturing process. the semiconductor device has a plurality of die pads, IGBTs, diodes, freewheel diodes, an HVIC and LVICs mounted on the plurality of die pads, a plurality of leads, and an encapsulation resin body that covers these component parts. In a manufacturing process, a single-plate lead frame having the above-described plurality of die pads and leads connected together can be prepared. The semiconductor device may be manufactured by using this single-plate lead frame. | 2015-03-26 |
20150084174 | SEMICONDUCTOR DEVICE LEADFRAME - For so called film assisted moulding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion. | 2015-03-26 |
20150084175 | SEMICONDUCTOR DEVICE LEADFRAME - For so called film assisted moulding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion. | 2015-03-26 |
20150084176 | HIGH EFFICIENCY MODULE | 2015-03-26 |
20150084177 | LEAD FRAME FOR MOUNTING LED ELEMENTS, LEAD FRAME WITH RESIN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES, AND LEAD FRAME FOR MOUNTING SEMICONDUCTOR ELEMENTS - A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region. | 2015-03-26 |
20150084178 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SPREADER AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system, and method of manufacture therefor, includes: a substrate; a mold cap formed on the substrate; fiducial mark inscribed in the mold cap; a thermal interface material applied over the substrate and referenced by the fiducial mark; and a heat spreader, mounted on the thermal interface material, precisely positioned by a position notch aligned relative to the fiducial mark. | 2015-03-26 |
20150084179 | SEMICONDUCTOR MODULE - A power semiconductor chip and a low-power portion that has power consumption lower than that of the power semiconductor chip are located on a predetermined surface side of a heat sink having conductivity. A first plate-shaped insulating member extends between the power semiconductor chip and the heat sink. A second plate-shaped insulating member extends between the low-power portion and the heat sink. A portion, which faces the low-power portion, of the second plate-shaped insulating member is thicker than a portion, which faces the power semiconductor chip, of the first plate-shaped insulating member. | 2015-03-26 |
20150084180 | SEMICONDUCTOR DEVICE INCLUDING HEAT DISSIPATING STRUCTURE - A semiconductor device includes a substrate serving as a base and having a surface on which electrodes are provided, a semiconductor chip mounted to the surface of the substrate, a sealing portion sealing the semiconductor chip and the surface of the substrate, first vias each penetrating the sealing portion in a thickness direction of the sealing portion to reach the electrodes on the surface of the substrate, external terminals connected to the first vias, and second vias provided near the semiconductor chip, extending to such a depth that the second vias do not penetrate the sealing portion, and insulated from the substrate and the semiconductor chip. | 2015-03-26 |
20150084181 | 3DIC Package Comprising Perforated Foil Sheet - A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS. | 2015-03-26 |
20150084182 | COOLING ASSEMBLY USING HEATSPREADER - Various embodiments relate to a microchip die cooling assembly comprising a circuit board; a microchip having an exposed die attached to the circuit board; a heatspreader having a top side and a bottom side; a heat sink having a bottom side and a top side comprising a cooling structure; a first thermal interface material in contact with the exposed die and the bottom side of the heatspreader; and a second thermal interface material in contact with the top side of the heat spreader and the bottom side of the heat sink. | 2015-03-26 |
20150084183 | INTEGRATED CIRCUITS WITH PROTECTED RESISTORS AND METHODS FOR FABRICATING THE SAME - Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided. | 2015-03-26 |
20150084184 | SEMICONDUCTOR DEVICE - A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern. | 2015-03-26 |
20150084185 | SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR DIE EMBEDDED BETWEEN AN EXTENDED SUBSTRATE AND A BOTTOM SUBSTRATE - A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive. | 2015-03-26 |
20150084186 | BUMP STRUCTURE HAVING A SINGLE SIDE RECESS - A bump structure includes a first end, and a second end opposite the first end. The bump structure further includes a first side connected between the first end and the second end. The bump structure further includes a second side opposite the first side. The second side is connected between the first end and the second end, and the second side comprises a recess for a reflowed solder material to fill. | 2015-03-26 |
20150084187 | METHODS OF FORMING HYDROPHOBIC SURFACES ON SEMICONDUCTOR DEVICE STRUCTURES, METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND SEMICONDUCTOR DEVICE STRUCTURES - A method of forming a hydrophobic surface on a semiconductor device structure. The method comprises forming at least one structure having at least one exposed surface comprising titanium atoms. The at least one exposed surface of at least one structure is contacted with at least one of an organo-phosphonic acid and an organo-phosphoric acid to form a material having a hydrophobic surface on the at least one exposed surface of the least one structure. A method of forming a semiconductor device structure and a semiconductor device structure are also described. | 2015-03-26 |
20150084188 | STACKABLE MOLDED MICROELECTRONIC PACKAGES - A microelectronic package has a microelectronic element and conductive posts or masses projecting above a surface of the substrate. Conductive elements at a surface of the substrate opposite therefrom are electrically interconnected with the microelectronic element. An encapsulant overlies at least a portion of the microelectronic element and may be in contact with the conductive posts or masses. The encapsulant may have openings permitting electrical connections with the conductive posts or masses. The openings may partially expose conductive masses joined to posts, fully expose top surfaces of posts and partially expose edge surfaces of posts, or may partially expose top surfaces of posts. | 2015-03-26 |
20150084189 | FORMATION OF THROUGH-SILICON VIA (TSV) IN SILICON SUBSTRATE - To form a through-silicon via (TSV) in a silicon substrate without using plating equipment or using sputtering equipment or small metal particles, and form an interlayer connection by stacking a plurality of such silicon substrates, a through hole of a silicon substrate is filled using molten solder itself. In detail, solid solder placed above the through hole of the silicon substrate is molten and the molten solder is guided to and filled in the internal space. A metal layer can be deposited on an internal surface of the through hole beforehand, and also an intermetallic compound (IMC) can be formed in a portion other than the metal layer. | 2015-03-26 |
20150084190 | Multi-Chip Package Structure and Method of Forming Same - A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least one V-shaped via and a plurality of bumps formed on and electrically coupled to the interconnect structures. | 2015-03-26 |
20150084191 | Multi-Chip Package and Method of Formation - A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar and a plurality of bumps formed on and electrically coupled to the interconnect structures. | 2015-03-26 |
20150084192 | TALL SOLDERS FOR THROUGH-MOLD INTERCONNECT - Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate. | 2015-03-26 |
20150084193 | EMBEDDED ON-CHIP SECURITY - Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs. The random electrical connections between MOSFETs are utilized for generation of unique keys for purposes such as authentication or identification. | 2015-03-26 |
20150084194 | PACKAGE VIAS FOR RADIO FREQUENCY ANTENNA CONNECTIONS - Via are described for radio frequency antenna connections related to a package. In one example, a package has a package substrate, a die attached to the package substrate, and a conductive via from the package substrate to an external surface of the package to make a radio frequency connection between the antenna and the package substrate. | 2015-03-26 |
20150084195 | SEMICONDUCTOR DEVICE HAVING FEATURES TO PREVENT REVERSE ENGINEERING - An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device. | 2015-03-26 |
20150084196 | Devices Formed With Dual Damascene Process - Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask. | 2015-03-26 |
20150084197 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer. | 2015-03-26 |
20150084198 | INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES - A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1. | 2015-03-26 |
20150084199 | Copper Ball Bond Features and Structure - An integrated circuit wire bond connection is provided having an aluminum bond pad ( | 2015-03-26 |
20150084200 | IMPRINTED MULTI-LEVEL MICRO-WIRE CIRCUIT STRUCTURE METHOD - A method of making a multi-level micro-wire structure includes imprinting first micro-channels in a curable first layer over a substrate with a first stamp, curing the first layer, and locating and curing a curable conductive ink in the first micro-channels to form first micro-wires. Second micro-channels are imprinted in a curable second layer in contact with the first layer with a second stamp, the second layer is cured, and a curable conductive ink is located and cured in the second micro-channels to form second micro-wires. At least one of the second micro-channels contacts at least one first micro-wire and a second micro-wire in at least one of the second micro-channels is in electrical contact with at least one first micro-wire. | 2015-03-26 |
20150084201 | IMPRINTED MICRO-WIRE CIRCUIT MULTI-LEVEL STAMP METHOD - A method of making a multi-level micro-wire structure includes imprinting first micro-channels in a curable first layer over a substrate, curing the first layer, and locating and curing a curable conductive ink in the first micro-channels to form first micro-wires. Multi-level second micro-channels are imprinted in a curable second layer in contact with the first layer with a multi-level stamp, the second layer is cured, and a curable conductive ink is located and cured in the multi-level second micro-channels to form multi-level second micro-wires. At least one of the multi-level second micro-channels contacts at least one first micro-wire. A multi-level second micro-wire in at least one of the multi-level second micro-channels is in electrical contact with at least one first micro-wire. | 2015-03-26 |
20150084202 | DIE EDGE SIDE CONNECTION - An apparatus comprises a first integrated circuit (IC) die that includes a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, a second IC die including a top layer, a bottom surface, a sidewall surface extending from a top surface of the top layer to the bottom surface, and at least one multi-surface contact pad, wherein the second IC die is arranged adjacent to the first IC die, and includes an electrically conductive bond in contact with at least one of the top surface or the side surface of the multi-surface contact pad of the first IC die and the top surface of the multi-surface contact pad of the second IC die. | 2015-03-26 |
20150084203 | CONTACT STRUCTURE AND FORMING METHOD - A method for forming a contact structure includes forming a stack of alternating active layers and insulating layers. The stack includes first and second sub stacks each with active layers separated by insulating layers. The active layers of each sub stack include an upper boundary active layer. A sub stack insulating layer is formed between the first and second sub stacks with an etching time different from the etching times of the insulating layers for a given etching process. The upper boundary active layers are accessed, after which the remainder of the active layers are accessed to create a stairstep structure of landing areas on the active layers. Interlayer conductors are formed to extend to the landing areas, the interlayer conductors separated from one another by insulating material. | 2015-03-26 |