13th week of 2009 patent applcation highlights part 13 |
Patent application number | Title | Published |
20090078907 | COMPOSITE VALVE ASSEMBLY FOR AIRCRAFT ENVIRONMENTAL CONTROL SYSTEMS - A valve assembly is provided including an injection molded flow body having at least one inlet port, at least one outlet port, and a flow passage there between. The injection molded flow body is formed of a high performance engineering thermoplastic resin. A plurality of reinforcement fibers may be homogeneously suspended in the high performance engineering thermoplastic resin and provide increased strength and temperature capability for use in high temperature applications. | 2009-03-26 |
20090078908 | POLISHING LIQUID - A polishing liquid for polishing a barrier layer of a semiconductor integrated circuit, which liquid includes: a quaternary ammonium cation; a corrosion inhibiting agent; a polymer compound having a sulfo group at a terminal; inorganic particles; and an organic acid, the pH of the polishing liquid being in the range of 1 to 7. | 2009-03-26 |
20090078909 | Method for storing hydrogen - An object is to provide a method for storing hydrogen that allows hydrogen to be easily stored and easily released, and the method comprises cooling a liquid mixture of a carbon compound capable of forming a molecular compound and a protic polar solvent while bringing hydrogen into contact with the liquid mixture, to form thereby a solid substance having hydrogen enclosed therein; as a result, the carbon compound capable of forming a molecular compound becomes caged in a clathrate that does not readily enclose hydrogen, unless under ultrahigh pressure; the carbon compound forms a molecular compound with the hydrogen, while a clathrate capable of enclosing the hydrogen therein under high-pressure conditions also forms a hydrogen clathrate, thereby allowing to increase hydrogen storage density; and the hydrogen can be stored thus by maintaining the state of the solid substance, and can be easily extracted by simply dissolving the solid substance in water. | 2009-03-26 |
20090078910 | FUNCTIONALIZED LONG-CHAIN OLEFIN MIXTURES AND USES THEREFOR - Novel mixtures of long-chain (C10-C20) olefins are functionalized by conversion to aldehydes using an OXO process, or to sulfates, sulfonates, sulfones, sulfides, or sulfoxides by direct sulfonation. The aldehydes may then be hydrogenated to form alcohols, or aminated to form amines or amides. The olefins starting mixture may be acquired as a byproduct of the tetramerization of ethylene in the presence of certain chromium-containing tetramerization catalysts. The functionalized mixtures, and derivatives prepared therefrom such as alkoxylates prepared from the alcohols, may be useful as surfactants that may offer improved performance in many applications, while their preparation based on a byproduct mixture reduces their cost and also reduces waste-handling issues for this non-targeted stream. | 2009-03-26 |
20090078911 | CHLORINE DIOXIDE GENERATING COMPOSITION - A chlorine dioxide generating composition capable of generating chlorine dioxide through reaction between a chlorite and an acid. The composition contains a solid form chlorite, a solid form acid, and a solid form, moisture slow-release agent capable of slowly releasing moisture retained therein. | 2009-03-26 |
20090078912 | Method For Determining Carbon Content Of A Hydrocarbon-Containing Mixture - A method for determining a carbon content value of a hydrocarbon-containing mixture. At least one composition-dependent bulk property of the hydrocarbon-containing mixture is measured and optionally at least one non-hydrocarbon component concentration is measured with the resulting measurements used in a carbon content correlation for calculating the carbon content of the hydrocarbon-containing mixture. The carbon content may be used in a hydrogen and/or synthesis gas production process for calculating a target flow rate of steam to be combined with the hydrocarbon-containing mixture to form a mixed feed having a target steam-to-carbon ratio. | 2009-03-26 |
20090078913 | CARBONACEOUS MATERIALS - A carbonaceous material is derived from a polysaccharide by carbonisation. The polysaccharide is preferably a starch. The carbonaceous material has mesoporosity and is useful as a solid catalytic support. | 2009-03-26 |
20090078914 | Methods and devices for electrophoretic deposition of a uniform carbon nanotube composite film - Methods and devices are provided relating to the homogeneous deposition of a composite film of carbon nanotubes by electrophoresis. The methods comprise linking carbon nanotubes to matrix particles prior to electrophoretic deposition. The methods improve the adhesion of the composite film to the substrate and reduce the surface roughness. Carbon nanotube films and electron field emission cathodes fabricated by this process demonstrate enhanced electron field emission characteristics. | 2009-03-26 |
20090078915 | Nonaqueous conductive nanoink composition - The present invention relates to a non-aqueous conductive nanoink composition including 20 to 85 parts by weight of metal nanoparticles which is chosen from silver, copper, nickel, platinum, palladium, and gold; 0.5 to 10 parts by weight of a polymer having an anhydride group; 15 to 80 parts by weight of a non-aqueous organic solvent. | 2009-03-26 |
20090078916 | TANTALUM CARBIDE NITRIDE MATERIALS BY VAPOR DEPOSITION PROCESSES - Embodiments of the invention generally provide compositions of tantalum carbide nitride materials. In one embodiment, a composition of a tantalum carbide nitride material is provided which includes the chemical formula of TaC | 2009-03-26 |
20090078917 | ELECTROCHROMIC ELECTROLYTE BLENDS - The present invention is directed to electrochromic electrolyte polymer blends. These blends comprise an amorphous polymer and an electrochromophore component. The electrochromophore component comprises a polyalkylene polymer copolymerized with an electrochromic moiety. The blends can be used to make elastomeric films and coatings that can be used in laminates, which can be used to form manufactured articles such as architectural and vehicular glazing, eyewear, displays and signage. | 2009-03-26 |
20090078918 | Methods and Structures With Fire Retardant Spheres for Implementing Enhanced Fire Protection - A method and fire retardant structures including fire retardant spheres are provided for implementing enhanced fire protection. A selected first fire retardant material is encapsulated in microspheres. The microspheres have a predefined melting temperature within a defined temperature range. The fire retardant structure is formed of the microspheres encapsulating the selected fire retardant material and included in an article being produced. In response to a fire event, the microspheres rupture or decompose releasing the encapsulated material to provide fire suppression. Alternatively, a fire retardant structure is formed of second microspheres having predefined expansion characteristics. A layer of the second microspheres is disposed between two layers of an article being produced. In response to a thermal fire event, the microspheres expand to fill the space between the layers, providing fire suppression | 2009-03-26 |
20090078919 | Support device - A support device comprises a base including a receiving portion disposed on the top of one side thereof for receiving a post which allows to hold a heavy object, a stopping mechanism defined between the post and the base and including teeth arranged on one side of the post, the base also including a rotatable engaging member affixed thereon for correspondingly engaging with the teeth, wherein the base further includes a pedal fitted in another side thereof so as to move vertically. Besides, between the pedal and the post is defined with a transmitting mechanism including a rotatable wheel pivotally disposed on the base and having a chain, one end of which is coupled to the bottom of the post, and another end of which is connected to the pedal, mounted thereon, such that while the pedal moves vertically, the post is urged to move vertically as well, thereby obtaining a quick and safe operation. | 2009-03-26 |
20090078920 | Rigid Telescopic Mechanism - Rigid telescopic mechanism comprised of rigid members and revolute joints in a geometric arrangement which allows for the longitudinal expansion of the mechanism which is characterized by the attribute that the end-member as well as some intermediate members are moving straight and parallel to themselves as well as by the property of the whole structure (a) not to shrink across the transverse direction while the mechanism extends and (b) to possess members which during the extension do not tend to align along the longitudinal axis of the expansion but maintain, instead, diagonal-oblique directions, thus participating in the raising of resistance against transverse and bending loads, consequently reducing the compressive and tensile stresses in the elements of the mechanism (members and joints). Mechanisms of this kind are employed (a) for approaching remote points in space by mechanical means, with the objective of transporting objects, or bearing loads, or moving tools between a base and a remote location whose position may be stationary or variable, (b) for exerting forces and moments at various points located at various distances away from the mechanism's base, (c) in robotic arms with links of varying length, (d) in outer space applications. | 2009-03-26 |
20090078921 | CABLE PULLER WITH PIVOT ADJUSTER FOR CONVERTING BETWEEN UPWARD AND DOWNWARD CABLE PULLING - A puller head and cable puller including the puller head are provided for pulling cable in an upward or a downward direction. The puller head includes a frame, a capstan mounted to the frame, and first and second retaining shaft apertures. The puller head is pivotally mounted to a boom of the cable puller through a pivot shaft. The capstan of the puller head is positioned rearward of the boom. The position of an upper most surface of the capstan relative to the boom is changed by pivoting the puller head between upward and downward pulling positions. The puller head is maintained in either the upward or downward pulling position through the use of a retaining shaft. | 2009-03-26 |
20090078922 | FIBER CABLE MADE OF HIGH-STRENGTH SYNTHETIC FIBERS FOR A HELICOPTER RESCUE WINCH - A fiber cable for helicopter rescue winches includes a plurality of load-bearing synthetic-fiber strands braided with one another, at least one electrically conductive insert, and a wear indicator providing a visual check of a state of the fiber cable. | 2009-03-26 |
20090078923 | Pocket Rail Construction - A rail structure for use as part of a fence construction. The rail has a rigid support member enclosed by a sleeve, the sleeve having a groove or channel extending along its longitudinal length and a hollow chamber for receiving the support member therein. The channel is dimensioned to receive a plurality of slats disposed in spaced relation to one another such that when received in the channels of opposed rails a fence section is formed. Various modifications to the basic rail structure permit construction of a privacy or containment fence section that may include a plurality of vertical segments, including for example lattice work. | 2009-03-26 |
20090078924 | Phase Change Memory with Various Grain Sizes - A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size. | 2009-03-26 |
20090078925 | Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication - A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers. | 2009-03-26 |
20090078926 | PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed. | 2009-03-26 |
20090078927 | Composite hard mask for the etching of nanometer size magnetic multilayer based device - A composite hard mask is disclosed that enables sub-100 nm sized MTJ cells to be formed for advanced devices such as spin torque MRAMs. The hard mask has a lower non-magnetic metallic layer such as Ru to magnetically isolate an overlying middle metallic spacer such as MnPt from an underlying free layer. The middle metallic spacer provides a height margin during subsequent processing to avoid shorting between a bit line and the MTJ cell in the final device. An upper conductive layer may be made of Ta and is thin enough to allow a MTJ pattern in a thin overlying photoresist layer to be transferred through the Ta during a fluorocarbon etch without consuming all of the photoresist. The MTJ pattern is transferred through the remaining hard mask layers and underlying MTJ stack of layers with a second etch step using a C, H, and O etch gas composition. | 2009-03-26 |
20090078928 | LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, AND INFORMATION DISPLAY DEVICE - A light-emitting device has a structure in which a semiconductor or a conductive substrate having a bottom electrode, a layer for generating hot electrons, quasi-ballistic electrons or ballistic electrons, a luminous layer, and a semitransparent surface electrode are deposited, or a structure in which a holes supply layer is provided between the luminous layer and the semitransparent surface electrode having the same structure. The light-emitting device realizes highly efficient light emission in a range from infrared rays to ultraviolet ray with smaller driving current than that of conventional injection-type or intrinsic EL devices. | 2009-03-26 |
20090078929 | NANOWIRE DEVICE AND METHOD OF MAKING A NANOWIRE DEVICE - A method of making nanowires includes providing a silicon substrate having a silicon dioxide insulation on the surface thereof. The silicon dioxide is etched to form one or more pillars, each having a plurality of sidewalls. A thin film of gold is deposited on a sidewall and is subjected to an annealing process. The annealing process causes the gold film to form a globular catalyst particle. The structure is placed in an LPCVD furnace into which is introduced silane gas. Silicon from the gas migrates through the catalyst particle and grows a nanowire from the sidewall of the pillar to a desired length. Electrical contacts are provided at each end of the nanowire to create an active component useable in an electronic circuit. | 2009-03-26 |
20090078930 | Quantum device, manufacturing method of the same and controlling method of the same - By bringing a tip of an AFM into contact with the surface of a GaAs substrate or an AlGaAs substrate, for example, applying a negative bias to the tip, and applying a positive bias to the GaAs substrate or the AlGaAs substrate, a donut-shaped oxide film is formed. Then, the oxide film is removed. As a result, a ring-shaped groove is formed in the surface of the GaAs substrate or the AlGaAs substrate. The oxide film can be removed by chemical etching, ultrasonic cleaning with water, a treatment with atomic hydrogen in a vacuum, or the like. Thereafter, a semiconductor film (InAs film or InGaAs film, for example) is epitaxially grown in the groove. Then, a capping layer which covers the semiconductor film and the GaAs substrate or the AlGaAs substrate is formed. | 2009-03-26 |
20090078931 | SYSTEMS, METHODS, AND APPARATUS FOR QUBIT STATE READOUT - A superconducting readout system includes a computation qubit; a measurement device to measure a state of the computation qubit; and a latch qubit that mediates communicative coupling between the computation qubit and the measurement device. The latch qubit includes a qubit loop that includes at least two superconducting inductors coupled in series with each other; a compound Josephson junction that interrupts the qubit loop that includes at least two Josephson junctions coupled in series with each other in the compound Josephson junction and coupled in parallel with each other with respect to the qubit loop; and a first clock signal input structure to couple clock signals to the compound Josephson junction. | 2009-03-26 |
20090078932 | SYSTEMS, DEVICES, AND METHODS FOR CONTROLLABLY COUPLING QUBITS - A coupling system may include first and second magnetic flux inductors communicatively coupled to a Josephson junction of an rf SQUID. The coupling system may allow transverse coupling between qubits. A superconducting processor may include at least one of the coupling systems and two or more qubits. A method may include providing first, second and third coupling structure to control the coupling system. | 2009-03-26 |
20090078933 | ORGANIC LIGHT EMITTING DEVICE - An organic light emitting device includes a first electrode disposed on a substrate, a plurality of organic function layers disposed on the first electrode and comprising an emitting layer, and a second electrode disposed on the organic function layers. One of the organic layers includes an inorganic material. This layer may be formed adjacent the first electrode or adjacent the second electrode to form top-emission or bottom-emission structures. | 2009-03-26 |
20090078934 | Zinc Oxide Based Compound Semiconductor Light Emitting Device - There is provided a semiconductor light emitting device in which light emitting efficiency is totally improved in case of emitting a light having a short wavelength of 400 nm or less by raising internal quantum efficiency by enhancing crystallinity of semiconductor layers laminated and by raising external quantum efficiency by taking out the light emitted by preventing the light emitted from being absorbed in the substrate or the like, as much as possible. In case of laminating ZnO compound semiconductor layers ( | 2009-03-26 |
20090078935 | SEMICONDUCTOR DEVICE - Electrode pads respectively have a probe region permitting probe contact and a non-probe region. In each of the electrode pads arranged zigzag in two or more rows, a lead interconnect for connecting another electrode pad with an internal circuit is not placed directly under the probe region but placed directly under the non-probe region. | 2009-03-26 |
20090078936 | SEMICONDUCTOR DEVICE - A PIN diode includes an anode electrode, a P layer, an I layer, an N layer and a cathode electrode. A polysilicon film is formed in a region near the pn junction or n | 2009-03-26 |
20090078937 | PRODUCTION METHODS OF PATTERN THIN FILMS, SEMICONDUCTOR ELEMENT, AND CIRCUIT SUBSTRATE, AND RESIST MATERIAL, SEMICONDUCTOR ELEMENT, AND CIRCUIT SUBSTRATE - The present invention provides production methods of a pattern thin film, a semiconductor element and a circuit substrate, capable of eliminating the number of photolithography processes needed for patterning; and a semiconductor element, a circuit substrate, and an electron device obtained by the production methods. The production method of the pattern thin film of the present invention is a production method of a pattern thin film, comprising the steps of: forming a first resist pattern film on a thin film formed on a substrate; forming a second resist pattern film; patterning the thin film using at least the second resist pattern film, wherein in the step of forming the second resist pattern film, a fluid resist material or an organic solvent is applied on a groove of a bank pattern formed using the first resist pattern film. | 2009-03-26 |
20090078938 | ELECTROPHORETIC DISPLAY DEVICE AND METHOD FOR MANUFACTURING THEREOF - It is an object to provide an electrophoretic display device having a thin film transistor which has highly reliable electric characteristics, lightweight, and flexibility. A gate insulating film is formed over a gate electrode, a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film, a buffer layer is formed over the microcrystalline semiconductor film, a pair of source and drain regions are formed over the buffer layer, a pair of the source and drain electrodes in contact with the source and drain regions are formed. Then, the inverted-staggered thin film transistor is interposed between the flexible substrates, and the thin film transistor is provided with electrophoretic display element which is electrically connected by the pixel electrode. Then, the electrophoretic display electrode is surrounded by the partition layer so as to cover the end portion of the pixel electrode and provided over the pixel electrode. | 2009-03-26 |
20090078939 | Display device and method for manufacturing the same - To provide a display device which can realize high performance of a field-effect transistor which forms a pixel of the display device and which can achieve improvement in an aperture ratio of a pixel, which has been reduced due to increase in the number of field-effect transistors, and reduction in the area of the field-effect transistor which occupies the pixel, without depending on a microfabrication technique of the field-effect transistor, even when the number of field-effect transistors in the pixel is increased. A display device is provided with a plurality of pixels in which a plurality of field-effect transistors including a semiconductor layer which is separated from a semiconductor substrate and is bonded to a supporting substrate having an insulating surface are stacked with a planarization layer interposed therebetween. | 2009-03-26 |
20090078940 | Location-controlled crystal seeding - A structure with location-controlled crystallization of an active semiconductor film using a crystal seed has been provided, along with an associated fabrication method. The method forms a first semiconductor film overlying a substrate having a crystallographic orientation. Typically, the structure is polycrystalline or single-crystal. The first semiconductor film is selectively etched, forming a seed region. An insulator is formed with an opening, exposing the seed region. An amorphous second semiconductor film is formed over the insulator layer. The second semiconductor film is laser annealed, partially melting the seed region. Crystal grains are laterally grown in the second semiconductor film having the same crystallographic orientation as the seed region. In TFT fabrication an etching is typically performed to remove the second semiconductor film overlying the seed region, and a transistor active region is formed in the remaining second semiconductor film. | 2009-03-26 |
20090078941 | BACKPLANE STRUCTURES FOR SOLUTION PROCESSED ELECTRONIC DEVICES - There is provided a backplane for an organic electronic device. The backplane has a TFT substrate; a multiplicity of electrode structures; and a bank structure defining a multiplicity of pixel openings on the electrode structures. The bank structure has a height adjacent to the pixel opening, h | 2009-03-26 |
20090078942 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an SiC substrate, a first SiC layer of first conductivity provided on the substrate, a second SiC layer of second conductivity provided on the first SiC layer, first and second SiC regions provided in the second SiC layer, facing each other and having the same depth, a third SiC region extending through the first SiC region and reaching the first SiC layer, a gate insulator formed on the first and second SiC regions and the second SiC layer interposed therebetween, a gate electrode formed on the gate insulator, a first contact of first conductivity formed on the second SiC region, a second contact of second conductivity formed on the second SiC region, reaching the second SiC layer through the second SiC region, and a top electrode formed on the first and second contacts, and a bottom electrode formed on a back surface of the substrate. | 2009-03-26 |
20090078943 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A nitride semiconductor device mainly made of a nitride semiconductor material having excellent heat dissipation characteristics and great crystallinity and a method for manufacturing thereof are provided. The method for manufacturing the nitride semiconductor includes vapor-depositing a diamond layer on a silicon substrate, bonding an SOI substrate on a surface of the diamond layer, thinning the SOI substrate, epitaxially growing an GaN layer on the thinned SOI substrate, removing the silicon substrate, and bonding, on a rear-surface of the diamond layer, a material having a thermal conductivity greater than a thermal conductivity of the silicon substrate. The SOI substrate has an outermost surface layer and a silicon oxide layer. In the thinning, the SOI substrate is thinned by selectively removed through the silicon oxide layer, so that only the outermost surface layer is left. | 2009-03-26 |
20090078944 | Light emitting device and method of manufacturing the same - This semiconductor light emitting device includes an optical cavity made of a group III nitride semiconductor having a major growth surface defined by a nonpolar plane and including a pair of cavity end faces parallel to c-planes, and a reflecting portion made of a group III nitride semiconductor having a major growth surface defined by a nonpolar plane and having a reflective facet opposed to one of the pair of cavity end faces and inclined with respect to a normal of the major growth surface. The optical cavity and the reflecting portion may be crystal-grown from the major surface of the substrate. The substrate is preferably a group III nitride semiconductor substrate having a major surface defined by a nonpolar plane. | 2009-03-26 |
20090078945 | Light emitting device - A light emitting device is provided that includes a substrate having a thin film transistor, and an insulation film disposed over the substrate and having a via hole to expose the thin film transistor. The light emitting device further includes a first electrode over the insulation film and connecting with the thin film transistor through the via hole, an emitting layer over the first electrode, a first function layer to cover the emitting layer, and a second electrode over the first function layer. A width of the first function layer is approximately 1.0 to 1.2 times a width of the emitting layer. | 2009-03-26 |
20090078946 | LIGHT EMITTING DEVICE - A light emitting device is disclosed. The light emitting device includes a substrate including a thin film transistor, an insulating film disposed over the thin film transistor, a first electrode disposed over the thin film transistor and connected to the thin film transistor, a function layer including at least one of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, which are sequentially disposed over the first electrode, and a second electrode disposed on the function layer. A thickness of the first electrode is substantially 0.29 to 0.35 times a thickness of the function layer. A thickness of the second electrode is substantially 0.29 to 0.69 times the thickness of the function layer. | 2009-03-26 |
20090078947 | SEMICONDUCTOR LIGHT EMITTING DEVICE - An end face emission type semiconductor light emitting device which include: a substrate; a first conductive type clad layer stacked on the substrate; an active region layer including an active layer stacked on the first conductive type clad layer; a second conductive type clad layer stacked on the active region layer such that a thickness of a portion thereof at least over an emission region of the active region layer in an emission end face adjacent area is thinner than a thickness of the other portion; and a second conductive type regrowth layer stacked on the second conductive type clad layer, which has a higher refractive index than the second conductive type clad layer. | 2009-03-26 |
20090078948 | ILLUMINATOR AND METHOD FOR PRODUCING SUCH ILLUMINATOR - The present invention relates to an illuminator ( | 2009-03-26 |
20090078949 | LIGHT EMITTING DEVICE WITH CONVERSION STRUCTURE - The invention relates to a light-emitting device comprising a conversion structure and one or several LEDs ( | 2009-03-26 |
20090078950 | Package structure with replaceable element for light emitting diode - A package structure for an LED is disclosed. The structure includes a first substrate, an LED chip, a second substrate, a protection layer and a replaceable optical element. The LED chip is disposed on the first substrate. The second substrate is disposed on the first substrate, and surrounds the LED chip. The second substrate has a first thread. The protection layer covers the LED chip. The replaceable optical element has a second thread, and is fastened to the second substrate through the first thread. An interior wall of the optical element corresponds to a surface of the protection layer in arc shape. | 2009-03-26 |
20090078951 | GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE - An object of the present invention is to provide a gallium nitride-based compound semiconductor light-emitting device having a reflective positive electrode configured to achieve excellent light extraction efficiency. | 2009-03-26 |
20090078952 | LIGHT-EMITTING CHIP DEVICE WITH HIGH THERMAL CONDUCTIVITY - This invention provides a light-emitting chip device with high thermal conductivity, which includes an epitaxial chip, an electrode disposed on a top surface of the epitaxial chip and a U-shaped electrode base cooperating with the electrode to provide electric energy to the epitaxial chip for generating light by electric-optical effect. The epitaxial chip includes a substrate and an epitaxial-layer structure with a roughening top surface and a roughening bottom surface for improving light extracted out of the epitaxial chip. A thermal conductive transparent reflective layer is formed between the substrate and the epitaxial-layer structure. The electrode base surrounds the substrate, the transparent reflective layer and a first cladding layer of the epitaxial-layer structure to facilitate the dissipation of the internal waste heat generated when the epitaxial chip emitting light. A method for manufacturing the chip device of the present invention is provided. | 2009-03-26 |
20090078953 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - The present invention provides a light emitting diode (LED) package, which includes a carrier substrate having a first surface and a second surface; a metal layer formed in the first surface of the carrier substrate, and a through hole formed in the central area of the metal layer to expose the portion of the first surface of the carrier substrate; a LED having a semiconductor layer capable of light emitting, and an N electrode and a P electrode on the two sides of the semiconductor layer, in which P electrode is electrically connected to the first surface of the metal layer; a first connecting element is electrically connected to the metal layer; a second connecting element is electrically connected to the N electrode; and an encapsulated material is formed to cover the LED, the metal layer, the exposed first connecting element and the second connecting element. | 2009-03-26 |
20090078954 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a semiconductor light emitting device and a method for manufacturing the same. The semiconductor light emitting device comprises a first conductive semiconductor layer comprising a first concave-convex pattern, a second concave-convex pattern on at least one pattern of the first concave-convex pattern, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer. | 2009-03-26 |
20090078955 | Micro-Emitter Array Based Full-Color Micro-Display - Disclosed is a semiconductor micro-emitter array for use in a full-color microdisplay. Each pixel includes three vertically-stacked red, green, and blue micro-emitters which minimizes pixel size. The microdisplay may be exclusively based on Group III-nitride semiconductors, with differing indium concentrations in three respective InGaN/GaN active regions for emitting the three RGB colors. Alternatively the microdisplay may be based on hybrid integration of InGaN based III-nitride semiconductors for blue and green emissions, and AlGaInP based (e.g., Group III-V) semiconductors for red emissions. | 2009-03-26 |
20090078956 | PACKAGE STRUCTURE OF PHOTOELECTRONIC DEVICE AND FABRICATING METHOD THEREOF - A package structure for photoelectronic devices comprises a silicon substrate, a first insulating layer, a reflective layer, a second insulating layer, a first conductive layer, a second conductive layer and a die. The silicon substrate has a first surface and a second surface, wherein the first surface is opposed to the second surface. The first surface has a reflective opening, and the second surface has at least two electrode via holes connected to the reflective opening and a recess disposed outside the electrode via holes. The first insulating layer overlays the first surface, the second surface and the recesses. The reflective layer is disposed on the reflective opening. The second insulating layer is disposed on the reflective layer. The first conductive layer is disposed on the surface of the second insulating layer. The second conductive layer is disposed on the surface of the second surface and inside the electrode via holes. The die is fixed inside the reflective opening and electrically connected to the first conductive layer. | 2009-03-26 |
20090078957 | LIGHT EMITTING DEVICE - A light emitting device includes a board, a semiconductor light emitting element formed on the board optionally via a submount, a cap sealing the semiconductor light emitting element and a reflector provided surrounding the cap. The cap has top and bottom surfaces that are parallel to the top surface of the semiconductor light emitting element, and the spacing between the top and bottom surfaces is 1-3 times the longest diagonal or the diameter of the semiconductor light emitting element. Also disclosed is a process for producing the device. | 2009-03-26 |
20090078958 | Assembly of a heat dissipating base and a lead frame for a light emitting diode packaging device and method for making the same - A light emitting diode packaging device includes: a heat dissipating base; a light emitting dice mounted on the heat dissipating base; a lead frame coupled electrically to the light emitting dice and having a protruding wall defining a confining space for extension of a protruding part of the heat dissipating base therethrough; at least one retaining member provided on one of the protruding part of the heat dissipating base and the protruding wall of the lead frame to retain the lead frame to the heat dissipating base; and a molding material molded on the heat dissipating base and the lead frame. | 2009-03-26 |
20090078959 | Solid-state optical device - A solid-state optical device includes a solid-state element, a power supplying/retrieving portion on which the solid-state element is mounted, the power supplying/retrieving portion supplying or retrieving electric power to/from the solid-state element, and a glass sealing material that seals the solid-state element. The glass sealing material has a thermal expansion coefficient equivalent to that of the power supplying/retrieving portion. The glass sealing material includes a P | 2009-03-26 |
20090078960 | LIGHT EMITTING DIODE WITH AUXILIARY ELECTRIC COMPONENT - An exemplary LED includes a substrate, an LED chip, a light pervious encapsulation, and an auxiliary electric component. The substrate includes a first surface, an opposite second surface, and an accommodating space defined therein between the first surface and the second surface. The LED chip is mounted on the first surface of the substrate. The light pervious encapsulation is formed on the substrate and covers the LED chip. The auxiliary electric component is received in the accommodating space between the first and second surfaces of the substrate. | 2009-03-26 |
20090078961 | NITRIDE-BASED LIGHT EMITTING DEVICE - The present invention relates to a nitride-based light emitting device having a buffer layer, an n-type nitride semiconductor layer, an active layer and a p-type semiconductor layer sequentially formed on a substrate, wherein an Al | 2009-03-26 |
20090078962 | Adjustable Field Effect Rectifier - An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference. | 2009-03-26 |
20090078963 | Nano-optoelectronic chip structure and method - The present invention relates to integrated structures of III-V and Silicon materials for making optoelectronic devices on chip compatible with complimentary metal oxide semiconductor (CMOS). As a result, various light generation, detection, switching, modulation, filtering, multiplexing, signal manipulation and beam splitting devices could be fabricated in semiconductor material such as silicon on insulator (SOI) and other material substrate. | 2009-03-26 |
20090078964 | ENHANCEMENT MODE III-NITRIDE SEMICONDUCTOR DEVICE WITH REDUCED ELECTRIC FIELD BETWEEN THE GATE AND THE DRAIN - An enhancement mode III-nitride heterojunction device that includes a region between the gate and the drain electrode thereof that is at the same potential as the source electrode thereof when the device is operating. | 2009-03-26 |
20090078965 | INDIVIDUALLY CONTROLLED MULTIPLE III-NITRIDE HALF BRIDGES - A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die. | 2009-03-26 |
20090078966 | Field-effect transistor, semiconductor chip and semiconductor device - A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact. | 2009-03-26 |
20090078967 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE HAVING A PLURALITY OF SEMICONDUCTOR CHIPS - The present invention comprises a semiconductor chip, and a semiconductor device having a plurality of semiconductor chips, that enables ESD protection from another semiconductor chip without increasing the chip area in case the semiconductor chip is Multi-Chip-Packaged, without wasting chip area in case the semiconductor chip is not Multi-Chip-Packaged. The exemplary semiconductor chip of the present invention includes an internal circuit and a first electrode pad electrically connected to a ground bus line of the first semiconductor chip in a region where an electrode pad, which gives and receives electric signals required for an operation of the internal circuit, cannot be provided. | 2009-03-26 |
20090078968 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR FORMING THE SAME - In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer. A wiring structure is determined based on a wiring structure equation expressing the relations among a voltage drop in the lines, the area occupied thereby, and a current consumed thereby and on a circuit characteristic equation expressing, when the circuit is subdivided while the ratio between the area of the circuit and a current consumed thereby is held constant, the relation between an area occupied by a circuit resulting from subdivision and a current consumed thereby. | 2009-03-26 |
20090078969 | SOLID-STATE IMAGING DEVICE, IMAGING APPARATUS, AND METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes: a semiconductor substrate; photoelectric conversion elements; vertical charge transfer paths that transfer charges generated in photoelectric conversion elements, in a vertical direction; a horizontal charge transfer path that transfers the charges transferred in vertical charge transfer paths, in a horizontal direction orthogonal to the vertical direction; a plurality of charge accumulating sections between the vertical charge transfer paths and the horizontal charge transfer path; a plurality of electrodes disposed above the respective charge accumulating sections, the plurality of electrodes being classified into a plurality of kinds of electrodes; wirings corresponding to the respective kinds of electrodes and extending in the horizontal direction above the plurality of electrodes; and a planarizing layer disposed between the wirings and an uneven surface caused by the plurality of electrodes that are present in areas overlapping the wirings, so as to planarize the uneven surface. | 2009-03-26 |
20090078970 | SEMICONDUCTOR DEVICE - A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor layer from a semiconductor substrate followed by bonding thereof over the substrate. Each of the plurality of field-effect transistors is covered with an insulating film which provides distortion of the semiconductor layer. Furthermore, the crystal axis of the semiconductor layer, which is parallel to the crystal plane thereof, is set to a channel length direction of the semiconductor layer, which enables production of the semiconductor device with high performance and low power consumption having an SOI structure. | 2009-03-26 |
20090078971 | SEMICONDUCTOR DEVICE WITH STRUCTURED CURRENT SPREAD REGION AND METHOD - A semiconductor device with structured current spread region and method is disclosed. One embodiment provides a drift portion of a first conductivity type, a current spread portion of the first conductivity type and first portions of the first conductivity type. The current spread portion and the first portions are arranged in a first plane on the drift portion, wherein the current spread portion surrounds at least partially the first portions. The semiconductor body further includes spaced apart body regions of a second conductivity type which are arranged on the current spread portion. Further, the doping concentration of the current spread portion is higher than the doping concentrations of the drift portion and of the first portions. | 2009-03-26 |
20090078972 | SENSOR THIN FILM TRANSISTOR, THIN FILM TRANSISTOR SUBSTRATE HAVING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A sensor thin film transistor includes a gate electrode, a gate insulation layer formed on the gate electrode, a semiconductor layer having a portion positioned above the gate electrode and on a side of the gate insulation layer opposite the gate electrode, and a source electrode and drain electrode having spaced apart ends positioned on the semiconductor layer, wherein the sensor thin film transistor is operative such that a signal-to-noise ratio is equal to or greater than about 200 when the gate-off voltage applied to the gate electrode is equal to or less than about 0V. | 2009-03-26 |
20090078973 | Image Sensor Element For Backside-Illuminated Sensor - Provides is a backside-illuminated sensor including a semiconductor substrate having a front surface and a back surface. A plurality of image sensor elements are formed on the front surface of the semiconductor substrate. At least one of the image sensor elements includes a transfer transistor and a photodetector. The gate of the transfer transistor includes an optically reflective layer. The gate of the transfer transistor, including the optically reflective layer, overlies the photodetector. In one embodiment, the gate overlies the photodetector by at least 5%. | 2009-03-26 |
20090078974 | Solid-state image capturing device; manufacturing method for the solid-state image capturing device; and electronic information device - A solid-state image capturing device is provided with a plurality of light receiving elements arranged on a surface section of a semiconductor substrate, a color filter of each color for each of the plurality of light receiving elements, and a plurality of microlenses each for condensing incident light into each of the plurality of light receiving elements, in which the interlayer insulation film is provided directly below the color filter of each color in a state where a passivation and hydrogen sintering process film is removed from the interlayer insulation film. | 2009-03-26 |
20090078975 | CMOS image sensor - There is provided a CMOS image sensor including: a photodiode receiving light to generate photogenerated charges; a transmission gate unit transmitting the photogenerated charges generated by the photodiode to a first floating diffusion area, and increasing the capacitance of the first floating diffusion area; a transfer transistor transferring the photogenerated charges of the first floating diffusion area transmitted by the transmission gate unit to a second floating diffusion area; and a drive transistor converting the photogenerated charges of the second floating diffusion area into a detection voltage. | 2009-03-26 |
20090078976 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THEREOF AS WELL AS DRIVING METHOD OF SOLID-STATE IMAGING DEVICE - A solid-state imaging device with a structure such that an electrode for reading a signal charge is provided on one side of a light-receiving sensor portion constituting a pixel; a predetermined voltage signal V is applied to a light-shielding film formed to cover an image pickup area except the light-receiving sensor portion; a second-conductivity-type semiconductor area is formed in the center on the surface of a first-conductivity-type semiconductor area constituting a photo-electric conversion area of the light-receiving sensor portion; and areas containing a lower impurity concentration than that of the second-conductivity-type semiconductor area is formed on the surface of the first-conductivity-type semiconductor area at the end on the side of the electrode and at the opposite end on the side of a pixel-separation area. | 2009-03-26 |
20090078977 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THEREOF AS WELL AS DRIVING METHOD OF SOLID-STATE IMAGING DEVICE - A solid-state imaging device with a structure such that an electrode for reading a signal charge is provided on one side of a light-receiving sensor portion constituting a pixel; a predetermined voltage signal V is applied to a light-shielding film formed to cover an image pickup area except the light-receiving sensor portion; a second-conductivity-type semiconductor area is formed in the center on the surface of a first-conductivity-type semiconductor area constituting a photo-electric conversion area of the light-receiving sensor portion; and areas containing a lower impurity concentration than that of the second-conductivity-type semiconductor area is formed on the surface of the first-conductivity-type semiconductor area at the end on the side of the electrode and at the opposite end on the side of a pixel-separation area. | 2009-03-26 |
20090078978 | IMAGE SENSOR HAVING A CHARGE STORAGE REGION PROVIDED WITHIN AN IMPLANT REGION - A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor. | 2009-03-26 |
20090078979 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate and a transistor formed on the semiconductor substrate. The semiconductor device also includes: a first interlayer insulation film formed on the semiconductor substrate including the upper portion of the transistor, a first contact formed to be connected through the first interlayer insulation film to the transistor, a ferroelectric capacitor formed to be connected to the first contact, a second interlayer insulation film formed on the first interlayer insulation film, and a second contact formed to connect the ferroelectric capacitor to a wiring through the second interlayer insulation film. The contact surfaces between the second contact and the ferroelectric capacitor have the same planar shape. | 2009-03-26 |
20090078980 | Method for Producing an Integrated Circuit, Integrated Circuit, DRAM Device and Memory Module - A method for producing an integrated circuit is disclosed. The integrated circuit includes an insulating material and a semiconducting material adjacent the insulating material. The semiconducting material is partially removed and the surface of the partially removed semiconducting material is treated. The insulating material is partially removed. | 2009-03-26 |
20090078981 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor memory device in which a plurality of capacitors each including a columnar lower electrode, a capacitor insulation film and an upper electrode are stacked with interlayer films therebetween, a contact plug connects an upper face of each lower electrode of a lower layer with a bottom face of each lower electrode of an upper layer, and another contact plug connects upper electrodes of the capacitors in respective layers with each other. | 2009-03-26 |
20090078982 | ALPHA HYDROXY CARBOXYLIC ACID ETCHANTS FOR SILICON MICROSTRUCTURES - α-Hydroxy carboxylic acid etchants for silicon microstructures are generally described. In one example, a method includes fabricating a protruding structure on a semiconductor substrate, the protruding structure comprising a first layer of silicon coupled with the semiconductor substrate, the first layer of silicon defining a bottom gate, a sacrificial layer of silicon germanium (SiGe) coupled with the first layer of silicon, and a second layer of silicon coupled with the layer of SiGe, fabricating a top gate that traverses the protruding structure, and selectively etching the sacrificial layer of SiGe using an etchant including hydrofluoric acid (HF), nitric acid (HNO | 2009-03-26 |
20090078983 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A MONOS type non-volatile semiconductor memory device which is capable of electrically writing, erasing, reading and retaining data, the memory device including source/drain regions, a first gate insulating layer, a first charge trapping layer formed on the first gate insulating layer, a second gate insulating layer formed on the first charge trapping layer, and a controlling electrode formed on the second gate insulating layer. The first charge trapping layer includes an insulating film containing Al and O as major elements and having a defect pair formed of a complex of an interstitial O atom and a tetravalent cationic atom substituting for an Al atom, the insulating film also having electron unoccupied levels within the range of 2 eV-6 eV as measured from the valence band maximum of Al | 2009-03-26 |
20090078984 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; a gate dielectric film that is formed on the semiconductor substrate; a floating gate electrode film that is formed on the gate dielectric film; an inter-gate dielectric film that includes: a metal oxide film that is formed on the floating gate electrode film; an electron trap film that is formed on the metal oxide film; and a silicon oxide film that is formed on the electron trap film; and a control gate electrode film that is formed on the inter-gate dielectric film. | 2009-03-26 |
20090078985 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel region, a first gate electrode disposed near its corresponding memory electrode with an insulating film interposed therebetween, and a second gate electrode disposed through insulating films and a charge storage region and electrically isolated from the first gate electrode. A first negative voltage is applied to the first well region to form a state of reverse bias greater than or equal to a junction withstand voltage between the second gate electrode and the memory electrode near the second gate electrode, thereby enabling injection of hot electrons into the charge storage region and injection of electrons from the well region to the charge storage region. | 2009-03-26 |
20090078986 | Manufacturing method for an integrated circuit including different types of gate stacks, corresponding intermediate integrated circuit structure and corresponding integrated circuit - The present invention provides a manufacturing method for an integrated circuit and a corresponding integrated circuit. The integrated circuit comprises a plurality of first devices, each first device including a charge storage layer and a control electrode comprising a plurality of layers; and a plurality of second devices coupled to at least one of the plurality of first devices, each second device including a control electrode comprising at least one layer different from said plurality of layers. | 2009-03-26 |
20090078987 | PROGRAMMABLE ELEMENT AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a programmable element, may include a semiconductor substrate, source/drain layers formed apart from each other in the upper surface of the semiconductor substrate, a gate insulating film including a charge-trapping film containing Hf and formed on a portion between the source/drain layers of the semiconductor substrate, and a gate electrode formed on the gate insulating film with a program voltage applied to the gate electrode. | 2009-03-26 |
20090078988 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a protection target element formed on a semiconductor substrate and includes a protection target element electrode, a substrate connecting part including a substrate connecting electrode electrically connected to the semiconductor substrate and a fuse structure provided between the protection target element electrode and the substrate connecting electrode and includes a fuse film configured to be torn by applying a predetermined current thereto. The protection target element electrode, the substrate connecting electrode and the fuse film are formed of an integral conductive film as long as the fuse film is not torn. | 2009-03-26 |
20090078989 | Method of forming silicon nitride at low temperature, charge trap memory device including crystalline nano dots formed by using the same, and method of manufacturing the charge trap memory device - Provided are a method of forming silicon nitride at a low temperature, a charge trap memory device including crystalline nano dots formed by using the same, and a method of manufacturing the charge trap memory device. The method of forming silicon nitride includes loading a substrate into a chamber of a silicon nitride deposition device comprising a filament; increasing a temperature of the filament to a temperature whereby a reactant gas to be injected into the chamber may be dissociated; and injecting the reactant gas into the chamber so as to form a crystalline silicon nitride film or crystalline silicon nitride nano dots on the substrate. In the method, the temperature of the filament may be maintained at 1,400° C.˜2,000° C., and a pressure in the chamber may be maintained at several to several ten torr when the reactant gas in injected into the chamber. | 2009-03-26 |
20090078990 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A). | 2009-03-26 |
20090078991 | STRESS ENHANCED SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING SAME - A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region. | 2009-03-26 |
20090078992 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In the present invention, an npn junction is formed by circularly forming a p− type impurity region and n+ type impurity regions on a same single-crystalline substrate as a MOS transistor. Multiple npn junctions are formed apart from each other in concentric circular patterns. With this configuration, steep breakdown characteristics can be obtained, which results in good constant-voltage diode characteristics. Being formed in a manufacturing process of a MOS transistor, the present protection diode contributes to process streamlining and cost reduction. By selecting the number of npn junctions according to breakdown voltage, control of the breakdown voltage can be facilitated. | 2009-03-26 |
20090078993 | SEMICONDUCTOR DEVICE WITH REDUCED GATE-OVERLAP CAPACITANCE AND METHOD OF FORMING THE SAME - A semiconductor device includes a vertically extending semiconductor portion above a semiconductor substrate, first and second diffusion regions being disposed near the bottom and top portions of the vertically extending semiconductor portion, respectively. A gate insulating film extends along the side surface of the vertically extending semiconductor portion which is separated by the gate insulating film from a gate electrode. The level of the top portion of the gate electrode is nearly equal to or lower than the level of the bottom portion of the second diffusion regions and the level of the bottom portion of the gate electrode is nearly equal to or higher than the level of the top portion of the first diffusion region. | 2009-03-26 |
20090078994 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed is a semiconductor device having an n-type drain region, a low concentration p-type body region formed on the n-type drain region, an n-type source region formed on the low concentration p-type body region, a high concentration p-type body region formed on the low concentration p-type body region, a gate insulating film, and a gate electrode, wherein a plurality of trenches T which extend in a same direction and each of which forms a continuous concavo-convex shape when viewed from above are formed from top faces of the source region and the high concentration body region and pass through the low concentration body region to reach into the drain region, and wherein the gate electrode is buried in each of the plurality of trenches. A maximum distance between two adjacent trenches T of the n-type source region is greater than a maximum distance between the two adjacent trenches T of the high concentration p-type body region. | 2009-03-26 |
20090078995 | Semiconductor device and method of manufacturing semiconductor device - A semiconductor device includes a first conductivity type layer of a first conductivity type, a body layer of a second conductivity type formed on the first conductivity type layer, a gate trench passing through the body layer so that the deepest portion thereof reaches the first conductivity type layer, a source region of the first conductivity type formed around the gate trench on the surface layer portion of the body layer, a gate insulating film formed on the bottom surface and the side surface of the gate trench, and a gate electrode embedded in the gate trench through the gate insulating film, and the bottom surface of the gate electrode and the upper surface of the first conductivity type layer are flush with each other. | 2009-03-26 |
20090078996 | Semiconductor device - A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher than the first conductive type impurity concentration of the semiconductor layer and lower than the first conductive type impurity concentration of the drain region. | 2009-03-26 |
20090078997 | DUAL METAL GATE FINFETS WITH SINGLE OR DUAL HIGH-K GATE DIELECTRIC - A first high-k gate dielectric layer and a first metal gate layer are formed on first and second semiconductor fins. A first metal gate ring is formed on the first semiconductor fin. In one embodiment, the first high-k gate dielectric layer remains on the second semiconductor fin. A second metal gate layer and a silicon containing layer are deposited and patterned to form gate electrodes. In another embodiment, a second high-k dielectric layer replaces the first high-k dielectric layer over the second semiconductor fin, followed by formation of a second metal gate layer. A first electrode comprising a first gate dielectric and a first metal gate is formed on the first semiconductor fin, while a second electrode comprising a second gate dielectric and a second metal gate is formed on the second semiconductor fin. Absence of high-k gate dielectric materials on a gate wiring prevents increase in parasitic resistance. | 2009-03-26 |
20090078998 | SEMICONDUCTOR DEVICE HAVING DECREASED CONTACT RESISTANCE - Semiconductor devices having improved contact resistance and methods for fabricating such semiconductor devices are provided. These semiconductor devices include a semiconductor device structure and a contact. The contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure. | 2009-03-26 |
20090078999 | SEMICONDUCTOR DEVICE STRUCTURES WITH FLOATING BODY CHARGE STORAGE AND METHODS FOR FORMING SUCH SEMICONDUCTOR DEVICE STRUCTURES. - Semiconductor device structures including a semiconductor body that is partially depleted to define a floating charge-neutral region supplying a floating body for charge storage and methods for forming such semiconductor device structures. The width of the semiconductor body is modulated so that different sections of the body have different widths. When electrically biased, the floating charge-neutral region at least partially resides in the wider section of the semiconductor body. | 2009-03-26 |
20090079000 | SEMICONDUCTOR DEVICE - An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable. | 2009-03-26 |
20090079001 | MULTI-CHANNEL ESD DEVICE AND METHOD THEREFOR - In one embodiment, an ESD device is configured to include a zener diode and a P-N diode. | 2009-03-26 |
20090079002 | Superjunction Structures for Power Devices and Methods of Manufacture - A power device includes an active region and a termination region surrounding the active region. A plurality of pillars of first and second conductivity type are alternately arranged in each of the active and termination regions. The pillars of first conductivity type in the active and termination regions have substantially the same width, and the pillars of second conductivity type in the active region have a smaller width than the pillars of second conductivity type in the termination region so that a charge balance condition in each of the active and termination regions results in a higher breakdown voltage in the termination region than in the active region. | 2009-03-26 |
20090079003 | Method for protecting circuits from damage due to currents and voltages during manufacture - A protection circuit network includes one or more protection devices, used to protect one or more devices in an integrated circuit (IC) design. The protection devices are globally coupled together, for connection to an internal or external power supply. During manufacture of the IC, the protection circuit network protects the at-risk devices. During operation of the IC, the protection circuit network is powered down, such that excessive current leakage is avoided. | 2009-03-26 |
20090079004 | METHOD FOR MAKING A TRANSISTOR WITH SELF-ALIGNED DOUBLE GATES BY REDUCING GATE PATTERNS - This invention relates to an improved microelectronic method for making a double gate structure for a transistor, and particularly gate patterns ( | 2009-03-26 |
20090079005 | Integrated Circuits and Methods of Design and Manufacture Thereof - Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives. | 2009-03-26 |
20090079006 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a semiconductor device including a semiconductor layer, a first metal main electrode provided on the semiconductor layer and having a first region and a second region, and a metal gate interconnect provided on the semiconductor layer and insulated from and interposed between the first region and the second region; a lead; and a conductive member made of a metal and connecting the first metal main electrode to the lead. The conductive member is bonded to the first region and the second region so as to cover the metal gate interconnect, and the conductive member has a recess on its lower surface above the metal gate interconnect to be spaced from the metal gate interconnect. | 2009-03-26 |