12th week of 2010 patent applcation highlights part 8 |
Patent application number | Title | Published |
20100072520 | Methods of Fabricating Transistors Having Buried P-Type Layers Coupled to the Gate - A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein. | 2010-03-25 |
20100072521 | METHOD FOR FORMING SILICIDE OF SEMICONDUCTOR DEVICE - A silicide forming method for a semiconductor device. A silicide forming method may include forming a gate electrode by depositing a gate oxide film and/or polysilicon over a silicon substrate and patterning. A silicide forming method may include forming a nitride film spacer over sidewalls of a gate electrode and simultaneously performing source/drain implant and amophization implant over a silicon substrate. A silicide forming method may include depositing an insulating film after performing source/drain and amophization implants. A silicide forming method may include partially and/or entirely exposing a source/drain and/or gate electrode disposed under an insulating film by etching an insulating film. A silicide forming method may include applying a metal film over a silicon substrate and forming silicide over regions etched by performing heat treatment over a source/drain and/or gate electrode. | 2010-03-25 |
20100072522 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device fabrication method includes the steps of (a) forming a dielectric film on a semiconductor substrate; (b) etching the dielectric film by a dry process; and (c) supplying thermally decomposed atomic hydrogen onto the semiconductor substrate under a prescribed temperature condition, to remove a damaged layer produced in the semiconductor substrate due to the dry process. | 2010-03-25 |
20100072523 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate electrode includes a second metal film formed on a first gate insulating film, and an insulating film formed, extending over side surfaces of the first gate electrode and upper surfaces of regions located in the first active region laterally outside the first gate electrode. The second MIS transistor includes a second gate electrode including a first metal film formed on a second gate insulating film and a conductive film formed on the first metal film, and the insulating film formed, extending over side surfaces of the second gate electrode and upper surfaces of regions located in the second active region laterally outside the second gate electrode. The first and second metal films are made of different metal materials. | 2010-03-25 |
20100072524 | Magnetic Devices Having Oxide Antiferromagnetic Layer Next To Free Ferromagnetic Layer - Magnetic multilayer structures, such as magnetic or magnetoresistive tunnel junctions (MTJs) and spin valves, having a magnetic biasing layer formed next to and magnetically coupled to the free ferromagnetic layer to achieve a desired stability against fluctuations caused by, e.g., thermal fluctuations and astray fields. Stable MTJ cells with low aspect ratios can be fabricated using CMOS processing for, e.g., high-density MRAM memory devices and other devices, using the magnetic biasing layer. Such multilayer structures can be programmed using spin transfer induced switching by driving a write current perpendicular to the layers to switch the magnetization of the free ferromagnetic layer. | 2010-03-25 |
20100072525 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to a method for manufacturing a semiconductor memory device of the present invention, a capacitor lower electrode film is left on the wiring layer located above a dummy transistor. In this manner, when processing of the capacitors is performed by removing a capacitor upper electrode film and a ferroelectric film, removal of the wiring layer can be prevented, and the connection between the diffusion layer of a select transistor and a bit line can be secured. | 2010-03-25 |
20100072526 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate; a ferroelectric capacitor comprising an upper electrode, a ferroelectric film, and a lower electrode above the semiconductor substrate; and an upper interlayer dielectric film surrounding a periphery of the ferroelectric capacitor, wherein a gap is provided between the ferroelectric capacitor and the upper interlayer dielectric film. | 2010-03-25 |
20100072527 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes: a transistor on a semiconductor substrate; an interlayer dielectric film covering the transistor; a ferroelectric capacitor comprising a first upper electrode, a ferroelectric film, and a lower electrode on the interlayer dielectric film; a contact plug which is in the interlayer dielectric film and electrically connects the lower electrode to the transistor; a second upper electrode on the first upper electrode, a side surface of the second upper electrode being formed in a forward tapered shape; and an interconnection electrically connected via the second upper electrode to the first upper electrode. | 2010-03-25 |
20100072528 | SPIN TRANSISTOR, INTEGRATED CIRCUIT, AND MAGNETIC MEMORY - A spin transistor includes a first ferromagnetic layer, a second ferromagnetic layer, a semiconductor layer between the first and second ferromagnetic layers, and a gate electrode on or above a surface of the semiconductor layer, the surface being between the first and second ferromagnetic layers. The first ferromagnetic layer comprises a ferromagnet which has a first minority spin band located at a high energy side and a second minority spin band located at a low energy side, and has a Fermi level in an area of the high energy side higher than a middle of a gap between the first and second minority spin bands. | 2010-03-25 |
20100072529 | STACK HAVING HEUSLER ALLOY, MAGNETORESISTIVE ELEMENT AND SPIN TRANSISTOR USING THE STACK, AND METHOD OF MANUFACTURING THE SAME - A stack includes a crystalline MgO layer, crystalline Heusler alloy layer, and amorphous Heusler alloy layer. The crystalline Heusler alloy layer is provided on the MgO layer. The amorphous Heusler alloy layer is provided on the crystalline Heusler alloy layer. | 2010-03-25 |
20100072530 | MAGNETIC RANDOM ACCESS MEMORTY - A magnetic random access memory of an aspect of the present invention including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed and recording layers, wherein the magnetization directions of the fixed and recording layers are in a parallel state or in an anti-parallel state depending on a direction of a current flowing between the fixed and recording layers, a first transistor having a gate and a first current path having one end connected to the fixed layer, a second transistor having a gate and a second current path having one end connected to the recording layer, a first bit line to which other end of the first current path is connected, and a second bit line to which other end of the second current path is connected. | 2010-03-25 |
20100072531 | Method for Forming a Memory Cell Comprising a Capacitor Having a Strontium Titaniumoxide Based Dielectric Layer and Devices Obtained Thereof - A method is disclosed for manufacturing Sr | 2010-03-25 |
20100072532 | Recessed Access Device For A Memory - Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess. | 2010-03-25 |
20100072533 | ASYMMETRIC CHANNEL DOPING FOR IMPROVED MEMORY OPERATION FOR FLOATING BODY CELL (FBC) MEMORY - An improved dynamic memory cell using a semiconductor fin or body is described. Asymmetrical doping is used in the channel region, with more dopant under the back gate to improve retention without significantly increasing read voltage. | 2010-03-25 |
20100072534 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile semiconductor memory device includes a gate insulating film formed on a semiconductor substrate, a first gate electrode corresponding to a memory cell transistor and a second gate electrode. The first gate electrode includes a floating gate electrode film, a first interelectrode insulating film and a control gate electrode film. The floating gate electrode film has a polycrystalline silicon film and the control gate electrode film having a silicide film. The second gate electrode includes a lower electrode film, a second interelectrode insulating film and an upper electrode film. The second interelectrode insulating film includes an opening. The lower electrode film includes a void below the opening of the second interelectrode insulating film. The upper electrode film includes a silicide film. The lower electrode film includes a polycrystalline silicon film and a silicide film which is located between the opening and the void. | 2010-03-25 |
20100072535 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a source region and a drain region provided apart from each other in a semiconductor substrate, a first insulating film provided on a channel region between the source region and the drain region, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer and including a stacked structure of a lanthanum aluminum silicate film and a dielectric film made of silicon oxide or silicon oxynitride, and a control gate electrode provided on the second insulating film. | 2010-03-25 |
20100072536 | Non-volatile memory device and method of manufacturing the same - In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved. | 2010-03-25 |
20100072537 | BAND ENGINEERED NANO-CRYSTAL NON-VOLATILE MEMORY DEVICE UTILIZING ENHANCED GATE INJECTION - Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of the present invention allow a reverse mode gate-insulator stack memory cell that utilizes the control gate for programming and erasure through a band engineered crested tunnel barrier. Charge retention is enhanced by utilization of high work function nano-crystals in a non-conductive trapping layer and a high K dielectric charge blocking layer. The band-gap engineered gate-stack with symmetric or asymmetric crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. | 2010-03-25 |
20100072538 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors. | 2010-03-25 |
20100072539 | MEMORY CELL OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory cell of a nonvolatile semiconductor memory device according to an embodiment of the invention has a MONOS structure. The charge storage layer of the memory cell includes insulating material layers. The relationship between the conduction band edge energy and valance band edge energy of the insulating material layers either increases gradually or decreases gradually from the tunnel insulating film toward the block insulating film. Furthermore, when the relative permittivity of the block insulating film is expresses as ∈ | 2010-03-25 |
20100072540 | ELECTRONIC CIRCUIT CONTROL ELEMENT WITH TAP ELEMENT - A technique for controlling a power supply with power supply control element with a tap element. An example power supply control element includes a power transistor that has first and second main terminals, a control terminal and a tap terminal. A control circuit is coupled to the control terminal. The tap terminal and the second main terminal of the power transistor are to control switching of the power transistor. The tap terminal is coupled to provide a signal to the control circuit substantially proportional to a voltage between the first and second main terminals when the voltage is less than a pinch off voltage. The tap terminal is coupled to provide a substantially constant voltage that is less than the voltage between the first and second main terminals to the control circuit when the voltage between the first and second main terminals is greater than the pinch-off voltage. | 2010-03-25 |
20100072541 | SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL AREA AND DECREASED LEAKAGE CURRENT - The semiconductor device includes an active region, a recess channel region including vertical channel structures, a gate insulating film, and a gate structure. The active region is defined by a device isolation structure formed in a semiconductor substrate. The recess channel region is formed in the active region. The vertical silicon-on-insulator (SOI) channel structures are disposed at sidewalls of both device isolation structures in a longitudinal direction of a gate region. The gate insulating film is disposed over the active region including the recess channel region. The gate structure is disposed over the recess channel region of the gate region. | 2010-03-25 |
20100072542 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND DATA PROCESSING SYSTEM - Modification of an SOD film is promoted in a hot oxidizing atmosphere. Elements under a liner film and a semiconductor substrate are prevented from being damaged by oxidation. | 2010-03-25 |
20100072543 | TRENCH MOSFET WITH ETCHING BUFFER LAYER IN TRENCH GATE - The present invention is to provide a trench MOSFET with an etching buffer layer in a trench gate, comprising: a substrate which has a first surface and a second surface opposite to each other and comprises at least a drain region, a gate region, and a source region which are constructed as a plurality of semiconductor cells with MOSFET effect; a plurality of gate trenches, each of which is extended downward from the first surface and comprises a gate oxide layer covered on a inner surface thereof and a gate conductive layer filled inside, comprised in the gate region; at least a drain metal layer formed on the second surface according to the drain region; at least a gate runner metal layer formed on the first surface according to the gate region; and at least a source metal layer formed on the first surface according to the source region; wherein the gate trenches distinguished into at least a second gate trench formed at a terminal of the source region and at least a first gate trenches wrapped in the source region; and the second gate trench comprises a gate contact hole which is filled with metal to form a gate metal contact plug, and a gate buffer layer which is formed in the gate conductive layer at the bottom of the gate contact hole in the second gate trench to prevent from over etching, causing gate-drain shortage. | 2010-03-25 |
20100072544 | METHOD OF FORMING AN MOS TRANSISTOR AND STRUCTURE THEREFOR - In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar. | 2010-03-25 |
20100072545 | Recessed Channel Array Transistors, and Semiconductor Devices Including a Recessed Channel Array Transistor - A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current. | 2010-03-25 |
20100072546 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which on-resistance is largely reduced. The semiconductor device includes an n type epitaxial layer ( | 2010-03-25 |
20100072547 | TECHNIQUES FOR CURVATURE CONTROL IN POWER TRANSISTOR DEVICES - Techniques for processing power transistor devices are provided. In one aspect, the curvature of a power transistor device comprising a device film formed on a substrate is controlled by thinning the substrate, the device having an overall residual stress attributable at least in part to the thinning step, and applying a stress compensation layer to a surface of the device film, the stress compensation layer having a tensile stress sufficient to counterbalance at least a portion of the overall residual stress of the device. The resultant power transistor device may be part of an integrated circuit. | 2010-03-25 |
20100072548 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device in which defects in characteristics due to electrostatic discharge is reduced and a method for manufacturing the semiconductor device are provided. The semiconductor device has at least one of these structures: (1) a structure in which a first and second insulating films are in direct contact with each other in a peripheral region of a circuit portion, (2) a structure in which a first and second insulators are closely attached to each other, and (3) a structure in which a first conductive layer and a second conductive layer are provided on outer surfaces of the first insulator and the second insulator, respectively, and electrical conduction between the first and second conductive layers is achieved at a side surface of the peripheral region. Note that the conduction at the side surface can be achieved by cutting a plurality of semiconductor devices into separate semiconductor devices. | 2010-03-25 |
20100072549 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to restrict strain relaxation even if a strained semiconductor element is formed on a very small minute layer. A semiconductor device includes: a substrate; a first semiconductor layer formed into a mesa shape above the substrate and having strain, and including source and drain regions of a first conductivity type located at a distance from each other, and a channel region of a second conductivity type different from the first conductivity type, the channel region being located between the source region and the drain region; second and third semiconductor layers formed on the source and drain regions, and controlling the strain of the first semiconductor layer, the second and third semiconductor layers containing impurities of the first conductivity type; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film. | 2010-03-25 |
20100072550 | Semiconductor device and method of manufacturing the same - A semiconductor device has plural columnar gate electrodes for plural MOSFETs formed in a row separately on a semiconductor substrate, and a semiconductor region which is formed in a part between the neighboring two columnar gate electrodes of the plural columnar gate electrodes to form a channel of the MOSFETs. | 2010-03-25 |
20100072551 | Semiconductor device and manufacturing method of the semiconductor device - A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer. | 2010-03-25 |
20100072552 | FIELD EFFECT TRANSISTOR FOR PREVENTING COLLAPSE OR DEFORMATION OF ACTIVE REGIONS - A field effect transistor includes an active region provided in a projecting part on a surface of a semiconductor substrate, the projecting part extending in a fixed direction parallel to the surface, and a gate electrode provided on a sidewall of the projecting part along the fixed direction with a gate insulating films interposed. | 2010-03-25 |
20100072553 | METAL GATE STRESS FILM FOR MOBILITY ENHANCEMENT IN FinFET DEVICE - A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film. | 2010-03-25 |
20100072554 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insulating film, and first source/drain regions formed in the semiconductor substrate on both sides of the first channel region, the first gate electrode comprising a first metal layer and a first conductive layer thereon; and a p-type transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second channel region formed in the semiconductor substrate under the second gate insulating film, and second source/drain regions formed in the semiconductor substrate on both sides of the second channel region, the second gate electrode comprising a second metal layer and a second conductive layer thereon, the second metal layer being thicker than the first metal layer and having the same constituent element as the first metal layer. | 2010-03-25 |
20100072555 | WAFER BONDING METHOD AND WAFER STACK FORMED THEREBY - A wafer bonding process that compensates for curvatures in wafer surfaces, and a wafer stack produced by the bonding process. The process entails forming a groove in a surface of a first wafer, depositing a bonding stack on a surface of a second wafer, aligning and mating the first and second wafers so that the bonding stack on the second wafer contacts a bonding site on the first wafer, and then heating the first and second wafers to reflow the bonding stack. The groove either surrounds the bonding site or lies entirely within the bonding site, and the heating step forms a molten bonding material, causes at least a portion of the molten bonding material to flow into the groove, and forms a bonding structure that bonds the second wafer to the first wafer. Bonding stacks having different lateral surface areas can be deposited to form bonding structures of different heights to compensate for variations in the wafer gap. | 2010-03-25 |
20100072576 | METHODS AND STRUCTURES FOR ALTERING STRAIN IN III-NITRIDE MATERIALS - Methods and structures for producing semiconductor materials, substrates and devices with improved characteristics are disclosed. Structures and methods for forming reduced strain structures include forming an interface between a support structure surface and a strained semiconductor layer. The support structure is selectively etched to form a plurality of semiconductor islands with reduced levels of strain. | 2010-03-25 |
20100072577 | Methods and Devices for Fabricating and Assembling Printable Semiconductor Elements - The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations. | 2010-03-25 |
20100072578 | Semiconductor chip and semiconductor wafer - A semiconductor chip which includes an element forming region formed over a substrate, a scribe line region which surrounds the element forming region, and a structure provided locally inside the scribe line region in at least one corner area of the semiconductor chip. The element forming region and the scribe line region include a plurality of interlayer dielectric films laminated over the substrate. The structure is constituted of corner pads sandwiching at least one of the interlayer dielectric films vertically in the direction of lamination, and vias interconnecting the corner pads. | 2010-03-25 |
20100072579 | Through Substrate Conductors - Structures and methods of forming through substrate vias are disclosed. In one embodiment, the method includes forming a through substrate opening from a top surface of a substrate, the top surface including active devices, and filling the first through substrate opening with an ancillary material. A conductive capping layer is formed over the ancillary material to cap the first through substrate opening. The substrate is thinned from a back surface to expose a portion of the ancillary material, the back surface being opposite to the top surface. The ancillary material is removed from the first through substrate opening, and a conductor is formed by filling a conductive material into the through substrate opening. | 2010-03-25 |
20100072580 | ULTRA-THIN OXIDE BONDING FOR SI TO SI DUAL ORIENTATION BONDING - A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the same or different crystal orientations. The interfacial layer can be an oxide layer from about 5 Angstroms to about 50 Angstroms. | 2010-03-25 |
20100072581 | COMPOSITION FOR FILM FORMATION, INSULATING FILM, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING THE SEMICONDUCTOR DEVICE - According to one aspect of the present invention, there is provided a composition for film formation, comprising a compound represented by general formula (I) or a hydrolyzed-dehydrocondensation product thereof: | 2010-03-25 |
20100072582 | Semiconductor Device and Method of Electrically Connecting a Shielding Layer to Ground Through a Conductive Via Disposed in Peripheral Region Around Semiconductor Die - A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate. | 2010-03-25 |
20100072583 | Semiconductor Device and Manufacturing Method of the Same - With the use of a conductive shield formed on the top or bottom side of a semiconductor integrated circuit, an electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) of the semiconductor integrated circuit due to electrostatic discharge is prevented, and sufficient communication capability is obtained. With the use of a pair of insulators which sandwiches the semiconductor integrated circuit, a highly reliable semiconductor device that is reduced in thickness and size and has resistance to an external stress can be provided. A semiconductor device can be manufactured with high yield while defects of shapes and characteristics due to an external stress or electrostatic discharge are prevented in the manufacturing process. | 2010-03-25 |
20100072584 | COPPER ALLOY SHEET FOR ELECTRIC AND ELECTRONIC PARTS - A Cu—Fe—P alloy sheet that is provided with the high strength and with the improved resistance of peel off of oxidation film, in order to deal with problems such as package cracks and peeling, is provided. A copper alloy sheet for electric and electronic parts according to the present invention is a copper alloy sheet containing Fe: 0.01 to 0.50 mass % and P: 0.01 to 0.15 mass %, respectively, with the remainder of Cu and inevitable impurities. A centerline average roughness Ra is 0.2 μm or less and a maximum height Rmax is 1.5 μm or less, and Kurtosis (degree peakedness) Rku of roughness curve is 5.0 or less, in measurement of the surface roughness of the copper alloy sheet in accordance with JIS B0601. | 2010-03-25 |
20100072585 | TOP EXPOSED CLIP WITH WINDOW ARRAY - A clip for a semiconductor device package may include a metal sheet including an array of windows and one or more conductive fingers. Each of the conductive fingers has a first end and a second end. The first end is electrically connected to the metal sheet at one of the windows. Each of the conductive fingers is adapted to provide electrical connection to a top semiconductor region of a semiconductor device or a lead frame at the second end. | 2010-03-25 |
20100072606 | Stacking Package Structure with Chip Embedded Inside and Die Having Through Silicon Via and Method of the same - The semiconductor device package structure includes a first die with a through silicon via (TSV) open from back side of the first die to expose bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via (TSV); a substrate with a second die embedded inside and top circuit wiring and bottom circuit wiring on top and bottom side of the substrate respectively; and a conductive through hole structure coupled between the terminal metal pads to the top circuit wiring and the bottom circuit wiring. | 2010-03-25 |
20100072607 | TAB PACKAGE CONNECTING HOST DEVICE ELEMENT - A device is provided in which a glass panel having beveled edge is flexibly connected to a TAB package. The outer lead portions of the TAB package include an end portion of first width connected to a connection pattern on the glass panel, a terminal portion having a second width greater than the first width, and a transition portion having a width that varies between the first and second widths. When the TAB package is connected the transition portion of the respective outer lead portions are disposed over the beveled edge of the glass panel. | 2010-03-25 |
20100072608 | Semiconductor device - A semiconductor device is disclosed which includes a metal base, a semiconductor chip, a lead, and a sealant. The semiconductor chip has an opposite pair of first and second electrode surfaces and a side surface. The semiconductor chip is fixed on the metal base with the first electrode surface solder-connected to the metal base. The lead is solder-connected to the second electrode surface of the semiconductor chip. The sealant seals, at least, the side surface of the semiconductor chip and solders connecting the metal base, the semiconductor chip, and the lead. Further, the lead has a small-cross-section portion which has a smaller cross-sectional area perpendicular to the longitudinal direction of the lead than other portions of the lead adjacent to the small-cross-section portion. | 2010-03-25 |
20100072609 | Socket for semiconductor integrated circuit - Provided is a socket for semiconductor integrated circuit allowing a semiconductor integrated circuit to be analyzed easily. The socket for semiconductor integrated circuit according to the invention is used by mounting a package thereon. The socket for semiconductor integrated circuit includes: a socket main body which covers both a front-side surface and a back-side surface of the package and is provided with a window formed above either of the two surfaces of the package; bottom-side socket pins provided corresponding respectively to package balls of the package; upper-side socket pins provided corresponding respectively to the package balls of the package at the time when the package is mounted upside down; and wirings which electrically connect the bottom-side socket pins to the corresponding upper-side socket pins, respectively. | 2010-03-25 |
20100072610 | Process for Precision Placement of Integrated Circuit Overcoat Material - The present invention provides a process for manufacturing an integrated circuit (IC) package and an integrated circuit (IC) package. The process, without limitation, includes providing an integrated circuit chip having a configuration, and forming a layer of overcoat material over the integrated circuit chip based upon the configuration. | 2010-03-25 |
20100072611 | Semiconductor Device and Method for Manufacturing the Same - An object is to provide a thin and small semiconductor device that has high reliability and high resistance to external stress and electrostatic discharge. Another object is to manufacture a semiconductor device with high yield while shape defects and defective characteristics which are caused by external stress or electrostatic discharge are prevented in the manufacturing process. A conductive shield covering a semiconductor integrated circuit prevents electrostatic breakdown (malfunction of the circuit or damage to a semiconductor element) of the semiconductor integrated circuit due to electrostatic discharge. By providing an antenna on the external side of the conductive shield, a sufficient communication capability is secured. With the use of a pair of insulators which sandwich the semiconductor integrated circuit, a thin and small semiconductor device that has resistance properties and high reliability can be provided. Further, shape defects and defective characteristics which are caused by external stress or electrostatic discharge are prevented in the manufacturing process, so that a semiconductor device can be manufactured with high yield. | 2010-03-25 |
20100072612 | BARE DIE PACKAGE WITH DISPLACEMENT CONSTRAINT - Embodiments of the present invention describe a bare die package and its methods of fabrication The bare die package comprises a die electrically coupled to a package substrate, and a displacement constraint. In an embodiment of the present invention, the displacement constraint is a plurality of members fixedly attached onto the package substrate and surrounds the die. When the bare die package is secured between a socket and a heat sink, the plurality of members provide structural support to the package substrate and prevent excessive substrate warpage. | 2010-03-25 |
20100072613 | INKJET PRINTED LEADFRAME - Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays. | 2010-03-25 |
20100072614 | 3-DIMENSIONAL INTEGRATED CIRCUIT DESIGNING METHOD - A 3-dimensional integrated circuit designing method includes forming a temporary layout region for an original integrated circuit on an XY plane, the plane being short in an X direction and long in a Y direction perpendicular to the X direction, dividing the temporary layout region into 2N (N is an integral number of not smaller than 2) or more subregions in the Y direction, configuring one block for every successive N subregions to prepare a plurality of blocks, and forming N layers of layout by alternately folding each of the blocks in the Y direction in units of one subregion to selectively set a kN-th (k is an integral number not less than 1) subregion and (kN+1)th subregion of each block to one of an uppermost layer and lowermost layer. | 2010-03-25 |
20100072615 | High-Electrical-Current Wafer Level Packaging, High-Electrical-Current WLP Electronic Devices, and Methods of Manufacture Thereof - The present invention has various aspects relating to the maximization of current carrying capacity of wafer level packaged chip scale solder pad mounted integrated circuits. In one aspect, the solder pad areas are maximized by using rectangular solder pads spaced as close together as reliable mounting to a circuit board will allow. In another aspect, multiple contact pads may be used for increasing the current capacity without using contact pads of different areas. In still another aspect, vias are used to directly connect one lead of high current component or components to a contact pad directly above that component, and to route a second lead of the high current component to an adjacent contact pad by way of a thick metal interconnect layer. | 2010-03-25 |
20100072616 | METHOD OF MANUFACTURING AN ELECTRONIC SYSTEM - A method of manufacturing an electronic system. One embodiment provides a semiconductor chip having a first main face and a second main face opposite to the first main face. A mask is applied to the first main face of the semiconductor chip. A compound is applied to the first main face of the semiconductor chip. The compound includes electronically conductive particles. The semiconductor chip is coupled to a carrier with the compound facing the carrier. | 2010-03-25 |
20100072617 | Multiple die structure and method of forming a connection between first and second dies in same - A multiple die structure includes a first die ( | 2010-03-25 |
20100072618 | Semiconductor Device and Method of Forming a Wafer Level Package with Bump Interconnection - A semiconductor device is made by providing a metal substrate for supporting the semiconductor device. Solder bumps are connected to the substrate. In one embodiment, a conductive material is deposited over the substrate and is reflowed to form the solder bumps. A semiconductor die is mounted to the substrate using a die attach adhesive. The semiconductor die has a plurality of contact pads formed over a surface of the semiconductor die. An encapsulant material is deposited over the solder bumps and the semiconductor die. The encapsulant is etched to expose the contact pads of the semiconductor die. A first redistribution layer (RDL) is formed over the encapsulant to connect each contact pad of the semiconductor die to one of the solder bumps. The substrate is removed to expose the die attach adhesive and a bottom surface of the solder bumps. | 2010-03-25 |
20100072619 | WIRE BONDING STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention relates to a wire bonding structure, and more particularly to a manufacturing method for said wire bonding structure. The wire bonding structure comprises a die that connects with a lead via a bonding wire. At least one bond pad is positioned on an active surface of the die, and a gold bump is provided on the bond pad; furthermore, a ball bond can be positioned upon the gold bump. The bond pad and the gold bump can separate the ball bond and the die, which can avoid damaging the die during the bonding process. | 2010-03-25 |
20100072620 | Semiconductor Chip with Backside Conductor Structure - Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure is formed in the bore to establish an electrically conductive pathway between the semiconductor device layer and the conductor structure. The conductor structure may provide a diagnostic pathway. | 2010-03-25 |
20100072621 | ELECTRONIC COMPONENT - An electronic component has a metallic layer on a substrate made of a semiconductor material, a diffusion barrier layer that is made of a material that has a small diffusion coefficient for the metal of the metallic layer being formed between the metallic layer and the substrate. | 2010-03-25 |
20100072622 | Method for forming Barrier Layer and the Related Damascene Structure - A method for forming barrier layers comprises steps of forming a first metal barrier layer covering a first dielectric layer and contacting a conductive layer through a via of the first dielectric layer, forming a barrier layer of metalized materials on the first metal layer, optionally forming a second metal barrier layer on the barrier layer of metalized materials, removing portions of the barrier layer of metalized materials above the via bottom in the first dielectric layer, and leaving the barrier layer of metalized materials remaining on the via sidewall in the first dielectric layer; and forming a second metal layer covering the barrier layer of metalized materials. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer. | 2010-03-25 |
20100072623 | SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT PLUGS, AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided herein. One fabrication method relates to the formation of conductive contact plugs for a semiconductor device. The method begins by providing a semiconductor device structure having a conductive contact region, a layer of insulating material overlying the conductive contact region, and a via formed in the layer of insulating material and terminating at the conductive contact region. The fabrication process then deposits a first electrically conductive material on the semiconductor device structure such that the first electrically conductive material at least partially fills the via. Then, the process anisotropically etches a portion of the first electrically conductive material located in the filled via, resulting in a lined via. Thereafter, the process deposits a second electrically conductive material on the semiconductor device structure such that the second electrically conductive material at least partially fills the lined via. | 2010-03-25 |
20100072624 | METAL INTERCONNECTION - A metal interconnection including a substrate, a first conductive structure, a second conductive structure, a complex plug and a plug is provided. The substrate includes a first region and a second region. The first conductive structure is disposed on the first region. The second conductive structure is disposed on the second region. The complex plug is disposed on the first conductive structure and includes a tungsten layer and a plurality of insulator columns, wherein an extended direction of each of the insulator columns is perpendicular to a surface of the substrate and the tungsten layer is electrically connected with the first conductive structure. The plug is disposed on the second conductive structure and electrically connected with the second conductive structure. | 2010-03-25 |
20100072625 | Semiconductor device including power supply pad and trunk wiring which are arranged at the same layer level - A semiconductor device includes a semiconductor substrate which includes a functional circuit, a trunk wiring which passes through a portion near a position immediately above a center portion of the functional circuit, a power supply pad which is connected to an end of the trunk wiring and placed at a layer level which is same as a layer level where the trunk wiring is placed, and a connection wiring which connects a substantially center portion of the functional circuit and the trunk wiring. | 2010-03-25 |
20100072626 | WAFER LEVEL PACKAGED MEMS INTEGRATED CIRCUIT - A wafer-level packaged integrated circuit includes a semiconductor substrate including a first silicon layer. A micro-electromechanical system (MEMS) device is integrated into the first silicon layer. A thin-film deposited sealing member is deposited over the first silicon layer and is configured to seal a cavity in the first silicon layer. At least one additional layer is formed over the sealing member. At least one under bump metallization (UBM) is formed over the at least one additional layer. | 2010-03-25 |
20100072627 | WAFER INCLUDING INTERCEPTING THROUGH-VIAS AND METHOD OF MAKING INTERCEPTING THROUGH-VIAS IN A WAFER - A semiconductor device includes a substrate; a first via provided in the substrate extending from a first side of the substrate to a first depth into the substrate, the first depth being less than a thickness of the substrate and the first via having a first width in one direction; a first conductive material provided in the first via; a second via provided in the substrate extending from a second side of the substrate to a second depth into the substrate, the second via having a second width in one direction, the second width being greater than the first width; and a second conductive material provided in the second via so as to form an electrical connection with the first conductive material provided in the first via. | 2010-03-25 |
20100072628 | SEMICONDUCTOR DEVICE - A semiconductor device includes a carrier and a first chip attached to the carrier. The semiconductor device includes a sintered insulation material over at least a portion of the carrier and the first chip. | 2010-03-25 |
20100072629 | Wiring Structure, Semiconductor Device Having the Wiring Structure, and Method for Manufacturing the Semiconductor Device - A wiring structure, a semiconductor device having the structure, and a method for manufacturing the semiconductor device are disclosed. The wiring structure includes a first metal layer, a second metal layer on the first metal layer, an insulating layer between the first metal layer and the second metal layer, and a metal via pattern formed in the insulating layer to electrically connect the first and second metal layers to each other. The metal via pattern includes a plurality of metal vias spaced apart from one another, and each of the metal vias includes a vertical via line extending in a vertical direction and a horizontal via line extending in a horizontal direction to cross the vertical via line. The wiring structure may achieve minimized chip defects, fewer cracks in the insulating layer, effective use of the occupation area of a semiconductor chip, and reduced chip size and manufacturing costs. | 2010-03-25 |
20100072630 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ADHESIVE SEGMENT SPACER - An integrated circuit package system includes attaching an adhesive segment spacer to an interposer assembly; mounting an integrated circuit over a carrier; mounting the interposer assembly over the integrated circuit with the adhesive segment spacer exposing an inner region of the integrated circuit and covering a periphery of the integrated circuit; and forming an encapsulation over the integrated circuit, the interposer assembly, and the adhesive segment spacer with the interposer assembly exposed with a recess in the encapsulation. | 2010-03-25 |
20100072631 | CONNECTION BY FITTING TOGETHER TWO SOLDERED INSERTS - A connection device between two components includes a hollow conductive insert, into which is fitted another conductive insert, the electrical connection between the two inserts being provided by means of a solder element. | 2010-03-25 |
20100072632 | BOND PAD STRUCTURE HAVING DUMMY PLUGS AND/OR PATTERNS FORMED THEREAROUND - A semiconductor structure is provided. In one embodiment, a bond pad is formed above one or more underlying layers of a substrate. A plurality of dummy plugs are spaced around the bond pad, the plurality of dummy plugs substantially vertically traversing the one or more underlying layers, wherein the plurality of dummy plugs anchor at least two of the underlying layers together to achieve improved mechanical strength. | 2010-03-25 |
20100072633 | Semiconductor apparatus with thin semiconductor film - A semiconductor apparatus includes a substrate having at least one terminal, a thin semiconductor film including at least one semiconductor device, the thin semiconductor film being disposed and bonded on the substrate; and an individual interconnecting line formed as a thin conductive film extending from the semiconductor device in the thin semiconductor film to the terminal in the substrate, electrically connecting the semiconductor device to the terminal. Compared with conventional semiconductor apparatus, the invented apparatus is smaller and has a reduced material cost. | 2010-03-25 |
20100072634 | PLANAR ENCAPSULATION AND MOLD CAVITY PACKAGE IN PACKAGE SYSTEM - An integrated circuit package system includes: providing a substrate; mounting a first package above the substrate, the first package having a mold cavity exposing an exposed portion on a first integrated circuit from a first package encapsulation; mounting a second package above the first package and attached to the exposed portion of the first integrated circuit; mounting a structure above the second package and connected to the substrate around the first package; and encapsulating the first package and the second package with an outer encapsulation having a completely planar top or a planar top co-planar to a top surface of the structure. | 2010-03-25 |
20100072635 | Protecting Sidewalls of Semiconductor Chips using Insulation Films - A method of forming an integrated circuit structure includes providing a wafer having a first semiconductor chip, a second semiconductor chip, and a scribe line between and adjoining the first semiconductor chip and the second semiconductor chip; forming a notch in the scribe line, wherein the notch has a bottom no higher than a top surface of a semiconductor substrate in the wafer; forming a first insulation film over the wafer, wherein the first insulation film extends into the notch; removing a portion of the first insulation film from a center of the notch, wherein a remaining portion of the first insulation film comprises an edge in the notch; and sawing the wafer to separate the first semiconductor chip and the second semiconductor chip. | 2010-03-25 |
20100072646 | Retract mechanism for injection blow molding - A bottom plug retract mechanism for use in a blow mold having a top die and a bottom die defining at least a portion of a mold cavity, the mechanism including a plug that is operable to move away from the mold cavity at an angle to the parting plane when the mold cavity is opened. | 2010-03-25 |
20100072647 | PATTERNING METHOD - A patterning method according to an embodiment of the present invention comprises: acquiring information about a surface state of an underlying film formed on a substrate; determining, based on the surface state, whether irregularity/foreign matter is present in each shot region in which a pattern is to be formed; and solidifying a resist agent while a first template, when it is determined that no irregularity/foreign matter is present in the shot region, or a second template that is different from the first template, when it is determined that irregularity/foreign matter is present in the shot region, is brought close to the underlying film on the shot region at a certain distance with the resist agent therebetween. | 2010-03-25 |
20100072648 | ALIGNED SUPPLY APPARATUS AND ALIGNED SUPPLY METHOD FOR GREEN TIRES - Positional misalignment between a mold and a green tire in a vulcanizer is identified in the PCI step and is fed back in real time to a green-tire supply apparatus so that the misalignment is automatically corrected. During post-cure inflation of a vulcanized tire (T), the RRO value of the tire is measured, and the measured RRO value is compared with a preset reference value. If the measured RRO value exceeds the reference value, a control signal is output to an apparatus for supplying a green tire to a vulcanizer. The green-tire supply apparatus performs positional correction of a green tire with respect to the vulcanizer's mold in accordance with the control signal, that is, performs correction of the position and angle of green-tire gripping means to adjust the concentricity and parallelism of the green tire with respect to the mold. | 2010-03-25 |
20100072649 | IMPRINT APPARATUS AND ARTICLE MANUFACTURING METHOD - An imprint apparatus molds resin dispensed on a shot region of a substrate with a mold and forms a pattern of resin on the shot region. The apparatus includes a mold stage configured to hold the mold, a substrate stage configured to hold the substrate, a drive mechanism configured to change a relative positional relationship between the mold stage and the substrate stage in an X-Y plane that defines a coordinate of the shot region and a Z-axis direction perpendicular to the X-Y plane, and a controller. The controller is configured to control the drive mechanism so that the mold and the shot region perform relative vibration, in the X-Y plane, with respect to a relative position where the mold and the shot region align, and a distance between the mold and the shot region decreases in the Z-axis direction in parallel with the vibration, and the resin is molded by the mold. | 2010-03-25 |
20100072650 | METHOD AND DEVICE FOR OPERATING A DRAWING LINE OR DRAWING UNIT - A method and device for operating a drawing line or drawing unit for drawing cables from polymer threads using a plurality of driven drawing rollers. According to the invention, each drawing roller is controlled to a prescribed motion value. To this end, each drawing roller is associated with a separately controllable drive device. | 2010-03-25 |
20100072651 | METHOD FOR THE PRODUCTION OF POLYURETHANE BLOCK FOAM - The invention relates to a process and a device for the production of polyurethane clock foam, in which the reaction mixture, after flowing through a mixer, flows freely from an outflow opening and then flows through an accumulation chamber, in which a static pressure is built up, a gap and finally an expansion chamber. | 2010-03-25 |
20100072652 | IMPRINT LITHOGRAPHY SYSTEM AND METHOD - System, method and process for imprinting a substrate using controlled deformation of a substrate and/or a template. The substrate and/or template may be positioned in single wave formation or double wave formation during an imprint lithography process. | 2010-03-25 |
20100072653 | IMPRINTING APPARATUS AND METHOD THEREFOR - There is provided an imprinting apparatus that transfers a pattern of a mold to a resin on a substrate, the imprinting apparatus including a deposition mechanism configured to deposit the resin onto the substrate; a first driving mechanism configured to change a relative position, on a plane parallel to the surface of the substrate, of the substrate and the mold; a second driving mechanism configured to change the relative position, on a plane parallel to the surface of the substrate, of the substrate and the deposition mechanism; and a control unit configured to control the deposition mechanism and the driving mechanism so as to perform a resin deposition process of depositing the resin onto the substrate and an imprint process of transferring the pattern of the mold to the resin on the substrate in parallel. | 2010-03-25 |
20100072654 | METHOD FOR PRODUCING PROFILE PARTS - The present invention relates to a method for producing profile parts, each having an L-shaped cross-section, or an assembled profile part having, in particular, a T-shaped cross-section. For this purpose a lay-up made of composite fibre material is initially placed on a forming tool. In a further step, the lay-up is deformed by the forming tool to form a profile having a preferably U-shaped cross-section, the profile thus exhibiting the book effect at each opposite end. In a further step, the profile is preferably cut in the longitudinal direction in order to produce two profile parts. The idea on which the invention is based is to allow the layers in the lay-up to shift during the deformation process and subsequently to produce a substantially right-angled chamfered end on the profile parts by means of a cutting process. The disadvantageous formation of corrugations and complex clamping of the lay-up are thus avoided. | 2010-03-25 |
20100072655 | Die, system, and method for coextruding a plurality of fluid layers - A die for coextruding a plurality of fluid layers generally includes a primary forming stem, one or more distribution plates, and a microlayer assembly. The microlayer assembly includes a microlayer forming stem and a plurality of microlayer distribution plates. | 2010-03-25 |
20100072676 | PRE-CONDITIONED FOAM PAD - Mattresses and methods for processing a flexible foam material for use in a mattress to provide a mattress foam material that has more consistent firmness over time and area. The methods include pre-conditioning the foam pad or mattress by applying a force across a substantial portion of a major surface of the mattress to compress or stretch the height of the foam, the length of the foam, and/or the width of the foam to break or open closed cells. In certain embodiments, the force is applied by repeatedly pressing a platen against the foam pad or placing the foam pad between one or more rollers. | 2010-03-25 |
20100072677 | Apparatus and Method for Preform Relaxation and Flow Control in Liquid Composite Molding Processes - A vacuum-induced injection molding apparatus is disclosed. The apparatus includes a tool surface having an injection port extending therethrough. A flexible film extends over and is sealingly coupled to the tool surface. The flexible film comprises an outer surface and an inner surface such that the flexible film inner surface and the tool surface define a volume. A vacuum chamber is sealingly coupled to the outer surface of the flexible film. A vacuum port is in fluid communication with the volume. A method of injection molding a polymer matrix composite is also disclosed. | 2010-03-25 |
20100072678 | Method and Apparatus for Producing a Composite Component - The invention relates to a method and device ( | 2010-03-25 |
20100072679 | Container Made From Expanded Plastic Film - A plastic film preform is expanded to form a container. The preform has a longitudinal axis that extends from an open top to a closed bottom. The preform is pressurized with a first pressure sufficient to cause side walls of the preform to expand outwardly and the bottom of the preform to be drawn inwardly thereby reducing a length of the preform along the longitudinal axis. Side molds are closed around the side walls of the preform, the closed side molds being larger than the expanded side walls. A bottom mold is closed to be adjacent to the bottom of the preform after pressurizing the preform with the first pressure. The preform is pressurized with a second pressure sufficient to expand the preform to fill the closed molds. The preform is thereby significantly stretched in a direction perpendicular to the longitudinal axis and minimally stretched along the longitudinal axis. | 2010-03-25 |
20100072680 | METHOD FOR INJECTION MOLDING OF HOLLOW ARTICLES OF PLASTIC MATERIAL - An injection molding method to manufacture hollow plastic parts, whereby at least one plastic part's hollow is shaped by evacuating an internal portion of the flowable material of an injection mold's cavity ( | 2010-03-25 |
20100072681 | METHOD AND DEVICE FOR THE INDUSTRIAL THERMAL TREATMENT OF ELONGATED MECHANICAL PARTS - A device for the thermal treatment of elongated mechanical parts including an oven having a cylinder barrel arranged into a heated enclosure, the barrel having at least one ring driven in rotation around an axis of axial symmetry of the cylinder barrel by a driving mechanism. The ring including at least one storage pipe parallel to the axis of axial symmetry able to receive at least one mechanical part to be heated, and the enclosure having an inlet and an outlet for the mechanical parts which are equidistant from the axis of axial symmetry for each ring of the barrel. A method for the thermal treatment of mechanical parts is also provided. | 2010-03-25 |
20100072682 | MINI TORCH WITH TORCH HOLDER AND TORCH ADAPTER - An exothermic mini torch includes a torch holder assembly for holding a consumable thermal torch. The torch holder assembly includes a body defining a recess into which the consumable thermal torch is inserted. A passage is defined in the body having a first end fluidly connected to the gas source and a second end fluidly connected to the recess for delivering gas from the gas source to the consumable thermal torch. A filter is optionally disposed between the gas source and the consumable thermal torch adjacent the second end of the passage for filtering the gas and preventing backflow of the gas into the body. A seal is received in the recess and is optionally annularly disposed between an outer circumferential surface of the consumable thermal torch and a portion of the body forming the recess to direct the gas into the consumable thermal torch. | 2010-03-25 |
20100072683 | LIQUID SEALED VIBRATION ISOLATING DEVICE - To form a relief valve for preventing the generation of the cavitation phenomenon into a simple and accurately operable structure, there are provided a central thin wall portion and a fixing portion in an elastic diaphragm provided in the partition member to have the fixing portion fixed in position. A relief valve is integrally formed with an outer peripheral portion of the fixing portion. The relief valve is provided with an inclined surface formed on the side of a secondary liquid chamber and a recessed portion opened on the side of a primary liquid chamber and has a difference in rigidity in the circumferential direction. When the primary liquid chamber turns negative pressure, a hydraulic liquid in the secondary liquid chamber opens the relief valve and leaks to the primary liquid chamber so as to prevent the generation of the cavitation phenomenon. | 2010-03-25 |
20100072684 | NODAL SPRING ASSEMBLY FOR AN ELECTRONIC TOOTHBRUSH - A nodal-mounted spring arrangement for an electronic toothbrush includes a V-shaped spring member secured at both ends so that it can operate in out-of-phase torsion mode along the axial dimension thereof. A mounting plate is connected between a node point along the V-shaped spring member and the housing of the toothbrush. In one embodiment, the V-shaped spring member includes opposing slots on opposite sides of the node point, the slots extending in an axial direction, creating an integrated torsion bar node spring, while reducing stress in the vicinity of the nodal point. In another embodiment, a nodal assembly comprises a diamond shaped or round insert having an upper surface configured generally to fit flush with the lower surface of the V-shaped spring member, a V-block shaped or flat shim member which is configured to mate the upper surface of the V-shaped spring member and the node spring, and an attachment member, such as a screw and nut combination, which tightly connects the mounting plate, the shim, the V-shaped spring member and the insert. | 2010-03-25 |
20100072685 | METHODS AND APPARATUS FOR A SUSPENSION SYSTEM WITH PROGRESSIVE RESISTANCE - A suspension component achieves progressive resistance via a secondary bleed valve, which functions as a support for the primary compression valve at higher displacements, in conjunction with a secondary nonlinear spring element configured to alter the force on the piston at high displacements. | 2010-03-25 |
20100072687 | JIG AND METHOD FOR PROCESSING CYLINDER BLOCK - In a dummy head (a jig for processing a cylinder block) having a dummy head body deforming a cylinder bore by assembling into a mounting surface of the cylinder block by bolt fastening, during the finish processing of the cylinder bore, a boss having a contact surface contacting a peripheral portion of the cylinder bore on the head mounting surface is provided on a mounting surface side for the cylinder block of the dummy head body, and at least the dummy head body has a higher rigidity than the cylinder block. | 2010-03-25 |
20100072688 | Machining unit - The invention refers to a machining unit with a work piece changing unit, the work piece changing unit having a cover which can swivel around a rotational axis, and opens and closes the working room of the machining unit for work piece changing processes. The work piece changing unit has at least two lifting and lowering work piece carriers separated by the cover. The work piece carrier remains in the working room during the machining by the machining unit. | 2010-03-25 |
20100072689 | MEDIA PROCESSING DEVICE, CONTROL METHOD FOR A MEDIA PROCESSING DEVICE, AND A CONTROL PROGRAM THEREFOR - A media processing device, a control method for a media processing device, and a control program for the same can accurately detect the last one or specified number of media stored in the media stacker. Media stackers store media in a stack. Media processing units write data and/or print a label on the media. A media transportation mechanism has a transportation arm that can hold the media and move vertically, and transports the media between the media stackers and the media processing units by movement of the transportation arm. A control unit controls the media processing units and the media transportation mechanism | 2010-03-25 |
20100072690 | SHEET FEEDING APPARATUS AND IMAGE FORMING APPARATUS - Sheets fed out of a cassette supporting the sheets by a pickup roller are separated and fed by a sheet separation feeding unit having a feed roller and a separating roller which is rotatable in a direction opposite to a sheet feeding direction. A charge eliminating mechanism for eliminating charges of the separating roller is arranged on the upstream side in the sheet feeding direction in a separation nip portion between the feed roller and the separating roller. | 2010-03-25 |