12th week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120068210 | LIGHT EMITTING COMPONENT AND MANUFACTURING METHOD THEREOF - A light emitting component, and more particularly to a white light emitting component with high light emitting efficiency are provided. The white light emitting component with high light emitting efficiency has properties of high driving voltage, high color render index and concentrated optical density. The light emitting component includes a plurality of different light emitting diode chip groups for emitting a number of lights in different wavelength ranges and a wavelength conversion fluorescent material. A manufacturing method by stacking miniature light emitting diode chip groups to form the white light emitting component is also provided. | 2012-03-22 |
20120068211 | LED PACKAGE STRUCTURE - An LED (light-emitting diode) package structure includes a substrate, at least one LED unit disposed on the substrate for generating a light beam, and an optical correcting element disposed within a travelling path of the light beam. The optical correcting element includes a transparent body disposed on and cooperating with the substrate to define a reception chamber with an opening for access into the reception chamber and a transparent encapsulated body injected into the reception chamber via the opening for encapsulating the LED unit therewithin. | 2012-03-22 |
20120068212 | LIGHT-EMITTING DEVICE - According to one embodiment, a light emitting device includes a light emitting element, a light reflector and a sealing resin layer. The light emitting element has a first major surface and a side surface and has an optical axis of emitted light perpendicular to the first major surface. The light reflector has a light reflecting surface capable of reflecting emission light from the side surface of the light emitting element. The sealing resin layer covers the light emitting element and the light reflecting surface, and includes a first curved surface having a vertex on the optical axis and being convex toward light emitting side and an envelope surface generated by moving a second curved surface. The second curved surface has a vertex on a line passing through the light reflecting surface and being parallel to the optical axis and is convex toward the light emitting side. | 2012-03-22 |
20120068213 | LIGHT EMISSIVE CERAMIC LAMINATE AND METHOD OF MAKING SAME - A laminated composite includes a wavelength-converting layer and a non-emissive blocking layer, wherein the emissive layer includes a garnet host material and an emissive guest material, and the non-emissive blocking layer includes a non-emissive blocking material. The metallic element constituting the non-emissive blocking material has an ionic radius which is less than about 80% of an ionic radius of an A cation element when the garnet or garnet-like host material is expressed as A | 2012-03-22 |
20120068214 | OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optoelectronic device is provided that includes a substrate having a surface and a normal direction perpendicular to the surface, a first semiconductor layer formed on the surface, and at least one hollow component formed between the first semiconductor layer and the surface. A method of fabricating an optoelectronic device is also provided that includes providing a substrate having a surface and a normal direction perpendicular to the surface, forming a first semiconductor layer on the surface, patterning the first semiconductor layer, forming a second semiconductor layer on the substrate and cover the patterned first semiconductor layer, and forming at least one hollow component formed between the first semiconductor layer and the surface. A height of the hollow component varies along with a first direction perpendicular to the normal direction and/or a width of the hollow component varies along with a second direction parallel with the normal direction. | 2012-03-22 |
20120068215 | LIGHT EMITTING DEVICE - A light emitting device is provided. According to an embodiment, the light emitting device includes a first layer to diffuse first light emitted from the active layer, and a second layer to convert the diffused first light into second light having a different wavelength than the first light. Accordingly, it may be possible to diffuse first light emitted from the light emitting structure and to wavelength-convert the first light into second light because the conversion layer including the first and second layers is disposed on the light emitting structure. | 2012-03-22 |
20120068216 | PHOTOELECTRIC DEVICE, METHOD OF FABRICATING THE SAME AND PACKAGING APPARATUS FOR THE SAME - A photoelectric device includes a ceramic substrate defining a cavity in a top thereof and having two electrode layers beside the cavity. A photoelectric die is received in the cavity. A first packing layer is received in the cavity and encapsulates the photoelectric die. The photoelectric die is electrically connected with the electrode layers via two wires. A reflective cup is mounted on the ceramic substrate and defines a receiving space above the top of the ceramic substrate and the first packing layer. A second packing layer is received in the receiving space and covers the first packing layer. | 2012-03-22 |
20120068217 | LIGHT EMITTING DEVICE - A light emitting device includes an active layer; at least a portion of the active layer constitutes a gain region. The gain region is continuous from a first end surface and a second end surface. The gain region includes a first portion extending from the first end surface to a first reflective surface in a direction tilted with respect to a normal to the first side surface as viewed two-dimensionally; a second portion extending from the second end surface to the second reflective surface in a direction tilted with respect to a normal to the first side surface as viewed two-dimensionally; and a third portion extending from the first reflective surface to the second reflective surface in a direction tilted with respect to a normal to the first reflective surface as viewed two-dimensionally. | 2012-03-22 |
20120068218 | THERMALLY EFFICIENT PACKAGING FOR A PHOTONIC DEVICE - The present disclosure provides a method of packaging for a photonic device, such as a light-emitting diode device. The packaging includes an insulating structure. The packaging includes first and second conductive structures that each extend through the insulating structure. A substantial area of a bottom surface of the light-emitting diode device is in direct contact with a top surface of the first conductive structure. A top surface of the light-emitting diode device is bonded to the second conductive structure through a bonding wire. | 2012-03-22 |
20120068219 | MICROENCAPSULATED PARTICLES AND PROCESS FOR MANUFACTURING SAME - Microencapsulated particles having improved resistance to moisture and extended release capabilities are produced by microencapsulating the particles in a film-forming, cross-linked, hydrolyzed polymer. | 2012-03-22 |
20120068220 | REVERSE CONDUCTING-INSULATED GATE BIPOLAR TRANSISTOR - According to one embodiment, in a reverse conducting-insulated gate bipolar transistor, the buffer layer is provided on the backside of the second base layer, has a higher impurity concentration in comparison with the second base layer. The first collector layer is in contact with a portion of the backside of the buffer layer, has a higher impurity concentration in comparison with the second base layer. The second collector layer is in contact with a portion of the backside of the buffer layer, is provided so as to surround the first collector layer, has a higher impurity concentration in comparison with the first base layer. The third collector layer is in contact with a portion of the backside of the buffer layer, is provided so as to surround the second collector layer, has a higher impurity concentration in comparison with the second collector layer. | 2012-03-22 |
20120068221 | SEMICONDUCTOR DEVICE - A semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes first and second regions. The first region is provided between the first trenches. The second region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer. The second region has less second conductivity type impurities than the first region. | 2012-03-22 |
20120068222 | Semiconductor Device and Method for Manufacturing the Same - According to an embodiment, a semiconductor device includes a first trench being provided in an N | 2012-03-22 |
20120068223 | BIDIRECTIONAL PROTECTION COMPONENT - A bidirectional protection component formed in a semiconductor substrate of a first conductivity type including a first implanted area of the first conductivity type, an epitaxial layer of the second conductivity type on the substrate and the first implanted area, a second area of the first conductivity type on the external side of the epitaxial layer, in front of the first area, and implanted with the same dose as the first area, a first metallization covering the entire lower surface of the substrate, and a second metallization covering the second area. | 2012-03-22 |
20120068224 | METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER - A method of producing a semiconductor wafer suited to form types of devices such as HBT and FET on a single semiconductor wafer is provided. The method, by repeating steps including introducing, into a reaction chamber for forming a semiconductor by crystal growth, a first-impurity gas containing an element or a compound containing a first impurity atom as a constituent, thereby producing semiconductor wafers, includes, after introducing the first-impurity gas: taking out a produced semiconductor wafer; disposing a first semiconductor in the reaction chamber; introducing, into the reaction chamber, a second-impurity gas containing an element or a compound containing, as a constituent, a second impurity atom exhibiting a conduction type opposite to the conduction type of the first impurity atom within the first semiconductor; heating the first semiconductor in an atmosphere of the second-impurity gas; and forming a second semiconductor on the heated first semiconductor by crystal growth. | 2012-03-22 |
20120068225 | BISPECTRAL MULTILAYER PHOTODIODE DETECTOR AND METHOD FOR MANUFACTURING SUCH A DETECTOR - A bispectral detector comprising upper and lower semiconductor layers of a first conductivity type in order to absorb a first and a second electromagnetic spectrum, separated by an intermediate layer that forms a barrier; semiconductor zones of a second conductivity type implanted in upper layer and lower layer and each implanted at least partially in the bottom of an opening that passes through upper layer and intermediate layer; and conductor elements connected to semiconductor zones. At least that part of each opening that passes through upper layer is separated from the latter by a semiconductor cap layer: whereof the concentration of dopants of the second conductivity type is greater than 10 | 2012-03-22 |
20120068226 | Formation of Devices by Epitaxial Layer Overgrowth - Methods and structures are provided for formation of devices on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer. | 2012-03-22 |
20120068227 | SEMICONDUCTOR DEVICE - A normally off semiconductor device with a reduced off-state leakage current, which is applicable to a power switching element, includes: a substrate; an undoped GaN layer formed above the substrate; an undoped AlGaN layer formed on the undoped GaN layer; a source electrode and a drain electrode, formed on the undoped GaN layer or the undoped AlGaN layer; a P-type GaN layer formed on the undoped AlGaN layer and disposed between the source electrode and the drain electrode; and a gate electrode formed on the P-type GaN layer, wherein the undoped GaN layer includes an active region including a channel and an inactive region not including the channel, and the P-type GaN layer is disposed to surround the source electrode. | 2012-03-22 |
20120068228 | HETEROJUNCTION BIOPLAR TRANSISTOR STRUCTURE WITH GaPSbAs BASE - A heterojunction bipolar transistor (HBT) structure with GaPSbAs base is disclosed. The HBT structure generally includes a substrate, a subcollector layer, a collector layer, a base layer, an emitter layer, an emitter cap layer, and a contact layer laminated from bottom to top sequentially, and optionally may further comprise a buffer layer between the substrate and the subcollector layer. The subcollector layer includes heavily-doped GaAs; the collector layer includes GaAs, InGaP, or AlGaAs; the base layer includes GaPAsSb compound; the emitter layer includes InGaP or AlGaAs; the emitter cap layer includes GaAs; the contact layer includes InGaAs; and the substrate includes semi-insulating GaAs. Since the base having GaPSbAs compound has lower band gap energy, the turn-on voltage of the transistors can be reduced. Furthermore, the GaPSbAs can form a type II band alignment with InGaP and AlGaAs emitters, the potential spike of the conduction band at the emitter-base interface is eliminated and thus further reduces the turn-on voltage of the transistors and reduces power consumption. As a result of the type II band alignment, the collector layer can be InGaP, or AlGaAs and other wide band gap materials, which increases the breakdown voltage and reduces the offset voltage and hence improves the power performance of the transistors. | 2012-03-22 |
20120068229 | Massively Parallel Interconnect Fabric for Complex Semiconductor Devices - An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations. | 2012-03-22 |
20120068230 | IMAGE SENSOR CAPABLE OF INCREASING PHOTOSENSITIVITY AND METHOD FOR FABRICATING THE SAME - An image sensor capable of overcoming a decrease in photo sensitivity resulted from using a single crystal silicon substrate, and a method for fabricating the same are provided. An image sensor includes a single crystal silicon substrate, an amorphous silicon layer formed inside the substrate, a photodiode formed in the amorphous silicon layer, and a transfer gate formed over the substrate adjacent to the photodiode and transferring photoelectrons received from the photodiode. | 2012-03-22 |
20120068231 | VERTICAL DISCRETE DEVICES WITH TRENCH CONTACTS AND ASSOCIATED METHODS OF MANUFACTURING - The present technology is related generally to vertical discrete devices with a trench at the topside of the vertical discrete devices. The trench is filled with a conducting material. In this approach, a drain or cathode of the vertical discrete devices is electrically connected to the topside to result in a small area with low RON*AREA. | 2012-03-22 |
20120068232 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention relates to a method for manufacturing a semiconductor device, and provides to reduce a contact resistance of a landing plug by forming the landing plug in such a manner that a polysilicon layer is deposited only on the surface of a landing plug contact hole, and a metal layer is buried in the rest of the landing plug contact hole in the process of forming a storage node contact or a bit line contact. | 2012-03-22 |
20120068233 | TRANSISTORS HAVING STRESSED CHANNEL REGIONS AND METHODS OF FORMING TRANSISTORS HAVING STRESSED CHANNEL REGIONS - A method of forming a field effect transistor and a field effect transistor. The method includes (a) forming gate stack on a silicon layer of a substrate; (b) forming two or more SiGe filled trenches in the silicon layer on at least one side of the gate stack, adjacent pairs of the two or more SiGe filled trenches separated by respective silicon regions of the silicon layer; and (c) forming source/drains in the silicon layer on opposite sides of the gate stack, the source/drains abutting a channel region of the silicon layer under the gate stack. | 2012-03-22 |
20120068234 | METHOD FOR SELF-ALIGNING A STOP LAYER TO A REPLACEMENT GATE FOR SELF-ALIGNED CONTACT INTEGRATION - Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the electrode and the substrate, removing a portion of the self aligned contact stop layer over the electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, and transforming the upper portion of the metal into a dielectric layer. Embodiments also include forming a hardmask layer over the removable gate electrode to protect the electrode during silicidation in source/drain regions of the semiconductor device. | 2012-03-22 |
20120068235 | INTEGRATED CIRCUIT - In accordance with an embodiment, an integrated circuit includes a first spin transistor and a second spin transistor. The first spin transistor has a first channel length. The first spin transistor includes a first node and a second node apart from the first node The second spin transistor is connected to the first transistor in series and has a second channel length different from the first channel length. The second spin transistor includes a third node and a fourth node apart from the third node The second node and the fourth node are electrically connected to each other. | 2012-03-22 |
20120068236 | NON-UNIFORM SWITCHING BASED NON-VOLATILE MAGNETIC BASED MEMORY - A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current. | 2012-03-22 |
20120068237 | SELF-ALIGNED STRAP FOR EMBEDDED CAPACITOR AND REPLACEMENT GATE DEVICES - After forming a planarization dielectric layer in a replacement gate integration scheme, disposable gate structures are removed and a stack of a gate dielectric layer and a gate electrode layer is formed within recessed gate regions. Each gate electrode structure is then recessed below a topmost surface of the gate dielectric layer. A dielectric metal oxide portion is formed above each gate electrode by planarization. The dielectric metal oxide portions and gate spacers are employed as a self-aligning etch mask in combination with a patterned photoresist to expose and metalize semiconductor surfaces of a source region and an inner electrode in each embedded memory cell structure. The metalized semiconductor portions form metal semiconductor alloy straps that provide a conductive path between the inner electrode of a capacitor and the source of an access transistor. | 2012-03-22 |
20120068238 | LOW IMPEDANCE TRANSMISSON LINE - Transmission lines employing transmission line units or elements within integrated circuits (ICs) are well-known. Typically, different heights for these transmission line units can vary the characteristics of the cell (and transmission line), and there is typically a tradeoff between impedance and space (layout) specifications. Here, a transmission line is provided, which is generally comprised of elements of the same general width, but having differing or tapered heights that allow for impedance adjustments for high frequency applications (i.e., 160 GHz). For example, a transmission line that is coupled to a balun, with the transmission line units decreasing in height near the balun's center tap to adjust the impedance of the transmission line for the balun, is shown. | 2012-03-22 |
20120068239 | SEMICONDUCTOR MEMORY DEVICE HAVING A FLOATING BODY CAPACITOR, MEMORY CELL ARRAY HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device having a floating body capacitor. The semiconductor memory device can perform a memory operation using the floating body capacitor. The semiconductor memory device includes an SOI substrate having a staked structure in which a base substrate having a conducting surface, a buried insulating layer and a device-forming layer are staked, a transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region, and a capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in the device-forming layer when the transistor is driven. | 2012-03-22 |
20120068240 | Semiconductor Device and Method using a Sacrificial Layer - A method of manufacturing a semiconductor device is disclosed. The method includes forming a first conductive layer over a substrate. The first conductive layer has a top surface and sidewalls, wherein the first conductive layer comprises an overhang of a non-conductive material along the sidewalls. The method further includes forming an insulating layer on the first conductive layer, and forming a sacrificial layer over the insulating layer and the overhang of the first conductive layer. The sacrificial layer is partially removed wherein a residue of the sacrificial layer remains beneath the overhang, and a second conductive layer is formed on the insulating layer. | 2012-03-22 |
20120068241 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure. | 2012-03-22 |
20120068242 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes horizontal patterns on a substrate and the horizontal patterns have at least one opening therein, a pad pattern in an upper region of the opening, an insulating gap fill structure in the opening, the insulating gap fill structure is between the pad pattern and the substrate, and the insulating gap fill structure includes a first gap fill pattern and a second gap fill pattern. The first gap fill pattern includes a first oxide and the second gap fill pattern includes a second oxide, and the second oxide has a different etching selectivity from that of the first oxide. The device further includes a semiconductor pattern that is between a sidewall of the gap fill structure and sidewalls of the horizontal patterns and between a sidewall of the pad pattern and the sidewalls of the horizontal patterns. | 2012-03-22 |
20120068243 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed. Of the insulating film, the portion between the lower surface of the memory gate electrode and the upper surface of a semiconductor substrate has silicon oxide films, and a silicon nitride film interposed between the silicon oxide films. Of the insulating film, the portion between a side surface of the control gate electrode and a side surface of the memory gate electrode is formed of a silicon oxide film, and does not have the silicon nitride film. | 2012-03-22 |
20120068244 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor memory device includes a plurality of multi-level memory cells provided on a major surface of a semiconductor substrate of a first conductivity type. A first semiconductor region of a second conductivity type is selectively provided in the surface of the semiconductor substrate between the multi-level memory cells. A second semiconductor region is provided deeper than the first semiconductor region and includes a first conductivity type impurity. A plurality of binary memory cells are provided on the major surface of the semiconductor substrate, and a third semiconductor region of the second conductivity type is selectively provided in the surface of the semiconductor substrate between the binary memory cells. Amount of the first conductivity type impurity compensating a second conductivity type impurity of the first semiconductor region is larger than that of the third semiconductor region. | 2012-03-22 |
20120068245 | NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS - A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed. | 2012-03-22 |
20120068246 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a method of manufacturing a semiconductor memory device is disclosed. The method can comprise forming a tunnel insulating film on a substrate, forming a charge storage layer including a conductor on the tunnel insulating film, forming an isolation trench which isolate the charge storage layer and the tunnel insulating film in the substrate, embedding an isolation insulating film in the isolation trench, removing a native oxide film which is formed on a surface of the charge storage layer, and forming an insulating film on a surface of the isolation insulating film and the surface of the charge storage layer. The process from the removing the native oxide film to the forming the insulating film carried out in a manufacture apparatus in which an oxygen concentration is controlled. | 2012-03-22 |
20120068247 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided are three-dimensional semiconductor devices. The devices may include gap-fill insulating patterns configured to upwardly extend from a substrate and an electrode structure defined by sidewalls of the gap-fill insulating patterns. Vertical structures may be provided between adjacent ones of the gap-fill insulating patterns to penetrate the electrode structure, and the vertical structures may include first and second rows of the vertical structures. A separation pattern may be provided between the first and second rows of vertical structures and include a separation semiconductor layer. The separation pattern extends along a direction parallel to the first and second rows of vertical structures. | 2012-03-22 |
20120068248 | POWER SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device, includes an element unit including a vertical-type MOSFET, the vertical-type MOSFET in including a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer sequentially stacked in order, an impurity concentration of the second semiconductor layer being lower than the first semiconductor layer, an insulator covering inner surfaces of a plurality of trenches, the adjacent trenches being provided with a first interval in between, and a diode unit including basically with the units of the element unit, the adjacent trenches being provided with a second interval in between, the second interval being larger than the first interval. | 2012-03-22 |
20120068249 | Nonvolatile memory device and method of manufacturing the same - The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer. | 2012-03-22 |
20120068250 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a semiconductor region, a tunnel insulating film provided on the semiconductor region, a charge storage insulating film provided on the tunnel insulating film and having a hafnium oxide including a cubic region, a block insulating film provided on the charge storage insulating film, and a control gate electrode provided on the block insulating film. | 2012-03-22 |
20120068251 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a multilayer body, a block layer, a charge storage layer, a tunnel layer, and a semiconductor pillar. The multilayer body includes a plurality of insulating films and electrode films alternately stacked. The multilayer body includes a through hole extending in stacking direction of the insulating films and the electrode films. The block layer is provided on an inner surface of the through hole. The charge storage layer is surrounded by the block layer. The tunnel layer is surrounded by the charge storage layer. The semiconductor pillar is surrounded by the tunnel layer. Dielectric constant of a portion of the tunnel layer on a side of the semiconductor pillar is higher than dielectric constant of a portion of the tunnel layer on a side of the charge storage layer. | 2012-03-22 |
20120068252 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a substrate, a multilayer body, a semiconductor member and a charge storage layer. The multilayer body is provided on the substrate, with a plurality of insulating films and electrode films alternately stacked, and includes a first staircase and a second staircase opposed to each other. The semiconductor member is provided in the multilayer body outside a region provided with the first staircase and the second staircase, and the semiconductor member extends in stacking direction of the insulating films and the electrode films. The charge storage layer is provided between each of the electrode films and the semiconductor member. The each of the electrode films includes a first terrace formed in the first staircase, a second terrace formed in the second staircase and a bridge portion connecting the first terrace and the second terrace. | 2012-03-22 |
20120068253 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory region and a non-memory region. The memory region includes a stacked structural body, a semiconductor pillar, a memory layer, an inner insulating film and an outer insulating film. The stacked structural body includes a plurality of electrode films stacked alternately along a first direction with a plurality of inter-electrode insulating films. The semiconductor pillar pierces the stacked structural body in the first direction. The memory layer is provided between the semiconductor pillar and each of the plurality of electrode films. The inner insulating film is provided between the memory layer and the semiconductor pillar. The outer insulating film is provided between the memory layer and each of the plurality of electrode films. The non-memory region is provided with the memory region along a second direction orthogonal to the first direction. The non-memory region includes an insulating part. | 2012-03-22 |
20120068254 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes a semiconductor substrate, first, second, third and fourth fin-type stacked layer structures, each having memory strings stacked in a first direction perpendicular to a surface of the semiconductor substrate, and each extending to a second direction parallel to the surface of the semiconductor substrate, a first part connected to first ends in the second direction of the first and second fin-type stacked layer structures each other, a second part connected to first ends in the second direction of the third and fourth fin-type stacked layer structures each other, a third part connected to second ends in the second direction of the first and third fin-type stacked layer structures each other, and a fourth part connected to second ends in the second direction of the second and fourth fin-type stacked layer structures each other. | 2012-03-22 |
20120068255 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess is provided, which extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells are provided on the substrate. This vertical stack of nonvolatile memory cells includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers are provided, which extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength. | 2012-03-22 |
20120068256 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film. | 2012-03-22 |
20120068257 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, there is provided a semiconductor memory device including an element region, a first gate insulating film, a charge accumulation layer, a second gate insulating film, a control gate electrode, and a control gate electrode. The charge accumulation layer covers the first gate insulating film. The second gate insulating film has a first portion and a second portion. The first portion covers an upper surface of the charge accumulation layer when a side of a surface on which the element region of the semiconductor substrate is demarcated is an upper side. The second portion covers a side surface of the charge accumulation layer. The control gate electrode covers the upper surface and the side surface of the charge accumulation layer via the second gate insulating film. A breakdown voltage of the first portion is higher than a breakdown voltage of the second portion. | 2012-03-22 |
20120068258 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a first main electrode, a control electrode, an extraction electrode, a second insulating film, a plurality of contact electrodes, and a control terminal. The first main electrode is electrically connected to a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type selectively provided on a surface of the first semiconductor region. The control electrode is provided on the first semiconductor region via a first insulating film. The extraction electrode is electrically connected to the control electrode. The second insulating film is provided on the first main electrode and the extraction electrode. The plurality of contact electrodes are provided in an inside of a plurality of first contact holes formed in the second insulating film and are electrically connected to the extraction electrode. The control terminal covers portions of the first main electrode provided on the first semiconductor region, on the second semiconductor region, and on the control electrode, respectively, and the extraction electrode, is electrically connected to the plurality of contact electrodes, and is electrically insulated from the first main electrode by the second insulating film. | 2012-03-22 |
20120068259 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure. | 2012-03-22 |
20120068260 | Method for producing a structure element and semiconductor component comprising a structure element - A semiconductor component includes a semiconductor body having a surface and a cutout in the semiconductor body. The cutout extends from the surface of the semiconductor body into the semiconductor body in a direction perpendicular to the surface. The cutout has a base and at least one sidewall. The component further includes a layer on the surface of the semiconductor body and in the cutout. The layer forms a well above the cutout. The well has a well base, a well edge and at least one well sidewall. The at least one well sidewall forms an angle α in the range of 20° to 80° with respect to the surface of the semiconductor body. The layer has at least one edge which, proceeding from the well edge, extends in the direction of the surface of the semiconductor body. | 2012-03-22 |
20120068261 | Replacement Metal Gate Structures for Effective Work Function Control - A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures. | 2012-03-22 |
20120068262 | Integrated MOSFET Device and Method with Reduced Kelvin Contact Impedance and Breakdown Voltage - A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned dielectric layer atop the Kelvin-contact source and the trench gate; a patterned top metal layer. As a result: a planar ledge is formed atop the Kelvin-contact source; the MOSFET device exhibits a lowered body Kelvin contact impedance and, owing to the presence of the planar ledge, a source Kelvin contact impedance that is lower than an otherwise MOSFET device without the planar ledge; and an integral parallel Schottky diode is also formed. | 2012-03-22 |
20120068263 | Power Switching Semiconductor Devices Including Rectifying Junction-Shunts - A semiconductor device includes a drift layer and a body region that forms a p-n junction with the drift layer. A contactor region is in the body region, and a shunt channel region extends through the body region from the contactor region to the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse bias the p-n junction between the drift region and the body region. | 2012-03-22 |
20120068264 | FORMING NARROW FINS FOR FINFET DEVICES USING ASYMMETRICALLY SPACED MANDRELS - A method of forming fins for fin-shaped field effect transistor (finFET) devices includes forming a plurality of sacrificial mandrels over a semiconductor substrate. The plurality of sacrificial mandrels are spaced apart from one another by a first distance along a first direction, and by a second distance along a second direction. Spacer layers are formed on sidewalls of the sacrificial mandrels such that portions of the spacer layers between sacrificial mandrels along the first direction are merged together. Portions of the spacer layers between sacrificial mandrels along the second direction remain spaced apart. The sacrificial mandrels are removed. A pattern corresponding to the spacer layers is transferred into the semiconductor layers to form a plurality of semiconductor fins. Adjacent pairs of fins are merged with one another at locations corresponding to the merged spacer layers. | 2012-03-22 |
20120068265 | WIRING LAYER STRUCTURE AND PROCESS FOR MANUFACTURE THEREOF - This wiring layer structure includes: an underlying substrate of a semiconductor substrate or a glass substrate; an oxygen-containing Cu layer or an oxygen-containing Cu alloy layer which is formed on the underlying substrate; an oxide layer containing at least one of Al, Zr, and Ti which is formed on the oxygen-containing Cu layer or the oxygen-containing Cu alloy layer; and a Cu alloy layer containing at least one of Al, Zr, and Ti which is formed on the oxide layer. | 2012-03-22 |
20120068266 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor having low leak current and high mobility are obtained in the same time in a dynamic circuit having a thin film transistor by selectively forming a cover film on a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter. | 2012-03-22 |
20120068267 | STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe. | 2012-03-22 |
20120068268 | TRANSISTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating a transistor structure includes the step of providing a substrate having a gate thereon. Then, a first spacer is formed at two sides of the gate. After that, an LDD region is formed in the substrate at two sides of the gate. Later, a second spacer comprising a carbon-containing spacer and a sacrificing spacer is formed on the first spacer. Subsequently, a source/drain region is formed in the substrate at two sides of the gate. Finally, the sacrificing spacer is removed entirely, and part of the carbon-containing spacer is also removed. The remaining carbon-containing spacer has an L shape. The carbon-containing spacer has a first carbon concentration, and the sacrificing spacer has a second carbon concentration. The first carbon concentration is greater than the second carbon concentration. | 2012-03-22 |
20120068269 | Producing a perfect P-N junction - This patent disclosure presents circuits, system, and method to produce an ideal memory cell and a method to produce a perfect PN junction without undesirable junction voltage and leakage current. These new inventions finally perfect the art to produce PN junction diode sixty years after PN junction diode was invented and the technology to produce an indestructible nonvolatile memory cell that is fast and small. | 2012-03-22 |
20120068270 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE DEVICE - A semiconductor device includes a first transistor including a gate electrode formed on semiconductor substrate with a gate insulating film interposed therebetween, a first sidewall formed on each side surface of the first gate electrode, and a source/drain diffusion layer; and a second transistor including a gate electrode formed on the semiconductor substrate with the gate insulating film interposed therebetween, a first sidewall formed on each side surface of the second gate electrode, a second sidewall formed outside the first sidewall. A nickel silicide layer is formed in each of upper portions of the gate electrode and the source/drain regions in a silicide formation region. The first sidewall is resistant an etching material used for etching the second sidewall. | 2012-03-22 |
20120068271 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - After forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited with a thickness of 10 nm or more over the semiconductor film while heating the substrate to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, and removing an oxide film on the semiconductor film, a Ni film is deposited over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. | 2012-03-22 |
20120068272 | CONDUCTIVE LAYERS FOR HAFNIUM SILICON OXYNITRIDE - Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum. | 2012-03-22 |
20120068273 | STRESSED BARRIER PLUG SLOT CONTACT STRUCTURE FOR TRANSISTOR PERFORMANCE ENHANCEMENT - A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices. | 2012-03-22 |
20120068274 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device has a substrate comprising an element isolation area, a plurality of tetragonal active areas on the substrate separated by the element isolation area from each other, each of the active areas having an impurity diffusion area, a large active area comprising at least a part of the active areas, an outline of the large active area including a bump. Among the impurity diffusion areas of the active areas, impurity diffusion areas facing through the element isolation area are electrically connected. | 2012-03-22 |
20120068275 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a high-dielectric constant insulating film including a high-dielectric constant film; forming a first conductive film including an oxide film on an upper surface thereof and containing at least one of high melting point metal or a compound thereof; forming a second conductive film containing silicon on the first conductive film with the oxide film being interposed therebetween; forming a mixing layer by performing ion implantation to the first and second conductive films to mix a constituent material of the oxide film and silicon of the second conductive film together; and forming the mixing layer into a conductive layer by performing heat treatment. | 2012-03-22 |
20120068276 | MICROSTRUCTURE WITH AN ENHANCED ANCHOR - The present disclosure provides a microstructure device with an enhanced anchor and a narrow air gap. One embodiment of a microstructure device provided herein includes a layered wafer. The layered wafer includes a silicon handle layer, a buried oxide layer formed on the handle layer, and a silicon device layer formed on the buried oxide layer. A top oxide layer is formed on the device layer. The top oxide layer, the device layer, and the buried oxide layer are etched, thereby forming trenches to create an anchor and a microstructure device in the device layer. In process of fabricating the device, a thermal oxide layer is formed along sides of the microstructure device to enclose the microstructure device in the buried oxide layer, the top oxide layer and the thermal oxide layer. Then, a poly layer if formed to fill in the trenches and enclose the anchor. After the poly layer fills in the trenches, the oxide layers enclosing the microstructure device are etched away, releasing the microstructure device. | 2012-03-22 |
20120068277 | Semiconductor Manufacturing and Semiconductor Device with semiconductor structure - Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted. | 2012-03-22 |
20120068278 | PULL UP ELECTRODE AND WAFFLE TYPE MICROSTRUCTURE - The present invention generally relates to MEMS devices and methods for their manufacture. The cantilever of the MEMS device may have a waffle-type microstructure. The waffle-type microstructure utilizes the support beams to impart stiffness to the microstructure while permitting the support beam to flex. The waffle-type microstructure permits design of rigid structures in combination with flexible supports. Additionally, compound springs may be used to create very stiff springs to improve hot-switch performance of MEMS devices. To permit the MEMS devices to utilize higher RF voltages, a pull up electrode may be positioned above the cantilever to help pull the cantilever away from the contact electrode. | 2012-03-22 |
20120068279 | DOMAIN WALL ASSISTED SPIN TORQUE TRANSFER MAGNETRESISTIVE RANDOM ACCESS MEMORY STRUCTURE - A semiconductor memory device includes a first ferromagnetic layer magnetically pinned and positioned within a first region of a substrate; a second ferromagnetic layer approximate the first ferromagnetic layer; and a barrier layer interposed between the first ferromagnetic layer and the first portion of the second ferromagnetic layer. The second ferromagnetic layer includes a first portion being magnetically free and positioned within the first region; a second portion magnetically pinned to a first direction and positioned within a second region of the substrate, the second region contacting the first region from a first side; and a third portion magnetically pinned to a second direction and positioned within a third region of the substrate, the third region contacting the first region from a second side. | 2012-03-22 |
20120068280 | Magnetic Nano-Ring Device and Method of Fabrication - A magnetic nano-ring device and method of fabrication includes providing a substrate; forming at least one nano-pillar on the substrate; depositing a plurality of electrodes on the substrate; depositing an anti-ferromagnetic layer on a first electrode of the plurality of electrodes; depositing a first ferromagnetic layer on the anti-ferromagnetic layer; depositing a tunnel barrier layer on the first ferromagnetic layer; depositing a second ferromagnetic layer on the tunnel barrier layer; planarizing the nano-pillars and the second ferromagnetic layer to form a co-planar nano-pillar and second ferromagnetic layer; depositing a second electrode on the co-planar nano-pillar and second ferromagnetic layer; and forming a nano-structure ring in a substantially cylindrical configuration. | 2012-03-22 |
20120068281 | MAGNETIC RECORDING ELEMENT AND NONVOLATILE MEMORY DEVICE - According to one embodiment, a magnetic recording element includes a stacked body including a first stacked unit and a second stacked unit. The first stacked unit includes a first ferromagnetic layer, a second ferromagnetic layer and a first nonmagnetic layer. Magnetization of the first ferromagnetic layer is substantially fixed in a first direction being perpendicular to a first ferromagnetic layer surface. The second stacked unit includes a third ferromagnetic layer, a fourth ferromagnetic layer and a second nonmagnetic layer. Magnetization of the fourth ferromagnetic layer is substantially fixed in a second direction being perpendicular to a fourth ferromagnetic layer surface. The first direction is opposite to the second direction. | 2012-03-22 |
20120068282 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - To provide a semiconductor device capable of suppressing a short circuit between an upper conductive element and a lower conductive element which constitute an MRAM, and a manufacturing method of the same. | 2012-03-22 |
20120068283 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device according to the present embodiment includes a selection element formed on a surface of a semiconductor substrate. A lower electrode is connected to the selection element. A magnetic tunnel junction element is provided on the lower electrode. An upper electrode is provided on the magnetic tunnel junction element. A growth layer is provided on the upper electrode and is composed of a conductive material and has a larger area than the upper electrode when viewed from above the surface of the semiconductor substrate. A wiring line is provided on the growth layer. | 2012-03-22 |
20120068284 | MAGNETORESISTIVE EFFECT ELEMENT AND MAGNETIC MEMORY - According to one embodiment, a magnetoresistive effect element includes a recording layer including ferromagnetic material with perpendicular magnetic anisotropy to a film surface and a variable orientation of magnetization, a reference layer including ferromagnetic material with perpendicular magnetic anisotropy to a film surface and an invariable orientation of magnetization, a nonmagnetic layer between the recording layer and the reference layer, a first underlayer on a side of the recoding layer opposite to a side on which the nonmagnetic layer is provided, and a second underlayer between the recording layer and the first underlayer. The second underlayer is a Pd film including a concentration of 3×10 | 2012-03-22 |
20120068285 | MAGNETORESISTIVE EFFECT ELEMENT, MAGNETIC MEMORY, AND METHOD OF MANUFACTURING MAGNETORESISTIVE EFFECT ELEMENT - According to one embodiment, a magnetoresistive effect element includes a first magnetic layer including perpendicular anisotropy to a film surface and an invariable magnetization direction, the first magnetic layer having a magnetic film including an element selected from a first group including Tb, Gd, and Dy and an element selected from a second group including Co and Fe, a second magnetic layer including perpendicular magnetic anisotropy to the film surface and a variable magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer. The magnetic film includes amorphous phases and crystals whose particle sizes are 0.5 nm or more. | 2012-03-22 |
20120068286 | MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetic random access memory includes a selection element formed on a semiconductor substrate, an interlayer dielectric film formed above the selection element, a contact layer formed in the interlayer dielectric film, and electrically connected to the selection element, a lower electrode layer made of a metal material, and electrically connected to the contact layer, a metal oxide insulating film made of an oxide of the metal material, and surrounding a side surface of the lower electrode layer, a magnetoresistive element formed on the lower electrode layer, an upper electrode layer formed on the magnetoresistive element, a sidewall insulating film formed on a side surface of the magnetoresistive element and a side surface of the upper electrode layer, and a bit line electrically connected to the upper electrode layer. | 2012-03-22 |
20120068287 | Highly Sensitive Photo-Sensing Element and Photo-Sensing Device Using the Same - According to the present invention, a highly sensitive photo-sensing element and a sensor driver circuit are prepared by planer process on an insulating substrate by using only polycrystalline material. Both the photo-sensing element and the sensor driver circuit are made of polycrystalline silicon film. As the photo-sensing element, a photo transistor is formed by using TFT, which comprises a first electrode | 2012-03-22 |
20120068288 | MANUFACTURING METHOD OF MOLDED IMAGE SENSOR PACKAGING STRUCTURE WITH PREDETERMINED FOCAL LENGTH AND THE STRUCTURE USING THE SAME - A manufacturing method of a molded image sensor packaging structure with a predetermined focal length and the structure using the same are disclosed. The manufacturing method includes: providing a substrate; providing a sensor chip disposed on the substrate; providing a lens module set over the sensing area of the chip to form a semi-finished component; providing a mold that has an upper mold member with a buffer layer; disposing the semi-finished component into the mold to form a mold cavity therebetween; injecting a molding compound into the mold cavity; and after transfer molding the molding compound, opening the mold and performing a post mold cure process to cure the molding compound. The buffer layer can fill the air gap between the upper surface of the lens module and the upper mold member, thereby preventing the upper surface of the lens module from being polluted by the molding compound. | 2012-03-22 |
20120068289 | Devices Having Enhanced Electromagnetic Radiation Detection and Associated Methods - Photosensitive semiconductor devices and associated methods are provided. In one aspect, a semiconductor device can include a semiconductor substrate and a semiconductor layer coupled to the semiconductor substrate, where the semiconductor layer has a device surface opposite the semiconductor substrate. The device also includes at least one textured region coupled between the semiconductor substrate and the semiconductor layer. In another aspect, the device further includes at least one dielectric layer coupled between the semiconductor substrate and the semiconductor layer. | 2012-03-22 |
20120068290 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND CAMERA MODULE - According to one embodiment, an insulation film is formed over the surface, backside, and sides of a first substrate. Next, the insulation film formed over the surface of the first substrate is removed. Then, a joining layer is formed over the surface of the first substrate, from which the insulation film has been removed. Subsequently, the first substrate is bonded to a second substrate via a joining layer. | 2012-03-22 |
20120068291 | IMAGE SENSING DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a solid-state image sensing device includes a semiconductor substrate on which a plurality of pixels are arranged, a transparent substrate including a first through via provided in an opening formed in advance to extend through, an adhesive including a second through via connected to the first through via and configured to bond the semiconductor substrate and the transparent substrate while exposing the pixels, and an imaging lens unit arranged on the transparent substrate. | 2012-03-22 |
20120068292 | POLYMERIZABLE COMPOSITION, AND PHOTOSENSITIVE LAYER, PERMANENT PATTERN, WAFER-LEVEL LENS, SOLID-STATE IMAGING DEVICE AND PATTERN FORMING METHOD EACH USING THE COMPOSITION - A polymerizable composition contains (A) a polymerization initiator that is an acetophenone-based compound or an acylphosphine oxide-based compound, (B) a polymerizable compound, (C) at least either a tungsten compound or a metal boride, and (D) an alkali-soluble binder. | 2012-03-22 |
20120068293 | SEMICONDUCTOR DEVICE HAVING IMAGE SENSOR - A pixel area for generating an image signal corresponding to incident light is formed on a semiconductor substrate. A light-shielding layer is formed on the semiconductor substrate around the pixel area. The light-shielding layer has a slit near the pixel area and shields the incident light. A passivation film is formed in the pixel area, on the light-shielding layer, and in the slit. A coating layer is formed in the slit of the light-shielding layer and on the passivation film in the pixel area. Microlenses are formed on the coating layer in the pixel area. | 2012-03-22 |
20120068294 | Image Sensor with Decreased Optical Interference Between Adjacent Pixels - An image sensor with decreased optical interference between adjacent pixels is provided. An image sensor, which is divided into a pixel region and a peripheral region, the image sensor including a photodiode formed in a substrate in the pixel region, first to Mth metal lines formed over the substrate in the pixel region, where M is a natural number greater than approximately 1, first to Nth metal lines formed over a substrate in the peripheral region, where N is a natural number greater than M, at least one layer of dummy metal lines formed over the Mth metal lines but formed not to overlap with the photodiode, and a microlens formed over the one layer of the dummy metal lines to overlap with the photodiode. | 2012-03-22 |
20120068295 | MULTILAYER BISPECTRAL PHOTODIODE DETECTOR - This bispectral detector comprises a plurality of unitary elements for detecting a first and a second electromagnetic radiation range, consisting of a stack of upper and lower semiconductor layers of a first conductivity type which are separated by an intermediate layer that forms a potential barrier between the upper and lower layers; and for each unitary detection element, two upper and lower semiconductor zones of a second conductivity type opposite to the first conductivity type, are arranged respectively so that they are in contact with the upper faces of the upper and lower layers so as to form PN junctions, the semiconductor zone being positioned, at least partially, in the bottom of an opening that passes through the upper and intermediate layers. The upper face of at least one of the upper and lower layers is entirely covered in a semiconductor layer of the second conductivity type. Cuts are made around each unitary detection element from the upper face of the stack and at least through the thickness of each semiconductor layer of the second conductivity type, entirely covering one or other of the upper and lower semiconductor layers of the first conductivity type, so as to form semiconductor zones of the second conductivity type. | 2012-03-22 |
20120068296 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: | 2012-03-22 |
20120068297 | HIGH VOLTAGE DEVICE HAVING SCHOTTKY DIODE - A high voltage device having a Schottky diode integrated with a MOS transistor includes a semiconductor substrate a Schottky diode formed on the semiconductor substrate, at least a first doped region having a first conductive type formed in the semiconductor substrate and under the Schottky diode, and a control gate covering a portion of the Schottky diode and the first doped region positioned on the semiconductor substrate. | 2012-03-22 |
20120068298 | SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a super junction structure includes: multiple first columns extending in a current flowing direction; and multiple second columns extending in the current flowing direction. The first and second columns are alternately arranged in an alternating direction. Each first column provides a drift layer. The first and second columns have a boundary therebetween, from which a depletion layer expands in case of an off-state. At least one of the first columns and the second columns have an impurity dose, which is inhomogeneous by location with respect to the alternating direction. | 2012-03-22 |
20120068299 | TRANSIENT VOLTAGE SUPPRESSORS - The present invention relates a transient voltage suppressor (TVS) for directional ESD protection. The TVS includes: a conductivity type substrate; a first type lightly doped region, having a first type heavily doped region arranged therein; a second type lightly doped region, having a second type heavily doped region and a third type heavily doped region arranged therein; a third type lightly doped region, having a fourth type heavily doped region arranged therein; a plurality of closed isolation trenches, arranged on the conductivity type substrate, wherein at least one of the plurality of closed isolation trenches is neighbored one of the type lightly doped regions; and a first pin. Accordingly, the TVS of present invention may adaptively provide effective ESD protection under positive and negative ESD stresses, improve the efficiency of ESD protection within the limited layout area. | 2012-03-22 |
20120068300 | Inductive getter activation for high vacuum packaging - An approach to activating a getter within a sealed vacuum cavity is disclosed. The approach uses inductive coupling from an external coil to a magnetically permeable material deposited in the vacuum cavity. The getter material is formed over this magnetically permeable material, and heated specifically thereby, leaving the rest of the device cavity and microdevice relatively cool. Using this inductive coupling technique, the getter material can be activated after encapsulation, and delicate structures and low temperature wafer bonding mechanisms may be used. | 2012-03-22 |
20120068301 | MONOLITHIC MAGNETIC INDUCTION DEVICE - Providing for a monolithic magnetic induction device having low DC resistance and small surface area is described herein. By way of example, the magnetic induction device can comprise a substrate (e.g., a semiconductor substrate) having trenches formed in a bottom layer of the substrate, and holes formed in the substrate between the trenches and an upper layer of the substrate. Additionally, the magnetic induction device can comprise a conductive coil embedded or deposited within the trenches. The magnetic induction device can further comprise a set of conductive vias formed in the holes that electrically connect the bottom layer of the substrate with the upper layer. Further, one or more integrated circuit components, such as active devices, can be formed in the upper layer, at least in part above the conductive coil. The vias can be utilized to connect to integrated circuit components with the conductive coil, where suitable. | 2012-03-22 |
20120068302 | ELECTRONIC DEVICE AND METHOD FOR DIRECT MOUNTING OF PASSIVE COMPONENTS - An electronic device including a semiconductor die, which has a top surface that is configured to operate as a printed circuit board so as to provide connections for at least one passive component, in particular a passive surface mounted device (SMD). | 2012-03-22 |
20120068303 | Semiconductor Device Comprising a Metal System Including a Separate Inductor Metal Layer - In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system. | 2012-03-22 |
20120068304 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a semiconductor substrate; forming an opening within the substrate; forming a conductive layer within the opening; and forming a semiconductor layer over the conductive layer. | 2012-03-22 |
20120068305 | LATERAL CAPACITOR AND METHOD OF MAKING - An active device region is formed in and on a semiconductor substrate. An interconnect layer is formed over the active device region, wherein the interconnect layer comprises a first dielectric material having a first dielectric constant, a first metal interconnect in the first dielectric material, and a second metal interconnect in the first dielectric material and laterally spaced apart from the first metal interconnect. A portion of the first dielectric material is removed such that a remaining portion of the first dielectric material remains within the interconnect layer, wherein the removed portion is removed from a location between the first and second metal interconnects. The location between the first and second metal interconnects from which the portion of the first dielectric material was removed is filled with a second dielectric material having a second dielectric constant, the second dielectric constant being higher than the first dielectric constant. | 2012-03-22 |
20120068306 | SEMICONDUCTOR PACKAGE INCLUDING DECOUPLING SEMICONDUCTOR CAPACITOR - A semiconductor package includes a packaging substrate including a first bond finger and a second bond finger, a first semiconductor chip mounted on the packaging substrate, and including a first chip pad and a second chip pad, the first bond finger being electrically connected to the first chip pad by a first bonding wire, and the second bond finger being electrically connected to the second chip pad by a second bonding wire, and a first decoupling semiconductor capacitor mounted on the first semiconductor chip, and including a first capacitor pad, the first capacitor pad being electrically connected to the second chip pad. | 2012-03-22 |
20120068307 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode. | 2012-03-22 |
20120068308 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCTION METHOD - A semiconductor device includes a semiconductor substrate, a heat generating device, and a heat radiating part. The heat generating device is provided on the semiconductor substrate, and the heat radiating part is provided above the heat generating device. The heat radiating part is thermally coupled with the semiconductor substrate through at least one contact part. | 2012-03-22 |
20120068309 | Transistor and Method of Manufacturing a Transistor - In accordance with an embodiment of the present invention a transistor is disclosed. The transistor comprises a collector, a base and an emitter, wherein a first end width of the base is larger than a middle width of the base, wherein a first end width of the collector is larger than a middle width of the collector, or wherein a first end width of the emitter is larger than a middle width of the emitter. | 2012-03-22 |