12th week of 2013 patent applcation highlights part 21 |
Patent application number | Title | Published |
20130069629 | METHOD OF IMPLEMENTATION OF PEAK HOLD IN A PHASING VOLTMETER - A high voltage phasing voltmeter comprises first and second probes. Each probe comprises an electrode for contacting a high voltage electrical conductor. The electrodes are connected in series with a resistor. A meter comprises a housing enclosing an electrical circuit for measuring true rms voltage. The electrical circuit comprises an input circuit for connection to the first and second probes and developing a scaled voltage representing measured voltage across the electrodes. A converter circuit converts the scaled voltage to a DC signal representing true rms value of the measured voltage. A peak hold circuit is connected to the converter circuit to hold a peak value of the true rms value. A display is connected to the peak hold circuit for displaying the peak value of the true rms value. | 2013-03-21 |
20130069630 | SELF-MONITORING COMPOSITE VESSEL FOR HIGH PRESSURE MEDIA - A high pressure media storage vessel including a wall made of at least one layer with barrier and piezoelectric properties. | 2013-03-21 |
20130069631 | CURRENT SENSING SYSTEM AND METHOD - There is provided a current sense circuit ( | 2013-03-21 |
20130069632 | APPARATUS AND METHOD FOR IMPROVED CURRENT SHUNT SENSING - An apparatus and method for improved current shunt sensing in an electrical system, such as a renewable energy electrical system, is disclosed. A current shunt according to aspects of the present disclosure includes a conductive portion that is placed in series with an electrical system The current shunt includes a sensing element that is used to measure the voltage across the conductive portion of the current shunt. The sensing element has an increased width relative to the width of the conductive portion of the shunt. The increased width of the sensing element provides for improved current shunt sensing that results in more accurate voltage (and thus current) measurements across a wide range of frequencies. | 2013-03-21 |
20130069633 | FAN SPEED DETECTION DEVICE - A fan speed detection circuit includes a counter, an integrating circuit, a current regulation circuit, a connector and a matching circuit. The connector electrically connects to the current regulation circuit and a fan. The counter outputs a pulse signal, the integrating circuit receives the pulse signal from the counter, and converts the pulse signal from the counter into a corresponding analog command signal. The current regulation circuit adjusts the current from the integrating circuit according to the command signal and outputs the adjusted current to the connector. The matching circuit converts the voltage from the connector and provides a suitable voltage for activating the counter to enable the counter to detect and quantify and record the rotation speed of the fan in all circumstances. | 2013-03-21 |
20130069634 | SPEED SENSOR COMPRISING A COSTAS LOOP - A speed sensor including at least one sensor element and an analog-to-digital converter that digitizes the output signals of the at least one sensor element, and a Costas loop unit that is connected to the output of the analog-to-digital converter. | 2013-03-21 |
20130069635 | DISPLACEMENT DETECTION DEVICE, VEHICLE STEERING SYSTEM, AND MOTOR - A motor rotation angle sensor includes a plurality of Hall elements and a plurality of switches, each a which is able to interrupt supply of power for operating a corresponding one of these Hall elements. | 2013-03-21 |
20130069636 | SENSING APPARATUS FOR MEASURING POSITION OF TOUCH OBJECT BY ELECTROMAGNETIC INDUCTION AND METHOD FOR CONTROLLING THE SAME - An electromagnetic sensing apparatus for measuring the position of a touch object by electromagnetic induction and a method for controlling the same are provided. The apparatus includes a loop unit including first and second sub-loop units for alternately receiving current and sensing an electromagnetic change; and a controller for controlling the first sub-loop unit to alternate between receiving the current and sensing the electromagnetic change in every one of a predetermined time period and controlling the second sub-loop unit to alternate between receiving the current and sensing the electromagnetic change in every predetermined time period, alternately with the first sub-loop unit | 2013-03-21 |
20130069637 | INDUCTIVE DETECTION ENCODER AND DIGITAL MICROMETER - An inductive detection encoder according to the present invention includes: first and second members which are oppositely disposed so as to relatively move in a measurement direction; a transmitting coil formed in the first member; a magnetic flux coupled body which is formed in the second member and coupled with a magnetic field generated by the transmitting coil; and a receiving coil formed in the first member and having receiving loops. At least one of the transmitting coil and the receiving coil has a specific pattern that impairs the uniformity and periodicity of a pattern; and a dummy pattern formed in a position corresponding to a specific phase relationship of a cycle generated by the track with respect to the specific pattern. | 2013-03-21 |
20130069638 | METHOD AND DEVICE FOR DETERMINING A CURRENT ANGULAR POSITION OF A ROTATABLE MAGNETIC COMPONENT IN AN ELECTRIC DRIVE - The invention relates to a method for determining the actual angle position of a rotatable magnetic component in an electric drive ( | 2013-03-21 |
20130069639 | Flexible Magnetostrictive Sensor - A flexible printed circuit board (PCB) magnetostrictive (MS) sensor comprising a first direct current (DC) bias PCB layer comprising a first plurality of conductive traces, a first alternating current (AC) PCB layer disposed on the first DC bias PCB layer, the first AC PCB layer comprising a first AC coil, a pocket PCB layer disposed on the first AC PCB layer, the pocket PCB layer to receive a strip of MS material, a second AC PCB layer disposed on the pocket PCB layer, the second AC PCB layer comprising a second AC coil, and a second DC bias PCB layer disposed on the second AC PCB layer, the second DC bias PCB layer comprising a second plurality of conductive traces. The traces from the first plurality of conductive traces are electrically coupled to traces from the second plurality of conductive traces. | 2013-03-21 |
20130069640 | VERTICAL HALL SENSORS - Embodiments relate to vertical Hall sensors for use with spinning current techniques. In an embodiment, a symmetric arrangement of two vertical Hall devices is used, in which all sense terminals of the Hall devices are used in all clock phases. Such a configuration can achieve better offset error suppression as compared with conventional solutions. | 2013-03-21 |
20130069641 | HALL SENSORS HAVING FORCED SENSING NODES - Embodiments relate to forced spinning Hall sensors. In embodiments, forced Hall sensors can provide reduced residual offset, lower current consumption and improved or complete rejection of nonlinear backbias effects when compared with conventional approaches. | 2013-03-21 |
20130069642 | Magnetic Sensor With Conducting Bevel - Various embodiments can have a magnetically responsive stack positioned on an air bearing surface (ABS) and disposed between at least first and second magnetic shields. Each magnetic shield may have a beveled portion distal to the ABS. The magnetically responsive stack can have a cross-track magnetization anisotropy proximal to the ABS. | 2013-03-21 |
20130069643 | TURN-TWIST APPARATUS REVEALING CURVATURE AND TORSION OF THE MAGNETIC FIELD - An apparatus for observing turns and twists in magnetic phenomena including a nonferrous box, a stationary platform set in the middle of the box with a post to support a magnet, a right-hand and a left-hand screws united with coupling and having moving platforms at equal distance from the middle fixed platform with posts to support the specimen, the specimen poised by the magnetic field, and to hover the specimen move the platforms back and forth in continuous and intermittent motions, dc stepper motor to provide the motion, and controlled by power supply, push button switches, and limit switches. | 2013-03-21 |
20130069644 | METHOD OF CONTROLLING AN MRI SYSTEM AND AN APPARATUS THEREFOR - A magnetic resonance imaging (MRI) system includes a radio frequency (RF) coil which receives timing information about a pulse sequence and stores the timing information in a memory of the RF coil. Then, when an RF excitation signal is transmitted, the RF coil performs decoupling. When a magnetic resonance (MR) echo signal is generated, the RF coil receives the MR echo signal and transmits the MR echo signal to a central controlling apparatus through a wireless channel. When a transmission error arises, the RF coil retransmits corresponding data in an idle time when the RF excitation signal is not transmitted or the MR echo signal is not generated. Thus, the RF coil is prevented from being damaged by the RF excitation signal and prevents the quality of an MR image from deteriorating compared to a synchronization-type communication method. | 2013-03-21 |
20130069645 | CHARACTERIZATION OF N-GLYCAN MIXTURES BY NUCLEAR MAGNETIC RESONANCE - The present disclosure provides nuclear magnetic resonance (NMR) methods for characterizing mixtures of N-linked glycans. Without limitation, methods of the present disclosure may be useful in characterizing monosaccharide composition, branching, fucosylation, sulfation, phosphorylation, sialylation linkages, presence of impurities and/or efficiency of a labeling procedure (e.g., labeling with a fluorophore such as 2-AB). In certain embodiments, the methods can be used quantitatively. In certain embodiments, the methods can be combined with enzymatic digestion to further characterize glycan mixtures. | 2013-03-21 |
20130069646 | METHOD FOR THE COMPARATIVE ANALYSIS OF PROTEIN PREPARATIONS BY MEANS OF NUCLEAR MAGNETIC RESONANCE - The invention relates to a method for the comparative analysis and control of the quality of a protein preparation by means of nuclear magnetic resonance (NMR) spectrometry. This method can be used to compare three-dimensional protein conformations in different protein preparations without requiring the samples to undergo any particular preparation. In particular, the method can be used to determine if a selected protein is in the same three-dimensional conformation in different protein preparations, if it is degraded in the formulation or if it is interacting with some of the excipients present. Specifically, the method can be used for the analysis and control of the quality of therapeutic compounds, particularly biodrugs or biosimilars, in different samples, without altering said samples. | 2013-03-21 |
20130069647 | TARGETED TRAVELLING WAVE MRI - A travelling wave MRI apparatus is provided that includes a coaxial waveguide arrangement, a cavity for placing therein a subject or object to be imaged, a device for applying a static magnetic field, a device for applying gradient magnetic fields, a device for coupling in electromagnetic excitation pulses having a predetermined operating frequency to induce nuclear magnetic resonance within the subject or object, and a device for detecting an electromagnetic signal resulting from the magnetic resonance. The coaxial waveguide arrangement placed in the cavity of the apparatus comprises a first and a second conductive member arranged in a coaxial arrangement with respect to one another, wherein the first conductive member is formed by a continuous tubular outer member and the second conductive member is formed by a tubular shaped inner member, which is divided in axial direction defining an investigation area. | 2013-03-21 |
20130069648 | METHOD AND MAGNETIC RESONANCE SCANNER FOR HYPERINTENSE DISPLAY OF AREAS IN THE VICINITY OF DIPOLE FIELDS - In a method and magnetic resonance apparatus for the hyperintense display of areas containing particles of magnetically active substances, in an examination region in a measurement volume of a magnetic resonance scanner, measurement data from the examination area are generated by a pulse sequence and recorded, the pulse sequence causing an echo time of less than one millisecond, so that a suppression of undesired signals is also caused. | 2013-03-21 |
20130069649 | MAGNETIZATION TRANSFER AND OFF-RESONANCE PROTOCOLS IN NMR - A method includes acquiring a signal intensity from a spin system after applying the radio frequency preparation pulses prior to the imaging readout or spectroscopic localization, and acquiring signal intensity starting with magnetization initially rotated to a certain angle by applying an initial pulse before the preparation scheme, and processing the data to generate an image or spectra corresponding to the spin system. The imaging or spectroscopy sequence is configured to provide data based on magnetization transfer or an off-resonance effect. | 2013-03-21 |
20130069650 | MAGNETIC RESONANCE IMAGING APPARATUS AND HIGH-FREQUENCY MAGNETIC FIELD PULSE MODULATION METHOD - Degradation of the slice excitation characteristics is prevented by making it possible to modulate a high frequency magnetic field pulse on the basis of a gradient magnetic field response that is actually used. In order to do so, an imaging pulse sequence including first and second measurement sequences is executed. In the first measurement sequence, the same slice selection gradient magnetic field pulse as a slice selection gradient magnetic field pulse used in the second measurement sequence is used. The phase of a magnetic resonance signal measured by the first measurement sequence is differentiated, and the waveform of the high frequency magnetic field pulse is calculated using the result. In the second measurement sequence, a high frequency magnetic field pulse with the calculated waveform is applied together with the slice selection gradient magnetic field pulse, and a magnetic resonance signal for an image is measured. | 2013-03-21 |
20130069651 | MRT Local Coil Apparatus for Diagnostics, Intervention and Therapy - An MRT local coil apparatus ( | 2013-03-21 |
20130069652 | RF COIL AND MAGNETIC RESONANCE IMAGING DEVICE - There is a provided a technology of receiving a magnetic resonance signal highly sensitively and with a uniform sensitivity distribution in an RF coil of an MRI device which is an RF coil including a switch circuit of switching a circuit configuration. The RF coil of the MRI device of the present invention includes a switch circuit of switching a circuit configuration. Also, the switch circuit switches the circuit configuration by being driven by a control signal received by wireless. For that purpose, the switch circuit includes an antenna of receiving the control signal and a conversion circuit of converting an alternating current voltage received into a direct current voltage. | 2013-03-21 |
20130069653 | DEVICE FOR POWER MEASUREMENT AND MAGNETIC RESONANCE DEVICE - A device for power measurement for the purposes of plausibility checking and/or calibration of a primary power measurement device on a power amplifier of a magnetic resonance device is provided. The device includes a circulator arranged between an output of the power amplifier and a switching device for connection of the power amplifier to a transmit antenna. A first input of the circulator is connected to the output of the power amplifier, a second input of the circulator is connected to the switching device, and a third input of the circulator is connected to a secondary power measurement device configured for measurement of a signal reflected on the open switching device or the transmit antenna. | 2013-03-21 |
20130069654 | Method and System for Passive Electroseismic Surveying - A method of passive surveying comprises generating one or more detected signals by passively detecting a signal generated within a subsurface earth formation due to a seismoelectric response or an electroseismic response in at least one porous subsurface earth formation containing at least one fluid, and processing the one or more detected signals to determine at least one property of the subsurface earth formation. | 2013-03-21 |
20130069655 | AT-BIT MAGNETIC RANGING AND SURVEYING - A bottom hole assembly configured for a subterranean drilling operation having a drill bit; a downhole tool deployed above the drill bit, at least a portion of the downhole tool free to rotate with respect to the drill bit about a longitudinal axis of the bottom hole assembly a sensor sub deployed axially between the drill bit and the downhole tool, the sensor sub configured to rotate with the drill bit about the longitudinal axis of the bottom hole assembly and free to rotate with respect to the downhole tool about the longitudinal axis and a tri-axial magnetic field sensor deployed in the sensor sub. | 2013-03-21 |
20130069656 | Borehole Resistivity Imager Using Discrete Energy Pulsing - A resistivity imager uses discrete energy pulsing to determine resistivity of a borehole. The imager has pulse generation circuitry that generates discrete energy pulses. An electrode array exposed to the borehole emits or discharges the discrete energy pulses into the formation. The variations of the formation subject the electrode to impedance levels in response to the discrete energy pulses, and measurement circuitry measures the discharge of the pulsed energy subjected to the impedances. From the measurements, control circuitry determines resistivity parameters of the formation around the borehole. These resistivity parameters can be stored in memory downhole or can be telemetered to the surface. When analyzed, the resistivity measurements can produce an image of the borehole's features, indicate borehole structures, direct geosteering of drilling, or the like. | 2013-03-21 |
20130069657 | ELECTROMAGNETIC SENSOR CABLE AND ELECTRICAL CONFIGURATION THEREFOR - An electromagnetic sensor cable has components including a first sensor cable segment having a plurality of spaced apart electrodes on the first sensor cable segment an electrical conductors coupled to the electrodes such that at least one of the electrodes is electrically connectible at at least one longitudinal end of the first sensor cable segment. The sensor cable includes a second sensor cable segment configured substantially the same as the first sensor cable segment. A first signal processing and configuration module has signal processing circuitry configured to perform at least one of measuring voltages across selected pairs of electrodes, and communicating signals representative of voltages measured across selected pairs of electrodes. The cable components are each configured to connect at the lateral ends one to another. | 2013-03-21 |
20130069658 | DIAGNOSTIC USE OF PHYSICAL AND ELECTRICAL BATTERY PARAMETERS AND STORING RELATIVE CONDITION DATA - In at least one embodiment, a power management module measures an electromagnetic radiation spectrum or a voltage response of a battery module. The measured electromagnetic radiation spectrum or voltage response of the battery is compared to a plurality of reference electromagnetic radiation spectrums or voltage responses, respectively, which may be determined for authentic batteries, for example. A relative condition of the battery, such as an age or state of health, may be estimated based on the measured electromagnetic radiation spectrum or voltage response of the battery module, and stored in a memory store. The rate of change of the relative condition of the battery over a period of time may be determined to identify potential defects in the battery. | 2013-03-21 |
20130069659 | POWER SUPPLYING SYSTEM - [Objective] To provide a power supplying system wherein the timing at which a storage unit conducts capacity learning is made to be more suitable. [Solution] A power supplying system supplies power to loads provided within a facility, and is provided with: a power storage unit that stores power by being charged, and supplies power by being discharged; and a capacity measurement unit that measures the remaining capacity of the power storage unit by executing a complete charging and a complete discharging of the power storage unit, in sequence. The capacity measurement unit obtains the operation schedule of the facility, and determines the timing at which the complete charging and the complete discharging of the power storage unit are to be conducted, on the basis of the operation schedule. | 2013-03-21 |
20130069660 | METHOD FOR IN SITU BATTERY DIAGNOSTIC BY ELECTROCHEMICAL IMPEDANCE SPECTROSCOPY - The invention is a method for estimating the internal state of a system for the electrochemical storage of electrical energy, such as a battery. For various internal states of batteries of the same type as a battery being analysed, impedance measurements are carried out by adding an electrical signal to the current passing through the batteries. Then, an RC circuit is used to model the impedances. Next, a relationship is calibrated between the SoC (and/or the SoH) and the parameters of the RC circuit using multivariate statistical analysis. A measurement of the impedance of the battery under analysis is carried out which is modeled using the RC circuit. Finally, the relationship of the equivalent electric circuit defined for the battery being analysed is used to estimate the internal state of that battery. | 2013-03-21 |
20130069661 | DIAGNOSTIC USE OF A PLURALITY OF ELECTRICAL BATTERY PARAMETERS - In at least one embodiment, a power management module measures different observable quantities of a battery, such as terminal voltage or current, and measures a voltage response of the battery based upon the measurements. The measured voltage response of the battery is compared to a plurality of reference voltage responses, which may be determined for authentic batteries, for example. If the measured voltage response corresponds to each of the reference voltage responses, the battery is authenticated for use with an electronic device. If necessary, additional voltage responses may be measured and compared against corresponding reference voltage responses until the battery is authenticated by a sufficient number of corresponding responses. A relative condition of the battery, such as an age or state of health, may also be estimated based on the measured voltage response of the battery. | 2013-03-21 |
20130069662 | SECONDARY BATTERY, INSPECTION APPARATUS AND INSPECTION METHOD FOR SECONDARY BATTERY, AND BATTERY INSPECTION SYSTEM - A plurality of detection units are connected respectively in parallel with a plurality of battery cells connected in series. The detection units each include an inductor and a zener diode connected in series. A battery checker includes a plurality of detection inductors and a single voltmeter that form a closed circuit. A plurality of detection inductors are arranged so that they are magnetically coupled respectively with the inductors of the plurality of detection units. Each zener diode is connected with the polarity to be reverse biased by the output voltage of the battery cell. Respective breakdown voltages of the zener diodes are set higher than the output voltage of each battery cell in normal use and different in a stepwise manner from each other. | 2013-03-21 |
20130069663 | Crack Detection in Ceramics Using Electrical Conductors - Various embodiments provide methods and systems for detecting cracks in ceramic electrolytes using electrical conductors. A method for testing an electrolyte material, such as a ceramic electrolyte material for use in a solid oxide fuel cell device, includes providing a conductive path on the electrolyte material, electrically connecting a probe across the conductive path, and measuring a value associated with the conductive path to determine the presence or absence of a crack in the material. | 2013-03-21 |
20130069664 | INDIRECT NON-CONTACT HIGH VOLTAGE MEASUREMENT ON ELECTRICAL POWER LINE - A non-contact electrical power line voltage measurement device comprises a probe including an insulated shield supporting an electrode to sense electrostatically induced voltage from the power line. The shield houses a high voltage resistor connected in series with the electrode. A meter comprises a housing operatively associated with the shield and enclosing a measurement circuit electrically connected to the high voltage resistor for measuring induced electrode voltage. A calibration circuit correlates measured electrode voltage to power line voltage. A display is driven by the measurement circuit for displaying actual power line voltage responsive to the electrode being a select distance from the power line. | 2013-03-21 |
20130069665 | USING A FIELD EFFECT DEVICE FOR IDENTIFYING TRANSLOCATING CHARGE-TAGGED MOLECULES IN A NANOPORE SEQUENCING DEVICE - A detector apparatus includes a field-effect transistor configured to undergo a change in amplitude of a source-to-drain current when at least a portion of a charge-tagged molecule translocates through the nanopore. In some implementations, the field-effect transistor is a carbon nanotube field effect transistor and the nanopore is located in a membrane. In other implementations, the field-effect transistor is a carbon nanotube field effect transistor and the nanopore is implemented in the form of a nano-channel in a semiconductor layer. | 2013-03-21 |
20130069666 | POWER SUPPLY AGING SYSTEM AND LOAD BALANCE CONTROL METHOD - A power supply aging system and a load balance control method. The power supply aging system includes: a system share supply unit ( | 2013-03-21 |
20130069667 | FAULT DETECTION FOR PARALLEL INVERTERS SYSTEM - According to one aspect, embodiments of the invention provide a method of operating a UPS system having a first UPS and a second UPS, the method comprising coupling at least one control line between the first UPS and the second UPS to operate the first UPS and the second UPS in a parallel mode of operation, providing output power from each of the first UPS and the second UPS to a load, detecting a fault condition in the UPS system, decoupling the at least one control line, operating the first UPS in a diagnostic mode of operation, and determining if the fault condition is associated with the first UPS. | 2013-03-21 |
20130069668 | WIRE HARNESS CONTINUITY INSPECTION METHOD AND WIRE HARNESS CONTINUITY INSPECTION PROGRAM - The time required for a success or failure determination step and the precision of the success or failure determination step are optimized by determining region-based connector or wiring information and by adjusting increase and decrease of the number of such patterns. Region-based connector or wiring information is created for at least every described region in numbers equal to the number of combinations of a first wire harness, a second wire harness, and a third wire harness. The first wire harness is one of first wire harnesses arrangeable in Main | 2013-03-21 |
20130069669 | ELECTROSTATIC SHIELDING TECHNIQUE ON HIGH VOLTAGE DIODES - A DC high potential testing meter comprises first and second probes. The first probe comprises an insulated shield supporting an electrode extending from a distal end of the shield. A high voltage resistor and a high voltage diode in the shield are connected in series with the electrode. A capacitance formed by a metallic collar across the high voltage diode provides uniform voltage distribution along the high voltage diode. The second probe comprises an insulated shield supporting an electrode. A high voltage resistor in the shield is connected in series with the electrode. A meter comprises a housing enclosing an electrical circuit for measuring voltage across the electrodes and provides an output representing measured voltage. | 2013-03-21 |
20130069670 | DIFFERENTIAL SIGNAL TRANSMISSION CABLE PROPERTY EVALUATING MECHANISM AND EVALUATING METHOD THEREFOR - A differential signal transmission cable property evaluating mechanism includes a substrate having a signal line pad to be connected with a signal line conductor of a differential signal transmission cable and a ground pad to be connected with a shield conductor of the differential signal transmission cable, a pressing member for pressing the signal line conductor to the signal line pad, a shield conductor holding sheet including an elastic insulating sheet and a metal foil provided over one side of the elastic insulating sheet, the shield conductor holding sheet provided for indirectly connecting the shield conductor and the ground pad to each other by contacting the metal foil with the shield conductor and the ground pad, and a clip for fixing the shield conductor holding sheet. | 2013-03-21 |
20130069671 | LOW POWER CAPACITIVE TOUCH DETECTOR - A low power capacitive detector is disclosed. The detector includes a mechanism to measure and detect touch on capacitive sensors. The detector uses signal processing to suppress noise and increase sensitivity. The detector does not require dedicated analog circuitry, making it easy to adopt in a microcontroller system. The detector can be scaled to a larger number of capacitive sensors without noticeable increase in silicon cost. | 2013-03-21 |
20130069672 | LOW POWER CAPACITIVE TOUCH DETECTOR - A low power capacitive detector is disclosed. The detector includes a mechanism to measure and detect touch on capacitive sensors. The detector uses signal processing to suppress noise and increase sensitivity. The detector does not require dedicated analog circuitry, making it easy to adopt in a microcontroller system. The detector can be scaled to a larger number of capacitive sensors without noticeable increase in silicon cost. | 2013-03-21 |
20130069673 | COMBINED HEATING AND CAPACITIVE SEAT OCCUPANT SENSING SYSTEM - A combined heating and capacitive seat occupant sensing system comprises a common mode choke configured so as to satisfy at least one of a plurality of conditions, which is taken into account by a decision unit of the system in such a way that an influence of the common mode choke on the decision is compensated. | 2013-03-21 |
20130069674 | APPARATUS FOR MEASURING A RADIUS OF A WORKPIECE - An apparatus for measuring a workpiece includes a capacitance probe mounted to a probe housing and a non-conductive spacer. The capacitance probe includes a probe tip with a sensor surface that emits an electric field. The non-conductive spacer extends between a probe contact surface and a workpiece contact surface. The probe contact surface covers the sensor surface, and the workpiece contact surface contacts the workpiece during the measuring of the radius. | 2013-03-21 |
20130069675 | CONDUCTIVE FLUID LEAK DETECTOR - A conductive fluid leak detector having an enclosed and secure housing is disclosed. The housing as well as a pair of conductive fluid sensing probes that project through the housing are tamper-resistant. The detector is provided with a switch for activation of a wash down mode which allows cleaning of the environment where the detector is installed without triggering an alarm. Upon activating the switch, the detector is deactivated for a predetermined period of time. The conductive fluid leak detector is coupled to an external maintenance or alarm system. When not deactivated or in the wash down mode, the detector sends a signal to the external system when conductive fluid is detected by the sensing probes. | 2013-03-21 |
20130069676 | Corrosion Detection Apparatus for Monitoring a State of Corrosion - A corrosion detection apparatus for permanently and integrally monitoring a state of corrosion of a component is provided. The corrosion detection apparatus makes it possible to use the change in electrical conductivity to detect corrosion of a component to be monitored. A corrosion-sensitive bridging element that establishes an electrical connection between a first electrical line section and a second electrical line section of a sensor circuit is used to change certain electrical properties of the sensor circuit. On account of the corrosion-sensitive property of the bridging element, the latter changes its electrical conductivity when corrosion starts. This makes it possible to use the sensor circuit to detect corrosion of the bridging element and thus of the component to be monitored. | 2013-03-21 |
20130069677 | ELECTROSTATIC SHIELDING TECHNIQUE ON HIGH VOLTAGE RESISTOR - A phasing voltage meter comprises first and second probes. Each probe comprises an insulated shield supporting an electrode for contacting a high voltage electrical conductor. The shield houses a high voltage resistor connected in series with the electrode. A capacitance formed by a metallic collar across the resistor compensates for stray capacitance across the resistor. A meter comprises a housing enclosing electrode circuit for measuring phasing voltage. The electrical circuit measures voltage across the electrodes and provides an output representing phasing voltage. | 2013-03-21 |
20130069678 | EFFICIENT METHODS AND APPARATUS FOR MARGIN TESTING INTEGRATED CIRCUITS - Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails. | 2013-03-21 |
20130069679 | Testing of Defibrillator Electrodes - A defibrillator ( | 2013-03-21 |
20130069680 | RISERS INCLUDING A PLURALITY OF HIGH ASPECT RATIO ELECTRICAL CONDUITS AND SYSTEMS AND METHODS OF MANUFACTURE AND USE THEROF - Risers including a plurality of high aspect ratio electrical conduits, as well as systems and methods of manufacture and/or use of the risers and/or the high aspect ratio electrical conduits. The systems and methods may include incorporation of the plurality of high aspect ratio electrical conduits within a substantially planar body that may include and/or be formed from a solid dielectric material. The plurality of electrical conduits may be configured to conduct a plurality of electric currents between a first surface of the body and a second, substantially opposed, surface of the body. The surfaces may include a plurality of contact pads configured to provide a robust and/or corrosion-resistant surface and/or to improve electrical contact between the riser and another device. The risers also may include a layered structure, wherein the layers are sequentially formed to increase a thickness of the riser and/or the aspect ratio of the electrical conduits. | 2013-03-21 |
20130069681 | TEST CARD FOR MOTHERBOARDS - A test card includes a power interface, a controller, a test interface, and a test point. The test interface includes a power pin, a start pin, and a data signal pin. The power interface is connected to the controller and the power pin, and also connected to an external power to receive a work voltage. The controller transmits a turn-on signal to the start pin. The test point is connected to the data signal pin. When an interface of a motherboard is connected to the test interface, the power pin, the start pin, and the data signal pin are connected to corresponding pins of the interface of the motherboard. The motherboard outputs a data signal to the test point through the motherboard interface and the test interface after the controller receives the turn-on signal. | 2013-03-21 |
20130069682 | CIRCUIT STRUCTURE OF TEST-KEY AND TEST METHOD THEREOF - A circuit structure of a test-key and a test method thereof are provided. The circuit structure comprises a plurality of transistors, a first conductive contact, a plurality of second conductive contacts and a plurality of third conductive contacts. The transistors are arranged in a matrix. The first conductive contact is electrically connected to one source/drain of each transistor in each column of the matrix. Each second conductive contact is electrically connected to the other source/drain of each transistor in a corresponding column of the matrix. Each third conductive contact is electrically connected to the gate of each transistor in a corresponding row of the matrix. In the method, a plurality of driving pulses are provided to the third conductive contacts in sequence, and a plurality of output signals are read from the second conductive contacts to perform an element-character analyzing operation when a row of the transistors is turned on. | 2013-03-21 |
20130069683 | TEST PROBE CARD - A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining | 2013-03-21 |
20130069684 | PROBE FOR INSPECTING ELECTRONIC COMPONENT - A probe for inspecting electronic components, and more particularly, to a probe for inspecting electronic components, which connects a target electronic component to an inspection apparatus to inspect defects of the target electronic component. The probe for inspecting electronic components includes: a cylinder body having a cylindrical shape; a piston body reciprocating between an inside and an outside of the cylinder body; a spring surrounding an outer circumference of the cylinder body and the piston body, and forcing a part of the piston body to resiliently move out of the cylinder body when inserted into the cylinder body; a probing unit extending from the cylinder body to be brought into contact with a target electronic component to be inspected as to flow of electric current therethrough; and a contact unit extending from the piston body to be connected to an inspection apparatus for inspecting the target electronic component. | 2013-03-21 |
20130069685 | INTEGRATED CIRCUIT TEST SOCKET HAVING TEST PROBE INSERTS - A test socket having a lid and a base with a cavity for receipt of an integrated circuit and removable test probe inserts having test probes positioned around a perimeter of the cavity. | 2013-03-21 |
20130069686 | PROBING DEVICE AND MANUFACTURING METHOD THEREOF - A probing device and manufacturing method thereof are provided. The manufacturing method includes first disposing a plurality of space transformers on a reinforcing plate and the space transformer includes several first pads. Then, the space transformer is fixed on the reinforcing plate. Thereafter, photoresist films having a plurality of openings is formed on the space transformer. The first pads are disposed in the openings. After that, a metal layer is formed and covered on the first pad. Later, the photoresist film is removed and the metal layer is planarized to form a second pad. Afterwards, the reinforcing plate is electrically connected with a PCB. Thereafter, a probe head having a plurality of probing area is provided and each probing area is corresponding to one of the space transformer. The probes in the probing area are electrically connected with the internal circuitry of the space transformer. | 2013-03-21 |
20130069687 | SOLAR SIMULATOR AND SOLAR CELL INSPECTION DEVICE - A solar simulator having improved measurement precision, including an array of light emitters having point light emitters planarly arranged in a given range, an effective irradiated region spaced apart from a surface having the array thereon, and a portion which absorbs at least a part of light from a direction which passes through a gap between the individual point light emitters. In a preferred aspect, the light absorption portion includes an absorption surface disposed in at least a part of the gaps between the light emitters. In another preferred aspect, a translucent board holds the light emitters and has a translucent portion corresponding to at least a part of the gaps between the light emitters, and an absorption layer at a position for absorbing light from the direction which passes through the translucent portion. | 2013-03-21 |
20130069688 | DIGITAL TEST SYSTEM AND METHOD FOR VALUE BASED DATA - Embodiments of the present invention provide an inequality indication system (IIS). The IIS provides built in test support which enables evaluation, in an on-chip digital logic circuit, of digital values as inequalities, with either a single pass/fail bit expressed on a device I/O or a readable register containing inequality evaluation results. The IIS enables the movement of value evaluation onto the device (chip) using a common simple method, well suited to address/data type structures or scan based structures, instead of off-chip, which then requires tester dependent custom code. The IIS, when enabled, overrides the TDO signal to allow it to function as an inequality indicator instead of a standard test data out signal. | 2013-03-21 |
20130069689 | Method For Operating Memory Device And Apparatuses Performing The Method - According to example embodiments, a method for operating a memory device includes receiving an on-die termination (ODT) signal through an ODT pin, and issuing a command or controlling an ODT circuit according to the ODT signal. | 2013-03-21 |
20130069690 | POWER CONTROL CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME - A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal. | 2013-03-21 |
20130069691 | INTEGRATED CIRCUIT HAVING A STANDARD CELL AND METHOD FOR FORMING - An integrated circuit includes a first plurality of transistors and a second plurality of transistors coupled together to form a standard cell that performs a logic function. Each of the first plurality of transistors is more critical to a speed of operation of the standard cell than any of the transistors of the second plurality of transistors. Each of the first plurality of transistors has a gate length longer than a gate length of any of the transistors of the second plurality of transistors. | 2013-03-21 |
20130069692 | STATE TRANSITIONING CLOCK GATING - In some embodiments, new clock gating approaches, referred hereafter as State Transition Gating (STG) methods and circuits are provided. In areas of circuit designs including sequential elements, the use of STG may be used to reduce dynamic power consumption. | 2013-03-21 |
20130069693 | SENSE AMPLIFIER AND ELECTRONIC APPARATUS USING THE SAME - A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected. | 2013-03-21 |
20130069694 | SEMICONDUCTOR DEVICE - A semiconductor device may be provided with a semiconductor substrate, an insulating film disposed on a surface of the semiconductor substrate, at least one electrode disposed on a surface of the insulating film, and a voltage applying circuit configured to apply a first voltage to the at least one electrode. The semiconductor substrate may be provided with a cell region and a non-cell region adjacent to the cell region. The cell region is provided with a semiconductor element, and the non-cell region is provided with a withstand voltage structure. The insulating film may be disposed on a surface of the non-cell region. The at least one electrode may be electrically insulated from the semiconductor substrate. The voltage applying circuit may apply the first voltage to the electrode during at least a part of a first period in which a second voltage is not applied to the semiconductor element. | 2013-03-21 |
20130069695 | Frequency Reference Signal Generating System and Method for Frequency Synthesizers - A system for generating a frequency reference signal comprising an oscillator, a direct digital synthesizer coupled to the oscillator and configured to receive a signal output from the oscillator, a digital to analog converter coupled to the direct digital synthesizer and configured to receive a sampled signal from the direct digital synthesizer and to convert the sampled signal to an analog waveform, and a bandpass filter coupled to the digital to analog converter and configured to select an aliased output signal from the digital to analog converter at a Nyquist zone other than a first Nyquist zone and to output the frequency reference signal. | 2013-03-21 |
20130069696 | Fractional-N Phase Locked Loop - A frequency division circuit with a rational-valued division ratio includes a frequency divider with a selectable integer-valued division ratio supplied with an input signal of a first frequency. An output signal provides a second frequency. A first sigma-delta modulator provides a first modulated control signal representative of a first fractional number. A second sigma-delta modulator provides a second modulated control signal of a second fractional number. The integer-valued division ratio of the frequency divider is modified in accordance with the modulation of the first and the second modulated control signals. | 2013-03-21 |
20130069697 | SYNCHRONIZER WITH HIGH RELIABILITY - A system and method for synchronizing asynchronous input signals with reliability. Each of a first and a second storage element in a synchronizer receives a first clock signal in a first clock domain. The second storage element may also receive a first reset signal generated by a second clock signal in the first clock domain different from the first clock signal. The first storage element receives a combination of an asynchronous data input signal and the first reset signal. The data input signal may be generated from circuitry utilizing a second clock domain different from the first clock domain. The second storage element additionally receives an output of a second combination of a stored output value of the first storage element and a second reset signal generated from the first clock signal. The second storage element stores a stable output value based at least on the asynchronous data input signal. | 2013-03-21 |
20130069698 | RESET SIGNAL GENERATING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - A reset signal generating circuit according to an aspect of the present invention includes: a first signal line that transmits a reference reset signal to a first node; a second signal line that transmits an inverted signal of the reference reset signal to a second node; a first inverting circuit that outputs an inverter signal of the signal transmitted to the second node; and a control circuit that makes a reset signal active regardless of the reference reset signal, when a logical value of the signal transmitted to the first node does not match a logical value of the signal output from the first inverting circuit. | 2013-03-21 |
20130069699 | Microwave Synthesizer - A microwave synthesizer is disclosed that may generate low phase noise and high frequency resolution microwave signals The microwave synthesizer may include a coarse-tuning loop, the coarse-tuning loop may be adopted to generate a first signal with coarsely adjustable frequency. The coarse-tuning loop may have a first voltage controlled oscillator (VCO). An output loop, the output loop may be adopted to generate a second signal with finely adjustable frequency. The output loop may have a second VCO. A frequency mixer may be configured to couple the coarse-tuning loop and the output loop. A frequency mixer may be adopted to subtract the first and second signals. A reference frequency source may be coupled to the coarse-tuning loop and the output loop to provide reference signal for the microwave synthesizer. | 2013-03-21 |
20130069700 | CIRCUIT AND METHOD FOR CONTROLLING MIXED MODE CONROLLED OSCILLATOR AND CDR CIRCUIT USING THE SAME - A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal. | 2013-03-21 |
20130069701 | PHASE INTERPOLATION CIRCUIT - A phase interpolation circuit including a first multiplexer, a second multiplexer, an interpolator and a duty-cycle repeater is provided. The first multiplexer receives a plurality of even order signals. The second multiplexer receives a plurality of odd order signals. The interpolator receives a first reference signal composed of one of the even order signals through the first multiplexer, and receives a second reference signal composed of one of the odd order signals through the second multiplexer. The interpolator divides a phase difference between the first reference signal and the second reference signal into a plurality of sub-phases according to a digital control signal, and selects one of the sub-phases to generate a differential input signal. The duty-cycle repeater adjusts the duty cycle of the differential input signal and accordingly generates a differential output signal with 50% duty cycle. | 2013-03-21 |
20130069702 | PWM SIGNAL OUTPUT CIRCUIT - A PWM-signal-output circuit includes a first output unit to output a PWM signal with a first duty cycle, in a first period in which a motor starts rotating, a second output unit to output the PWM signal whose duty cycle increases toward a second duty cycle and decreases from the second duty cycle in a period from a logic level change in speed signal until its subsequent logic level change, in a second period following the first, the speed signal having a period corresponding to a motor-rotation speed and a logic level changing alternately, and a third output unit to output the PWM signal whose duty cycle increases toward that of the input signal and thereafter decreases from that of the input signal in a period from a logic level change in the speed signal until its subsequent logic level change, after the second period elapses. | 2013-03-21 |
20130069703 | UNIFORM-FOOTPRINT PROGRAMMABLE-SKEW MULTI-STAGE DELAY CELL - Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell. | 2013-03-21 |
20130069704 | ONE-WIRE COMMUNICATION CIRCUIT AND ONE-WIRE COMMUNICATION METHOD - A communication circuit facilitating communication between a first equipment and a second equipment including a conversion circuit, an input port, an output port, and a communication port is disclosed. The conversion circuit converts an input signal to a first intermediate signal, and converts a second intermediate signal to an output signal. The input port inputs the input signal to the first conversion circuit. The output port outputs the output signal to the control unit. The communication port inputs the second intermediate signal to the conversion circuit, and outputs the first intermediate signal to the second equipment. A voltage of the first intermediate signal is determined based on a voltage of a power source if the first intermediate signal is logic high, and a voltage of the second intermediate signal is determined based on the voltage of the power source if the second intermediate signal is logic high. | 2013-03-21 |
20130069705 | SYSTEMS AND METHODS FOR LOWERING INTERCONNECT CAPACITANCE - Methods and apparatus for lowering the capacitance of an interconnect, are disclosed. An example apparatus may include an interconnect formed in at least one integrated circuit and configured to pass a signal through at least a portion of the at least one integrated circuit. The apparatus may include a transmitter to operate at a first voltage and a second voltage, and to output to an end node of the interconnect a reduced swing signal ranging from the first voltage to a third voltage. The third voltage may be between the first and second voltages, and the reduced swing signal may operate to reduce a capacitance of the interconnect when compared to operating the transmitter at the second voltage. Additional apparatus and methods are disclosed. | 2013-03-21 |
20130069706 | APPARATUS AND METHODS FOR ADAPTIVE COMMON-MODE LEVEL SHIFTING - Apparatus and methods for adaptive level shifting are provided. In one embodiment, a method of level shifting in an adaptive level shifter (ALS) is provided. The technique includes charging a first capacitor and a second capacitor each to a voltage that is about equal to a difference between a common mode voltage of a differential input voltage signal and a reference voltage. The technique can further include inserting the first capacitor between a first input and a first output of the ALS and the second capacitor between the second input and a second output of the ALS. The technique can further include switching the first capacitor and the second capacitor such that the first capacitor is inserted between the second input and the second output and the second capacitor is inserted between the first input and the first output. | 2013-03-21 |
20130069707 | LEVEL SHIFTER CIRCUIT - An embedded system includes a level shifter circuit for generating a forward supply voltage level in a predefined range. A sense circuit senses a core supply voltage level of the embedded system and compares the sensed core supply voltage level with a predetermined minimum core supply voltage level needed to generate the forward supply voltage. A reset circuit maintains one or more input nodes and one or more internal nodes of the level shifter circuit at a predetermined voltage level when the core supply voltage level is less than the predetermined minimum core supply voltage level. | 2013-03-21 |
20130069708 | SEMICONDUCTOR INTEGRATED CIRCUIT, RF MODULE USING THE SAME, AND RADIO COMMUNICATION TERMINAL DEVICE USING THE SAME - One high-frequency switch Qm supplied with transmit and receive signals to ON, and another high-frequency switch Qn supplied with a signal of another system to OFF are controlled. In the other high-frequency switch Qn, to set V-I characteristics of near-I/O gate resistances Rg | 2013-03-21 |
20130069709 | AC POWERED LOGIC CIRCUITS AND SYSTEMS INCLUDING SAME - AC powered logic circuits and systems including same are disclosed. According to one aspect, a system including a logic circuit powered using an alternating current (AC) power source includes at least one supply transistor connected to receive voltages of opposite phases from an AC power source such that the at least one supply transistor is strongly on during a first phase of the voltage of the AC power source and is strongly off during a second phase opposite the first phase of the voltage of the AC power source and at least one logic circuit connected to be powered by the AC power source through the at least one supply transistor and producing an output at an output terminal responsive to an input received at an input terminal. | 2013-03-21 |
20130069710 | POWER TRANSISTOR WITH CONTROLLABLE REVERSE DIODE - An electronic circuit includes a transistor device that can be operated in a reverse operation mode and a control circuit. The transistor device includes a source region, a drain region, a body region and a drift region, a source electrode electrically connected to the source region, a pn junction formed between the body region and the drift region, a gate electrode adjacent the body region and dielectrically insulated from the body region, and a depletion control structure adjacent the drift region. The depletion control structure has a control terminal and is configured to generate a depletion region in the drift region dependent on a drive signal received at the control terminal. The control circuit is coupled to the control terminal of the depletion control structure and configured to drive the depletion control structure to generate the depletion region when the transistor device is operated in the reverse operation mode. | 2013-03-21 |
20130069711 | CHARGE PUMP SYSTEM CAPABLE OF STABILIZING AN OUTPUT VOLTAGE - A charge pump system includes a charge pump, a ring oscillator, a comparing circuit and a discharge circuit. When an output voltage of the charge pump is relatively low, the comparing circuit turns on the ring oscillator to make the ring oscillator provide an oscillation output to the charge pump to raise the output voltage of the charge pump. When the output voltage of the charge pump is relatively high, the comparing circuit turns off the ring oscillator to stop the ring oscillator from providing the oscillation output to the charge pump, the comparing circuit also makes the discharge circuit provide a discharge path to the charge pump to quickly reduce the output voltage of the charge pump. | 2013-03-21 |
20130069712 | POWER SEMICONDUCTOR DEVICES AND FABRICATION METHODS - We describe a RESURF semiconductor device having an n-drift region with a p-top layer and in which a MOS (Metal Oxide Semiconductor) channel of the device is formed within the p-top layer. | 2013-03-21 |
20130069713 | SEMICONDUCTOR DEVICE - A microcomputer includes a first switch coupled between a main power supply terminal and a power supply node, and a second switch coupled between an auxiliary power supply terminal and the power supply node. The microcomputer compares a voltage V1 of the main power supply terminal with a reference voltage VR1. When V1>VR1, the microcomputer turns on the first switch and turns off the second switch, and when V12013-03-21 | |
20130069714 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR DEVICE - A semiconductor device and a method of operating the semiconductor device. The semiconductor device includes a voltage generator configured to generate a test voltage, a graphene transistor configured to receive a gate-source voltage based on the test voltage, and a detector configured to detect whether the gate-source voltage is a Dirac voltage of the graphene transistor, and output a feedback signal applied to the voltage generator indicating whether the gate-source voltage is the Dirac voltage. | 2013-03-21 |
20130069715 | PSRR IN A VOLTAGE REFERENCE CIRCUIT - Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node. | 2013-03-21 |
20130069716 | TUNABLE VOLTAGE-CONTROLLED PSEUDO-RESISTOR - A tunable voltage-controlled pseudo-resistor structure, comprising: a symmetric PMOS transistor circuit and an auto-tuning circuit connected in series. Input of the auto-tuning circuit is connected to a central position V | 2013-03-21 |
20130069717 | Display Device and Method of Canceling Offset Thereof - A method of canceling an offset of display device includes coinciding offset directions of amplifiers with one another and canceling offsets of the amplifiers through a chopping operation. | 2013-03-21 |
20130069718 | APPARATUS AND METHODS FOR ELECTRONIC AMPLIFICATION - Apparatus and methods for electronic amplification are provided. In one embodiment, an amplifier includes a first adaptive level shifter (ALS), a second ALS, a first transconductance amplification circuit, a second transconductance amplification circuit, and a transimpedance amplification circuit. The first ALS and the second ALS are electrically coupled to the first and second transconductance amplification circuits to improve the input voltage range and common-mode rejection ratio (CMRR) of the amplifier. The transimpedance amplification block is electrically coupled to the first and second transconductance amplification blocks and generates an output voltage of the amplifier. The first ALS receives a differential input voltage, and the second ALS is configured to receive a feedback signal configured to change in relation to the output voltage signal. | 2013-03-21 |
20130069719 | AMPLIFIER CIRCUIT, DETECTOR ARRANGEMENT AND METHOD FOR OPERATING AN AMPLIFIER - An amplifier circuit comprises a measurement path with an amplifier ( | 2013-03-21 |
20130069720 | APPARATUS AND METHODS FOR ELECTRONIC AMPLIFICATION - Apparatus and methods for electronic amplification are provided. In one embodiment, a method amplifying a differential input voltage signal using a first NMOS transistor and a second NMOS transistor is provided. The method includes controlling a drain-source voltage of the first NMOS transistor using a first high voltage NMOS transistor and a first high voltage PMOS transistor. The first high voltage NMOS and PMOS transistors are electrically connected in parallel and to a drain of the first NMOS transistor. The method further includes controlling a drain-source voltage of the second NMOS transistor using a second high voltage NMOS transistor and a second high voltage PMOS transistor. The second high voltage NMOS and PMOS transistors are electrically connected in parallel and to a drain of the second NMOS transistor. | 2013-03-21 |
20130069721 | AMPLIFYING CIRCUIT - A circuit includes a first circuit module with a first input node, a second input node and an output node. The first circuit module receives an input signal at the first input node and generates an amplified signal at the output node. The circuit further includes a second circuit module coupled between the output node and a reference potential line. The second circuit selectively draws a current from the output node in response to a first control signal. The first control signal is generated in response to sensing a voltage fluctuation at a power supply node which supplies power to the first circuit module. | 2013-03-21 |
20130069722 | MULTI-BAND AMPLIFIER AND METHOD OF AMPLIFYING MULTI-BAND - Provided is a multi-band amplifier and a method of amplifying a multi-band. The multi-band amplifier includes a wireless signal input terminal into which a first frequency band signal and a second frequency band signal are input, a first impedance matching part connected to the wireless signal input terminal and configured to match an input impedance in a first frequency band, a second impedance matching part connected to the wireless signal input terminal and configured to match an input impedance in a second frequency band, a common source amplifier to which the first impedance matching part and the second impedance matching part, and a common gate amplifier connected to the common source amplifier. Accordingly, performance degradation can be reduced in comparison with a conventional amplifier, broadband amplification as well as narrow band amplification can be performed, and an amplification gain can be adjusted. | 2013-03-21 |
20130069723 | POWER AMPLIFICATION CIRCUIT HAVING TRANSFORMER - In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted. | 2013-03-21 |
20130069724 | SUPPLY INDEPENDENT BIASING CIRCUIT - A supply-independent biasing source includes an upper current mirror including first and second PMOS transistors and a lower current mirror coupled to the upper current mirror including first and second NMOS transistors. The first NMOS and first PMOS transistors have drain terminals coupled together and form a first stack of transistors and the second NMOS and second PMOS transistors have drain terminals coupled together and form a second stack of transistors. A first resistive load is connected to one of the first and second stacks, wherein the resistive load comprises a first MOSFET transistor biased at triode region. | 2013-03-21 |
20130069725 | RF POWER AMPLIFIER - A reduction is achieved in the primary-side input impedance of a transformer (voltage transformer) as an output matching circuit without involving a reduction in Q-factor. An RF power amplifier includes transistors, and a transformer as the output matching circuit. The transformer has a primary coil and a secondary coil which are magnetically coupled to each other. To the input terminals of the transistors, respective input signals are supplied. The primary coil is coupled to each of the output terminals of the transistors. From the secondary coil, an output signal is generated. The primary coil includes a first coil and a second coil which are coupled in parallel between the respective output terminals of the transistors, and each magnetically coupled to the secondary coil. By the parallel coupling of the first and second coils of the primary coil, the input impedance of the primary coil is reduced. | 2013-03-21 |
20130069726 | POWER AMPLIFICATION APPARATUS - According to one embodiment, a power amplification apparatus includes an field effect transistor (FET), a first decoupling element, a power supply circuit, a second decoupling element, and a third decoupling element. The FET is arranged within a package having an input terminal and an output terminal, and power-amplify an input signal from the input terminal to a transmission signal. The first decoupling element decreases an inductance component of the transmission signal output from the FET. The power supply circuit supplies a driving power to the FET. The second decoupling element cut an RF component. The third decoupling element decreases an impedance of a drain bias circuit over a wide band. | 2013-03-21 |
20130069727 | Transimpedance Amplifier and Method Thereof - A transimpedance method and apparatus are provided. In one implementation an apparatus includes a common-gate amplifier for receiving a first current from a first circuit node and outputting a second current to a second circuit node, and a load circuit coupled to the second circuit node, the load circuit comprising a diode-connected MOS (metal-oxide semiconductor field effect transistor), wherein a gate terminal of the MOS is coupled to a drain terminal of the MOS via a resistor. In one embodiment, a current-mode input is injected to the first circuit node and the apparatus further comprises a biasing circuit for outputting a substantially constant current to the first circuit node. | 2013-03-21 |
20130069728 | Automatic bias operational amplifying circuit and system - An automatic bias operational amplifying circuit, includes a control sub-circuit and an offset sub-circuit connected to the control sub-circuit. The control sub-circuit includes a first input terminal, a second input terminal, a first field-effect transistor connected to the offset sub-circuit, a second field-effect transistor connected to the first input terminal, a third field-effect transistor connected to the second input terminal, a first output terminal connected to the second field-effect transistor, a second output terminal connected to the third field-effect transistor, a first resistor connected to the first output terminal, and a second resistor connected to the second output terminal. The offset sub-circuit includes a reference voltage terminal, a comparator connected between the reference voltage terminal and the control sub-circuit, a third resistor connected between the comparator and the second output terminal, and a fourth resistor connected between the comparator and the first output terminal Its system is further provided. | 2013-03-21 |