09th week of 2016 patent applcation highlights part 64 |
Patent application number | Title | Published |
20160064228 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC MATERIAL AND SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR - An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A first protection layer is formed over the semiconductor structure. The first protection layer covers the logic transistor region and the input/output transistor region. At least a portion of the ferroelectric transistor region is not covered by the first protection layer. After the formation of the first protection layer, a ferroelectric transistor dielectric is deposited over the semiconductor structure, the ferroelectric transistor dielectric and the first protection layer are removed from the logic transistor region and the input/output transistor region, an input/output transistor dielectric is formed over the input/output transistor region and a logic transistor dielectric is formed over at least the logic transistor region. | 2016-03-03 |
20160064229 | METHOD AND APPARATUS FOR THINNING WAFER - A method and an apparatus for thinning a wafer are provided. The method for thinning a wafer, according to one embodiment of the present invention, comprises the steps of: irradiating a line beam focused at a specific depth of the wafer; scanning the wafer by using the line beam so as to form an interface at the specific depth of the wafer; and cleaving the wafer on which the interface is formed into a pattern wafer and a dummy wafer. | 2016-03-03 |
20160064230 | WAFER PROCESSING METHOD - A wafer processing method includes a first grinding step and a second grinding step. In the first grinding step, first grinding abrasives are moved in a processing feed direction that is a direction orthogonal to a holding surface of a chuck table of grinding apparatus and a wafer is ground to form a first circular recess in the back surface of the wafer. In the second grinding step, second grinding abrasives formed of finer abrasive grains than the first grinding abrasives are moved down in an oblique direction from the center side of the wafer toward the periphery of the wafer and the first circular recess is ground. | 2016-03-03 |
20160064231 | FAST ATOMIC LAYER ETCH PROCESS USING AN ELECTRON BEAM - An etch process gas is provided to a main process chamber having an electron beam plasma source, and during periodic passivation operations a remote plasma source provides passivation species to the main process chamber while ion energy is limited below an etch ion energy threshold. During periodic etch operations, flow from the remote plasma source is halted and ion energy is set above the etch threshold. | 2016-03-03 |
20160064232 | ION BEAM ETCH WITHOUT NEED FOR WAFER TILT OR ROTATION - Various embodiments herein relate to methods and apparatus for etching feature on a substrate. In a number of embodiments, no substrate rotation or tilting is used. While conventional etching processes rely on substrate rotation to even out the distribution of ions over the substrate surface, various embodiments herein achieve this purpose by moving the ion beams relative to the ion source. Movement of the ion beams can be achieved in a number of ways including electrostatic techniques, mechanical techniques, magnetic techniques, and combinations thereof. | 2016-03-03 |
20160064233 | PROCESSING SYSTEMS AND METHODS FOR HALIDE SCAVENGING - Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools. | 2016-03-03 |
20160064234 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes etching a substrate to form a plurality of first trenches and a plurality of second trenches performed at an electrostatic chuck (ESC) temperature between about 90° C. to 120° C. in the substrate, wherein each trench of the plurality of first trenches extends downward from the substrate major surface to a first height, and each trench of the plurality of second trenches extends downward from the substrate major surface to a second height greater than the first height. The method includes forming a first isolation structure in each of the plurality of first trenches. The method includes forming a second isolation structure in each of the plurality of second trenches, wherein a difference between a height of the first isolation structure and the first height equals a difference between a height of the second isolation structure and the second height. | 2016-03-03 |
20160064235 | MASK PATTERN STRUCTURES, METHODS OF FORMING HOLES USING THE SAME, AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - In a method of forming holes, a plurality of guide patterns physically spaced apart from each other is formed on an object layer. The guide pattern has a ring shape and includes a first opening therein. A self-aligned layer is formed on the object layer and the guide patterns to fill the first opening. Preliminary holes are formed by removing portions of the self-aligned layer which are self-assembled in the first opening and between the guide patterns neighboring each other. The object layer is partially etched through the preliminary holes. | 2016-03-03 |
20160064236 | METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS - A method includes forming a layer of material above a semiconductor substrate and performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above the layer of material, wherein the first and second pluralities of spacers are positioned above respective first and second regions of the semiconductor substrate and have a same initial width and a same pitch spacing. A masking layer is formed above the layer of material so as to cover the first plurality of spacers and expose the second plurality of spacers, and a first etching process is performed through the masking layer on the exposed second plurality of spacers so as to form a plurality of reduced-width spacers having a width that is less than the initial width, wherein the first plurality of spacers and the plurality of reduced-width spacers define an etch mask. | 2016-03-03 |
20160064237 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is disclosed. A substrate having a first area and a second area is provided. A target layer and a hard mask layer are sequentially formed on the substrate in the first area and in the second area. Transfer patterns are formed in a spacer form on the hard mask layer in the first area. A photoresist layer is formed directly on the hard mask layer, and covers the transfer patterns and the hard mask layer in the first area and in the second area. The photoresist layer in the first area is removed. The hard mask layer is patterned by using the transfer patterns as a mask. | 2016-03-03 |
20160064238 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a material layer on the substrate; forming a patterned first hard mask on the material layer; forming a patterned second hard mask on the material; utilizing the patterned first hard mask and the patterned second hard mask to remove part of the material layer for forming sacrificial mandrels; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; and using the sidewall spacers to remove part of the substrate. | 2016-03-03 |
20160064239 | Method for Integrated Circuit Patterning - Provided is a method of patterning a substrate. The method includes patterning a resist layer formed over the substrate to result in a resist pattern and treating the resist pattern with an ion beam. The ion beam is generated with a gas, such as CH | 2016-03-03 |
20160064240 | Method for Integrated Circuit Patterning - A method includes forming a resist over a substrate, resulting in a layer of resist scum between the resist and the substrate. The method further includes forming trenches in the resist, wherein at least a portion of the layer of resist scum remains between the trenches and the substrate. The method further includes forming a first material layer in the trenches, wherein the first material layer has a higher etch resistance than the resist in an etching process. The method further includes performing the etching process to the first material layer, the resist, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate. | 2016-03-03 |
20160064241 | Method for Planarizing Semiconductor Device - A method for planarizing a semiconductor device is provided. The method includes steps hereinafter. A substrate is provided with a first dielectric layer covering at least one electrode structure formed thereon. A chemical-mechanical polishing (CMP) process is performed on the first dielectric layer until the at least one electrode structure is exposed. A second dielectric layer is deposited covering the at least one electrode structure and the first dielectric layer. An etching-back process is performed on the second dielectric layer until the at least one electrode structure is exposed. | 2016-03-03 |
20160064242 | METHOD AND APPARATUS FOR PROCESSING WAFER-SHAPED ARTICLES - A device for processing wafer-shaped articles comprises a closed process chamber that provides a gas-tight enclosure. A rotary chuck is located within the closed process chamber. A heater is positioned relative to the chuck so as to heat a wafer shaped article held on the chuck from one side only and without contacting the wafer shaped article. The heater emits radiation having a maximum intensity in a wavelength range from 390 nm to 550 nm. At least one first liquid dispenser is positioned relative to the chuck so as to dispense a process liquid onto a side of a wafer shaped article that is opposite the side of the wafer-shaped article facing the heater. | 2016-03-03 |
20160064243 | CHEMICAL PLANARIZATION METHOD AND APPARATUS - A chemical planarization method according to an embodiment includes a step of forming a hydrophobic protective film on a film to be processed with surface asperity. A dissolving solution for dissolving the film to be processed is supplied to the surface of the protective film. A processing body with a hydrophobic surface is brought into contact with or brought closed to the protective film, and a portion of the protective film is selectively removed by hydrophobic interaction from the film to be processed. The film to be processed is dissolved by the dissolving solution after the portion of the protective film is removed. | 2016-03-03 |
20160064244 | ATOMIC LAYER ETCH PROCESS USING AN ELECTRON BEAM - Atomic layer etching using alternating passivation and etching processes is performed with an electron beam plasma source, in which the ion energy is set to a low level below the etch threshold of the material to be etched during passivation and to a higher level above the etch threshold during etching but below the etch threshold of the unpassivated material. | 2016-03-03 |
20160064245 | ETCHING METHOD - Disclosed is a method for etching a first region including a multi-layer film formed by providing silicon oxide films and silicon nitride films alternately, and a second region having a single silicon oxide film. The etching method includes: providing a processing target object including a mask provided on the first region and the second region within a processing container of a plasma processing apparatus; generating plasma of a first processing gas including a hydrofluorocarbon gas within the processing container that accommodates the processing target object; and generating plasma of a second processing gas including a fluorocarbon gas within the processing container that accommodates the processing target object. The step of generating the plasma of the first processing gas and the step of generating the plasma of the second processing gas are alternately repeated. | 2016-03-03 |
20160064246 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF PROCESSING A SUBSTRATE - A method of processing a substrate is provided. A substrate is placed on a turntable provided in a process chamber. The process chamber includes a process area for supplying an etching gas and a purge area for supplying a purge gas. The process area and the purge area are arranged along a rotational direction of the turntable and divided from each other. The etching gas is supplied into the process area. The purge gas is supplied into the purge area. The turntable rotates to cause the substrate placed on the turntable to pass through the process area and the purge area once per revolution, respectively. A film deposited on a surface of the substrate is etched when the substrate passes the process are. An etching rate of the etching or a surface roughness of the film is controlled by changing a rotational speed of the turntable. | 2016-03-03 |
20160064247 | ETCHING METHOD - A method for selectively etching a first region of silicon oxide with respect to a second region of silicon nitride includes a first step of exposing a target object having the first region and the second region to a plasma of a processing gas containing a fluorocarbon gas, etching the first region, and forming a deposit containing fluorocarbon on the first region and the second region. The method further includes a second step of etching the first region by a radical of the fluorocarbon contained in the deposit. In the first step, the plasma is generated by a high frequency power supplied in a pulsed manner. Further, the first step and the second step are repeated alternately. | 2016-03-03 |
20160064248 | DOUBLE PATTERNING METHOD - In some embodiments, the disclosure relates to a method of forming an integrated circuit device. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions. A mandrel is formed over the first mask layer and the cut regions, and the first mask layer is etched using the mandrel form a patterned first mask. The substrate is etched according to the patterned first mask and the cut regions to form trenches in the substrate, and the trenches are filled with conductive metal to form conductive lines. | 2016-03-03 |
20160064249 | LOCAL DOPING OF TWO-DIMENSIONAL MATERIALS - This disclosure provides systems, methods, and apparatus related to locally doping two-dimensional (2D) materials. In one aspect, an assembly including a substrate, a first insulator disposed on the substrate, a second insulator disposed on the first insulator, and a 2D material disposed on the second insulator is formed. A first voltage is applied between the 2D material and the substrate. With the first voltage applied between the 2D material and the substrate, a second voltage is applied between the 2D material and a probe positioned proximate the 2D material. The second voltage between the 2D material and the probe is removed. The first voltage between the 2D material and the substrate is removed. A portion of the 2D material proximate the probe when the second voltage was applied has a different electron density compared to a remainder of the 2D material. | 2016-03-03 |
20160064250 | METHODS OF FORMING METASTABLE REPLACEMENT FINS FOR A FINFET SEMICONDUCTOR DEVICE BY PERFORMING A REPLACEMENT GROWTH PROCESS - Various methods are disclosed herein for forming alternative fin materials that are in a stable or metastable condition. In one case, a metastable replacement fin is grown to a height that is greater than an unconfined stable critical thickness of the replacement fin material and it has a defect density of 10 | 2016-03-03 |
20160064251 | METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA - A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package. | 2016-03-03 |
20160064252 | ELECTRONIC MODULE HAVING AN OXIDE SURFACE FINISH AS A SOLDER MASK, AND METHOD OF MANUFACTURING ELECTRONIC MODULE USING ORGANIC SOLDERABILITY PRESERVATIVE AND OXIDE SURFACE FINISH PROCESSES - An electronic module includes a substrate, conductive pads at top and bottom surfaces of the substrate, at least one electronic component disposed on the top surface of the substrate and soldered to the pads at the top surface of the substrate, a molding compound covering the at least one electronic component, and a solder resist comprising an organo-metallic compound at regions between respective ones of the pads at the bottom surface of the substrate. The module is manufactured using both an OSP surface finishing process to coat the pads at the top surface of the substrate with OSP so as to protect the pads from oxidation while the electronic component is being connected to the substrate, and an oxide surface finish process to form the solder resist. | 2016-03-03 |
20160064253 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, which improves the mounting reliability of the semiconductor device. A plurality of leads are sandwiched and cut between an upper mold and a lower mold. There are gaps between a post (guide rail) and a bush (rail holder) which control sliding movement of the upper mold. After the leads are sandwiched between the upper mold and the lower mold and before they are cut, the positional relation between the lower mold supporting the leads and the upper mold in contact with the lower surfaces of the leads is adjusted. | 2016-03-03 |
20160064254 | HIGH DENSITY IC PACKAGE - The present invention discloses a high density IC package with a core substrate. The core substrate has four lateral sides; each lateral side extends to and flushes with a corresponding lateral side of the package. Further, a bottom first redistribution circuit following IC design rule or TFTLCD design rule is fabricated on a bottom side of the core substrate, and a bottom second redistribution circuit following PCB design rule is fabricated on a bottom side of the first redistribution circuit. | 2016-03-03 |
20160064255 | METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A method for manufacturing a chip arrangement, including disposing a chip over a carrier, wherein the bottom side of the chip is electrically connected to the first carrier side via one or more contact pads on the chip bottom side, disposing a first encapsulation material over the first carrier side, wherein the first encapsulation material at least partially surrounds the chip, and disposing a second encapsulation material over a second carrier side, wherein the second encapsulation material is in direct contact with the second carrier side. | 2016-03-03 |
20160064256 | SUBSTRATE LIQUID PROCESSING APPARATUS - A substrate liquid processing apparatus includes a cup | 2016-03-03 |
20160064257 | SUBSTRATE LIQUID PROCESSING METHOD AND SUBSTRATE LIQUID PROCESSING APPARATUS - Disclosed is a substrate liquid processing method. The method includes producing a processing liquid including deionized water, carbon dioxide, and ammonia, which has a PH of a predetermined value in a range of pH 5 to 9; and processing a substrate having a metal exposed, using the processing liquid. | 2016-03-03 |
20160064258 | Adapter Tool and Wafer Handling System - An adapter tool that is configured to be attached to a loadport of a wafer handling system includes a support member, and first and second guiding elements supported by the support member. The first and second guiding elements are arranged for placing a first wafer magazine and a second wafer magazine, respectively. The adapter tool further includes a housing supported by the support member that is configured to house the first and the second wafer magazines, respectively, and first and second openings in the housing, respectively. The first and second openings are aligned with the first and second guiding elements. | 2016-03-03 |
20160064259 | SUBSTRATE LIQUID PROCESSING APPARATUS - A substrate liquid processing apparatus includes a substrate holding device which holds a substrate in horizontal position and rotate the substrate around vertical axis of the substrate, a liquid discharge device which is positioned underneath central portion of lower surface of the substrate in the horizontal position and discharges processing liquid toward the lower surface of the substrate, and a gas discharge passage structure which has a gas discharge passage formed around the discharge device such that drying gas passes through. The discharge device has a head including a cover which is extending beyond upper end of the passage such that the cover is covering the upper end of the passage, a liquid discharge port which is protruding from the cover toward the substrate in the horizontal position, and a curved portion which is formed between the port and cover such that the curved portion has a surface bending downward. | 2016-03-03 |
20160064260 | ION INJECTOR AND LENS SYSTEM FOR ION BEAM MILLING - The embodiments herein relate to methods and apparatus for performing ion etching on a semiconductor substrate, as well as methods for forming such apparatus. In some embodiments, an electrode assembly may be fabricated, the electrode assembly including a plurality of electrodes having different purposes, with each electrode secured to the next in a mechanically stable manner. Apertures may be formed in each electrode after the electrodes are secured together, thereby ensuring that the apertures are well-aligned between neighboring electrodes. In some cases, the electrodes are made from degeneratively doped silicon, and the electrode assembly is secured together through electrostatic bonding. Other electrode materials and methods of securing may also be used. The electrode assembly may include a hollow cathode emitter electrode in some cases, which may have a frustoconical or other non-cylindrical aperture shape. A chamber liner and/or reflector may also be present in some cases. | 2016-03-03 |
20160064261 | DISPATCHING METHOD AND SYSTEM - A method of dispatching wafer lots through a plurality of process chambers, wherein the process chambers are disposed in at least one machine. The method includes: receiving wafer lot information and process chamber data, wherein the wafer lot information identifies the wafer lots to be processed at the machine, and the process chamber data includes process information associated with the process chambers; determining a load factor of each process chamber based on the wafer lot information and process chamber data; receiving historical data of run lots previously processed through the process chambers, and determining a processing time of the wafer lots based on the historical data; generating a dispatching criteria for the wafer lots based on the load factors of the process chambers and the determined processing time of the wafer lots; and dispatching the wafer lots through the process chambers based on the dispatching criteria. | 2016-03-03 |
20160064262 | SEMICONDUCTOR MANUFACTURING APPARATUS, SEMICONDUCTOR MANUFACTURING SYSTEM, AND SEMICONDUCTOR MANUFACTURING METHOD - The semiconductor manufacturing apparatus includes a film forming part and a control part. The film forming part forms a stacked film on a semiconductor substrate. The stacked film has a lower layer and an upper layer on the lower layer. The control part controls the film forming part. The control part controls the film forming part to form the upper layer film in which an inclination of a film thickness is inverted with respect to that of the lower layer film. | 2016-03-03 |
20160064263 | Low Variability Robot - An apparatus including a frame, a first position sensor, a drive and a chamber. The frame has at least three members including at least two links forming a movable arm and an end effector. The end effector and the links are connected by movable joints. The end effector is configured to support a substrate thereon. The first position sensor is on the frame proximate a first one of the joints. The first position sensor is configured to sense a position of two of the members relative to each other. The drive is connected to the frame. The drive is configured to move the movable arm. The frame is located in the chamber, and the drive extends through a wall in the chamber. | 2016-03-03 |
20160064264 | HIGH TEMPERATURE ELECTROSTATIC CHUCKING WITH DIELECTRIC CONSTANT ENGINEERED IN-SITU CHARGE TRAP MATERIALS - Techniques are disclosed for methods and apparatuses for increasing the breakdown voltage while substantially reducing the voltage leakage of an electrostatic chuck at temperatures exceeding about 300 degrees Celsius in a processing chamber. | 2016-03-03 |
20160064265 | TEMPORARILY BONDING SUPPORT SUBSTRATE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, there is provided a temporarily bonding support substrate including an underlayer and a heat generable layer. A device substrate is to be temporarily bonded to the heat generable layer on an opposite side of the underlayer. | 2016-03-03 |
20160064266 | PROCESSING APPARATUS, PROCESSING METHOD, AND DEVICE MANUFACTURING METHOD - A processing apparatus that performs processing to a wafer is provided, the processing apparatus comprising a wafer chuck disposed on a stage and that holds the wafer; three pins that attract the wafer and move the wafer from the wafer chuck; and a control unit that is configured to stop or decrease the attraction of the three pins based on information about a through hole of the wafer when the wafer is moved from the wafer chuck by the three pins. | 2016-03-03 |
20160064267 | SEALING STRUCTURE FOR WORKPIECE TO SUBSTRATE BONDING IN A PROCESSING CHAMBER - A sealing structure is between a workpiece or substrate and a carrier for plasma processing. In one example, a substrate carrier has a top surface for holding a substrate, the top surface having a perimeter and a resilient sealing ridge on the perimeter of the top surface to contact the substrate when the substrate is being carried on the carrier. | 2016-03-03 |
20160064268 | Wafer Susceptor with Improved Thermal Characteristics - A substrate-retaining device with improved thermal uniformity is provided. In an exemplary embodiment, the substrate-retaining device includes a substantially circular first surface with a defined perimeter, a plurality of contact regions disposed at the perimeter, and a plurality of noncontact regions also disposed at the perimeter. The contact regions are interspersed with the noncontact regions. Within each of the noncontact regions, the first surface extends past where the first surface ends within each of the contact regions. In some such embodiments, each region of the plurality of contact regions includes a contact surface disposed above the first surface. | 2016-03-03 |
20160064269 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to an embodiment includes a first wire and a second wire, a bottom nitride film, a side nitride film, and a top layer. The first and second wires are arranged on a base layer. The bottom nitride film is arranged on the base layer between the first and second wires. The side nitride film is respectively arranged on side surfaces of the first and second wires. The top layer is arranged on the first and second wires. An air gap exists between the first and second wires. The air gap is enclosed by the bottom nitride film, the side nitride film, and the top layer in a cross section orthogonal to an extending direction of the wires. | 2016-03-03 |
20160064270 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING AIR GAP SPACERS - A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal suicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described. | 2016-03-03 |
20160064271 | Inverted Trapezoidal Recess for Epitaxial Growth - A semiconductor device having an epitaxial layer a method of manufacture thereof is provided. The semiconductor device has a substrate with a trench formed therein and a recess formed below the trench. The recess has sidewalls with a (111) crystal orientation. The depth of the trench is such that the depth is greater than or equal to one-half a length of sidewalls of the recess. An epitaxial layer is formed in the recess and the trench. The depth of the trench is sufficient to cause dislocations formed between the interface of the semiconductor substrate and the epitaxial layer to terminate along sidewalls of the trench. | 2016-03-03 |
20160064272 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an embodiment, a method for manufacturing a semiconductor device includes transferring a continuous second layer, forming a third layer, and removing the second layer. The second layer is transferred onto a first layer. The first layer has a first opening. The second layer covers the first opening to form a first air gap. The third layer is formed on the first layer. The third layer has a second opening. The second opening is positioned on the first air gap. The second layer is removed through the second opening. | 2016-03-03 |
20160064273 | Method for Producing a Conductor Line - A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed. | 2016-03-03 |
20160064274 | STRUCTURE AND FORMATION METHOD OF DUAL DAMASCENE STRUCTURE - A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate and a via hole in the dielectric layer. The via hole has an oval cross section. The semiconductor device structure further includes a trench in the dielectric layer, and the via hole extends from a bottom portion of the trench. The trench has a trench width wider than a hole width of the via hole. In addition, the semiconductor device structure includes one or more conductive materials filling the via hole and the trench and electrically connected to the conductive feature. | 2016-03-03 |
20160064275 | Selective Deposition With Alcohol Selective Reduction And Protection - Methods of selectively depositing a metal selectively onto a metal surface relative to a dielectric surface. Methods include reducing a metal oxide surface to a metal surface and protecting a dielectric surface to minimize deposition thereon. | 2016-03-03 |
20160064276 | Word Line with Multi-Layer Cap Structure - Word lines are formed from a stack of layers that includes a metal (e.g. tungsten) layer with an overlying multi-layer cap structure. The multi-layer cap structure includes a layer with a low etch rate to protect metal from damage during anisotropic etching. The multi-layer cap structure includes a layer with stress (e.g. tensile) that is opposite to the stress of the metal (e.g. compressive) to provide low combined stress. | 2016-03-03 |
20160064277 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING NANOWIRES - Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes. | 2016-03-03 |
20160064278 | ELECTRIC CONNECTION ELEMENT MANUFACTURING METHOD - A surface of a silicon substrate is coated with a silicon oxide layer. A manganese silicate layer is then deposited on the silicon oxide layer using a process of performing at least one step of dipping the substrate into a manganese amidinate solution. A copper layer is then deposited on the manganese silicate layer using a process of performing a step of dipping the substrate into a copper amidinate solution. An anneal is performed to stabilize one or both of the manganese silicate layer and copper layer. | 2016-03-03 |
20160064279 | SEMICONDUCTOR DEVICE HAVING STABLE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked; semiconductor patterns configured to pass through the stacked structure; and contact plugs electrically coupled to the conductive layers, respectively, wherein each of the conductive layers includes a first region which has a first thickness, and a second region electrically coupled to the first region and a second thickness greater than the first thickness, and a second region of a lower conductive layer located under a second region of an upper conductive layer. | 2016-03-03 |
20160064280 | METHOD FOR FORMING THREE-DIMENSIONAL INTERCONNECTION, CIRCUIT ARRANGEMENT COMPRISING THREE-DIMENSIONAL INTERCONNECTION, AND METAL FILM-FORMING COMPOSITION FOR THREE-DIMENSIONAL INTERCONNECTION - In a method for forming a three-dimensional interconnection, a contact plug is formed within a through hole provided in a substrate and an upper wire formed on an upper side of the substrate and a lower wire formed on a lower side are electrically connected to one another by the contact plug. A coating film is formed on an upper surface of the substrate and inner surface of the through hole by applying a metal film-forming composition containing at least one salt of and a particle of a metal to the substrate provided with the through hole. A metal film is formed by heating the coating film, and plated by filling up the through hole by depositing a conductor on the metal film by a plating process using the metal film as a seed layer. An excess conductor deposited in the plating is removed by a chemical mechanical polishing process. | 2016-03-03 |
20160064281 | MULTIHEIGHT CONTACT VIA STRUCTURES FOR A MULTILEVEL INTERCONNECT STRUCTURE - Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner. | 2016-03-03 |
20160064282 | METHOD FOR INSULATING SINGULATED ELECTRONIC DIE AND STRUCTURE - In one embodiment, a method of forming an electronic device includes providing a wafer having plurality of die separated by spaces. The method includes plasma singulating the wafer through the spaces to form singulation lines that expose side surfaces of the plurality of die. The method includes forming an insulating layer on the exposed side surfaces. In one embodiment, the steps of singulating and forming the insulating layer are carried out with the wafer mounted to a carrier substrate that supports the wafer and singulated die during both steps. | 2016-03-03 |
20160064283 | Method And Device For The Production Of Wafers With A Pre-Defined Break Initiation Point - The present invention relates to a method for the production of layers of solid material ( | 2016-03-03 |
20160064284 | METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE - Method for fabricating a semiconductor structure. The method includes: providing a crystalline silicon substrate; defining an opening in a dielectric layer on the crystalline silicon substrate, the opening having sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; providing a confinement structure above the dielectric layer, thereby forming a confinement region between the confinement structure and the dielectric layer; and growing a crystalline compound semiconductor material in the confinement region thereby at least partially filling the confinement region. The present invention also provides an improved compound semiconductor structure and a device for fabricating such semiconductor structure. | 2016-03-03 |
20160064285 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - On a peripheral circuit area upon a semiconductor substrate, an NMOS gate stack, comprising a first high-dielectric film, an NMOS gate metal, and a first semiconductor film, is formed, and a PMOS gate stack, comprising a second high-dielectric film, a PMOS gate metal, and a second semiconductor film, is formed so that a predetermined step is formed between the NMOS gate stack and the PMOS gate stack. A third semiconductor film is formed over the entire surface of the semiconductor substrate so as to fill in the step. The third semiconductor film is planarized by way of CMP so as to form a fourth semiconductor film that is thinner than the third semiconductor film. | 2016-03-03 |
20160064286 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS - Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit is provided. The method includes providing a semiconductor substrate with a first gate structure and a second gate structure and a shallow trench isolation region outside of the first and second gate structures, depositing a mask on the first gate structure, and depositing a protection layer on the shallow trench isolation region to embed a STI protective cap. | 2016-03-03 |
20160064287 | FORMATION OF NICKEL SILICON AND NICKEL GERMANIUM STRUCTURE AT STAGGERED TIMES - A method includes providing a first source/drain contact, providing a second source/drain contact, and surrounding the first and second source/drain contacts with a dielectric material layer. The providing a first source/drain contact and the providing a second source/drain contact are performed one after the other. | 2016-03-03 |
20160064288 | DUAL CHANNEL MATERIAL FOR finFET FOR HIGH PERFORMANCE CMOS - Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and pFET device regions are then recessed. A relaxed silicon germanium alloy fin portion is formed on a topmost surface of each recessed silicon fin portion or on exposed surface of the substrate. A compressively strained silicon germanium alloy fin portion is formed on each relaxed silicon germanium alloy fin portion within the pFET device region, and a strained silicon-containing fin portion is formed on each relaxed silicon germanium alloy fin portion within the nFET device region. Sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion are then exposed. A functional gate structure is provided on the exposed sidewall surfaces of each compressively strained silicon-containing germanium alloy fin portion and each tensile strained silicon-containing fin portion. | 2016-03-03 |
20160064289 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF - A method for forming a semiconductor structure includes sequentially providing a semiconductor substrate having NFET regions and NFET regions; forming an insulation layer on the semiconductor substrate; forming a sacrificial layer on the insulation layer; forming first trenches in the PFET regions, and second trenches in in the NFET regions; forming a third trench on the bottom of each of the first trenches and the second trenches; forming a first buffer layer in each of the first trenches and the second trenches by filling the third trenches; forming a first semiconductor layer on each of the first buffer layers in the first trenches and the second teaches; removing the first semiconductor layers in the second trenches; forming a second buffer layer with a top surface lower than the insolation layer in each of second trenches; and forming a second semiconductor layer on each of the second buffer layers. | 2016-03-03 |
20160064290 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF - A method for forming a semiconductor structure is provided. The method includes providing a substrate having a first region and a second region; and forming at least one first trench in the first region of the substrate, and at least one second trench in second region of the substrate. The method also includes forming a first liner layer on side and bottom surfaces of the first trench, and the side and bottom surfaces of the second trench; and performing a rapid thermal oxy-nitridation process on the first liner layer to release a tensile stress between the first liner layer and the substrate. Further, the method includes removing a portion of the first liner layer in the first region to expose the first trench; and forming a second liner layer on the side and bottom surface of the first trench. | 2016-03-03 |
20160064291 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ | 2016-03-03 |
20160064292 | METHOD OF MEASURING BREAKDOWN VOLTAGE OF SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT - A method of measuring a breakdown voltage of a semiconductor element includes the steps below. A wafer provided with a plurality of semiconductor elements each having an electrode is prepared. The wafer is divided into a plurality of chips provided with at least one semiconductor element. After the step of division into the plurality of chips, a breakdown voltage of the semiconductor element is measured while a probe is in contact with the electrode of the semiconductor element in an insulating liquid. | 2016-03-03 |
20160064293 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - Forming a semiconductor arrangement includes non-destructively determining a first spacer height of a first sidewall spacer adjacent a dummy gate and a second spacer height of a second sidewall spacer adjacent the dummy gate based upon a height of a photoresist as measured using optical critical dimension (OCD) spectroscopy. When the photoresist is sufficiently uniform, a hard mask etch is performed to remove a hard mask from the dummy gate and to remove portions of sidewall spacers of the dummy gate. A gate electrode is formed between the first sidewall spacer and the second sidewall spacer to form a substantially uniform gate. Controlling gate formation based upon photoresist height as measured by OCD spectroscopy provides a non-destructive manner of promoting uniformity. | 2016-03-03 |
20160064294 | SEMICONDUCTOR MANUFACTURING FOR FORMING BOND PADS AND SEAL RINGS - An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers. | 2016-03-03 |
20160064295 | TEST KEY ARRAY - The present invention provides a test key array including a lower conductive pattern, and the lower conductive pattern includes a plurality of first L-shaped traces parallel to each other, an upper conductive pattern, where the upper conductive pattern includes a plurality of second L-shaped traces parallel to each other, the lower conductive pattern crosses to the upper conductive pattern, and a plurality of cross regions are defined between the lower conductive pattern and the upper conductive pattern, and a plurality of conductive plugs, disposed on parts of the cross regions, electrically connecting to the lower conductive pattern and the upper conductive pattern. | 2016-03-03 |
20160064296 | MARKER PATTERN FOR ENHANCED FAILURE ANALYSIS RESOLUTION - A marker pattern for enhancing resolution of a defect location along an axis in semiconductor defect analysis, and in particular, a marker pattern providing greater resolution in locating bit line defects using thermal laser stimulation methods such as OBIRCH. In an example, the marker pattern may consist of large markers, each having a set of associated small markers. Each of the small markers may be offset along an axis from each other. By identifying the small marker and its associated large marker which align with the defect, the bit line containing the defect may be more easily identified. | 2016-03-03 |
20160064297 | UNDER-FILL MATERIAL, SEALING SHEET, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - Provided are an under-fill material which is capable of reducing a difference in thermal response behavior between a semiconductor element and an adherend and which makes it easy and convenient to perform alignment for mounting the semiconductor element, a sealing sheet including the under-fill material, and a method for producing a semiconductor device using the under-fill material. In the under-fill material of the present invention, a haze is 70% or less before a heat curing treatment, and a storage elastic modulus E′ [MPa] and a thermal expansion coefficient α [ppm/K] after the under-fill material is subjected to a heat curing treatment at 175° C. for 1 hour satisfy the following formula (1) at 25° C.: 100002016-03-03 | |
20160064298 | Embedding additive particles in encapsulant of electronic device - An electronic device comprising a carrier having a mounting surface, at least one electronic chip mounted on the mounting surface, an encapsulant at least partially encapsulating the carrier and the at least one electronic chip, and a plurality of capsules in the encapsulant, wherein the capsules comprise a core comprising an additive and comprise a shell, in particular a crackable shell, enclosing the core. | 2016-03-03 |
20160064299 | STRUCTURE AND METHOD TO MINIMIZE WARPAGE OF PACKAGED SEMICONDUCTOR DEVICES - A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns. | 2016-03-03 |
20160064300 | FAN-OUT WAFER LEVEL PACKAGE - A fan-out wafer level package is provided. The fan-out wafer level package includes a semiconductor element, a molding compound, a first fan-out structure, a conductive heat spreader, and a plurality of solder balls. The semiconductor element includes a plurality of bonding pads. The molding compound covers the semiconductor element. The first fan-out structure is formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads. The conductive heat spreader is formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material. The solder balls are formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material. | 2016-03-03 |
20160064301 | SEMICONDUCTOR DEVICE - One semiconductor device includes a wiring board, a semiconductor chip, and an encapsulation body. The wiring board includes an insulating base, a conductive pattern that is formed on one surface of the insulating base, and a heat dissipation via that is connected to the conductive pattern. The heat dissipation via is provided so as to penetrate through the insulating base from one surface to the other surface, while being exposed from the lateral side of the insulating base. The semiconductor chip is mounted on the wiring board so as to overlap the conductive pattern. The encapsulation body is formed on the wiring board so as to cover the semiconductor chip. | 2016-03-03 |
20160064302 | SEMICONDUCTOR MODULE - A semiconductor module uses pin bonding and improves cooling capacity. The semiconductor module includes a semiconductor element; a pin electrically and thermally connected to an upper surface of the semiconductor element; a pin wiring substrate having a first metal film and a second metal film respectively provided on the rear and front surfaces of a pin wiring insulating substrate, the first metal film being bonded to the pin; a first DCB substrate having a third metal film and a fourth metal film respectively provided on the rear and front surfaces of a first ceramic insulating substrate, the third metal film being bonded to a lower surface of the semiconductor element; a first cooler thermally connected to the fourth metal film; and a second cooler that thermally connected to the second metal film. | 2016-03-03 |
20160064303 | COOLING APPARATUS FOR A HEAT-GENERATING ELEMENT - A cooling apparatus for a heat-generating element includes: a heat sink on which the heat-generating element is mounted; a cooling component having a recess, the cooling component and the heat sink being faced and joined to each other so that the recess forms a coolant passage; and a sealing member provided between the heat sink and the cooling component so as to seal the coolant passage and separate an interior and exterior of the coolant passage. A first distance is longer than a second distance with regard to a distance between facing surfaces of the heat sink and the cooling component near the sealing member, the first distance being between the facing surfaces at an interior side of the coolant passage separated by the sealing member, and the second distance is a distance between the facing surfaces at an exterior side of the coolant passage separated by the sealing member. | 2016-03-03 |
20160064304 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a stacked unit having a semiconductor module, a first cooler having a first opening and a first coolant flow path that is connected to the first opening, and a second cooler that has a second opening and a second coolant flow path that is connected to the second opening, and being formed by the first cooler and the second cooler sandwiching the semiconductor module and being stacked such that the first opening and the second opening face each other; a seal member that is arranged between the first opening and the second opening that are adjacent in a stacking direction, and that connect the first opening and the second opening; and a winding member that keeps pressure applied to the stacked unit in the stacking direction by being wound around the stacked unit. | 2016-03-03 |
20160064305 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a stacked unit including a semiconductor module and a plurality of coolers each having a flow passage through which a coolant flows, the semiconductor module being disposed between the coolers; a coolant supply-discharge pipe configured to supply the coolant to the coolers or discharge the coolant from the coolers, the coolant supply-discharge pipe being passed through the stacked unit in a stacking direction of the stacked unit; a displacement restricting member provided at a first end portion of the coolant supply-discharge pipe, the displacement restricting member being configured to restrict displacement of the stacked unit in the stacking direction of the stacked unit; and a pressurizing member provided at a second end portion of the coolant supply-discharge pipe, the pressurizing member being configured to apply force to the stacked unit in a direction toward the first end portion. | 2016-03-03 |
20160064306 | LIQUID COOLED COMPLIANT HEAT SINK AND RELATED METHOD - A heat sink and method for using the same for use in cooling an integrated circuit (IC) chip is provided herein. The heat sink includes a manifold block, a liquid-filled cooling system, and a compliant foil affixed to the manifold block and backed by a liquid in the closed loop cooling system. The pressure provided by the liquid behind the foil causes the foil to bow, and to conform to non-planarities in the surface of the IC chip, thus reducing air gaps and increasing thermal coupling between the IC chip and the heat sink. | 2016-03-03 |
20160064307 | LIQUID COOLING OF SEMICONDUCTOR CHIPS UTILIZING SMALL SCALE STRUCTURES - A semiconductor assembly for use with forced liquid and gas cooling. A relatively rigid nano-structure (for example, array of elongated nanowires) extends from an interior surface of a cap toward a top surface of a semiconductor chip, but, because of the rigidness and structural integrity of the nano-structure built into the cap, and of the cap itself, the nano-structure is reliably spaced apart from the top surface of the chip, which helps allow for appropriate cooling fluid flows. The cap piece and nano-structures built into the cap may be made of silicon or silicon compounds. | 2016-03-03 |
20160064308 | SEMICONDUCTOR MODULE - A semiconductor module includes first and second semiconductor elements connected to pins, respectively; a first pin wiring substrate having first and second metal films bonded to the pin on the upper and lower surfaces; a first DCB substrate having third and fourth metal films on the upper and lower surfaces, the third metal film being bonded to the lower surface of the first semiconductor element; a second DCB substrate having fifth and sixth metal films respectively provided on the lower and upper surfaces, the fifth metal film being bonded to the upper surface of the second semiconductor element; a second pin wiring substrate having seventh and eighth metal films bonded to the pin, on the upper and lower surfaces; a connection member connected to the second and fifth metal films; a first cooler connected to the fourth metal film; and a second cooler connected to the sixth metal film. | 2016-03-03 |
20160064309 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a chip having a plurality of joint pads; a component having a plurality of metal caps on one side and having a grinded surface on the other side, wherein the metal caps are in contact with the joint pads of the chip. | 2016-03-03 |
20160064310 | SEMICONDUCTOR PACKAGE HAVING ROUTING TRACES THEREIN - A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package. | 2016-03-03 |
20160064311 | LEAD FRAME CONSTRUCT FOR LEAD-FREE SOLDER CONNECTIONS - An electronics packaging arrangement, a lead frame construct for use in an electronics packaging arrangement, and a method for manufacturing an electronics packaging arrangement. A lead frame made of copper, for example, includes a metallic barrier layer of nickel, for example, to prevent oxidation of the metal of the lead frame. A relatively thin wetting promoting layer of copper, for example, is provided on the metallic barrier layer to promote uniform wetting of a solder, such as a lead-free, zinc-based solder, onto the lead frame during a die connect process by which a chip is connected to the lead frame. A copper/zinc intermetallic layer is formed during the flow and solidification of the solder. Substantially all of the copper in the copper layer is consumed during formation of the copper/zinc intermetallic layer, and the intermetallic layer is sufficiently thin to resist internal cracking failure during manufacture and subsequent use of the electronics packaging arrangement. | 2016-03-03 |
20160064312 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device that can achieve downsizing of the semiconductor device. Convex portions are pressed against side surfaces other than one side surface of one chip mounting portion, thereby fixing the chip mounting portion without forming a convex portion corresponding to the one side surface of the chip mounting portion. Likewise, convex portions are pressed against side surfaces other than one side surface of the other chip mounting portion, thereby fixing the other chip mounting portion without forming a convex portion corresponding to the one side surface of the other chip mounting portion. | 2016-03-03 |
20160064313 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - A electronic multi-output device having a substrate including a pad and pins. A composite first chip has a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface. Patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. The second terminals are connected by discrete first and second metal clips to respective substrate pins. A composite second chip has a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to be vertically attached with its first terminals to the first and second clips, respectively. The third terminals are connected by discrete clips to respective substrate pins. The common second terminal is connected by a common clip to a substrate pin. | 2016-03-03 |
20160064314 | INTERPOSER STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure relates to an interposer structure and a manufacturing method thereof. The interposer structure includes a first dielectric layer, a conductive pad, and a bump. The conductive pad is disposed in the first dielectric layer, wherein a top surface of the conductive pad is exposed from a first surface of the first dielectric layer, the conductive pad further includes a plurality of connection feet, and the connection feet protrude from a bottom surface of the conductive pad to a second surface of the first dielectric layer. The bump is disposed on the second surface of the first dielectric layer, and the bump directly contacts to the connection feet. Through the aforementioned interposer structure, it is sufficient to achieve the purpose of improving the electrical performance of the semiconductor device and avoiding the signal being loss through the TSV. | 2016-03-03 |
20160064315 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar, wherein the conductive trace comprises a width W | 2016-03-03 |
20160064316 | PACKAGE SUBSTRATE WITH IMPROVED RELIABILITY - A packaged semiconductor device having a package substrate that includes a plurality of electrical contacts on a first major surface and a die positioned on a second major surface. Each of the plurality of electrical contacts includes a perimeter portion. A first subset of the electrical contacts have more than fifty percent of the perimeter portion bounded by a solder mask. A second subset of the electrical contacts have less than fifty percent of the perimeter portion bounded by a solder mask. The die is positioned over only the first subset of the electrical contacts. | 2016-03-03 |
20160064317 | INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above. | 2016-03-03 |
20160064318 | PACKAGE SUBSTRATE AND METHOD FOR MANUFACTURING PACKAGE SUBSTRATE - A package substrate includes an outermost interlayer, an outermost conductive layer including first pads positioned to mount at electronic component and second pads positioned to mount another electronic component, a first conductive layer including first circuits and formed such that the outermost interlayer is on the first conductive layer and that the first circuits are connecting the first and second pads, an inner interlayer formed such that the first conductive layer is on the inner interlayer, a second conductive layer formed such that the inner interlayer is on the second conductive layer, via conductors penetrating through the outermost interlayer and including first via conductors connecting the first conductive layer and the first pads and second via conductors connecting the first conductive layer and the second pads, and third via conductors penetrating through the inner interlayer and positioned such that the first and third via conductors form stacked via conductors. | 2016-03-03 |
20160064319 | WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE - A wiring substrate includes an insulating layer, a wiring layer, a via wiring, and a solder resist layer. The wiring layer includes a pad body that constitutes a part of a pad and a wiring pattern including an upper surface. The pad includes the pad body, a first metal layer formed on an upper surface of the pad body and including an embedded part embedded in the insulating layer and a projecting part including upper and side surfaces and projecting from the upper surface of the insulating layer, and a second metal layer including an upper surface and covering the upper and side surfaces of the projecting part. The upper surface of the pad body and the upper surface of the wiring pattern are on the same plane. The upper surface of the second metal layer is positioned lower than the upper surface of the solder resist layer. | 2016-03-03 |
20160064320 | COUPLING OF AN INTERPOSER TO A PACKAGE SUBSTRATE - An integrated circuit chip stack and a method for forming the same in which bond pads of an interposer are directly bonded to bond pads of a package substrate using only pre-solder. The interposer can have a bond pad pitch of less than 150 micrometers. The interposer can be an organic interposer. The pro-solder can be melted to make contact with the bond pads of the package substrate and the interposer. After solidifying, the pre-solder can form an electrical connection between a bond pad of the interposer and a bond pad of the package substrate. | 2016-03-03 |
20160064321 | METHOD AND STRUCTURE TO REDUCE THE ELECTRIC FIELD IN SEMICONDUCTOR WIRING INTERCONNECTS - Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines. | 2016-03-03 |
20160064322 | DESIGNED-BASED INTERCONNECT STRUCTURE IN SEMICONDUCTOR STRUCTURE - Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation: | 2016-03-03 |
20160064323 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer. | 2016-03-03 |
20160064324 | SEMICONDUCTOR PACKAGE WITH EMBEDDED CAPACITOR AND METHODS OF MANUFACTURING SAME - A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor. | 2016-03-03 |
20160064325 | SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR - In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors. | 2016-03-03 |
20160064326 | MODULAR FUSES AND ANTIFUSES FOR INTEGRATED CIRCUITS - Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers. | 2016-03-03 |
20160064327 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask. | 2016-03-03 |