09th week of 2011 patent applcation highlights part 39 |
Patent application number | Title | Published |
20110051472 | METHOD AND SYSTEM FOR EFFICIENT POWER CONTROL WITH MULTIPLE MODES - Method and system for efficient power control with multiple modes. According to an embodiment, the present invention provides a power system with selectable power modes. The power system includes a first terminal for outputting energy, and the first terminal is electrically coupled to a load. The system also includes a pulse-frequency modulation (PFM) component that is configured to adjust a pulse frequency based on the load. The system additionally includes a pulse-width modulation (PWM) component that is configured to adjust a pulse width based on the load. The system further includes a switch that is electrically coupled to the first terminal. Also, the system includes a control component, the control component being configured to provide a control signal that is capable of causing the switch to be turned on or off. The control signal is associated with an output of the PWM component and the pulse width if an output is greater than a predetermined value. The control signal is associated with an output of the PFM component and the pulse frequency if an output is lower than a predetermined value. | 2011-03-03 |
20110051473 | SWITCHING INVERTERS AND CONVERTERS FOR POWER CONVERSION - A switching inverter having two single-ended EF | 2011-03-03 |
20110051474 | RESONANT POWER CONVERSION APPARATUS - A resonant power conversion apparatus includes a transformer T | 2011-03-03 |
20110051475 | REGULATOR CIRCUITRY FOR REDUCING RIPPLE RESULTED FROM LINE VOLTAGE TRANSMITTING TO SECONDARY SIDE OF POWER TRANSFORMER - The present invention discloses a regular circuitry for reducing ripple resulting from a line voltage transmitting to a secondary side of a power transformer. The regular circuitry electrically connected in parallel with the power transformer includes a ripple sampling circuit, a proportional amplifier circuit, and a reversing amplifier circuit. The ripple sampling circuit selects a sampling ripple from the input port of the power transformer, which is electrically connected in series between a primary side rectification circuit and a secondary side rectification circuit. The proportional amplifier circuit receives the sampling ripple to generate an amplified sampling ripple. The amplified sampling ripple transmits to the reversing amplifier circuit so that a reversed sampling ripple is generated. Thus, the reversed sampling ripple can be input to the output port of the power transformer to superimpose on the signal output from the power transformer to reduce the ripple resulting from the line voltage. | 2011-03-03 |
20110051476 | ENVIRONMENTALLY FRIENDLY POWER SUPPLY - A power supply for converting AC to a regulated DC output current, utilizing two serial switched mode power supplies, the first providing an intermediate DC output voltage with only moderate ripple properties, this output being input to the second, which operates as a DC/DC converter to provide the desired output with low ripple and good regulation. The diode rectifier assembly has no reservoir/smoothing capacitor, or one of much smaller capacitance than in prior art power supplies. The large resulting rectifier output ripple is overcome by use of the two power supply units, at least the first having a smoothing capacitor at its output. A majority of the energy stored in this capacitor is utilized during each AC half cycle. Such power supplies also provide improved hold-up times. The power supply is also constructed to have low standby power consumption, by use of a double burst configuration. | 2011-03-03 |
20110051477 | Front-end circuit of power converter - A front-end circuit of a power converter has a power connection wiring detecting circuit, a power switch and a control unit. The power connection wiring detecting circuit is connected to an AC power. The control unit is connected to the power connection wiring detecting circuit. The power switch is connected to the power loop. The control unit turns on or off the AC power loop through the power switch. When the power connection wiring is correctly connected with the AC power, the control unit turns on the power switch and the front-end circuit outputs the AC power to the back-end circuit. When the power connection wiring is incorrectly connected with the AC power, the control unit turns off the power switch and the AC power is not outputted to the back-end circuit. | 2011-03-03 |
20110051478 | POWER CONVERSION DEVICE - A three-level PWM converter ( | 2011-03-03 |
20110051479 | Systems and Methods for Controlling Phases of Multiphase Voltage Regulators - A multi-phase voltage regulator is disclosed. The multi-phase voltage regulator includes a voltage regulator controller. Phase output stages are coupled to the voltage regulator controller. The voltage regulator controller and the phase output stages are configured to provide regulated voltages at one or more output nodes. The voltage regulator controller is configured to monitor one or more conditions of the phase output stages and to control one or more of the phase output stages based, at least in part, on the one or more conditions. | 2011-03-03 |
20110051480 | 20 PHASE-SHIFTING AUTOTRANSFORMER - The invention relates to autotransformers used notably for converting alternating (AC) electric power into direct (DC) power. And more precisely, to autotransformers designed to be connected to a three-phase voltage supply of given amplitude supplying three first output voltages (C | 2011-03-03 |
20110051481 | FREQUENCY CONVERTER - The present invention provides a frequency converter including a frequency conversion device capable of accommodating a Si-series MMIC and also a GaAs-series MMIC by using a magneto-resistance element. A frequency converter according to an embodiment of the present invention includes: a frequency conversion device having a magneto-resistance element with a magnetization free layer, an intermediate layer, and a magnetization pinned layer; a magnetic field application mechanism for applying a magnetic field to the frequency conversion device; a local oscillator for applying a local oscillation signal to the frequency conversion device; and an input terminal electrically connected to the above frequency conversion device for receiving an external input signal. Further, the local oscillator includes a magneto-resistance element capable of generating the local oscillation signal by outputting an AC voltage according to a resistance change thereof. | 2011-03-03 |
20110051482 | CONTENT ADDRESSABLE MEMORY ARRAY PROGRAMMED TO PERFORM LOGIC OPERATIONS - A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed. | 2011-03-03 |
20110051483 | CONTENT ADDRESSABLE MEMORY ARRAY - A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of a logical combination of at least two different inputs. | 2011-03-03 |
20110051484 | LOW ACTIVE POWER CONTENT ADDRESSABLE MEMORY - A dynamic, content addressable memory (CAM) cell includes a match line, a write line, a first pair of complementary bit lines for read and search operations, and a second pair of complementary bit lines for write operations; a first storage transistor connected between one of the first pair of complementary bit lines and the match line; a second storage transistor connected between the other of the first pair of complementary bit lines and the match line; a first write transistor connected between a gate of the first storage transistor and one of the second pair of complementary bit lines; and a second write transistor connected between a gate of the second storage transistor and the other of the second pair of complementary bit lines, with both the first and second write transistors having a gate connected to the write line. | 2011-03-03 |
20110051485 | CONTENT ADDRESSABLE MEMORY ARRAY WRITING - A memory system for storing one or more addresses includes a transposable memory having word lines, bit lines, transposed word lines and transposed bit lines and that receives and stores an input array having dimensions M by N and a content addressable memory (CAM) that reads the transposed word lines of the transposable memory to form input words and that stores the input words in an N by M array. | 2011-03-03 |
20110051486 | CONTENT ADDRESSABLE MEMORY REFERENCE CLOCK - A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic. | 2011-03-03 |
20110051487 | Read only memory cell for storing a multiple bit value - A read only memory cell for storing a multiple bit value is disclosed. The read only memory cell comprises: at least three output lines, each of the at least three output lines representing a different multiple bit value; a switching device connected between a single one of the three output lines and a voltage source. The switching device provides an electrical connection between the voltage source and the single one of the three output lines in response to a switching signal, a voltage of the connected output line switching value in response to connection to the predetermined voltage and the multiple bit value represented by the output line is thereby selected. There is also an output device provided for outputting the selected multiple bit value. | 2011-03-03 |
20110051488 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device to an exemplary aspect of the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a plurality of column selectors, a common signal line pair including one common line commonly connected to one of each of the plurality of bit line pairs, and the other common line commonly connected to the other of each of the plurality of bit line pairs, a sense amplifier amplifying the potential difference of the common signal line pair, and a plurality of capacitance adding circuits that balance with parasitic capacitances of the column selectors which are not selected, the capacitance adding circuits being provided respectively between the one of each of the bit line pairs and the other common line and between the other of each of the bit line pairs and the one common line. | 2011-03-03 |
20110051489 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first inverter and a second inverter each having an input and an output, the output of each of the first and second inverters being connected to the input of the other so that data is stored, a CMOS switch configured to connect the input of the first inverter and a write bit line, a read MOS transistor having a gate connected to the output of the first inverter, and a MOS switch configured to connect the read MOS transistor to a read bit line. The first and second inverters have different sizes and are connected to different source power supplies. | 2011-03-03 |
20110051490 | ARRAY ARCHITECTURE AND OPERATION FOR MAGNETIC RACETRACK MEMORY - A high density memory architecture comprising magnetic racetrack memory and a method of operation. The memory architecture comprises a plurality of magnetic memory structures, each the structure formed of magnetic material; a sensing device associated with each magnetic memory structure; first decoder device initiating a track select signal for activating a single magnetic memory structure from among the plurality to perform a bit read or bit storage operation; a bit drive device for applying a first signal to form a new magnetic memory domain associated with a bit value to be stored in the activated magnetic memory structure at a first position thereof during a bit storage operation; and, a second decoder applying a second signal for advancing each the formed magnetic memory domain toward a second position of the activated memory structure. The sensing device reads a memory bit value stored at a magnetic domain at the second position of the activated memory structure. Subsequent thereto, a new magnetic memory domain associated with a bit value just read is formed such that the magnetic memory structure is returned to its original state at an end of the bit read operation. | 2011-03-03 |
20110051491 | FERROELECTRIC RANDOM ACCESS MEMORY AND MEMORY SYSTEM - Certain embodiments provide a ferroelectric random access memory comprising a first buffer, a second buffer, a third buffer, a first controlling unit, a second controlling unit, a memory cell array, a sense amplifier circuit, and a third controlling unit. The first buffer outputs a first signal changed from a first value to a second value based on notification of power-down. The second buffer stops supply of inner clock signal with the change of the first signal from the first value to the second value. The third buffer receives an address signal corresponding to data to be read or written. The first controlling unit receives a command signal. The second controlling unit generates a basic signal that has a third value when the command signal indicates a bank active command and has a fourth value when the command signal indicates a precharge command and the first signal has the second value. The sense amplifier circuit reads data via a pair of bit lines from the memory cell corresponding to the address signal. The third controlling unit controls write back to the memory cell from which the data are read so as to be performed after an elapse of a predetermined time from the time the basic signal has the third value and when the basic signal has the fourth value. | 2011-03-03 |
20110051492 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including: a cell array with memory cells arranged therein, the memory cell storing a resistance state as data in a non-volatile manner; a write buffer configured to supply voltage and current to a selected memory cell in accordance with data to be written in it; and a write control circuit configured to make a part of current supplied to the selected memory cell flow out in accordance with the selected memory cell's state change in a write mode. | 2011-03-03 |
20110051493 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array configured as an arrangement of memory cells each arranged between a first line and a second line and each including a variable resistor. A control circuit controls a voltage applied to the first line or the second line. A current limiting circuit limits a current flowing through the first line or the second line to a certain upper limit or lower. In a case where a writing operation or an erasing operation to a memory cell is implemented a plural number of times repeatedly, the current limiting circuit sets the upper limit in the writing operation or erasing operation of the p-th time higher than the upper limit in the writing operation or erasing operation of the q-th time (q | 2011-03-03 |
20110051494 | MEMORY HAVING TUNNEL BARRIER AND METHOD FOR WRITING AND READING INFORMATION TO AND FROM THIS MEMORY - A resistive memory comprises a tunnel barrier. The tunnel barrier is in contact with a memory material which has a memory property that can be changed by a write signal. Because of the exponential dependence of the tunnel resistance on the parameters of the tunnel barrier, a change in the memory property has a powerful effect on the tunnel resistance, whereby the information stored in the memory material can be read. A solid electrolyte (ion conductor), for example, is suitable as a memory layer, wherein the ions thereof can be moved relative to the interface with the tunnel barrier by the write signal. The memory layer, however, can also be, for example, a further tunnel barrier, the tunnel resistance of which can be changed by the write signal, for example by displacement of a metal layer present in this tunnel barrier. The invention further provides a method for storing and reading information to and from a memory. | 2011-03-03 |
20110051495 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH NO DECREASE IN READ MARGIN AND METHOD OF READING THE SAME - According to one embodiment, a plurality of memory cells, each composed of a variable-resistance element and a diode, are arranged at the intersections of a plurality of word lines and a plurality of bit lines. The sense amplifier compares a voltage corresponding to current in a memory cell selected from the plurality of memory cells with a reference voltage to detect data read from the selected memory cell. The controller generates the reference voltage according to the logical value of a signal output from the sense amplifier. The controller, before detecting data in the memory cell, adjusts the reference voltage on the basis of current flowing in one of a plurality of bit lines connected to a plurality of memory cells in a half-selected state detected by the sense amplifier. | 2011-03-03 |
20110051496 | Resistive Random Access Memory and the Method of Operating the Same - A resistive random access memory utilizing gate induced drain leakage current as the read operation current and the write operation current and a method of operation the same, wherein the resistive random access memory including a plurality of arrayed memory cells, a plurality of bit-lines and a plurality word-lines, each memory cell including: a switching resistor having a first terminal and a second terminal, the first terminal of the switching resistor being connected to one bit-line; and a MOSFET being connected to the second terminal and having a gate, a source, a drain and a substrate, the gate being connected to one word-line, the read operation current and the write operation current of the memory cell being gate induced drain leakage current of the MOSFET. The RRAM array presented in this invention has superior scalability for resistors as well as transistors, which leads to a memory array with higher density. | 2011-03-03 |
20110051497 | METHOD OF MEASURING A RESISTANCE OF A RESISTIVE MEMORY DEVICE - A method of measuring a resistance of a memory cell in a resistive memory device can be provided by applying a data write pulse to a selected cell of the resistive memory device, applying a resistance read pulse to the selected cell after a delay time measured from a time of applying the data write pulse, measuring a drop voltage at the cell responsive to a pulse waveform output when applying the resistance read pulse to the selected cell, measuring a total current through the cell using the drop voltage and an internal resistance of a test device coupled to the cell, and determining a resistance of the resistive memory device using the total current and a voltage of the resistance read pulse. | 2011-03-03 |
20110051498 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell, a power supply circuit, an interconnection and a discharging circuit. The memory cell includes a variable resistance element whose resistance varies by application of a voltage. The power supply circuit outputs the voltage to be applied to the memory cell. The interconnection is formed between the power supply circuit and the memory cell and supplies the voltage output from the power supply circuit to the memory cell. The discharging circuit is connected to the interconnection. The discharging circuit discharges electric charge accumulated in the interconnection after a first operation of applying the voltage to the memory cell is ended and before a second operation of applying the voltage to the memory cell next is started. | 2011-03-03 |
20110051499 | METHOD FOR ADJUSTING A RESISTIVE CHANGE ELEMENT USING A REFERENCE - A method of adjusting a resistive change element using a reference is disclosed. The method comprises inspecting a resistive change element to determine a first state; comparing the first state to a reference wherein said reference provides stimulus parameters corresponding to a transition from the first state to a second state; and applying the stimulus parameters to the resistive change element. A resistive change memory cell array is also disclosed. | 2011-03-03 |
20110051500 | NONVOLATILE MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE - Provided is a nonvolatile memory element which is capable of performing a stable resistance change operation at a low breakdown voltage. | 2011-03-03 |
20110051501 | MEMORY CONTROL WITH SELECTIVE RETENTION - The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines ( | 2011-03-03 |
20110051502 | Flexible Word-Line Pulsing For STT-MRAM - A method for generating a variable pulse width signal on an integrated circuit (IC) chip, includes receiving a first clock signal on the IC chip and receiving a second clock signal on the IC chip having a variable delay relative to the first clock signal. A signal having a rising edge triggered by a rising edge of the first clock signal and a falling edge triggered by a rising edge of the second clock signal is output. The output signal is provided to circuitry on the chip, such as a magnetoresistive junction (MTJ) cell of a spin torque transfer magnetic random access memory (STT-MRAM). | 2011-03-03 |
20110051503 | Magnetic Devices and Structures - Magnetic devices, magnetoresistive structures, and methods and techniques associated with the magnetic devices and magnetoresistive structures are presented. For example, a magnetic device is presented. The magnetic device includes a ferromagnet, an antiferromagnet coupled to the ferromagnet, and a nonmagnetic metal proximate to the ferromagnet. The antiferromagnet provides uniaxial anisotropy to the magnetic device. A resistance of the nonmagnetic metal is dependent upon a direction of a magnetic moment of the ferromagnet. | 2011-03-03 |
20110051504 | CREATING SHORT PROGRAM PULSES IN ASYMMETRIC MEMORY ARRAYS - The present invention provides methods and apparatus for adjusting voltages of bit and word lines to create short programming pulses to program a memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, switching the first line from the first voltage to a second voltage, and switching the first line from the second voltage to the first voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results. The switching operations together may create a first pulse. | 2011-03-03 |
20110051505 | REDUCING PROGRAMMING TIME OF A MEMORY CELL - The present invention provides methods and apparatus for adjusting voltages of bit and word lines to program a two terminal memory cell. The invention may include setting a first line connected to a memory cell to a first voltage from a first line standby voltage, charging a second line connected to the memory cell to a predetermined voltage from a second line standby voltage, and switching the first line from the first voltage to a second voltage. The voltage difference between the first voltage and the predetermined voltage is such that a safe voltage results that does not program the memory cell. A voltage difference between the second voltage and the predetermined voltage is such that a programming voltage operative to program the memory cell results. | 2011-03-03 |
20110051506 | FLEXIBLE MULTI-PULSE SET OPERATION FOR PHASE-CHANGE MEMORIES - Methods and apparatus are provided that include reading a plurality of sets of program pulse tuning instructions from a memory page, the memory page including a plurality of memory cells; and creating a plurality of program pulses in accordance with the plurality of sets of program pulses to program the plurality of memory cells. The plurality of sets of program pulse tuning instructions may be different from one another in at least one respect. | 2011-03-03 |
20110051507 | MAINTENANCE PROCESS TO ENHANCE MEMORY ENDURANCE - Subject matter disclosed herein relates to enhancing an operational lifespan of non-volatile memory. | 2011-03-03 |
20110051508 | MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY - A method and device for performing a program operation of a phase change memory (PCM) cell. The method includes the steps of applying one or more programming pulses according to a predefined programming scheme to achieve a target resistance level of the PCM cell, wherein the programming scheme is operable to perform in a first programming mode one or more annealing steps to approach the target resistance, wherein the programming scheme is operable to perform in a second programming mode one or more melting steps, wherein the programming scheme is operable to start in the first programming mode and to switch to the second programming mode if the target resistance level of the PCM cell has been undershot in the first programming mode. | 2011-03-03 |
20110051509 | System and Method to Manufacture Magnetic Random Access Memory - A system and method to manufacture magnetic random access memory is disclosed. In a particular embodiment, a method of making a magnetic tunnel junction memory system includes forming a portion of a metal layer into a source line having a substantially rectilinear portion. The method also includes coupling the source line, at the substantially rectilinear portion, to a first transistor using a first via. The first transistor is configured to supply a first current received from the source line to a first magnetic tunnel junction device. The method includes coupling the source line to a second transistor using a second via, where the second transistor is configured to supply a second current received from the source line to a second magnetic tunnel junction device. | 2011-03-03 |
20110051510 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH TRANSFERS A PLURALITY OF VOLTAGES TO MEMORY CELLS AND METHOD OF WRITING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, a bit line, and a voltage generator. The memory cell array includes each of a plurality of memory cells. Each of the memory cells includes a charge storage layer and a control gate and is capable of holding two or more levels of data. The bit line is capable of transferring data to the memory cells in a one-to-one correspondence. The voltage generator carries out a verify operation by applying a verify voltage to the memory cells after performing first writing by applying a first voltage and then a second voltage lower than the first voltage to the control gate. | 2011-03-03 |
20110051511 | DIGITAL FILTERS WITH MEMORY - A memory device that, in certain embodiments, includes a memory element coupled to a bit-line and a quantizing circuit coupled to the memory element via the bit-line. In some embodiments, the quantizing circuit includes an analog-to-digital converter having an input and output and a digital filter that includes memory. The input of the analog-to-digital converter may be coupled to the bit-line, and the output of the analog-to-digital converter may be coupled to the digital filter. | 2011-03-03 |
20110051512 | 3D MEMORY DEVICES DECODING AND ROUTING SYSTEMS AND METHODS - 3D memory devices are disclosed, such as those that include multiple two-dimensional tiers of memory cells. Each tier may be fully or partially formed over a previous tier to form a memory device having two or more tiers. Each tier may include strings of memory cells where each of the strings are coupled between a source select gate and a drain select gate such that each tier is decoded using the source/drain select gates. Additionally, the device can include a wordline decoder for each tier that is only coupled to the wordlines for that tier. | 2011-03-03 |
20110051513 | METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES - The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell. | 2011-03-03 |
20110051514 | NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM INCORPORATING SAME, AND METHOD OF OPERATING SAME - A nonvolatile memory device performs a program operation comprising applying a program pulse to selected memory cells, detecting a number of fail bits among the selected memory cells, the fail bits comprising failed program bits and disturbed inhibit bits, and determining a program completion status of the program operation based on the number of detected fail bits. | 2011-03-03 |
20110051515 | NONVOLATILE SEMICONDUCTOR MEMORY - Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte. | 2011-03-03 |
20110051516 | Semiconductor Device - A semiconductor device comprises a transistor comprising a gate, a source, a drain, and a gate insulating layer, and an auxiliary line formed over the drain and electrically insulated from the drain. During a turn-off operation of the transistor, voltage to increase a resistance of the drain is supplied to the auxiliary line. | 2011-03-03 |
20110051517 | PARTIAL SPEED AND FULL SPEED PROGRAMMING FOR NON-VOLATILE MEMORY USING FLOATING BIT LINES - Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher. | 2011-03-03 |
20110051518 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device, in which flag data read of a flag data region is performed during data write, comprises: a nonvolatile memory cell array having an ordinary data region and the flag data region allocated to a one page range in which read and write are simultaneously performed; and a one page amount of sense amplifiers, each of the sense amplifiers comprising a data latch for retaining write data. During read of the flag data by the sense amplifier circuit, in the case of one of the sense amplifiers corresponding to the flag data region, read flag data is transferred to the data latch. In the case of one of the sense amplifiers corresponding to the ordinary data region, write data retained by the data latch is rewritten regardless of read cell data. | 2011-03-03 |
20110051519 | Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface - A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. An enable signal defines a beginning and termination of a reading or writing operation. Reading one nonvolatile memory array may be interrupted for another operation and then resumed. | 2011-03-03 |
20110051520 | NONVOLATILE MEMORY DEVICE, DRIVING METHOD THEREOF, AND MEMORY SYSTEM HAVING THE SAME - A nonvolatile memory device (NVM), memory system and apparatus include control logic configured to perform a method of applying negative voltage on a selected wordline of the NVM. During a first time a first high voltage level is applied to the channel of a transistor of a address decoder and a ground voltage is applied to the well of the transistor. And, during a second time a second high voltage level is applied to the channel of the transistor, and within the second time interval a first negative voltage is applied to the well of the transistor. The first high voltage level is higher than the second high voltage level, and a voltage applied on the selected wordline is negative within the second time interval. | 2011-03-03 |
20110051521 | FLASH MEMORY MODULE AND METHOD FOR PROGRAMMING A PAGE OF FLASH MEMORY CELLS - A flash memory module and a method for programming a page of flash memory cells, the method includes: receiving a cycle count indication indicative of a number of program cycles of the page of memory cells; setting a value of a programming parameter of a programming operation based on the cycle count indication; and programming at least one flash memory cell of the page of flash memory cells by performing the programming operation. | 2011-03-03 |
20110051522 | METHOD OF PROGRAMMING FLASH MEMORY OF THE DIFFERENTIAL CELL STRUCTURES FOR BETTER ENDURANCE - A method of programming a differential flash memory cell having a first and a second memory cell is disclosed. The first memory cell includes a first transistor associated with a first threshold voltage and the second memory cell includes a second transistor associated with a second threshold voltage. The method includes reading the first and second memory cells to determine a current associated with the first and second threshold voltages. The first threshold voltage is equal to a first value and the second threshold voltage is equal to a second value. The method further includes determining if the first current corresponds to a predetermined logic state. If the current does not correspond to the predetermined logic state, the first and second memory cells are programmed. The programming includes changing the first threshold voltage from the first value to a third value and the second threshold voltage from the second value to a fourth value. | 2011-03-03 |
20110051523 | SMALL UNIT INTERNAL VERIFY READ IN A MEMORY DEVICE - Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of columns of memory cells (e.g., memory block). Mask data is loaded into a third dynamic data cache of three dynamic data caches. The expected data is loaded into a second data cache. After a read operation of programmed columns of memory cells, the read data is compared to the expected data and error bit indicators are stored in the second data cache in the error bit locations. The second data cache is masked with the mask data so that only those error bits that are unmasked are counted. If the number of unmasked error bit indicators is greater than a threshold, the memory block is marked as unusable. | 2011-03-03 |
20110051524 | Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device - A method and apparatus for operation for the NAND-like dual charge retaining transistor NOR flash memory cells begins by erasing, verifying over-erasing the threshold voltage level of the erased charge retaining transistors to an erased threshold voltage level. Then method progresses by programming one of two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to a first programmed threshold voltage level, and programming the other of the two charge retaining transistors of the NAND-like dual charge retaining transistor NOR flash memory cells to the first programmed threshold voltage level or to a second programmed threshold voltage level. Combinations of the erased threshold voltage level and the first and second programmed threshold voltage levels determine an internal data state of the NAND-like dual charge retaining transistor NOR flash memory cells which are then decoded to ascertain the external data logical state. | 2011-03-03 |
20110051525 | POWER SAVING METHOD AND CIRCUIT THEREOF FOR A SEMICONDUCTOR MEMORY - A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first part code of a currently received address code is different from the first part code of a last received address code, otherwise a second boost process is activated. | 2011-03-03 |
20110051526 | METHOD FOR PROGRAMMING A MEMORY STRUCTURE - A memory structure includes a first memory cell and a second memory cell located at an identical bit line and adjacent to the first memory cell. Each memory cell includes a substrate, a source, a drain, a charge storage device, and a gate. A method for programming the memory structure includes respectively providing a first gate biasing voltage and a second gate biasing voltage to the gates of the first memory cell and the second memory cell, boosting an absolute value of a channel voltage of the first memory cell to generate electron and hole pairs at the drain of the second memory cell through gate-induced drain leakage or band-to-band tunneling, and injecting the hole of the generated electron and hole pairs into the charge storage device of the first memory cell to program the first memory cell. | 2011-03-03 |
20110051527 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V | 2011-03-03 |
20110051528 | Dynamic Semiconductor Memory With Improved Refresh Mechanism - Various embodiments for implementing refresh mechanisms in dynamic semiconductor memories that allow simultaneous read/write and refresh operations. In one embodiment, the invention provides a synchronous multi-bank dynamic memory circuit that employs a flag to indicate a refresh mode of operation wherein refresh operation can occur in the same bank at the same time as normal access for read/write operation. In a specific embodiment, to resolve conflicts between addresses, an address comparator compares the address for normal access to the address for refresh operation. In case of a match between the two addresses, the invention cancels the refresh operation at that array and allows the normal access to proceed. | 2011-03-03 |
20110051529 | MEMORY DEVICE - Systems and methods for reading data from or writing data to a memory device. The methods involve receiving a first pulse signal having a first pulse frequency at the memory device. The methods also involve generating, at the memory device, a second pulse signal using the first pulse signal. The second pulse signal is a compliment of the first pulse signal. The second pulse signal has a second pulse frequency that is equal to the first frequency. The first pulse signal is used to control first read/write operations so that first data is output from or input to the memory device at a first data rate. The first and second pulse signals are used to control second read/write operations so that second data is output from or input to the memory device at a second data rate. The second data rate is twice the first data rate. | 2011-03-03 |
20110051530 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF UPDATING DATA STORED IN THE SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device executes, in address units, operation for inverting data stored in a memory cell designated by an internal address and writing the data in the memory cell and increments the internal address every time inversion writing operation for the memory cell is executed. | 2011-03-03 |
20110051531 | DATA OUTPUT CONTROL CIRCUIT OF A DOUBLE DATA RATE (DDR) SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE RESPONSIVE TO A DELAY LOCKED LOOP (DLL) CLOCK - A semiconductor memory device using system clock with a high frequency can maintain a constant operation margin even in the change of operation environments including voltage level, temperature, and process. The semiconductor memory device includes an output control signal generator configured to be responsive to a read pulse that is activated in response to a read command, to generate an odd number of first output source signals corresponding to a rising edge of a system clock and a even number of second output source signals corresponding to a falling edge of the system clock, and an output enable signal generator configured to generate a first rising enable signal and a falling enable signal on the basis of the first output source signal and generate a second rising enable signal on the basis of the second output source signal, according to column address strobe (CAS) latencies, the first rising enable signal being activated earlier than the second rising enable signal by a half cycle of the system clock. | 2011-03-03 |
20110051532 | REFERENCE LEVEL GENERATION WITH OFFSET COMPENSATION FOR SENSE AMPLIFIER - An approach that provides reference level generation with offset compensation for a sense amplifier is described. In one embodiment, an arbitrary reference level is generated to provide an offset that compensates for device mismatch and voltage threshold of a sense amplifier. | 2011-03-03 |
20110051533 | INTERNAL VOLTAGE GENERATOR CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - An internal voltage generator circuit is disclosed. The internal voltage generator circuit includes a comparator configured to compare a first voltage with a reference voltage and to output a comparison signal. The circuit further includes an internal voltage driver configured to receive an external voltage and the comparison signal and to output an internal voltage at an internal voltage output terminal, based on the comparison signal. The circuit further includes a voltage divider circuit including first and second resistor units and a first voltage output terminal between the first and second resistor units, configured to receive the internal voltage, and configured to output the first voltage based on the resistance values of the first and second resistor units, the first and second resistor units connected in series, and the first voltage being output through the first voltage output terminal. The circuit further includes a control signal generator circuit configured to generate at least one resistor control signal for controlling the resistance value of the first resistor unit and at least one resistor control signal for controlling the resistance value of the second resistor unit, on the basis of the comparison signal and a precharge command. | 2011-03-03 |
20110051534 | Semiconductor storage device and its control method - A semiconductor storage device, in which successive reading and successive writing of data having a predetermined length from and to a memory cell specified by a certain address are performed, includes a plurality of memory cells, address input terminals through which the address is input, data output terminals through which read data having the predetermined length is output, and data input terminals through which write data having the predetermine length is input. Part of the address input terminals are also used as the data output terminals. In this way, the operation of successive reading and successive writing performed in succession at the same address can be made faster without increasing the number of terminals. | 2011-03-03 |
20110051535 | Fin-Type Device System and Method - A fin-type device system and method is disclosed. In a particular embodiment, a method of fabricating a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes forming a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent a second BOX layer face of the BOX layer. | 2011-03-03 |
20110051536 | SIGNAL DELAY CIRCUIT AND A SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A signal delay circuit that includes a delay unit configured to delay an input signal for a first delay time and output the delayed input signal; a first delay adjusting unit configured to adjust the first delay time according to a variation in a level of a power supply voltage supplied to the delay unit; and a second delay adjusting unit configured to offset an amount of time the first delay time is adjusted by the first delay adjusting unit. | 2011-03-03 |
20110051537 | Address Multiplexing in Pseudo-Dual Port Memory - A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to be complete. A multiplexer is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time. | 2011-03-03 |
20110051538 | METHODS AND MEMORY DEVICES FOR REPAIRING MEMORY CELLS - Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section. | 2011-03-03 |
20110051539 | Method and structure for SRAM VMIN/VMAX measurement - A parametric test circuit is disclosed (FIG. | 2011-03-03 |
20110051540 | Method and structure for SRAM cell trip voltage measurement - A parametric test circuit is disclosed (FIG. | 2011-03-03 |
20110051541 | Semiconductor device - A semiconductor device including a plurality of memory cells arranged in a matrix pattern, a write amplifier which writes write data to the memory cell in synchronization with a clock, a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock, a plurality of column select switches which connect the plurality of the memory cells with the sense amplifier and the write amplifier, a column address decoder which makes the column select switch corresponding to one column among the plurality of the memory cells a conductive state based on a column address, a row address decoder which activates the memory cell of one row based on a row address, and a test write circuit which writes data corresponding to a logical level of a test signal to the memory cell based on a test mode signal. | 2011-03-03 |
20110051542 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ACCESSING THE MEMORY CIRCUITS - A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. A sense amplifier is coupled with the bit line. The sense amplifier is capable of precharging the bit line to a first voltage that is substantially equal to and higher than a threshold voltage (V | 2011-03-03 |
20110051543 | SENSE AMPLIFIER AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - A semiconductor integrated circuit having a sense amplifier includes first and second inverters each having an output terminal coupled to an input terminal of the other inverter. The first inverter is configured to be activated in response to a first and a third activation signals, and the second inverter is configured to be activated in response to a second and a fourth activation signals. The first and third activation signals and the second and fourth activation signals are provided through separate signal sources from each other. | 2011-03-03 |
20110051544 | DEVICE FOR MIXING AND/OR KNEADING FOOD PRODUCTS - A device for mixing and/or kneading food products. The device includes a container having an inlet, an outlet, and at least one rotary shaft extending substantially in a longitudinal direction of the container. The at least one rotary shaft includes at least one tool, the at least one tool including at least one bar connected to the at least one rotary shaft via spacers. The at least one rotary shaft further includes an operative area to continuously mix and/or knead the food products, the operative area extending in a longitudinal direction of the at least one rotary shaft. | 2011-03-03 |
20110051545 | Multi-screw extruder - There is provided a multi-screw extruder for reclaiming foam made of cross-linked polymer material into reusable material by causing the foam to pass through a kneading zone, wherein the kneading zone is divided into at least preceding and subsequent two kneading zones and a temperature equalizing transfer zone for equalizing temperature of the material passing through the zone is provided between the preceding kneading zone and the subsequent kneading zone. | 2011-03-03 |
20110051546 | FLUID BLENDING APPARATUS AND PROCESS - A process for blending a plurality of fluids utilizes an apparatus including a blending tank having at least one inlet and an outlet; a first supply line and a second supply line in fluid communication with the at least one inlet; the first supply line being in fluid communication with a first fluid source and having a first timing valve disposed between the first fluid source and the at least one inlet; the second supply line being in fluid communication with a second fluid source and having a second timing valve disposed between the second fluid source and the at least one inlet; a controller operatively connected to the first and second timing valves for controlling frequency and duration of actuation of the first and second timing valves. | 2011-03-03 |
20110051547 | ARRANGEMENT AND METHOD AT A MILKING STATION FOR ACHIEVING A REPRESENTATIVE MILK SAMPLE - A method and arrangement for providing a representative milk sample from one animal, includes milk extracting parts, a receiver, a milk transferring part to transfer the milk from the receiver to a sampling unit, milk stirring parts adapted to stir the milk before transferring a sample part of the milk to the sample unit, a milk yield determining part, a stirring time determining part, the arrangement adapted to terminate the stirring of the milk when the time period ends so that a satisfactorily stirring can be accomplished without subjecting the milk to excessive stirring. | 2011-03-03 |
20110051548 | ROTATABLE MIXING DEVICE AND DYNAMIC MIXING METHOD - The present invention generally relates to a rotatable mixing device, a dynamic mixing apparatus, and a high throughput workflow system and dynamic mixing method employing the same. | 2011-03-03 |
20110051549 | Nucleation Ring for a Central Insert - A central insert causes maximum fluid velocity to shift away from an external tube wall reducing friction losses at the tube wall. Centrifugal forces pull fluid away from a central insert wall minimizing friction at the insert wall. The insert may be used in the context of nozzles, flow tubes, vortex tubes, and other fluid pathways. In a nozzle, grooves may be added to the nozzle wall. By introducing these grooves at the exit or end of a nozzle, nucleation may be improved and cavitation may be triggered prior to a fluid entering an expansion tube. The nucleation ring may also be placed at the beginning of a nozzle such that cavitation starts within the nozzle. | 2011-03-03 |
20110051550 | System and Method for Deployment of Seismic Data Recorders - A system and method for deployment of a plurality of seismic recorder assemblies from a survey vessel on the ocean bottom is disclosed. The seismic recorder assemblies are self contained, autonomous nodal devices which are capable of receiving and recording reflected seismic energy and storing the data locally while operating for an extended period of time. The assemblies each have two or more attachment points for the connection of separate connecting cable segments. | 2011-03-03 |
20110051551 | Sensor grouping for dual sensor marine seismic streamer and method for seismic surveying - A method for marine seismic surveying includes towing a streamer in a body of water. The streamer includes a plurality of spaced apart sensor groups, each including a plurality of longitudinally spaced apart pressure sensors and particle motion responsive sensors. Signals are detected at each of the sensors in response to actuation of a seismic energy source. Components of the sampled motion signals in each group above a selected frequency are combined to generate respective group motion signals. Components of the motion responsive signals below the selected frequency are velocity filtered. The velocity filtered signals are combined with the group motion signals to generate full bandwidth motion responsive signals corresponding to each sensor group. | 2011-03-03 |
20110051552 | METHODS AND APPARATUS TO CALCULATE A DISTANCE FROM A BOREHOLE TO A BOUNDARY OF AN ANISOTROPIC SUBTERRANEAN ROCK LAYER - Methods and apparatus to calculate a distance from a borehole to a boundary of an anisotropic subterranean rock layer are disclosed. A disclosed example method includes transmitting a first signal from a first transmitter at a first location in a borehole traversing a subterranean formation, receiving the first signal at a first receiver after a first time period at a second location in the borehole, receiving the first signal at a second receiver after a second time period at a third location in the borehole, and calculating a first distance from the first transmitter to a first portion of a boundary of a subterranean rock layer adjacent to the borehole by compensating for an anisotropy of the subterranean rock layer based on the first time period and the second time period. | 2011-03-03 |
20110051553 | DETERMINING THE QUALITY OF A SEISMIC INVERSION - A method for evaluating a quality of a seismic inversion. The method includes performing a first match between seismic data and borehole seismic data at one or more borehole locations to generate an estimate of a wavelet in the seismic data. The method then performs a seismic inversion on the seismic data using the estimate of the wavelet to generate inverted seismic data. After performing the seismic inversion, the method converts the inverted seismic data into one or more reflectivity traces. The method then includes performing a second match between the one or more reflectivity traces and one or more traces in the seismic data and performing a third match between the one or more reflectivity traces and one or more traces in the borehole seismic data. After performing the second and third matches, the method determines the quality of the seismic inversion based on the first match, the second match, the third match or combinations thereof. | 2011-03-03 |
20110051554 | INSONIFICATION DEVICE THAT INCLUDES A THREE-DIMENSIONAL NETWORK OF EMITTERS ARRANGED IN AT LEAST TWO CONCENTRIC SPIRALS, WHICH ARE DESIGNED TO GENERATE A BEAM OF HIGH-INTENSITY FOCUSSED WAVES - The invention concerns a device ( | 2011-03-03 |
20110051555 | System and Method for Determining Location of Submerged Submersible Vehicle - An aspect of the present invention is drawn to method of determining a location of a submersible vehicle. The method includes obtaining first bearing information based on a location of a ship at a first time relative to the submersible vehicle and receiving broadcast information from the ship, wherein the broadcast information includes location information related to a second location of the ship at a second time, a velocity of the ship at the second time and a course of the ship at the second time. The method further includes obtaining second bearing information based on the second location of the ship at the second time relative to the submersible vehicle, obtaining a velocity of the submersible vehicle at the second time and obtaining a course of the submersible vehicle at the second time. The method still further includes determining the location of the submersible vehicle based on the first bearing information, the second location of the ship at the second time, the velocity of the ship at the second time, the course of the ship at the second time, the second bearing information, the velocity of the submersible vehicle at the second time and the course of the submersible vehicle at the second time. | 2011-03-03 |
20110051556 | MONOPOLE ACOUSTIC TRANSMITTER RING COMPRISING PIEZOELECTRIC MATERIAL - A monopole acoustic transmitter for logging-while-drilling comprising as a ring that comprises one or more piezoelectric arc segments. The ring is oriented in a plane whose normal is essentially coincident with the major axis of a logging tool in which it is disposed. The ring disposed within a recess on the outer surface of a short, cylindrical insert. The insert is inserted into a drill collar, rather than into the wall of the collar. The ring can comprise a continuous ring of piezoelectric material, or alternately arc segments or active ring segments of piezoelectric ceramic bonded to segments of other materials such as alumina to increase the frequency or heavy metals such as tungsten to reduce the frequency. The material and dimensions of the material used in-between the piezoelectric segments is chosen to alter the frequency of the ring. | 2011-03-03 |
20110051557 | Apparatus and Method for Control Using a Humming Frequency - A device controller configured to control physical devices using an audible humming frequency that includes: a humming frequency module, a humming command module, and a control command module. The humming frequency module may be configured to determine humming frequenc(ies) using a detected humming signal(s). The humming command module may be configured to compute humming command(s) based on the humming frequenc(ies). The control command module may be configured to generate control command(s) using received key command(s) and humming command(s). | 2011-03-03 |
20110051558 | System for Determining the Work Time of a Work Tool - A system for determining the work time of a work tool is disclosed. The system has a work tool. The system also has a work tool movement sensor adapted to produce a signal indicative of a movement of the work tool. The system further has a controller adapted to produce a signal indicative of a work time of the work tool as a function of the movement of the work tool. | 2011-03-03 |
20110051559 | Before/After Specific Weekday Determination Device, Program Media, Method, Daylight Saving Time Determination Device, And Timepiece - A before/after specific weekday determination device that determines if an evaluation date is before or after a specific date that is identified as an n-th (where n is an integer of 1 or more) specific weekday from the beginning or the end of a specific month. The before/after specific weekday determination device is utilized in a daylight saving time determination device, and in a timepiece. | 2011-03-03 |
20110051560 | Remote automatic setting of clock radio - The time and/or date display of a clock radio is settable remotely and automatically by a radio frequency information signal. The time and/or date display is initially set in manufacturing of the clock radio simultaneously to a plurality of clock radio units, and the display may also be adjusted with an adjusting radio frequency signal broadcast to a plurality of clock radio units simultaneously. | 2011-03-03 |
20110051561 | Timepiece With Internal Antenna - A timepiece with an internal antenna, including: a case that is made from a conductive material; a movement that is housed in the case and has a plurality of motors that drive staffs disposed at a plurality of locations; a dial that is made from a nonconductive material; and a patch antenna that is disposed inside the case on the back side of the dial, receives radio signals transmitted from an external source, and includes a dielectric and an electrode formed in the dielectric; wherein the patch antenna is disposed separated at least a specific distance from the inside surface of the case, and the staffs are disposed between the case and the patch antenna. | 2011-03-03 |
20110051562 | ANALOGUE DISPLAY DEVICE INCLUDING A PLANETARY GEAR DRIVE - The invention concerns a timepiece ( | 2011-03-03 |
20110051563 | Energy Saving Digital Timepiece - A timepiece includes a casing, a display, a timepiece core unit, and a current processing circuitry. The current processing circuitry includes a rectifying circuitry, an oscillating circuitry, and an output circuitry. The rectifying circuitry is adapted for electrically connected with an AC power source, and arranged to rectify the AC. The oscillating circuitry is electrically connected with the rectifying circuitry, and is arranged to transform the DC outputted from the rectifying circuitry back into AC having a predetermined voltage and a frequency. The output circuitry is electrically connected with the oscillating circuitry, and is arranged to rectifying the AC output from the oscillating circuitry into a DC pulses output, wherein the DC output from the output circuitry is electrically transmitted to the timepiece circuitry for triggering an operation thereof so as to allow the signal generator to generate accurate time signal to display the current time by the display. | 2011-03-03 |
20110051564 | Windup portable timepiece and method of operating crown with which this timepiece is equipped - A portable timepiece has a timepiece exterior assembly having a case band containing a movement having a one-way clutch transmitting rotation to wind up a mainspring to the mainspring and preventing transmission of rotation to rewind the mainspring to the mainspring, and a winding stem, a winding stem pipe with a male screw portion arranged outside the case band being fixed to the case band, a crown connected to the winding stem being detachably brought into the male screw portion, an engagement end surface of the crown being brought into contact with a lock surface of the case band to maintain the crown in a lock state. The portable timepiece is characterized in that when placing the crown in the lock state, the crown is rotated in a direction opposite to the winding-up direction of the mainspring, and when releasing the lock state to wind up the mainspring, the crown is rotated in the same direction as the mainspring winding-up direction. | 2011-03-03 |
20110051565 | ASSEMBLY FOR SECURING THE OUTER END OF THE BALANCE-SPRING OF A SPRUNG BALANCE DEVICE FOR A TIMEPIECE - Assembly for securing the outer end of the balance-spring ( | 2011-03-03 |
20110051566 | Slip gear structure and timepiece equipped with the same - Disclosed is a slip gear structure which is easy to handle at the time of dismantling/assembly and which does not easily suffer breakage even if dismantling/assembly is repeated, and a timepiece equipped with the same. A slip gear structure for a timepiece includes: a gear main body portion in the form of an annular plate having in the outer periphery thereof tooth portions, there being provided spring portions extending across an inner opening; and a positioning member equipped with a small diameter plate-like portion having a central hole with which a shaft is rotatably fit-engaged and a pair of support wall portions arranged on both sides of the central hole and protruding from one surface. When the slip gear structure is in a non-fit-engaged state with respect to the shaft, the spring portions of the gear main body are elastically pressed against side edge portions of the support wall portions, with central spring portions thereof situated between the side edge portions protruding into the central hole; and when the slip gear structure is in a fit-engaged state with respect to the shaft at the central hole, the central spring portions of the spring portions of the gear main body portion are elastically pressed against the shaft for slip engagement with the shaft. | 2011-03-03 |
20110051567 | TIMEPIECE WITH A STRIKING WORK FITTED WITH A GONG - The striking work device of a timepiece ( | 2011-03-03 |
20110051568 | GONG FOR TIMEPIECE STRIKING WORK - The striking work device of a timepiece includes a gong ( | 2011-03-03 |
20110051569 | BAND, WRISTWATCH WITH THE BAND AND METHOD OF MAKING THE BAND - A band, a wristwatch with the band and a method of making the band are described. The band includes a strip-like body with a series of holes provided therein along a length thereof for adjusting an effective length thereof. The body includes a band-shaped support layer of woven or knit fabric of bundles of one or more kinds of fibers, the fibers being selected from a group including carbon fibers, glass fibers, aramid fibers and boron fibers. The body also includes a first resin layer adhering closely to one surface of the support layer, and a second resin layer adhering closely to the other surface of the support layer. The fibers of the support layer extend at a predetermined angle to longitudinal and transverse directions of the body. | 2011-03-03 |
20110051570 | Portable timepiece - A wristwatch is equipped with a timepiece exterior assembly, an exhaust button, a coil spring, and seal members. A pipe provided in the exterior assembly so as to establish communication between the interior and exterior thereof has seal surfaces and escape portions. The button is equipped with a shaft portion inserted into the pipe and exhibiting a detachment preventing portion to be caught by a pipe edge portion from within the exterior assembly, and a button portion depressed from the outside of the exterior assembly. The spring, which urges the button in an anti-pushing-in direction, is provided between the button portion and the timepiece exterior assembly. Seal members, mounted to the shaft portion in correspondence with the seal surfaces are moved between a sealing position and an exhaust position through axial reciprocating movement of the button, and, while in contact with the seal surfaces, define a closed space S together with the outer periphery of the shaft portion and an escape portion opposed to this outer periphery. | 2011-03-03 |
20110051571 | Portable timepiece - A wristwatch is equipped with a timepiece exterior assembly, a valve member, a coil spring, and seal members. A pipe provided in the exterior assembly so as to establish communication between the interior and exterior thereof has seal surfaces and escape portions. The valve member is equipped with a valve member shaft portion inserted into the pipe and exhibiting a detachment preventing portion to be caught by a pipe edge portion from the outside of the exterior assembly, and a valve member head portion arranged inside the exterior assembly. The spring, which urges the valve member toward the inner side of the exterior assembly, is provided between the valve member head portion and the timepiece exterior assembly. Seal members mounted to the valve member shaft portion in correspondence with the seal surfaces are moved between a sealing position and an exhaust position through axial reciprocating movement of the valve member, and, while in contact with the seal surfaces, define a closed space S together with the outer periphery of the valve member shaft portion and an escape portion opposed to this outer periphery. | 2011-03-03 |