07th week of 2016 patent applcation highlights part 45 |
Patent application number | Title | Published |
20160049265 | Ultra Low Travel Keyboard - A keyboard or keyboard key that has a force sensor that measures the force imparted to the key when a user presses the key or rests a finger on a key. Key embodiments may also include an actuator that excites the in order to provide feedback to the user in accordance with various feedback methods disclosed herein. | 2016-02-18 |
20160049266 | FABRIC KEYBOARD - An input device, such as a keyboard, includes one or more keys that each includes a keycap operable to move within an aperture of a frame to activate a switch and fabric disposed over the frame and keycap. A first region of the fabric is bonded to the keycap and a second region of the fabric is bonded to the frame. The first region may be an embossed region and the second region may be an unembossed region. The fabric may dampen sound from within the keyboard, such as noise related to movement of the keycap, activation of the switch, and so on. The fabric may also form a barrier that restricts passage of contaminants into the aperture and/or other portions of the input device. | 2016-02-18 |
20160049267 | Remote Controlled Light Switch Cover Assembly - A remote controlled light switch cover assembly is described for converting a standard rocker switch into a remote controlled switch. In one embodiment, a method is described, performed by the remote controlled light switch cover, comprising receiving a wireless signal to actuate the standard rocker switch, activating an electric motor that causes a wiper to move along a surface of the standard rocker switch, detecting when the wiper has actuated the standard rocker switch, causing the electric motor to rotate in a reverse direction from the first direction, which causes the wiper to move back towards a valley of the standard rocker switch, detecting when the wiper is positioned over the valley, and in response to detecting when the wiper is positioned over the valley, causing the electric motor to stop rotating, causing the wiper to remain positioned over the valley. | 2016-02-18 |
20160049268 | Switchgear - Magnetic force of a permanent magnet can be converted into arc driving force efficiently, and the permanent magnet can be insulated from arc heat so as to suppress magnetic deterioration, whereby breaking performance can be secured over a long period of time. In order to solve the above-described problems, the switchgear of the present invention includes: a fixed side contactor that is provided to a fixed side conductor; a moving contact that can be driven reciprocally with respect to the fixed side contactor, the moving contact being supported by a movable side conductor via a movable side contactor, the moving contact performing opening and closing operation by contacting to and separating from the fixed side contactor; and a permanent magnet generating a magnetic field on an arc to extinguish the arc through the opening operation, the arc being generated between the fixed side contactor and the moving contact, and the permanent magnet is provided on a tip portion of the fixed side conductor to be positioned closer to the movable side contactor side than the fixed side contactor, and the permanent magnet is covered with an insulating member. | 2016-02-18 |
20160049269 | DISCONNECTING SWITCH UNIT - A disconnecting switch unit or isolating switching device includes a first contact piece and a second contact piece which are movable relative to each other and between which a disconnection or isolation zone is formed when the pieces are separate. A compression device has a compression chamber accommodating a fluid. The compression chamber protrudes at least temporarily into the disconnection or isolation zone. | 2016-02-18 |
20160049270 | SPRING CONTACT, INERTIA SWITCH, AND METHOD OF MANUFACTURING AN INERTIA SWITCH - A spring contact, an inertia switch, and a method of manufacturing an inertia switch are provided. The spring contact includes a conductive body portion having an outer edge and an inner edge partially surrounding an open area, a split in the conductive body portion, the split extending between the outer edge and the inner edge, and a conductive contact finger extending from the inner edge into the open area. The inertia switch includes a shell; a mass movably positioned within the shell; the spring contact positioned within the mass; a biasing member positioned between the spring contact and the header; and a conductive member extending through the header. The biasing member provides a bias between the spring contact within the mass and the conductive member. The method includes at least partially closing the split in the spring contact during insertion of the spring contact within the mass. | 2016-02-18 |
20160049271 | PYROTECHNICALLY ACTUATED SWITCH - A switch may comprise a metal plate. A eutectic alloy may be proximate to the metal plate. An insulating material may be proximate to the insulating material. The insulating material may include a recess in the insulating material adjacent the eutectic alloy. A lead may be fixed in place by the insulating material. A first end of the lead is exposed from the insulating material by the recess. | 2016-02-18 |
20160049272 | PROTECTIVE ELEMENT - To spread flux evenly across the entire surface of a rectangular meltable conductor, a protective element includes: an insulating substrate; a heat-generating resistor disposed on the insulating substrate; a first and a second electrodes laminated onto the insulating substrate; a heat-generating element extracting electrode overlapping the heat-generating resistor in a state electrically insulated therefrom and electrically connected to the heat-generating resistor on a current path between the first and the second electrodes; a rectangular meltable conductor laminated between the heat-generating element extracting electrode and the first and the second electrodes for interrupting a current path between the first electrode and the second electrode by being melted by heat; and a plurality of flux bodies disposed on the meltable conductor; wherein the flux bodies are disposed along the heat-generating resistor. | 2016-02-18 |
20160049273 | ELECTROMAGNETIC CONTACTOR - An electromagnetic contactor includes: a lower frame having an accommodation space therein; a bobbin having a fixed core, and accommodated in the lower frame; a movable core inserted into the bobbin so as to be moveable up and down; a spring installed between the bobbin and the movable core, and configured to provide an upward restoration force to the movable core; and a ‘b’ contact switch installed at one side of the bobbin, wherein a button for operating a switch lever of the ‘b’ contact switch is provided at a movable core plate positioned above the movable core. | 2016-02-18 |
20160049274 | CIRCUIT BREAKERS WITH HANDLE BEARING SLEEVES - Circuit breakers with handles having a handle bearing sleeve that contacts an upper end portion of a moving arm and allows the arm to rotate to “OFF”, “ON” and “TRIP” positions, typically with about 90 degrees of rotation. | 2016-02-18 |
20160049275 | FUSE FOR AN ELECTRICAL CIRCUIT AND PRINTED CIRCUIT BOARD HAVING A FUSE - Described is a fuse for an electrical circuit, comprising two contact arms, each having at least one connecting pin for inserting into a hole of a printed circuit board, and a spring which connects the two contact arms in an electrically conductive manner. According to this disclosure, it is provided that the spring is fastened to at least one of the two contact arms by means of a fastening means that loses its strength at a trigger temperature of the fuse, wherein the fuse is formed in such a manner that by inserting the connecting pins into holes of a printed circuit board, the spring is loaded such that the spring lifts from the at least one contact arm by spring force as soon as the fastening means loses its strength due to overheating. Moreover, a printed circuit board comprising such a fuse is described. | 2016-02-18 |
20160049276 | INTEGRATED GAS DISCHARGE TUBE AND PREPARATION METHOD THEREFOR - Provided is an integrated gas discharge tube. In the integrated gas discharge tube, the structure of the gas discharge tube is regulated into an upper cover and an insulative base, and the internal side surface and the external side surface of the bottom surface of the insulative base are respectively subject to electrode integration, so that the discharge effect of the gas discharge tube is effectively increased and the preparation process and the preparation flow of a multi-terminal-to-ground gas discharge tube are greatly simplified so as to greatly simplify the preparation process and to realize batch production and high integration of the gas discharge tube. Also provided is a preparation method for an integrated gas discharge tube. | 2016-02-18 |
20160049277 | ION BEAM SOURCE - An ion beam source includes a magnetic field unit including a first side facing a target object to be treated and a second side, where the first side is opened and the second side is closed, and the first side includes a plurality of magnetic pole portions arranged at predetermined intervals with an N-pole and an S-pole alternatively or with same magnetic poles and configured to form a closed loop of plasma electrons and an electrode unit arranged at a lower end of the closed loop. The ion beam source is configured to rotate the plasma electrons within a process chamber along the closed loop, to generate plasma ions from an internal gas within the process chamber, and to provide the plasma ions to the target object. | 2016-02-18 |
20160049278 | Apparatus for Charged Particle Lithography System - An apparatus for use in a charged particle multi-beam lithography system is disclosed. The apparatus includes a plurality of charged particle doublets each having a first aperture and each configured to demagnify a beamlet incident upon the first aperture thereby producing a demagnified beamlet. The apparatus further includes a plurality of charged particle lenses each associated with one of the charged particle doublets, each having a second aperture, and each configured to receive the demagnified beamlet from the associated charged particle doublet and to realize one of two states: a switched-on state, wherein the demagnified beamlet is allowed to travel along a desired path, and a switched-off state, wherein the demagnified beamlet is prevented from traveling along the desired path. In embodiments, the first aperture is greater than the second aperture, thereby improving particle beam efficiency in the charged particle multi-beam lithography system. | 2016-02-18 |
20160049279 | PLASMA DEVICE - A plasma device is proposed, the plasma device including a first member including a chuck unit accommodated with an antenna coil or a processed article so rotating as to generate a plasma inside a chamber, and a second member connected with a first harmonics power source, whereby a second harmonics power source that has pulsed a first harmonics power source is applied to the first member in response to the relative rotation of a first terminal of first member and a second terminal of second member. | 2016-02-18 |
20160049280 | COMPACT CONFIGURABLE MODULAR RADIO FREQUENCY MATCHING NETWORK ASSEMBLY FOR PLASMA PROCESSING SYSTEMS - A compact configurable radio frequency (RF) matching network for matching RF energy output from an RF generator to a variable impedance load is disclosed. The matching network includes an input connector; an output connector; and a component assembly array including one or more tune and load electrical components. At least one of the electrical components is coupled to the input connector, at least one of the electrical components is coupled to the output connector, the component assembly array is adapted to be arranged in a selected topology, and the selected topology is adapted to reduce RF energy reflected from the variable impedance load. Numerous other aspects are provided. | 2016-02-18 |
20160049281 | DIFFERENTIALLY PUMPED REACTIVE GAS INJECTOR - One process that may be used to remove material from a surface is ion etching. In certain cases, ion etching involves delivery of both ions and a reactive gas to a substrate. The disclosed embodiments permit local high pressure delivery of reactive gas to a substrate while maintaining a much lower pressure on portions of the substrate that are outside of the local high pressure delivery area. The low pressure is achieved by confining the high pressure reactant delivery to a small area and vacuuming away excess reactants and byproducts as they leave this small area and before they enter the larger substrate processing region. The disclosed techniques may be used to increase throughput while minimizing deleterious collisions between ions and other species present in the substrate processing region. | 2016-02-18 |
20160049282 | Data Directed Acquisition of Imaging Mass - A method of ion imaging is disclosed comprising scanning a sample at a first resolution and acquiring first mass spectral data related to a first pixel location. A determination is then made as to whether or not the first mass spectral data satisfies a condition, wherein if it is determined that the first mass spectral data does satisfy the condition then the method further comprises: (i) switching to acquire second mass spectral data related to a second pixel location which is substantially adjacent to the first pixel location so that the second mass spectral data is acquired at a second resolution which is higher than the first resolution; and (ii) determining whether or not the second mass spectral data satisfies the condition, wherein if it is determined that the second mass spectral data does satisfy the condition then the method further comprises acquiring third mass spectral data related to a third pixel location which is substantially adjacent to the first or second pixel locations so that the third mass spectral is acquired at the second resolution and wherein if it is determined that the second or third mass spectral data does not satisfy the condition then the method further comprises switching back to scanning the sample at the first resolution. | 2016-02-18 |
20160049283 | LASER ABLATION CELL - A laser ablation cell ( | 2016-02-18 |
20160049284 | METHOD FOR DETECTING AND QUANTIFYING A TARGET ANALYTE IN A SAMPLE - The invention relates to a method for identifying and quantifying by mass spectrometry at least one target analyte in a sample, comprising the following steps:
| 2016-02-18 |
20160049285 | IMPROVEMENTS IN AND RELATING TO THE PRODUCTION AND CONTROL OF IONS - Techniques are provided for generating charged droplets of liquid entrained within a gas flow within a vacuum chamber and for controlling the gas flow. The gas flow with the entrained charged droplets of liquid is jetted into the vacuum chamber along a predetermined jetting axis. The gas jet is received within a gas conduit housed within the vacuum chamber and having a conduit bore coaxial with the predetermined jetting axis. The received gas jet is caused to be restrained to form a laminar gas flow entrained with charged droplets inside of the gas conduit for guiding the entrained charged droplets therealong. | 2016-02-18 |
20160049286 | ABRIDGED ION TRAP - TIME OF FLIGHT MASS SPECTROMETER - An improved trap-TOF mass spectrometer has a set of electrodes arranged to produce both a quadrupolar RF confining field and a substantially homogeneous dipole field. In operation, ions are first confined by the RF field and then, at a selected time, the RF confining field is discontinued and the dipole field is used to accelerate the ions so as to initiate a TOF MS analysis. The apparatus of the present invention may be used alone or in conjunction with other analyzers to produce mass spectra from analyte ions. | 2016-02-18 |
20160049287 | ION TRAP ARRAY - The invention “Ion Trap Array (ITA)” pertains generally to the field of ion storage and analysis technologies, and particularly to the ion storing apparatus and mass spectrometry instruments which separate ions by its character such as mass-to-charge ratio. The aim of this invention is providing an apparatus for ion storage and analysis comprising at least two or more rows of parallel placed electrode array wherein each electrode array includes at least two or more parallel bar-shaped electrodes, by applying different phase of alternating current voltages on different bar electrodes to create alternating electric fields inside the space between two parallel electrodes of different rows of electrode arrays, multiple linear ion trapping fields paralleled constructed in the space between the different rows of electrode arrays which are open to adjacent each other without a real barrier. This invention also provides a method for ion storage and analysis involving with the trapping, cooling and mass-selected analyzing of ions by this apparatus mentioned which constructs multiple conjoint linear ion trapping fields in the space between the different rows of electrode arrays | 2016-02-18 |
20160049288 | TRANSMISSION WINDOW FOR A VACUUM ULTRAVIOLET GAS DISCHARGE LAMP - A transmission window ( | 2016-02-18 |
20160049289 | APPARATUS AND METHOD OF TREATING SURFACE OF SEMICONDUCTOR SUBSTRATE - In one embodiment, an apparatus of treating a surface of a semiconductor substrate comprises a substrate holding and rotating unit, first to fourth supplying units, and a removing unit. A substrate holding and rotating unit holds a semiconductor substrate, having a convex pattern formed on its surface, and rotates the semiconductor substrate. A first supplying unit supplies a chemical onto the surface of the semiconductor substrate in order to clean the semiconductor substrate. A second supplying unit supplies pure water to the surface of the semiconductor substrate in order to rinse the semiconductor substrate. A third supplying unit supplies a water repellent agent to the surface of the semiconductor substrate in order to form a water repellent protective film onto the surface of the convex pattern. A fourth supplying unit supplies alcohol, which is diluted with pure water, or acid water to the surface of the semiconductor substrate in order to rinse the semiconductor substrate. A removing unit removes the water repellent protective film with the convex pattern being left. | 2016-02-18 |
20160049290 | METHOD FOR MANUFACTURING SEMICONDUCTOR HEMT DEVICE WITH STOICHIMETRIC SILICON NITRIDE LAYER - A semiconductor device includes: a compound semiconductor stack structure including a plurality of compound semiconductor layers stacked over a semiconductor substrate; and a first insulating film covering the surface of the compound semiconductor stack structure, the first insulating film being a silicon nitride film including, on the top side, a first region containing nitrogen element in excess of the stoichiometric ratio. | 2016-02-18 |
20160049291 | METHOD OF FORMING THIN FILM OF SEMICONDUCTOR DEVICE - Provided is a method of forming a thin film of a semiconductor device. The method includes forming a precursor layer on a surface of a substrate by supplying a precursor gas into a chamber, discharging the precursor gas remaining in the chamber to an outside of the chamber by supplying a purge gas into the chamber, supplying a reactant gas into the chamber, generating plasma based on the reactant gas, forming a thin film by a chemical reaction between plasma and the precursor layer and radiating extreme ultraviolet (EUV) light into the chamber, and discharging the reactant gas and the plasma remaining in the chamber by supplying a purge gas into the chamber. | 2016-02-18 |
20160049292 | Semiconductor Device Manufacturing Method - There is provided a semiconductor device manufacturing method, including: a film forming process in which, by supplying a solution for modifying a surface layer of a resist to a target object having a resist pattern and allowing the solution to infiltrate into the resist, a film having elasticity and having no compatibility with the resist is formed in the surface layer of the resist; and a heating process in which the target object having the film formed thereon is heated. | 2016-02-18 |
20160049293 | METHOD AND COMPOSITION FOR PROVIDING PORE SEALING LAYER ON POROUS LOW DIELECTRIC CONSTANT FILMS - Described herein is a method and composition comprising same for sealing the pores of a porous low dielectric constant (“low k”) layer by providing an additional thin dielectric film, referred to herein as a pore sealing layer, on at least a surface of the porous, low k layer to prevent further loss of dielectric constant of the underlying layer. In one aspect, the method comprises: contacting a porous low dielectric constant film with at least one organosilicon compound to provide an absorbed organosilicon compound and treating the absorbed organosilicon compound with ultraviolet light, plasma, or both, and repeating until a desired thickness of the pore sealing layer is formed. | 2016-02-18 |
20160049294 | Mixed Lithography Approach for E-Beam and Optical Exposure Using HSQ - In one aspect, a method of forming a wiring layer on a wafer is provided which includes: depositing a HSQ layer onto the wafer; cross-linking a first portion(s) of the HSQ layer using e-beam lithography; depositing a hardmask material onto the HSQ layer; patterning the hardmask using optical lithography, wherein the patterned hardmask covers a second portion(s) of the HSQ layer; patterning the HSQ layer using the patterned hardmask in a manner such that i) the first portion(s) of the HSQ layer remain and ii) the second portion(s) of the HSQ layer covered by the patterned hardmask remain, wherein by way of the patterning step trenches are formed in the HSQ layer; and filling the trenches with a conductive material to form the wiring layer on the wafer. | 2016-02-18 |
20160049295 | METHOD FOR TREATING A SUBSTRATE AND A SUBSTRATE - A method for treating a compound semiconductor substrate, in which method in vacuum conditions a surface of an In-containing III-As, III-Sb or III-P substrate is cleaned from amorphous native oxides and after that the cleaned substrate is heated to a temperature of about 250-550° C. and oxidized by introducing oxygen gas onto the surface of the substrate. The invention relates also to a compound semiconductor substrate, and the use of the substrate in a structure of a transistor such as MOSFET. | 2016-02-18 |
20160049296 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes carrying out an anodic oxidation of a surface region of a semiconductor substrate to form an oxide layer at a surface of the semiconductor substrate by generating an attracting electrical field between the semiconductor substrate and an external electrode within an electrolyte to attract oxidizing ions of the electrolyte, causing an oxidation of the surface region of the semiconductor substrate. Further, the method includes reducing the number of remaining oxidizing ions within the oxide layer, while the semiconductor substrate is within an electrolyte. | 2016-02-18 |
20160049297 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENT, AND ELECTRONIC COMPONENT - Provided is a method for producing an electronic component, which is capable of forming a cured adhesive layer easily with high accuracy. | 2016-02-18 |
20160049298 | METHOD OF FORMING GERMANIUM FILM AND APPARATUS THEREFOR - There is provided a method of forming a germanium (Ge) film on a surface of a target object, which includes: supplying an aminosilane-based gas into a processing chamber in which the target object is loaded; supplying a high-order silane-based gas of disilane or higher into the processing chamber; and supplying a Ge source gas into the processing chamber. A process temperature in supplying the Ge source gas is set to fall within a range from a temperature, at which the Ge source gas is thermally decomposed or higher, to 300 degrees C. or less. | 2016-02-18 |
20160049299 | Growing III-V Compound Semiconductors from Trenches Filled with Intermediate Layers - A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars. | 2016-02-18 |
20160049300 | METHOD AND APPARATUS FOR MANUFACTURING LOW TEMPERATURE POLY-SILICON FILM, AND LOW TEMPERATURE POLY-SILICON FILM - Disclosed are a method and an apparatus for manufacturing low temperature poly-silicon film, and a low temperature poly-silicon film. The method includes: providing a substrate; forming an amorphous silicon film; applying different temperatures to different regions of the amorphous silicon film by using an excimer laser annealing method, to change the amorphous silicon film into a molten state; and recrystallizating the amorphous silicon film in the molten state, a region having a lower temperature serving as a starting point, a region having a higher temperature serving as an end point, to form a low temperature poly-silicon film. The low temperature poly-silicon film manufactured by the above method and apparatus has a greater size of the crystalline grain and a larger electronic mobility than in the existing technology. | 2016-02-18 |
20160049301 | Method of Tuning Work Function for A Semiconductor Device - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes forming pre-tuned-work-function (preTWF) layer over a substrate, applying an angular-doping process to the preTWF layer to change a work function of the preTWF layer (referred to as a tuned work function (TWF) layer). The angular-doping process includes injecting a doping species beam to the preTWF layer with a distribution of injecting angle and forming a metal fill layer over the TWF layer. | 2016-02-18 |
20160049302 | METHOD OF FORMING A SEMICONDUCTOR CIRCUIT ELEMENT AND SEMICONDUCTOR CIRCUIT ELEMENT - The present disclosure provides a method of forming a semiconductor circuit element and a semiconductor circuit element, wherein the semiconductor circuit element is formed on the basis of a replacement gate process replacing a dummy gate structure of a semiconductor device of the semiconductor circuit element by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a high-k material that is in the ferroelectric phase. In some illustrative embodiments herein, a semiconductor device is provided, the semiconductor device having a gate structure disposed over an active region of a semiconductor substrate. Herein, the gate structure comprises a spacer structure and a dummy gate structure which is replaced by a gate oxide structure and a gate electrode material, wherein the gate oxide structure comprises a ferroelectric high-k material. | 2016-02-18 |
20160049303 | METHOD FOR FORMING A MEMORY STRUCTURE HAVING NANOCRYSTALS - A method of forming a semiconductor structure uses a substrate. A first insulating layer is formed over the substrate. An amorphous silicon layer is formed over the first insulating layer. Heat is applied to the amorphous silicon layer to form a plurality of seed nanocrystals over the first insulating layer. Silicon is epitaxially grown on the plurality of seed nanocrystals to leave resulting nanocrystals. | 2016-02-18 |
20160049304 | SYSTEM, METHOD AND APPARATUS FOR PLASMA ETCH HAVING INDEPENDENT CONTROL OF ION GENERATION AND DISSOCIATION OF PROCESS GAS - A method of etching a wafer includes injecting a source gas mixture into a process chamber. The injecting includes injecting the source gas into multiple hollow cathode cavities in a top electrode, generating plasma in each of the cavities, and outputting the plasma from corresponding outlets of the cavities into a wafer processing region in the chamber, where the processing region is located between the outlets and a surface to be etched. An etchant gas mixture is injected into the processing region through injection ports in the top electrode such that the etchant gas mixes with the plasma output from the outlets. The etchant gas is prevented from flowing into the outlets of the cavities by the plasma flowing from the outlets. Mixing the etchant gas and the output from the cavities generates a desired chemical species in the processing region and thereby enables the surface to be etched. | 2016-02-18 |
20160049305 | METHOD FOR CRITICAL DIMENSION REDUCTION USING CONFORMAL CARBON FILMS - Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded. | 2016-02-18 |
20160049306 | Methods of Manufacturing Semiconductor Device - The present inventive concept provides methods of manufacturing a semiconductor device including forming an inner mask layer on an etching target film, the inner mask layer including a polymer; forming a porous film on the etching target film, the porous film covering the inner mask layer; supplying an acid source to an outer surface area of the inner mask layer through the porous film; inducing a chemical reaction of the polymer included in the inner mask layer in the outer surface area by using the acid source; forming inner mask patterns by removing a chemically reacted portion of the inner mask layer; and etching the etching target film by using at least a portion of the porous film and the inner mask patterns as an etching mask. | 2016-02-18 |
20160049307 | Patterning method for IC fabrication using 2-D layout decomposition and synthesis techniques - Various multiple-mask patterning methods by employing the layout decomposition and stitching technique are invented. The inventions pertain to methods of decomposing and synthesizing two-dimensional features on a substrate having the feature density increased to multiple times (up to eight times) of what is possible using the standard optical lithographic technique; and methods to release the overlay requirement when patterning the critical layers of semiconductor devices. The invented processes allow IC designers to pattern random two-dimensional circuit features that are beyond the resolution capability of optical lithography. They provide production-worthy methods for the semiconductor industry to continue IC scaling beyond the half pitch of 10 nm. | 2016-02-18 |
20160049308 | SUBSTRATE PROCESSING METHOD - A substrate processing method includes a phosphoric acid processing step of supplying a phosphoric acid aqueous solution, which contains silicon and has a silicon concentration lower than a saturation concentration, to a front surface of a substrate, a liquid volume reducing step of reducing a volume of the phosphoric acid aqueous solution on the substrate, after the phosphoric acid processing step, and a rinse replacing step of supplying a rinse liquid having a temperature lower than that of the phosphoric acid aqueous solution supplied to the front surface of the substrate in the phosphoric acid processing step to the front surface of the substrate covered with the phosphoric acid aqueous solution at least partially, after the liquid volume reducing step. | 2016-02-18 |
20160049309 | Substrate Processing Method - A method for passivating a surface of a semiconductor substrate with fluorine-based layer to protect the surface against oxidation and allow longer queue times. According to one embodiment, the method includes providing a substrate having an oxidized layer formed thereon, replacing the oxidized layer with a fluorine-based layer, exposing the fluorine-based layer to an oxidizing atmosphere, where the fluorine-based layer protects the substrate against oxidation by the oxidizing atmosphere, and removing the fluorine-based layer from the substrate using a plasma process. According to another embodiment, the method includes providing a passivated substrate in a vacuum processing tool, the passivated substrate having a fluorine-based layer thereon that is effective for protecting the passivated substrate against oxidation by an oxidizing atmosphere, removing the fluorine-based layer from the passivated substrate using a microwave plasma process in the vacuum processing tool, thereby forming a clean substrate, and processing the clean substrate under vacuum conditions. | 2016-02-18 |
20160049310 | Method for Selective Oxide Removal - A method for removing oxide selective to a material comprising at least silicon and at least nitrogen is disclosed, the method comprising providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising at least silicon and at least nitrogen, providing on said structure an oxide layer overlying at least a part of said region, and removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid part of said region, wherein said etching is done only by providing an etchant gas comprising boron, whereby a voltage bias lower than 30 V is applied to the structure. | 2016-02-18 |
20160049311 | WAFER BACKSIDE PARTICLE MITIGATION - A method of particle mitigation which includes obtaining a semiconductor wafer having a nonfunctional backside and a functional frontside on which semiconductor devices are formed by one or more lithography processes; coating the backside with a layer comprising silicon or amorphous carbon; planarizing the coated backside by a planarizing process; placing the semiconductor wafer onto a wafer chuck such that the wafer chuck makes direct contact with the coated backside; and while maintaining the coated backside in direct contact with the wafer chuck, performing a first lithographic process on the frontside. | 2016-02-18 |
20160049312 | PLASMA TREATING APPARATUS, SUBSTRATE TREATING METHOD, AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A substrate treating method may be performed by a plasma treating apparatus. The substrate treating method may include: providing a substrate on a platform in a lower portion of an inner space of a process chamber; directing a first process gas upward from a first nozzle formed at an inner wall of the process chamber into an upper portion of the inner space, the first process gas being an inert gas and wherein the first nozzle is an obliquely upward-oriented nozzle structured to direct the first process gas upward; directing a second process gas downward from a second nozzle formed at a inner wall of the process chamber into a lower portion of the inner space, the second process gas being hydrogen gas and wherein the second nozzle is an obliquely downward-oriented nozzle structured to direct the second process gas downward; and applying a microwave to the upper portion of the inner space to excite the first process gas and the second process gas into plasma, and then processing the substrate. | 2016-02-18 |
20160049313 | METHOD OF OUTGASSING A MASK MATERIAL DEPOSITED OVER A WORKPIECE IN A PROCESS TOOL - Embodiments of the invention include methods and apparatuses for outgassing a workpiece prior to a plasma processing operation. An embodiment of the invention may comprise transferring a workpiece having a mask to an outgassing station that has one or more heating elements. The workpiece may then be heated to an outgassing temperature that causes moisture from the mask layer to be outgassed. After outgassing the workpiece, the workpiece may be transferred to a plasma processing chamber. In an additional embodiment, one or more outgassing stations may be located within a process tool that has a factory interface, a load lock coupled to the factory interface, a transfer chamber coupled to the load lock, and a plasma processing chamber coupled to the transfer chamber. According to an embodiment, an outgassing station may be located within any of the components of the process tool. | 2016-02-18 |
20160049314 | ETCHING METHOD - An etching method for etching an object to be processed in a processing chamber including a first electrode and a second electrode disposed facing the first electrode and configured to receive the object to be processed thereon is provided that includes steps of intermittently supplying first high frequency power to either the first electrode or the second electrode while supplying second high frequency power lower than the first high frequency power to the second electrode, supplying a process gas containing hydrogen bromide HBr and oxygen O | 2016-02-18 |
20160049315 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A conventional semiconductor device used for a power supply circuit such as a DC/DC converter has problems of heat dissipation and downsizing, in particular has the problems of heat dissipation and others in the event of downsizing. A semiconductor device has a structure formed by covering a principal surface of a semiconductor chip having the principal surface and a plurality of MIS type FETs formed over the principal surface with a plurality of metal plate wires having pectinate shapes; allocating the pectinate parts alternately in a planar view over the principal surface; and further electrically coupling the plural metal plate wires to a plurality of terminals. | 2016-02-18 |
20160049316 | EMBEDDED PACKAGE IN PCB BUILD UP - An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device. | 2016-02-18 |
20160049317 | SUBSTRATE SUPPORTING UNIT, SUBSTRATE PROCESSING APPARATUS, AND METHOD OF MANUFACTURING SUBSTRATE SUPPORTING UNIT - A substrate supporting unit, a substrate processing apparatus, and a method of manufacturing the substrate supporting unit are provided. The substrate supporting unit includes a susceptor provided with heaters to heat a substrate placed on the susceptor, and including a first temperature region and a second temperature region having a higher temperature than that of the first temperature region; a heat dissipating member including a contact surface being in thermal contact with the second temperature region; and a reflecting member disposed approximately in parallel with one surface of the susceptor to reflect heat emitted from the susceptor toward the susceptor. | 2016-02-18 |
20160049318 | FLOATING MOLD TOOL FOR SEMICONDCUTOR PACKAGING - Tooling for molding a packaged semiconductor device includes a clamping plate, a cavity bar, and an attachment mechanism. The cavity bar has a mold half that has a mold cavity for molding the packaged semiconductor device. The mold half has teeth and a space between pairs of adjacent teeth. The teeth and the spaces support bending of leads of a lead frame of the packaged semiconductor device. The attachment mechanism affixes the cavity bar to the clamping plate and permits the cavity bar to slide relative to the clamping plate. This sliding of the cavity bar enables proper alignment with a mating cavity bar to reduce the likelihood of resin bleed. | 2016-02-18 |
20160049319 | PACKAGING INSERT - A packaging insert includes a frame that is configured to occupy a selected amount of space within a container at least in an area corresponding to a periphery of the container contents, such as silicon wafers. The packing insert includes a plurality of spring members projecting from the frame at an oblique angle relative to a reference surface on the frame. The spring members are configured to flex or move responsive to contact with a surface on the container as the container is closed. The resiliency of the spring members provides a secure positioning of the packaging insert within the container that facilitates maintaining the contents of the container, such as silicon wafers, in a desired condition within the container. | 2016-02-18 |
20160049320 | WAFER CARRIER - A wafer carrier comprises a body part constructed and arranged to accommodate a wafer and including first and second layers which are stacked in sequence. A cover is mountable to the body part. A first air filter is positioned on the cover. A second air filter is positioned on a side of the body part. The second layer is positioned between the first layer and an inner region of the body part. A surface of the second layer facing the inner region is subjected to charge prevention processing. | 2016-02-18 |
20160049321 | SEMICONDUCTOR BAKING APPARATUS AND OPERATION METHOD THEREOF - A semiconductor baking apparatus includes a load lock chamber, a process chamber, a transfer chamber, a first interior door, and a controller. The process chamber has a first accommodating space therein. The transfer chamber has a second accommodating space therein, and the transfer chamber is connected to the load lock chamber and the process chamber. The first interior door is between the process chamber and the transfer chamber. When the first interior door is opened, the first accommodating space is communicated with the second accommodating space. The controller is programmed to open the first interior door when the semiconductor baking apparatus idles. | 2016-02-18 |
20160049322 | CONTAINER OPENING/CLOSING DEVICE - The present invention provides a container opening/closing device for opening and closing a lid of a container. The container comprises a container body including an opening and the lid detachably attached to the opening. The device comprises an opening/closing mechanism including a holding portion for holding the lid and a pressing mechanism. The opening/closing mechanism opens and closes the opening by moving the holding portion between a closing position and an open position. The pressing mechanism presses a peripheral edge of the holding portion toward the container body when the opening/closing mechanism moves the lid from the open position to the closing position. | 2016-02-18 |
20160049323 | METHOD AND APPARATUS OF PROCESSING WAFERS WITH COMPRESSIVE OR TENSILE STRESS AT ELEVATED TEMPERATURES IN A PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION SYSTEM - Embodiments of the present disclosure provide an electrostatic chuck for maintaining a flatness of a substrate being processed in a plasma reactor at high temperatures. In one embodiment, the electrostatic chuck comprises a chuck body coupled to a support stem, the chuck body having a substrate supporting surface, and the chuck body has a volume resistivity value of about 1×10 | 2016-02-18 |
20160049324 | STACK, METHOD FOR TREATING SUBSTRATE MATERIAL, TEMPORARY FIXING COMPOSITION, AND SEMICONDUCTOR DEVICE - A stack includes a substrate material that has a circuit surface and that is temporarily fixed on a support via a temporary fixing material. The temporary fixing material includes a temporary fixing material layer (I) that is in contact with the circuit surface of the substrate material and a temporary fixing material layer (II) that is formed on the support-facing surface of the layer (I). The temporary fixing material layer (I) is formed of a temporary fixing composition (i) that includes a thermoplastic resin (Ai), a polyfunctional (meth)acrylate compound (Bi), and a radical polymerization initiator (Ci), and the temporary fixing material layer (II) is formed of a temporary fixing composition (ii) that includes a thermoplastic resin (Aii) and a release agent (Dii). | 2016-02-18 |
20160049325 | ASSEMBLY FOR HANDLING A SEMICONDUCTOR DIE AND METHOD OF HANDLING A SEMICONDUCTOR DIE - In various embodiments, an assembly for handling a semiconductor die is provided. The assembly may include a carrier with a surface. The assembly may also include an adhesive tape fixed to the surface of the carrier. The adhesive tape may be configured to adhere to the semiconductor die. The adhesive tape may include adhesive, the adhesion of which can be reduced by means of electromagnetic waves. The assembly may further include an electromagnetic source configured to apply electromagnetic waves to the adhesive tape to reduce adhesion of the adhesive tape to the semiconductor die. The assembly may additionally include a die pick-up component configured to pick up the semiconductor die from the adhesive tape. | 2016-02-18 |
20160049326 | TRANSFER UNIT - A transfer unit transferring a wafer from or to a cassette is provided. The transfer unit includes a holding portion holding the wafer under suction and a driving portion moving the holding portion. The holding portion includes a body, a plurality of suction openings formed on the upper surface of the body so as to be spaced from each other, a vacuum transmitting passage connected to a vacuum source for transmitting a vacuum from the vacuum source to the suction openings, and a plurality of suction pads provided at the suction openings, each suction pad being formed of an elastic material. The suction openings are spaced from each other in the radial direction of the wafer, and the suction pads are selectively provided at any desired ones of the suction openings. | 2016-02-18 |
20160049327 | METHODS OF FABRICATING BEOL INTERLAYER STRUCTURES - Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s). | 2016-02-18 |
20160049328 | METHOD FOR IMPROVING ADHESION BETWEEN POROUS LOW K DIELECTRIC AND BARRIER LAYER - A semiconductor device and method for manufacturing the same are provided. The method includes providing a semiconductor substrate, forming a porous low-k dielectric layer on the semiconductor substrate, forming a through-hole and a trench of a copper interconnect structure, performing a helium plasma treatment on an exposed surface of the porous low-k dielectric layer, performing a nitrogen plasma treatment on the exposed surface of the porous low-k dielectric layer to form a silicon nitride layer, performing an argon plasma treatment on the silicon nitride layer, and forming a diffusion barrier layer on bottoms and sidewalls of the through-hole and the trench of the copper interconnect structure. Through the successive helium, nitrogen and argon plasma treatments, the low-k dielectric layer has a smooth and dense surface that increases the adhesion strength between the low-k dielectric layer and the diffusion barrier layer to improve reliability and yield of the semiconductor device. | 2016-02-18 |
20160049329 | Long-term heat treated integrated circuit arrangements and methods for producing the same - An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment. | 2016-02-18 |
20160049330 | STRUCTURE AND FORMATION METHOD OF DAMASCENE STRUCTURE - A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate. The semiconductor device structure further includes a conductive via surrounded by the dielectric layer and electrically connected to the conductive feature. The conductive via has a lower end and an upper end larger than the lower end, and the conductive via has a side surface curved inward. | 2016-02-18 |
20160049331 | INTEGRATED CLUSTER TO ENABLE NEXT GENERATION INTERCONNECT - Embodiments of the present invention generally relate to methods for forming a metal structure and passivation layers. In one embodiment, metal columns are formed on a substrate. The metal columns are doped with manganese, aluminum, zirconium, or hafnium. A dielectric material is deposited over and between the metal columns and then cured to form a passivation layer on vertical surfaces of the metal columns. | 2016-02-18 |
20160049332 | METHODS OF FORMING CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES - One method disclosed herein includes, among other things, a method of forming a contact structure to a source/drain region of a transistor device. The transistor device includes a gate structure and a gate cap layer positioned above the gate structure. The method includes forming an extended-height epi contact structure that is conductively coupled to the source/drain region. The extended-height epi contact structure includes an upper surface that is positioned at a height level that is above a height level of an upper surface of the gate cap layer. The method further includes performing an etching process to trim at least a lateral width of a portion of the extended-height epi contact structure, and, after performing the etching process, forming a metal silicide material on at least a portion of the trimmed extended-height epi contact structure and forming a conductive contact on the metal silicide material. | 2016-02-18 |
20160049333 | DESIGN METHOD OF TIP SHAPE OF CUTTING MEMBER, SEMICONDUCTOR CHIP MANUFACTURING METHOD, CIRCUIT BOARD, AND ELECTRONIC APPARATUS - A design method includes a process of preparing plural cutting members having different degrees of taper in a tip portion thereof, a process of preparing plural grooves on a front surface side having the same shape, a process of confirming a breakage status when a groove on a rear surface side is formed by the plural cutting members, and a process of selecting, when it is confirmed that both of a cutting member that causes breakage and a cutting member that does not cause the breakage are included, the degree of taper of the cutting member that does not cause the breakage as a tip shape of a cutting member to be used in a mass production process. | 2016-02-18 |
20160049334 | TAPE-BASED EPITAXIAL LIFT OFF APPARATUSES AND METHODS - Embodiments of the invention generally relate to apparatuses and methods for producing epitaxial thin films and devices by epitaxial lift off (ELO) processes. In one embodiment, a method for forming thin film devices during an ELO process is provided which includes coupling a plurality of substrates to an elongated support tape, wherein each substrate contains an epitaxial film disposed over a sacrificial layer disposed over a wafer, exposing the substrates to an etchant during an etching process while moving the elongated support tape, and etching the sacrificial layers and peeling the epitaxial films from the wafers while moving the elongated support tape. Embodiments also include several apparatuses, continuous-type as well as a batch-type apparatuses, for forming the epitaxial thin films and devices, including an apparatus for removing the support tape and epitaxial films from the wafers on which the epitaxial films were grown. | 2016-02-18 |
20160049335 | METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE - Methods for manufacturing a semiconductor device including a field effect transistor include forming first fins protruding from a substrate including a first region and a second region, the first fins including silicon-germanium (SiGe), forming a first mask pattern to expose the first fins disposed in the second region, the first mask pattern covering the first fins disposed in the first region, oxidizing the first fins in the second region to form second fins in the second region, and forming germanium (Ge)-rich layers each disposed on a surface of a respective one of the second fins. | 2016-02-18 |
20160049336 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a trench defining a plurality of active fins in a substrate, forming a sacrificial layer on the plurality of active fins, forming a sacrificial oxide layer, and removing the sacrificial oxide layer. The forming the sacrificial oxide layer includes heat-treating the sacrificial layer and surfaces of the plurality of active fins. | 2016-02-18 |
20160049337 | METHOD OF PATTERNING DOPANT FILMS IN HIGH-K DIELECTRICS IN A SOFT MASK INTEGRATION SCHEME - A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch. | 2016-02-18 |
20160049338 | STRUCTURE AND METHOD FOR FINFET DEVICE - The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner. | 2016-02-18 |
20160049339 | BLOCK PATTERNING PROCESS FOR POST FIN - A method of reducing etch time needed for patterning an organic planarization layer (OPL) in a block mask stack so as to minimize damages to gate structures and fin structures in a block mask patterning process is provided. The block mask stack including an OPL, a developable antireflective coating (DARC) layer atop the OPL and a photoresist layer atop the DARC layer is employed to mask one conductivity type of FinFET while exposing the other conductivity type FinFET during source/drain ion implantation. The OPL is configured to have a minimum thickness sufficient to fill in spaces between semiconductor fins and to cover the semiconductor fins. The DARC layer is configured to planarize topography of semiconductor fins so as to provide a planar top surface for the ensuing lithography and etch processes. | 2016-02-18 |
20160049340 | STRESS SENSOR FOR A SEMICONDUCTOR DEVICE - In a particular embodiment, an apparatus includes a stress sensor located on a first side of a semiconductor device. The apparatus further includes circuitry located on a second side of the semiconductor device. The stress sensor is configured to detect stress at the semiconductor device. In another particular embodiment, a method includes receiving data from a stress sensor located on a first side of a packaged semiconductor device. The packaged semiconductor device includes circuitry located on a second side of the packaged semiconductor device. The data indicates stress detected by the stress sensor. The method further includes performing a test associated with the packaged semiconductor device based on the data. | 2016-02-18 |
20160049341 | INTEGRATED CIRCUIT CHIP WITH CORRECTED TEMPERATURE DRIFT - An integrated circuit chip includes trenches at least partially surrounding a critical portion of a circuit that is sensitive to temperature variations. The trenches are locally interrupted in order to permit circuit connections to pass between the critical portion and an outer portion containing a remainder of the circuit. The critical portion includes heating resistors and a temperature sensor. | 2016-02-18 |
20160049342 | Module Arrangement For Power Semiconductor Devices - A module arrangement for power semiconductor devices, including one or more power semiconductor modules, wherein the one or more power semiconductor modules include a substrate with a first surface and a second surface being arranged opposite to the first surface, wherein the substrate is at least partially electrically insulating, wherein a conductive structure is arranged at the first surface of the substrate, wherein at least one power semiconductor device is arranged on the conductive structure and electrically connected thereto, wherein the one or more modules includes an inner volume for receiving the at least one power semiconductor device which volume is hermetically sealed from its surrounding by a module enclosure, wherein the module arrangement includes an arrangement enclosure at least partly defining a volume for receiving the one or more modules, and wherein the arrangement enclosure seals covers the volume. | 2016-02-18 |
20160049343 | METHOD FOR MANUFACTURING COMPOSITE BODY AND COMPOSITION - Provided is a method for manufacturing a composite body, the method containing: a composition preparation process of preparing a composition that contains a polymer having a cationic functional group and having a weight average molecular weight of from 2,000 to 1,000,000, and that has a pH of from 2.0 to 11.0; a composite member preparation process of preparing a composite member that includes a member A and a member B, a surface of the member B having a defined isoelectric point, and that satisfies a relationship: the isoelectric point of a surface of the member B< the pH of the composition2016-02-18 | |
20160049344 | Wafer Level Overmold for Three Dimensional Surfaces - Embodiments of the invention include a method for shaping a flexible integrated circuit to a curvature and the resulting structure. A flexible circuit is provided. An epoxy resin and amine composition is deposited on the flexible integrated circuit. The deposited epoxy resin and amine composition is B-staged. The flexible integrated circuit is placed within a mold of a curvature. The B-staged epoxy resin and amine composition is cured subsequent to placing the flexible integrated circuit within the mold of the curvature. | 2016-02-18 |
20160049345 | LOW-STRESS DUAL UNDERFILL PACKAGING - The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses, improving adhesion properties, and reducing thermal resistance in flip chip packages by using more than one underfill material deposited in different regions of the flip chip interface. According to one embodiment, a method of forming a first underfill in an interior region of an interface such that a periphery region of the interface remains open, and forming a second underfill in the periphery region is disclosed. | 2016-02-18 |
20160049346 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds. | 2016-02-18 |
20160049347 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer made of nitride semiconductor, an ohmic electrode and a schottky electrode both formed on the semiconductor layer, a first insulating film containing a small amount of hydrogen per unit volume for covering the semiconductor device on a top face defined between the ohmic electrode and the schottky electrode and also covering the schottky electrode, and a second insulating film formed on the first insulating film and containing a greater amount of hydrogen per unit volume than the first insulating film. | 2016-02-18 |
20160049348 | SEMICONDUCTOR BORDER PROTECTION SEALANT - A semiconductor package includes a semiconductor unit containing an active circuitry layer. The semiconductor package also includes a plurality of bonding pads on the active circuitry layer, which are configured to be connected to corresponding external conductive connectors. The semiconductor package also includes a protective sealant coating filling grooved edges of the active circuitry layer. The protective sealant coating contains an exterior wafer-singulated surface. | 2016-02-18 |
20160049349 | SYSTEMS AND METHODS FOR THERMAL DISSIPATION - A package on package semiconductor structure includes a first package positioned above a first surface of a substrate, a second package positioned above the first package, and a first thermal element positioned between the first package and the second package, wherein the first thermal element is separated from the second package by an air gap and the thermal element provides a heat path for heat generated by the first package. | 2016-02-18 |
20160049350 | SEMICONDUCTOR DEVICE AND HEAT-DISSIPATING MECHANISM - A semiconductor device includes a semiconductor chip which can be a heat-generating semiconductor chip or a semiconductor relay substrate in which an integrated circuit or wiring is built in. A sintered-silver-coated film is adhered on a surface layer part of the semiconductor substrate, interposed by a silicon oxide film. A heat-dissipating fin (heat sink), which may be copper or aluminum, is bonded on the sintered-silver-coated film, interposed by an adhesive layer. | 2016-02-18 |
20160049351 | High-Power Electronic Device Packages and Methods - A high power electronic device package constructed to include a high power electronic device having an epitaxial surface attached to a thermally conductive submount by a thermally conductive interface layer having a eutectic metal contact therein. A gallium nitride high electron mobility transistor (GaN HEMT) having a transistor structure formed of a GaN thin film layer bonded to a thermally conductive host substrate via a thermally conductive interface layer disposed therebetween, and a method of forming the GaN HEMT. The GaN HEMTs can be used in such applications as, for example, power amplifiers with x-band radio frequency (RF) power outputs for micro-radar applications. | 2016-02-18 |
20160049352 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 2016-02-18 |
20160049353 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in an upper surface of the casing, and forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. | 2016-02-18 |
20160049354 | POWER SEMICONDUCTOR MODULE AND METHOD FOR COOLING POWER SEMICONDUCTOR MODULE - The present disclosure relates to a power semiconductor module comprising a printed circuit board (PCB), and to method of cooling such a power semiconductor module. The module comprises a power semiconductor device and an island of thermally conducting foam embedded into the printed circuit board. The power semiconductor device and the island of thermally conducting foam are positioned on top of each other, and the island is arranged to form a path for a flowing coolant cooling the power semiconductor device. | 2016-02-18 |
20160049355 | Thinned Processed Wafer Having Devices and Vias and Related Method - A semiconductor wafer having a plurality of through substrate vias (TSVs) is disclosed. The semiconductor wafer includes a stepped support ring on an outer edge of the semiconductor wafer, a usable back side region of the semiconductor wafer substantially enclosed by the stepped support ring, and the plurality of TSVs extending from a front side of the semiconductor wafer to the usable back side region of the semiconductor wafer. The stepped support ring includes a step between an outer ring and an inner ring of the stepped support ring. The semiconductor wafer further includes a back side metal on the usable back side region of the semiconductor wafer, a plurality of semiconductor devices on the front side of the semiconductor wafer, where at least one of the plurality of semiconductor devices is coupled to the back side metal through at least one of the plurality of TSVs. | 2016-02-18 |
20160049356 | CHIP-ON-FILM PACKAGE HAVING BENDING PART - A chip-on-film package comprises a film substrate comprising upper and lower surfaces, and a side having a bending part. A first output interconnection formed on the upper surface of the film substrate extends from a semiconductor chip disposed on the upper surface toward the bending part. A second output interconnection includes an upper output interconnection formed on the upper surface of the film substrate, and a lower output interconnection formed on the lower surface and extending onto the bending part. An input interconnection includes an upper input interconnection formed on the upper surface of the film substrate and a lower input interconnection formed on the lower surface and extending away from the bending part. Through-vias are formed to pass through the film substrate and electrically connect the upper output interconnection to the lower output interconnection, and the upper input interconnection to the lower input interconnection. | 2016-02-18 |
20160049357 | THIN PLASTIC LEADLESS PACKAGE WITH EXPOSED METAL DIE PADDLE - A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps. The electronic package includes a leadframe having a plurality of leads, wherein each of the leads has a lead tip, an opening formed within the leadframe, a die paddle that is disposed within the opening and is isolated from each of the lead tips, a tape that is adhered to a back side of the leadframe, leads, and die paddle, and a die, wherein the die is attached to the die paddle and is connected by wires to a bump disposed on each of the lead tips. | 2016-02-18 |
20160049358 | ELECTRONIC CIRCUIT, PRODUCTION METHOD THEREOF, AND ELECTRONIC COMPONENT - An electronic circuit according to this invention includes a printed circuit board and an electronic component that is soldered onto the printed circuit board. The electronic component is a flat package including a die pad exposed to outside and external electrode terminals. A gap is provided between the printed circuit board and the electronic component. The printed circuit board is provided with a hole between the die pad and the external electrode terminals in planar view. The gap is filled with insulating resin at least partially between the die pad and the external electrode terminals. The insulating resin is injected through the hole. | 2016-02-18 |
20160049359 | INTERPOSER WITH CONDUCTIVE POST AND FABRICATION METHOD THEREOF - An interposer is provided, including a substrate body, a plurality of conductive posts formed in the substrate body, and a plurality of conductive pads formed on the substrate body and electrically connected to the conductive posts. The conductive pads and the conductive posts are integrally formed. As such, no interface is formed between the conductive pads and the conductive posts, thereby preventing delamination or cracking from occurring between the conductive pads and the conductive posts. | 2016-02-18 |
20160049360 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and including an upper portion formed on a side of the chip, a lower portion formed on another side of the chip, and a cooling inlet and a cooling outlet for transferring a coolant, provided in an upper surface of the casing, and forming outer sidewalls of the upper portion and inner sidewalls of the lower portion, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. | 2016-02-18 |
20160049361 | MAKING ELECTRICAL COMPONENTS IN HANDLE WAFERS OF INTEGRATED CIRCUIT PACKAGES - A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond. | 2016-02-18 |
20160049362 | Interconnect Structure and Method of Forming the Same - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate; a dielectric layer over the contact layer, wherein the dielectric layer has an opening, the opening exposing a portion of the contact layer; a silicide layer over the exposed portion of the contact layer; a barrier layer along sidewalls of the opening; an alloy layer over the barrier layer; a glue layer over the alloy layer; and a conductive plug over the glue layer. | 2016-02-18 |
20160049363 | Semiconductor Device and Method - A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved. | 2016-02-18 |
20160049364 | INTERCONNECT STRUCTURES WITH FULLY ALIGNED VIAS - A method of forming a fully aligned via connecting two metal lines on different Mx levels by forming a recessed opening above a first metal line in a first ILD; forming a cap on the first ILD and in the recessed openings; forming a second ILD on the cap; forming a metal trench hardmask above the second ILD, forming a metal trench pattern in the metal trench hardmask; forming a via pattern that is self aligned to the metal trench pattern and above a portion of the first metal line; forming a via opening exposing the first metal line by transferring the via pattern and metal trench pattern to lower levels, the via pattern is self-aligned to the recessed opening; and forming a via and a third metal line in the via opening and the transferred metal trench pattern, respectively. | 2016-02-18 |