07th week of 2015 patent applcation highlights part 17 |
Patent application number | Title | Published |
20150041881 | Embedded SONOS Based Memory Cells - A memory device that includes a non-volatile memory (NVM) transistor which has an indium doped channel and a gate stack overlying the channel formed in a first region of a substrate and a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate in which the gate oxide of the MOS and the oxide layer of the NVM transistor are formed concurrently. | 2015-02-12 |
20150041882 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer. | 2015-02-12 |
20150041883 | SEMICONDUCTOR DEVICE - An object of the present invention is to improve the ESD resistance of an electrostatic protection element. | 2015-02-12 |
20150041884 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a power semiconductor device including: a first semiconductor region of a first conductivity type; second semiconductor regions formed in the first semiconductor region and being of a second conductivity type; a well region formed above the second semiconductor regions and being of the second conductivity type; and a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers formed from a lower portion of the device extending a in a direction of height of the device, and in the case that the widest width of the of the second semiconductor region of the n | 2015-02-12 |
20150041885 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate. | 2015-02-12 |
20150041886 | VERTICAL POWER TRANSISTOR DEVICE - A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer. | 2015-02-12 |
20150041887 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor layer surrounding a bottom of the trench gate, a second semiconductor layer disposed along one of end portions of the trench gate in a longitudinal direction of the trench gate, one of end portions of the second semiconductor layer contacting the body layer and the other of the end portions of the second semiconductor layer contacting the first semiconductor layer, and a connecting layer, one of end portions of the connecting layer being connected to the body layer and the other of the end portions of the connecting layer being connected to the first semiconductor layer, the connecting layer contacting the second semiconductor layer, and the connecting layer being separated from the one of the end portions of the trench gate in the longitudinal direction of the trench gate by the second semiconductor layer. | 2015-02-12 |
20150041888 | SEMICONDUCTOR DEVICE INCLUDING BURIED BIT LINE, AND ELECTRONIC DEVICE USING THE SAME - A semiconductor device includes: an active region defined by a device isolation film, an upper portion of which is divided into a first active pillar and a second active pillar; a first gate formed to proceed between the first active pillar and the second active pillar so as to obliquely cross the active region, and formed to contact the first active pillar; a second gate formed to proceed between the first active pillar and the second active pillar so as to obliquely cross the active region, and formed to cross the second active pillar; a conductive line formed below the first gate and the second gate, and commonly coupled to the first pillar and the second pillar; and an insulation film formed to enclose the conductive line within the active region. | 2015-02-12 |
20150041889 | MULTI-GATE VDMOS TRANSISTOR AND METHOD FOR FORMING THE SAME - Various embodiments provide multi-gate VDMOS transistors. The transistor can include a substrate having a first surface and a second surface opposite to the first surface, a drift layer on the first surface of the substrate, and an epitaxial layer on the drift layer. The transistor can further include a plurality of trenches. Each trench can pass through the epitaxial layer and a thickness portion of the drift layer. The transistor can further include a plurality of gate structures. Each gate structure can fill the each trench. The transistor can further include a plurality of doped regions in the epitaxial layer. Each doped region can surround a sidewall of the each gate structure. The transistor can further include a source metal layer on the epitaxial layer to electrically connecting the plurality of doped regions, and a drain metal layer on the second surface of the substrate. | 2015-02-12 |
20150041890 | HIGH VOLTAGE LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LDMOSFET) HAVING A DEEP FULLY DEPLETED DRAIN DRIFT REGION - Disclosed are semiconductor structures. Each semiconductor structure can comprise a substrate and at least one laterally double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) on the substrate. Each LDMOSFET can have a fully-depleted deep drain drift region (i.e., a fully depleted deep ballast resistor region) for providing a relatively high blocking voltage. Different configurations for the drain drift regions are disclosed and these different configurations can also vary as a function of the conductivity type of the LDMOSFET. Additionally, each semiconductor structure can comprise an isolation band positioned below the LDMOSFET and an isolation well positioned laterally around the LDMOSFET and extending vertically to the isolation band such that the LDMOSFET is electrically isolated from both a lower portion of the substrate and any adjacent devices on the substrate. | 2015-02-12 |
20150041891 | Ultra-High Voltage Laterally-Diffused MOS Devices and Methods of Forming the Same - Embodiments for the present disclosure include a semiconductor device, an ultra-high voltage (UHV) laterally-diffused metal-oxide-semiconductor (LDMOS) transistor, and methods of forming the same. An embodiment includes a first well region of a first conductivity type in a top surface of a substrate, and a second well region of a second conductivity type in the top surface of the substrate. The second well region laterally separated from the first well region by a portion of the substrate. The embodiment further includes a third region of the second conductivity type in the first well region, and a first field oxide region in the first well region, a second field oxide region in the second well region, the second field oxide region having a second bottom surface, and the first field oxide region having a first bottom surface lower than the second bottom surface and on and directly contacting the third region. | 2015-02-12 |
20150041892 | SEMICONDUCTOR DEVICE - There are provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a source region disposed apart from a drain region, a first body region surrounding the source region, a deep well region disposed below the drain region, and a second body region disposed below the first body region. A bottom surface of the second body region is not coplanar with a bottom surface of the deep well region, and the first body region has a different conductivity type from the second body region. | 2015-02-12 |
20150041893 | LDMOS DEVICE AND FABRICATION METHOD - Various embodiments provide LDMOS devices and fabrication methods. An N-type buried isolation region is provided in a P-type substrate. A P-type epitaxial layer including a first region and a second region is formed over the P-type substrate. The first region is positioned above the N-type buried isolation region, and the second region surrounds the first region. An annular groove is formed in the second region to surround the first region and to expose a surface of the N-type buried isolation region. Isolation layers are formed on both sidewalls of the annular groove. An annular conductive plug is formed in the annular groove between the isolation layers. The annular conductive plug is in contact with the N-type buried isolation region at the bottom of the annular conductive plug. A gate structure of an LDMOS transistor is formed over the first region of the P-type epitaxial layer. | 2015-02-12 |
20150041894 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device capable of increasing a breakdown voltage without an additional epitaxial layer or buried layer with respect to a high-voltage horizontal MOSFET. | 2015-02-12 |
20150041895 | SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE - Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region. | 2015-02-12 |
20150041896 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE - A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device. | 2015-02-12 |
20150041897 | ANCHORED STRESS-GENERATING ACTIVE SEMICONDUCTOR REGIONS FOR SEMICONDUCTOR-ON-INSULATOR FINFET - After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin. | 2015-02-12 |
20150041898 | BULK FINFET SEMICONDUCTOR-ON-NOTHING INTEGRATION - Methods and structures for forming fully insulated finFETs beginning with a bulk semiconductor substrate are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first epitaxial layer may be sacrificial. A final gate structure may be formed around the fin structures, and the first epitaxial layer removed to form a void between a fin and the substrate. The void may be filled with an insulator to fully insulate the fin. | 2015-02-12 |
20150041899 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate including first and second regions, a first transistor provided on the first region to include a first channel region protruding from the substrate, and a second transistor provided on the second region to include a second channel region and a gate electrode extending between the substrate and the second channel region. The first channel region may include a lower semiconductor pattern containing a different material from the second channel region and an upper semiconductor pattern containing the same material as the second channel region. | 2015-02-12 |
20150041900 | TRANSISTORS WITH VARIOUS LEVELS OF THRESHOLD VOLTAGES AND ABSENCE OF DISTORTIONS BETWEEN NMOS AND PMOS - The invention relates to an integrated circuit comprising a semi-conducting substrate and first and second cells. Each cell comprises first and second transistors of nMOS and pMOS type including first and second gate stacks including a gate metal. There are first and second ground planes under the first and second transistors and an oxide layer extending between the transistors and the ground planes. The gate metals of the nMOS and of a pMOS exhibit a first work function and the gate metal of the other pMOS exhibiting a second work function greater than the first work function. The difference between the work functions is between 55 and 85 meV and the first work function Wf1 satisfies the relation Wfmg−0.04−0.005*Xge2015-02-12 | |
20150041901 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device may include a string including at least one drain select transistor, a plurality of first memory cells, a first connection element, a plurality of second memory cells, a second connection element, a plurality of third memory cells, and at least one source select transistor, wherein the at least one drain select transistor, the plurality of first memory cells, the plurality of second memory cells, the plurality of third memory cells, and the at least one source select transistor connected serially via the first connection element and the second connection element. | 2015-02-12 |
20150041902 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first junction region formed over an active region; a gate region formed over the active region to substantially surround the first junction region; a second junction region formed over the active region outside the gate region on a first side of the first junction region; and a third junction region formed over the active region outside the gate region on a second side of the first junction region which is opposite to the first side, wherein the second junction region and the third junction region are disposed such that the gate region exists between the second junction region and the third junction region. | 2015-02-12 |
20150041903 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a plurality of transistors formed over a substrate, a support body including a horizontal portion and protrusions, wherein the horizontal portion covers at least one of the transistors, and the protrusions are formed over the horizontal portion and located between the transistors, and conductive layers and insulating layers alternately stacked over the support body and protruding upwardly along the sidewalls of the protrusions. | 2015-02-12 |
20150041904 | BLANKET SHORT CHANNEL ROLL-UP IMPLANT WITH NON-ANGLED LONG CHANNEL COMPENSATING IMPLANT THROUGH PATTERNED OPENING - A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers. | 2015-02-12 |
20150041905 | METHODS OF FORMING REPLACEMENT GATE STRUCTURES FOR TRANSISTORS AND THE RESULTING DEVICES - Disclosed herein are illustrative methods and devices that involve forming spacers with internally trimmed internal surfaces to increase the width of the upper portions of a gate cavity. In some embodiments, the internal surface of the spacer has a stepped cross-sectional configuration or a tapered cross-sectional configuration. In one example, a device is disclosed wherein the P-type work function metal for a PMOS device is positioned only within the lateral space defined by the untrimmed internal surfaces of the spacers, while the work function adjusting metal for the NMOS device is positioned laterally between the lateral spaces defined by both the trimmed and untrimmed internal surfaces of the sidewall spacers. | 2015-02-12 |
20150041906 | METHODS OF FORMING STRESSED FIN CHANNEL STRUCTURES FOR FINFET SEMICONDUCTOR DEVICES - One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches. | 2015-02-12 |
20150041907 | IC WITH FLOATING BURIED LAYER RING FOR ISOLATION OF EMBEDDED ISLANDS - An integrated circuit (IC) includes a substrate having a p-type semiconductor surface. A first nwell includes an area surrounding a first plurality of semiconductor devices formed in the semiconductor surface having a first n-buried layer (NBL) thereunder. A vertical diode formed in the semiconductor surface surrounds the first nwell including a pwell on top of a floating NBL ring. A second nwell formed in the semiconductor surface includes an area surrounding the floating NBL ring and surrounds a second plurality of semiconductor devices having a second NBL thereunder. | 2015-02-12 |
20150041908 | METHOD OF MANUFACTURING A FinFET DEVICE USING A SACRIFICIAL EPITAXY REGION FOR IMPROVED FIN MERGE AND FinFET DEVICE FORMED BY SAME - A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors. | 2015-02-12 |
20150041909 | COMPLETING MIDDLE OF LINE INTEGRATION ALLOWING FOR SELF-ALIGNED CONTACTS - In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET having complete middle of line integration. Specifically, a hard mask layer and set of spacers are removed from the gate stacks leaving behind (among other things) a set of dummy gates. A liner layer is formed over the set of dummy gates and over a source-drain region adjacent to the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates and the source-drain region. An inter-layer dielectric (ILD) is then deposited over the set of dummy gates and over the source-drain region, and the set of dummy gates are then removed. The result is an environment in which a self-aligned contact to the source-drain region can be deposited. | 2015-02-12 |
20150041910 | INTEGRATED CIRCUITS WITH A PARTIALLY-DEPLETED REGION FORMED OVER A BULK SILICON SUBSTRATE AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods of fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a bulk silicon substrate that is lightly-doped with a first dopant type divided into a first device region and a second device region, and a well region that is lightly-doped with a second dopant type formed in the second device region. The integrate circuit further includes heavily-doped source/drain extension regions of the first dopant type aligned to a first gate electrode structure and heavily-doped source/drain extension regions of the second dopant type aligned to a second gate electrode structure, and an intermediately-doped halo region of the second dopant type formed underneath the first gate electrode structure and an intermediately-doped halo regions of the first dopant type underneath the second gate electrode structure. Still further, the integrated circuit includes heavily-doped source/drain regions. | 2015-02-12 |
20150041911 | 3D TRANSISTOR CHANNEL MOBILITY ENHANCEMENT - A method of forming a semiconductor structure includes growing an epitaxial doped layer over an exposed portion of a plurality of fins. The epitaxial doped layer combines the exposed portion of the fins to form a merged source and drain region. An implantation process occurs in the fins through the epitaxial doped layer to change the crystal lattice of the fins to form amorphized fins. A nitride layer is deposited over the semiconductor structure. The nitride layer covers the merged source and drain regions. A thermal treatment is performed in the semiconductor structure to re-crystallize the amorphized fins to form re-crystallized fins. The re-crystallized fins, the epitaxial doped layer and the nitride layer form a strained source and drain region which induces stress to a channel region. | 2015-02-12 |
20150041912 | Gate Stacks Including TaXSiYO for MOSFETS - Provided are field effect transistor (FET) assemblies and methods of forming thereof. An FET assembly may include a dielectric layer formed from tantalum silicon oxide and having the atomic ratio of silicon to tantalum and silicon (Si/(Ta+Si)) of less than 5% to provide a low trap density. The dielectric layer may be disposed over an interface layer, which is disposed over a channel region. The same type of the dielectric layer may be used a common gate dielectric of an nMOSFET (e.g., III-V materials) and a pMOSFET (e.g., germanium). The channel region may include one of indium gallium arsenide, indium phosphate, or germanium. The interface layer may include silicon oxide to provide a higher energy barrier. The dielectric layer may be formed using an atomic layer deposition technique by adsorbing both tantalum and silicon containing precursors on the deposition surface and then oxidizing both precursors in the same operation. | 2015-02-12 |
20150041913 | SEMICONDUCTOR DEVICE HAVING TRI-GATE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate including an NMOS region, a fin active region protruding from the substrate in the NMOS region, the fin active region including an upper surface and a sidewall, a gate dielectric layer on the upper surface and the sidewall of the fin active region, a first metal gate electrode on the gate dielectric layer, the first metal gate electrode having a first thickness at the upper surface of the fin active region and a second thickness at the sidewall of the fin active region, and a second metal gate electrode on the first metal gate electrode, the second metal gate electrode having a third thickness at the upper surface of the fin active region and a fourth thickness at the sidewall of the fin active region, wherein the third thickness is less than the fourth thickness. | 2015-02-12 |
20150041914 | MATCHING TECHNIQUES FOR WIDE-BANDGAP POWER TRANSISTORS - There are disclosed impedance matching networks and technique for impedance matching to microwave power transistors. Distributed capacitor inductor networks are used so as to provide a high degree of control and accuracy, especially in terms of inductance values, in comparison to existing lumped capacitor arrangements. The use of bond wires is reduced, with inductance being provided primarily by microstrip transmission lines on the capacitors. | 2015-02-12 |
20150041915 | Semiconductor Arrangement with Active Drift Zone - A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices. | 2015-02-12 |
20150041916 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A co-implant concentration of a source region of a pull-down transistor is higher than those of other co-implant concentrations. Thus, dopants in a halo region of the source region may be prevented from excessively being diffused into a channel region during a post annealing process. As a result, dispersion of saturation threshold voltages of unit memory cells may be reduced. | 2015-02-12 |
20150041917 | FIELD-EFFECT TRANSISTOR STACK VOLTAGE COMPENSATION - Field-effect transistor (FET) stack voltage compensation. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series between the first and terminal and the second terminal. Each switching element has a parameter that is configured to yield a desired voltage drop profile among the connected switching elements. Such a desired voltage drop profile can be achieved by some or all FETs in a stack having variable dimensions such as variable gate width or variable numbers of fingers associated with the gates. | 2015-02-12 |
20150041918 | Self-Aligned Dual-Metal Silicide and Germanide Formation - A method includes growing an epitaxy semiconductor region at a major surface of a wafer. The epitaxy semiconductor region has an upward facing facet facing upwardly and a downward facing facet facing downwardly. The method further includes forming a first metal silicide layer contacting the upward facing facet, and forming a second metal silicide layer contacting the downward facing facet. The first metal silicide layer and the second metal silicide layer comprise different metals. | 2015-02-12 |
20150041919 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor is provided with a MOS transistor and 1st to 5th signal lines. The MOS transistor has a gate finger structure with gate terminals. The 1st line is formed parallel to a gate width direction at each of ends of gate terminals and connected to one end of one gate terminal. The 2nd line connected to the 1st line is formed perpendicular to the direction outside an active region. The 3rd line with a smaller line width than a gate width is formed perpendicular to the direction and connected to each drain on the active region. The 4th line connected to a source is formed parallel to the direction. The 5th line connected to the 4th line is formed such that the 5th line does not overlap the 2nd line. | 2015-02-12 |
20150041920 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND MANUFACTURING METHOD THEREOF - An electrostatic discharge (ESD) protection device includes two N-metal oxide semiconductor (NMOS) elements and a doped region. The two NMOS elements are arranged on a P-substrate, and each NMOS element includes a gate, a source, and a drain. The source and the drain are arranged on two opposite sides of the gate. The doped region is implanted into an outer space of the two NMOS surrounding the two NMOS, and a PN junction is formed by the doped region and the P-substrate. | 2015-02-12 |
20150041921 | INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES - Roughly described, an integrated circuit transistor structure has a body of semiconductor material, the body having two longitudinally spaced doped source/drain volumes with a channel between, a gate stack disposed outside the body and facing at least one of the surfaces of the body along the channel. The body contains an adjustment volume, longitudinally within the channel volume and spaced behind the first surface by a first distance and spaced longitudinally from both the source/drain volumes. The adjustment volume comprises an adjustment volume material having, at each longitudinal position, an electrical conductivity which differs from that of the adjacent body material at the same longitudinal position, at least while the transistor is in an off-state. In one embodiment the adjustment volume material is a dielectric. In another embodiment the adjustment volume material is an electrical conductor. | 2015-02-12 |
20150041922 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a pair of complementary signal lines, a first transistor including a gate, a source, and a drain, one of the source and the drain of the first transistor being coupled to one of the pair of the complementary signal lines, and a second transistor including a gate, a source, and a drain, the gate of the second transistor being coupled to the gate of the first transistor, one of a source and a drain of the second transistor coupled to an other of the source and the drain of the first transistor, and an other of the source and the drain of the second transistor being coupled to the other of the pair of the complementary signal lines. A direction of a gate width of the first transistor is different from a direction of a gate width of the second transistor. | 2015-02-12 |
20150041923 | Multi-Gate FETs and Methods for Forming the Same - A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation. | 2015-02-12 |
20150041924 | N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE - A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a second side of the inter-block isolation structure. A patterned gate conductor layer includes a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins. The first and second gate conductors are connected by an inter-block conductor. | 2015-02-12 |
20150041925 | P TYPE MOSFET AND METHOD FOR MANUFACTURING THE SAME - Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer. | 2015-02-12 |
20150041926 | TUNGSTEN GATES FOR NON-PLANAR TRANSISTORS - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate. | 2015-02-12 |
20150041927 | MEMS DEVICE WITH DIFFERENTIAL VERTICAL SENSE ELECTRODES - A MEMS device includes a first sense electrode and a first portion of a sense mass formed in a first structural layer, where the first sense electrode is fixedly coupled with the substrate and the first portion of the sense mass is suspended over the substrate. The MEMS device further includes a second sense electrode and a second portion of the sense mass formed in a second structural layer. The second sense electrode is spaced apart from the first portion of the sense mass in a direction perpendicular to a surface of the substrate, and the second portion of the sense mass is spaced apart from the first sense electrode in the same direction. A junction is formed between the first and second portions of the sense mass so that they are coupled together and move concurrently in response to an imposed force. | 2015-02-12 |
20150041928 | WAFER ENCAPSULATED MICROELECTROMECHANICAL STRUCTURE - A cavity is formed within a first substrate together with trenches that separate first and second portions of the first substrate from each other and from the remainder of the first substrate. The first portion of the first substrate is disposed within the cavity and constitutes a microelectromechanical structure, while the second portion of the substrate is disposed at least partly within the cavity and constitutes a first portion of an electrical contact. A second substrate is secured to the first substrate over the cavity to define a chamber containing the microelectromechanical structure. The second substrate has a first portion that constitutes a second portion of the electrical contact and is disposed in electrical contact with the second portion of the first substrate such that the electrical contact extends from within the chamber to an exterior of the chamber. | 2015-02-12 |
20150041929 | Packaged Microphone with Multiple Mounting Orientations - A packaged microphone has a base and a lid that at least in part form a package having a plurality of exterior sides and an interior chamber. The packaged microphone also has a flexible substrate having a first portion within the interior chamber, and a second portion, extending from the interior chamber, having at least two sets of pads. A MEMS microphone die is mounted to the first portion of the flexible substrate, and each set of pads is in electrical communication with the microphone die. One set of pads is on a first exterior side of the package, and a second set of pads is on a second exterior side of the package. | 2015-02-12 |
20150041930 | ACOUSTIC TRANSDUCER - There is provided an acoustic transducer including: a substrate formed to have a hollow part through which acoustic waves are input; a diaphragm formed on the substrate and covering the hollow part; and a back plate disposed so as to cover at least a portion of the diaphragm, wherein a ring-shaped groove extended along an edge of the diaphragm is formed in the substrate. | 2015-02-12 |
20150041931 | Embedded Micro Valve In Microphone - A microelectromechanical system (MEMS) apparatus includes a base. A MEMS device is disposed on the base. A cover encloses the MEMS device on the base. A port extends through the base, and the MEMS device is disposed over the port. A diaphragm is embedded within the base and has at least some portions that extend across the port. In an open position, the diaphragm allows the passage of sound energy from the exterior of the apparatus to the interior of the apparatus. In a closed position, the diaphragm makes contact with an outer surface of the port to at least partially block the passage of sound energy from the exterior of the apparatus to the interior of the apparatus. | 2015-02-12 |
20150041932 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS. | 2015-02-12 |
20150041933 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC JUNCTIONS USING BCC COBALT AND SUITABLE FOR USE IN SPIN TRANSFER TORQUE MEMORIES - A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer includes body-centered cubic Co. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. | 2015-02-12 |
20150041934 | METHOD AND SYSTEM FOR PROVIDING MAGNETIC MEMORIES SWITCHABLE USING SPIN ACCUMULATION AND SELECTABLE USING MAGNETOELECTRIC DEVICES - A magnetic memory is described. In one aspect, the magnetic memory includes magnetic junctions and at least one semi-spin valve (SSV) line adjacent to the magnetic junctions. Each magnetic junction includes a magnetic free layer. The SSV line(s) include a ferromagnetic layer and a nonmagnetic layer between the ferromagnetic layer and the magnetic junctions. The SSV line(s) are configured to exert a spin accumulation induced torque on at least a portion of the magnetic junctions due to an accumulation of spin polarized current carriers from a current that is substantially in-plane. The free layer is configured to be written using at least the spin accumulation induced torque. In another aspect, the magnetic memory includes magnetic memory cells and at least one spin torque (ST) line that is analogous to the SSV line. Each magnetic memory cell includes magnetic junction(s) analogous to those above and magnetoelectric selection device(s). | 2015-02-12 |
20150041935 | High Thermal Stability Reference Structure with Out-of-Plane Anisotropy for Magnetic Device Applications - Enhanced Hc and Hk in addition to higher thermal stability up to at least 400° C. are achieved in magnetic devices by adding dusting layers on top and bottom surfaces of a spacer in a synthetic antiferromagnetic (SAF) structure to give a RL1/DL1/spacer/DL2/RL2 reference layer configuration where RL1 and RL2 layers exhibit perpendicular magnetic anisotropy (PMA), the spacer induces antiferromagnetic coupling between RL1 and RL2, and DL1 and DL2 are dusting layers that enhance PMA. Dusting layers are deposited at room temperature to 400° C. RL1 and RL2 layers are selected from laminates such as (Ni/Co)n, L1 | 2015-02-12 |
20150041936 | PASSIVATION OF BACK-ILLUMINATED IMAGE SENSOR - A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry. | 2015-02-12 |
20150041937 | NANOWIRE STRUCTURED COLOR FILTER ARRAYS AND FABRICATION METHOD OF THE SAME - Color filter array devices and methods of making color filter array devices are disclosed herein. A color filter array may include a substrate having a plurality of pixels thereon, one or more nanowires associated with each of the plurality of pixels, wherein each of the one or more nanowires extends substantially perpendicularly from the substrate, and an optical coupler associated with each of the one or more nanowires. A method of making a color filter array may include, making an array of nanowires, wherein each of the nanowires extend substantially perpendicularly from a substrate, disposing a transparent polymer material to substantially encapsulate the nanowires, removing the nanowires from the substrate, providing a pixel array comprising a plurality of pixels, wherein a hard polymer substantially covers an image plane of the pixel array, disposing the array of nanowires on the pixel array, and removing the transparent polymer encapsulating the nanowires. | 2015-02-12 |
20150041938 | PASSIVATION OF BACK-ILLUMINATED IMAGE SENSOR - A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry. | 2015-02-12 |
20150041939 | IMAGE SENSOR HAVING LENS TYPE COLOR FILTER AND METHOD FOR FABRICATING THE SAME - The image sensor includes lens-type color filters having a uniform shape for a plurality of pixels. The image sensor includes a plurality of pixels formed in a substrate, a plurality of color filter housings formed over outer boundaries of the respective pixels, and a plurality of color filters filled in spaces defined by the respective color filter housings, wherein the clock filter housings surround edges of the respective color filters with a given curvature. | 2015-02-12 |
20150041940 | IMAGE SENSOR AND ELECTRONIC DEVICE INCLUDING THE SAME - An image sensor includes a semiconductor substrate integrated with at least one first photo-sensing device sensing light in a first wavelength region and at least one second photo-sensing device sensing light in a second wavelength region shorter than the first wavelength region, a photoelectric device including a pair of electrodes facing each other and a light absorption layer between the electrodes, the photoelectric device selectively absorbing light in a third wavelength region between the first wavelength region and the second wavelength region, and a nanostructural body between the semiconductor substrate and the photoelectric device, the nanostructural body including at least two parts having different optical paths. | 2015-02-12 |
20150041941 | SOLID-STATE IMAGING DEVICE - According to one embodiment, a solid-state imaging device including a semiconductor substrate having a light receiving portion, a color filter layer and a selective reflection layer. The color filter layer includes a color filter portion and is provided above a first main surface of the semiconductor substrate. The color filter portion has a transmission band for transmitting light of a predetermined wavelength band and absorbs light outside the transmission band. The selective reflection layer is provided between the first main surface of the semiconductor substrate and the color filter layer so as to contact with the color filter portion. The selective reflection layer has substantially the same refraction index as the color filter portion with respect to light within the transmission band. The refraction index of the selective reflection layer is substantially different from that of the color filter portion with respect to light outside the transmission band. | 2015-02-12 |
20150041942 | SOLID-STATE IMAGE PICKUP DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A solid-state image pickup device, including: a plurality of pixels; a separation structure provided along a boundary line adjacent to the plurality of pixels; the separation structure includes a groove provided from a back surface of the semiconductor substrate to a depth corresponding to a wavelength, the groove being positioned along the boundary line, a first separation layer provided in the groove, and a second separation layer provided above the first separation layer and corresponding to the boundary line, the second separation layer being connected to the first separation layer; and methods including the same. | 2015-02-12 |
20150041943 | METHOD FOR FABRICATING A THICK MULTILAYER OPTICAL FILTER WITHIN AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT COMPRISING A THICK MULTILAYER OPTICAL FILTER - A multilayer optical filter is provided for an integrated circuit including a substrate and a metallization layer interconnection part. The optical filter is formed from a first filter part located within the interconnection part and positioned over a photosensitive region of the substrate. The optical filter further includes a second filter part positioned above the first filter part and the interconnection part. The first and second filter parts each include a metal layer. The first and second filter parts are separated from each other as a function of a wavelength in vacuum of an optical signal to be filtered and received by the photosensitive region. | 2015-02-12 |
20150041944 | IMAGE SENSOR, FABRICATING METHOD THEREOF, AND DEVICE COMPRISING THE IMAGE SENSOR - Image sensor, fabricating method thereof, and device comprising the image sensor are provided, which comprises a substrate in which a photoelectric transformation device is formed, an interconnection structure formed on the substrate and including multiple intermetal dielectric layers and multiple metal interconnections placed in the multiple intermetal dielectric layers, the interconnection structure defining a cavity aligned corresponding to the photoelectric transformation device, a moisture absorption barrier layer conformally formed on a top of the interconnection structure and in the cavity; and a light guide unit formed on the moisture absorption barrier layer and including light transmittance material filling the cavity, wherein the moisture absorption barrier layer is formed with a uniform thickness on both sides and a bottom of the cavity and on a top surface of the multiple intermetal dielectric layer. | 2015-02-12 |
20150041945 | PICKUP DEVICE STRUCTURE WITHIN A DEVICE ISOLATION REGION - A device includes a device isolation region formed into a semiconductor substrate, a doped pickup region formed into the device isolation region, a dummy gate structure that includes at least one structure that partially surrounds the doped pickup region, and a via connected to the doped pickup region. | 2015-02-12 |
20150041946 | Edge Termination Structure with Trench Isolation Regions - A semiconductor device includes a semiconductor body and an edge termination structure. The edge termination structure comprises a first oxide layer, a second oxide layer, a semiconductor mesa region between the first oxide layer and the second oxide layer, and a doped field region comprising a first section in the semiconductor mesa region, and a second section in a region below the semiconductor mesa region. The second section overlaps the first and the second oxide layers in the region below the semiconductor mesa region. | 2015-02-12 |
20150041947 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND DISPLAY DEVICE - An objective of the present invention is to increase production efficiency of high-performance flexible semiconductor devices. A semiconductor device manufacturing method includes: a step of forming an insulating substrate ( | 2015-02-12 |
20150041948 | SEMICONDUCTOR DEVICE INCLUDING STI STRUCTURE AND METHOD FOR FORMING THE SAME - Semiconductor devices and fabrication methods are disclosed. A mask layer having an opening is formed on a semiconductor substrate. The semiconductor substrate is etched along the opening of the mask layer to form a trench therein. The mask layer is laterally etched from the opening of the mask layer along a top surface of the semiconductor substrate to expose a surface portion of the semiconductor substrate on each side of the opening. A liner oxide layer is formed by a thermal oxidation process on interior surface of the trench and on the exposed surface portion of the semiconductor substrate. The thermal oxidation process is controlled such that an upper corner between the top surface of the semiconductor substrate and the trench is rounded after the liner oxide layer is formed. An insulation layer is formed on the liner oxide layer and fills the trench. | 2015-02-12 |
20150041949 | Shallow Trench Isolation Area Having Buried Capacitor - A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area. | 2015-02-12 |
20150041950 | CONDUCTOR WITH SUB-LITHOGRAPHIC SELF-ALIGNED 3D CONFINEMENT - A three-dimensionally (3d) confined conductor advantageously used as an electronic fuse and self-aligned methods of forming the same. By non-conformal deposition of a dielectric film over raised structures, a 3d confined tube, which may be sub-lithographic, is formed between the raised structures. Etching holes which intersect the 3d confined region and subsequent metal deposition fills the 3d confined region and forms contacts. When the raised structures are gates, the fuse element may be located at the middle of the line (i.e. in pre-metal dielectric). Other methods for creating the structure are also described. | 2015-02-12 |
20150041951 | ELECTRONIC FUSE VIAS IN INTERCONNECT STRUCTURES - An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above the first metallization level, a metal via in the second metallization level, an interface region where the metal via meets the first metallization level, and a damaged region at the interface region. Embodiments further include a method including providing a first metallization level including a metal structure, forming a capping layer on the first metallization level, forming an opening in the capping layer that exposes a portion of the metal structure; forming above the capping layer an adhesion layer contacting the metal structure, forming an insulating layer above the adhesion layer, etching the insulating layer and the adhesion layer to form a recess exposing the metal structure, and filling the fuse via recess to form a fuse via. | 2015-02-12 |
20150041952 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes an interposer structure. The interposer structure includes an interposer substrate, a ground, through vias, a dielectric layer, and an inductor. The through vias are formed in the interposer substrate and electrically connected to the ground. The dielectric layer is on the interposer substrate. The inductor is on the dielectric layer. | 2015-02-12 |
20150041953 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a semiconductor component includes a common mode filter monolithically integrated with a protection device. The common mode filter may be composed of first, second, third, and fourth coils, wherein each coil has first and second terminals and the first coil is magnetically coupled to the second coil and the third coil is magnetically coupled to the fourth coil. The protection device has a first terminal coupled to the first terminal of the first coil and a second terminal coupled to the first terminal of the third coil. An energy storage element has a terminal coupled to the second and first terminals of the first and second coils, respectively. Another embodiment includes monolithically integrating a common mode filter with a protection device and monolithically integrating a metal-insulator-metal capacitor with the common mode filter. | 2015-02-12 |
20150041954 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - In accordance with an embodiment, a semiconductor component, includes a common mode filter monolithically integrated with a protection device. The common mode filter includes a plurality of coils and the protection device has a terminal coupled to a first coil and another terminal coupled to a second coil. | 2015-02-12 |
20150041955 | Multi-Die Fine Grain Integrated Voltage Regulation - A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used. | 2015-02-12 |
20150041956 | ISOLATION SCHEME FOR BIPOLAR TRANSISTORS IN BICMOS TECHNOLOGY - Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures. | 2015-02-12 |
20150041957 | BIPOLAR JUNCTION TRANSISTOR HAVING MULTI-SIDED BASE CONTACT - A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT. | 2015-02-12 |
20150041958 | INTEGRATION OF DENSE AND VARIABLE PITCH FIN STRUCTURES - Semiconductor devices and method for forming the same. Methods for forming fin structures include forming a protective layer over a set of mandrels in a variable fin pitch region; forming first sidewalls around a set of mandrels in a uniform fin pitch region; removing the set of mandrels in the uniform fin pitch region; removing the protective layer; forming second sidewalls around the first sidewalls in the uniform fin pitch region and the mandrels in the variable fin pitch region; removing the first sidewalls and the mandrels; and etching an underlying layer around the second sidewalls. | 2015-02-12 |
20150041959 | HARDMASK COMPOSITION FOR FORMING RESIST UNDERLAYER FILM, PROCESS FOR PRODUCING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A hardmask composition for forming a resist underlayer film, a process for producing a semiconductor integrated circuit device, and a semiconductor integrated circuit device, the hardmask composition including an organosilane polymer, a stabilizer, the stabilizer including methyl acetoacetate, ethyl-2-ethylacetoacetate, nonanol, decanol, undecanol, dodecanol, acetic acid, phenyltrimethoxysilane, diphenylhexamethoxydisiloxane, diphenylhexaethoxydisiloxane, dioctyltetramethyldisiloxane, tetramethyldisiloxane, decamethyltetrasiloxane, dodecamethylpentasiloxane, hexamethyldisiloxane, or mixtures thereof, and a solvent, wherein the solvent includes acetone, tetrahydrofuran, benzene, toluene, diethyl ether, chloroform, dichloromethane, ethyl acetate, propylene glycol methyl ether acetate, propylene glycol ethyl ether acetate, propylene glycol propyl ether acetate, ethyl lactate, γ butyrolactone, methyl isobutyl ketone, or mixtures thereof, the solvent is present in an amount of about 70 to about 99.9% by weight, based on a total weight of the composition, and the stabilizer is present in an amount of about 0.0001 to about 3.0% by weight, based on a total weight of the composition. | 2015-02-12 |
20150041960 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is formed a first concave portion that extends inside a semiconductor substrate from a main surface thereof. An insulating film is formed over the main surface, over a side wall and a bottom wall of the first concave portion so as to cover an element and to form a capped hollow in the first concave portion. A first hole portion is formed in the insulating film so as to reach the hollow in the first concave portion from an upper surface of the insulating film, and to reach the semiconductor substrate on the bottom wall of the first concave portion while leaving the insulating film over the side wall of the first concave portion. There is formed a second hole portion that reaches the conductive portion from the upper surface of the insulating film. The first and second hole portions are formed by the same etching treatment. | 2015-02-12 |
20150041961 | Through silicon via structure - A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via. | 2015-02-12 |
20150041962 | Semiconductor Device with Cell Trench Structures and Contacts and Method of Manufacturing a Semiconductor Device - First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width. | 2015-02-12 |
20150041963 | Semiconductor Device Having a Surface with Ripples - According to one embodiment of a semiconductor device, the semiconductor device includes a semiconductor substrate having a first surface, an insulation layer having a laterally varying thickness on the first surface, and a metal layer on the first surface. The insulation layer has ripples in its surface facing the metal layer. According to another embodiment of a semiconductor device, the semiconductor device includes a semiconductor substrate having a first surface and including at least one of a laterally varying thickness and an inclined first surface. The first surface of the semiconductor substrate has ripples. | 2015-02-12 |
20150041964 | Apparatus and Methods for Low K Dielectric Layers - Methods and apparatus for a low k dielectric layer of porous SiCOH. A method includes placing a semiconductor substrate into a vapor deposition chamber; introducing reactive gases into the vapor deposition chamber to form a dielectric film comprising SiCOH and a decomposable porogen; depositing the dielectric film to have a ratio of Si—CH | 2015-02-12 |
20150041965 | Power Semiconductor Device and Method - A power semiconductor device includes a semiconductor body having a first side, a second side opposite the first side and an outer rim. The semiconductor body includes an active region, an edge termination region arranged between the active region and the outer rim, a first doping region in the active region and connected to a first electrode arranged on the first side, a second doping region in the active region and the edge termination region and connected to a second electrode arranged on the second side, a drift region between the first doping region and the second doping region, the drift region including a first portion adjacent to the first side and a second portion arranged between the first portion and the second doping region, and an insulating region arranged in the edge termination region between the second doping region and the first portion of the drift region. | 2015-02-12 |
20150041966 | Methods and Systems for Dopant Activation Using Microwave Radiation - Systems and methods are provided for activating dopants in a semiconductor structure. For example, a semiconductor structure including a plurality of dopants is provided. One or more microwave-absorption materials are provided, the microwave-absorption materials being capable of increasing an electric field density associated with the semiconductor structure. Microwave radiation is applied to the microwave-absorption materials and the semiconductor structure to activate the plurality of dopants for fabricating semiconductor devices. The microwave-absorption materials are configured to increase the electric field density in response to the microwave radiation so as to increase the semiconductor structure's absorption of the microwave radiation to activate the dopants. | 2015-02-12 |
20150041967 | Molded Semiconductor Package with Backside Die Metallization - A semiconductor package is manufactured by providing a semiconductor die with a terminal at a first side of the die, providing a material coupled to the die at an opposing second side of the die and embedding the die in a molding compound so that the die is covered by the molding compound on all sides except the first side. The molding compound is thinned at a side of the molding compound adjacent the second side of the die, to expose the material at the second side of the die without exposing the second side of the die. An electrical connection is formed to the terminal at the first side of the die. In the case of a transistor die, the terminal can be a source terminal and the transistor die can be attached source-down to a metal block such as a die paddle of a lead frame. | 2015-02-12 |
20150041968 | IMAGE FORMING APPARATUS, CHIP, AND CHIP PACKAGE - An image forming apparatus including an engine unit to perform an image forming operation, and a board unit to control the engine unit. The board unit includes at least one chip package that includes a chip. The chip includes first pads to transmit a first type of signal, a second pad to transmit a second type of signal, and a third pad interposed between the first and second pads, to reduce cross-talk between the first and second types of signals. | 2015-02-12 |
20150041969 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a semiconductor structure having a carrier, a circuit portion formed on the carrier and a plurality of semiconductor elements disposed on the circuit portion; disposing a lamination member on the semiconductor elements; forming an insulating layer on the circuit portion for encapsulating the semiconductor elements; and removing the carrier. The lamination member increases the strength between adjacent semiconductor elements so as to overcome the conventional cracking problem caused by a CTE mismatch between the semiconductor elements and the insulating layer when the carrier is removed. | 2015-02-12 |
20150041970 | SEMICONDUCTOR DEVICE - A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern. | 2015-02-12 |
20150041971 | STACKED SEMICONDUCTOR APPARATUS - A stacked semiconductor apparatus includes a main die, a plurality of slave dies, and a vertical interposer. The vertical interposer is vertically stacked on the main die. | 2015-02-12 |
20150041972 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is disclosed, which includes: a first substrate; a first semiconductor component disposed on the first substrate; a second substrate disposed on the first semiconductor component and electrically connected to the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate and encapsulating the first semiconductor component and the conductive elements. The present invention can control the height and volume of the conductive elements since the distance between the first substrate and the second substrate is fixed by bonding the second substrate to the first semiconductor component. | 2015-02-12 |
20150041973 | SEMICONDUCTOR DEVICES INCLUDING UNITARY SUPPORTS - A semiconductor device includes a plurality of cylindrical structures located at vertices and central points of a plurality of hexagons in a honeycomb pattern, and a unitary support having a plurality of openings. Each of the openings exposes a part each of four of the cylindrical structures. Each of the openings has the shape of a parallelogram or an oval substantially. A first distance between opposite cylindrical structures of a first pair of the four cylindrical structures exposed by each opening is shorter than a second distance between opposite cylindrical structures of a second pair of the four cylindrical structures exposed by the opening. The first distance is equal to a distance between the central point and each of the vertices of the hexagon. | 2015-02-12 |
20150041974 | SINTERED BODY OF SILVER FINE PARTICLE - A sintered body of silver fine particles for a bonding member to bond components of a semiconductor device, wherein an activation energy for creep of the sintered body of the silver fine particles is from 0.4 to 0.75 times that of an activation energy for a lattice diffusion of bulk silver. | 2015-02-12 |
20150041975 | SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF - A semiconductor package includes a first package comprising a circuit board and a first semiconductor die mounded on the circuit board, and a second package comprising a mounting board. At least one second semiconductor die may be mounted on the mounting board, and one or more leads may be electrically connected to the mounting board and/or the second semiconductor die. An adhesion member may bond the first package to the second package, and an encapsulant may encapsulate the first package and the second package. the circuit board, the mounting board, and the one or more leads may be arranged to surround the first semiconductor die and the second semiconductor die, and the plurality of leads may be electrically connected to the circuit board and to a constant potential or ground, to reduce the effects of external electromagnetic interference upon the semiconductor package. | 2015-02-12 |
20150041976 | SEMICONDUCTOR DEVICE SEALED IN A RESIN SECTION AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor chip having a pad electrode formed on an upper surface thereof; a resin section sealing the first semiconductor chip with the upper surface and a side surface of the first semiconductor chip being covered and a lower surface of die first semiconductor chip being exposed; a columnar electrode communicating between the upper surface and the lower surface of the resin section with the upper surface and the lower surface of the columnar electrode being exposed on the resin section and at least a part of the side surface of the columnar electrode being covered; and a bonding wire connecting the pad electrode and the columnar electrode with a part of the bonding wire being embedded in the columnar electrode as one end of the bonding wire being exposed on the lower surface of the columnar electrode and the remaining part of the bonding wire being covered with the resin section, and a method for manufacturing the same. | 2015-02-12 |
20150041977 | STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a via formed in a dielectric layer to expose a contact pad and a capture pad formed in the via and over the dielectric layer. The capture pad has openings over the dielectric layer to form segmented features. The solder bump is deposited on the capture pad and the openings over the dielectric layer. | 2015-02-12 |
20150041978 | SEMICONDUCTOR DEVICE - The semiconductor device | 2015-02-12 |
20150041979 | METHOD TO ENHANCE RELIABILITY OF THROUGH MOLD VIA TMVA PART ON PART POP DEVICES - A Through Mold Via (TMV) Integrated Circuit (IC) package is provided as a bottom IC package for a TMV Package on Package (POP) configuration. The TMV IC package has an overmold top portion having a substantially flat surface and spacer or standoff features extending upward from the flat surface. The spacer or standoff features are configured to abut the bottom surface of the top POP package during softer reflow in order to maintain a gap of predetermined height between the top and bottom IC packages. | 2015-02-12 |
20150041980 | Semiconductor Package with Reduced Thickness - A method for forming a reduced thickness semiconductor package is disclosed and may include providing a first die with an active layer, a through-silicon via (TSV), and a pattern and an under bump metal (UBM) in a dielectric layer on the active layer. A carrier may be bonded to the dielectric layer and the UBM. The first die may be thinned to expose the TSV. A bump pad may be formed on the exposed TSV and a second die may be bonded to the bump pad. The first die, the second die, and an outer surface of the dielectric layer may be encapsulated utilizing a first encapsulant. The carrier may be removed from the dielectric layer and the UBM, and a solder ball may be formed on the UBM. A groove may be formed through the dielectric layer and into the first die. | 2015-02-12 |