06th week of 2009 patent applcation highlights part 14 |
Patent application number | Title | Published |
20090032765 | Selective barrier polishing slurry - The aqueous slurry is useful for chemical mechanical polishing a semiconductor substrate having copper interconnects. The slurry contains by weight percent, 0 to 25 oxidizing agent, 0.1 to 30 abrasive particles, 0.001 to 5 benzenecarboxylic acid, 0.00002 to 5 multi-component surfactant, the multi-component surfactant having a hydrophobic tail, a nonionic hydrophilic portion and an anionic hydrophilic portion, the hydrophobic tail having 6 to 30 carbon atoms and the nonionic hydrophilic portion having 10 to 300 carbon atoms, 0.001 to 10 inhibitor for decreasing static etch of the copper interconnects, 0 to 5 phosphorus-containing compound for increasing removal rate of the copper interconnects, 0 to 10 complexing agent formed during polishing and balance water. | 2009-02-05 |
20090032766 | COMPOSITION AND METHOD FOR SELECTIVELY ETCHING GATE SPACER OXIDE MATERIAL - A gate spacer oxide material removal composition and process for at least partial removal of gate spacer oxide material from a microelectronic device having same thereon. The anhydrous removal composition includes at least one organic solvent, at least one chelating agent, a base fluoride:acid fluoride component, and optionally at least one passivator. The composition achieves the selective removal of gate spacer oxide material relative to polysilicon and silicon nitride from the vicinity of the gate electrode on the surface of the microelectronic device with minimal etching of metal silicide interconnect material species employed in the gate electrode architecture. | 2009-02-05 |
20090032767 | Mercury Dispensing Compositions and Device Using the Same - Compositions for mercury dispensing in lamps are disclosed, comprising a first component comprising mercury and at least a metal selected between titanium and zirconium and a second component consisting of aluminum or either a compound or an alloy including at least 40% by weight of aluminum, wherein the weight ratio between the first and the second component is equal to or lower than 9:1; optionally, the compositions may also include a third component, selected among metals or oxides capable of reacting exothermically with aluminum. | 2009-02-05 |
20090032768 | WATER-SOLUBLE PHENYLENEDIAMINE COMPOSITIONS AND METHODS FOR STABILIZING ETHYLENICALLY UNSATURATED COMPOUNDS AND MONOMERS - Compositions and methods for inhibiting polymerization of ethylenically unsaturated monomers are provided. The compositions include a water-soluble phenylenediamine composition. | 2009-02-05 |
20090032769 | Liquid antioxidant mixtures - The present invention provides for liquid antioxidant mixtures of octylated/butylated diphenylamine, phenothiazine and octadecyl (3,5-di-tert-butyl-4-hydroxyphenyl)-propionate. The antioxidant mixtures are useful for polyurethane stabilization. | 2009-02-05 |
20090032770 | Insoluble and Branched Polyphosphonates and Methods Related Thereto - Insoluble polyphosphonates produced via a transesterification process, methods for preparing such insoluble polyphosphonates and polymer compositions and articles of manufacture including such insoluble polyphosphonates are described herein. | 2009-02-05 |
20090032771 | LIQUID CRYSTAL COMPOSITION AND LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal composition having a negative dielectric anisotropy that includes two components, wherein the first component is at least one compound selected from the group consisting of compounds represented by formula (1), and the second component is at least one compound selected from the group consisting of compounds represented by formula (2): | 2009-02-05 |
20090032772 | LUMINESCENT MATERIAL - The invention relates to a luminescent material comprising a luminescent particle ( | 2009-02-05 |
20090032773 | OXYGEN SCAVENGING COMPOSITION AND METHOD FOR MAKING SAME - The present invention provides polymeric compositions comprising an hydrogenated anthraquinone derivative and/or its enol/enolate tautomer. Methods of scavenging oxygen and preventing transmission of oxygen into a package using said compositions are also provided. | 2009-02-05 |
20090032774 | DEAGGREGATED ELECTRICALLY CONDUCTIVE POLYMERS AND PRECURSORS THEREOF - Deaggregated substituted and unsubstituted polyparaphenylenes, polyparaphenylevevinyles, polyanilines, polyazines, polythiophenes, poly-p-phenylene sulfides, polyfuranes, polypyrroles, polyselenophene, polyacetylenes formed from soluble precursors and combinations thereof and copolymers thereof and methods of fabrication are described. The deaggregated polymer molecules when subsequently doped show higher electrical conductivity. Agents such as lithium chloride, m-cresol and nonylphenol are used to deaggregate the polymer molecules. The deaggregating agents can be added prior to or during doping the molecules. | 2009-02-05 |
20090032775 | POLYCRYSTALLINE CONDUCTING POLYMERS AND PRECURSORS THEREOF HAVING ADJUSTABLE MORPHOLOGY AND PROPERTIES - Polycrystalline materials containing crystallies of precursors to electrically conductive polymers and electrically conductive polymers are described which have an adjustable high degree of crystallinity. The intersticial regions between the crystallites contains amorphous material containing precursors to electrically conductive polymers and/or electrically conductive polymers. The degree of crystallinity is achieved by preparing the materials under conditions which provide a high degree of mobility to the polymer molecules permitting them to associate with one another to form a crystalline state. This is preferable achieved by including additives, such as plasticizers and diluents, to the solution from which the polycrystalline material is formed. The morphology of the polycrystalline material is adjustable to modify the properties of the material such as the degree of crystallinity, crystal grain size, glass transition temperature, thermal coefficient of expansion and degree of electrical conductivity. High levels of electrical conductivity are achieved in in the electrically conductive polycrystalline materials without stretch orienting the material. The enhanced electrical conductivity is isotropic as compared to a stretch oriented film which has isotropic electrical conductivity. | 2009-02-05 |
20090032776 | ELECTROLUMINESCENT MATERIALS AND THEIR USE - The invention relates to polymers containing at least 0.5 mol % of units of formula (3) | 2009-02-05 |
20090032777 | CARBON NANOTUBE DISPERSION LIQUID AND TRANSPARENT CONDUCTIVE FILM USING SAME - Disclosed is a carbon nanotube dispersion liquid which enables to easily form a transparent conductive film. Also disclosed is a transparent conductive film obtained by using such a carbon nanotube dispersion liquid. Specifically disclosed is a carbon nanotube dispersion liquid containing a carbon nanotube (A), a dispersing agent (B) composed of an organic compound containing one of a carboxyl group, epoxy group, amino group and sulfonyl group and having a boiling point of not less than 30˚C and not more than 150˚C, and a solvent (C). Also disclosed are a transparent conductive film containing a layer composed of a solid component of such a dispersion liquid, and a method for producing such a transparent conductive film. | 2009-02-05 |
20090032778 | ELECTRICALLY CONDUCTIVE FIBER AND BRUSH - There is provided a conductive fiber containing a conductive substance, and having stable conductive performance with a small variation in its conductive performance. | 2009-02-05 |
20090032779 | CONDUCTIVE PATTERN FORMATION INK, CONDUCTIVE PATTERN AND WIRING SUBSTRATE - A conductive pattern formation ink capable of producing a conductive pattern with reduced likelihood of generation of cracks, a conductive pattern which is small in the number of cracks generated, low in specific resistance and superior in high-frequency characteristics, and a wiring substrate provided with the conductive pattern which is small in the number of cracks generated, low in specific resistance and superior in high-frequency characteristics are provided. The conductive pattern formation ink is used for forming a conductive pattern on a base member by patterning and comprised of a dispersion solution. The dispersion solution includes a solvent, metal particles dispersed in the solvent, and an anti-cracking agent contained in the solvent, wherein the anti-cracking agent is contained for preventing generation of cracks in the conductive pattern during desolvation of the solvent. | 2009-02-05 |
20090032780 | NICKEL PASTE - Nickel paste includes nickel powder, a resin binder and an organic solvent, wherein the nickel powder includes less than 100 ppm sulfur. This provides the nickel paste that the change in viscosity due to sulfur included in the paste can be preferably restrained by using nickel powder including extremely small amount of sulfur. Limitation of sulfur to the extremely small amount causes superior stability, and then, since kinds of solvents and resin binders are not limited, the change in viscosity can be preferably restrained with using the solvent that is hard to cause the chemical attack on the green sheet as described above. Thus, nickel paste that is hard to cause the chemical attack and the change in viscosity can be provided. | 2009-02-05 |
20090032781 | Nanorice particles: hybrid plasmonic nanostructures - A new hybrid nanoparticle, i.e., a nanorice particle, which combines the intense local fields of nanorods with the highly tunable plasmon resonances of nanoshells, is described herein. This geometry possesses far greater structural tunability than previous nanoparticle geometries, along with much larger local field enhancements and far greater sensitivity as a surface plasmon resonance (SPR) nanosensor than presently known dielectric-conductive material nanostructures. In an embodiment, a nanoparticle comprises a prolate spheroid-shaped core having a first aspect ratio. The nanoparticle also comprises at least one conductive shell surrounding said prolate spheroid-shaped core. The nanoparticle has a surface plasmon resonance sensitivity of at least 600 nm RIU | 2009-02-05 |
20090032782 | PHOTOCHROMIC MATERIALS HAVING EXTENDED PI-CONJUGATED SYSTEMS AND COMPOSITIONS AND ARTICLES INCLUDING THE SAME - Various non-limiting embodiments disclosed herein relate to photochromic materials having extended pi-conjugated systems, such as an indeno-fused naphthopyran, which comprises a group that extends the pi-conjugated system of the indeno-fused naphthopyran bonded at the 11-position thereof. Further, the photochromic materials according to certain non-limiting embodiments disclosed herein may display hyperchromic absorption of electromagnetic radiation as compared to conventional photochromic materials and/or may have a closed-form absorption spectrum that is bathochromically shifted as compared to conventional photochromic materials. Other non-limiting embodiments relate to photochromic compositions and photochromic articles, such as optical elements, made using the disclosed photochromic materials, and methods of making the same. | 2009-02-05 |
20090032783 | COUNTERBALANCING SHAFT ACCOMMODATING STRUCTURE - A counterbalancing shaft accommodating structure includes: a pair of counterbalancing shafts, provided in an oil pan attached to a lower end portion of an engine; and a housing, adapted to accommodate the counterbalancing shafts in the oil pan. An upper end portion of the housing is provided further upwards than the lower end portion of the engine. An opening is formed continuously to expand over both rotational axes of the pair of counterbalancing shafts in an upper surface of the housing. | 2009-02-05 |
20090032784 | Winch strap and method - A detachable winch strap is shown and disclosed. The winch strap is attached to a winch and the bow eye of a water vehicle. The winch strap is detachable at a connector located near the winch. Detaching the connector results in a first strap that remains fixed to the winch and a second strap that remains attached to a bow eye of the water vehicle. The second strap can then be used as a bow line for docking and other functions. When launching and loading a water vehicle from and onto a trailer, it is not necessary to get into the water or onto the trailer or lean over the bow to attach or detach the winch strap hook from the eye on the bow of the vehicle. Applicant's winch strap can be installed in existing winches. A method for launching and loading a trailer with the described winch strap is also disclosed. | 2009-02-05 |
20090032785 | SAFETY DEVICE - A safety device for a fall arrest system comprises: a body, attachment means for attaching the safety device to a support structure, a drum mounted for rotation relative to the body, a safety line wound on the drum, a speed sensitive clutch connected to the drum, and a linear energy absorber connecting the body to the attachment means, in which the speed sensitive clutch is adapted to respond to rotation of the drum relative to the body in a direction tending to unwind the safety line from the drum and above a predetermined speed by locking the drum against further rotation in said direction relative to the body, and the linear energy absorber is adapted to respond, when the speed sensitive clutch has locked the drum, to an applied load along the safety line greater than a threshold value by deploying and absorbing energy so that the attachment means moves away from the body. | 2009-02-05 |
20090032786 | SPARE TIRE CARRIER HAVING OVERLOAD PROTECTION WITH CONTROLLED CABLE PAYOUT - A tire carrier assembly is operative to provide a controlled payout of cable in response to an application of a minimum predetermined amount of force upon the tire carrier assembly. The tire carrier assembly includes a housing having a bottom wall and a side wall extending outwardly from the bottom wall defining an interior space. A rotation shaft is coupled to the housing and having a longitudinal axis. A sheave is coupled to the shaft and rotatable about the longitudinal axis. A gear member extends from the sheave and is rotatable therewith about the longitudinal axis. A pin fixedly secured to the housing. A torque plate has a gear portion epicyclically engaged with the gear member of the sheave. The torque plate has an arm portion extending generally radially outwardly with respect to the gear portion. The torque plate has a closed-ended slot formed in the arm portion and receiving the pin therethrough. The arm portion has legs extending along opposite sides of the slot. At least one of the legs has a weakened area at which the arm portion deforms in response to an application of a predetermined amount of force upon the tire carrier assembly and contacts an inner surface of the housing to provide a controlled payout of a cable from the sheave. | 2009-02-05 |
20090032787 | Hoisting and pulling device - A hoisting and pulling device including a main body frame | 2009-02-05 |
20090032788 | CLIMB RESISTANT SAFETY SECURITY FENCE - A large, hollow cylindrical top rail is installed along the top surface of a security fence. The rail has a lengthwise groove and fence post holes cut from the bottom of it. The hollow round rail is placed over the fence and fence posts and secured to the fence by removable fasteners. A spacer may also be inserted between the top of the fence post and the top of the rail to increase the height of the security rail. Lights, security cameras or motion detectors may be placed inside the hollow top rail. Once the top rail is in position, expandable foam is injected into the hollow area of the rail. The foam adheres to the fence and posts and the top rail is permanently attached to the fence. The fasteners may then be removed. The rail is slick, round and approximately a foot in diameter. This precludes anyone attempting to scale the fence from obtaining a handhold on the top of the fence. The top rail is weatherproof, electrically insulated and immovable and not only prevents anyone from scaling the fence but also protects the fence from the elements, vandalism and damage. The top rail may be applied to existing security fences or may be a new installation. The top rail makes the security fence virtually impossible to breach but is not as dangerous as barbed wire or razor wire topped fences. | 2009-02-05 |
20090032789 | Impact Attenuator System - An impact attenuator system includes a hyperelastic member that comprises an energy-absorbing material which behaves in a rate-independent hyperelastic manner so that its permanent set is minimized and the material can absorb tremendous amounts of impact energy while remaining fully recoverable. | 2009-02-05 |
20090032790 | Portable electric fence - An electric fence is provided. The electric fence includes a plurality of panels that are releasably connected to one another to form at least a partial enclosure. Each of the panels has a frame that includes a top horizontal member, a bottom horizontal member, and two side vertical members. The panels are arranged side by side such that the vertical members of adjacent panels are releasably connected to one another. The frame carries a wire member that is electrically conductive for use in delivering an electrical shock to livestock that comes into contact with the wire member. | 2009-02-05 |
20090032791 | High Impact Resistant Barrier/Fence - A barrier is disclosed which includes a connected pair of upstanding and equidistantly spaced first and second walls which together define a channel having a bottom and an open top. Dirt or rock fill (or fill of any other non-vegetative material) is poured into or otherwise placed in the channel between the walls to cover the bottom of the channel and at least partially fill the channel. The area of the channel containing the fill may be lined with geo-textile material to help contain the fill. | 2009-02-05 |
20090032792 | Arrangement and method for connecting fence sections - A fence includes an upright post and one or more rails radiating from the post. An arrangement for connecting the post to the rail or rails includes a carrier that can be mounted on the post and one or more holders for the rail or rails. Each holder is attached to the carrier by a hinge that allows the respective holder to pivot or rotate relative to the carrier in two different planes. An accessory bracket for flexible rails and a gate hinge may also be connected to the carrier. | 2009-02-05 |
20090032793 | Resistor Random Access Memory Structure Having a Defined Small Area of Electrical Contact - A memory cell device, of the type that includes a memory material switchable between electrical property states by application of energy, includes first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug. The dielectric form is wider near the first electrode, and is narrower near the phase change plug. The area of contact of the conductive film with the phase change plug is defined in part by the geometry of the dielectric form over which the conductive film is formed. Also, methods for making the device include steps of constructing a dielectric form over a first electrode, and forming a conductive film over the dielectric form. | 2009-02-05 |
20090032794 | PHASE CHANGE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A phase change memory device is disclosed. A first dielectric layer having a sidewall is provided. A bottom electrode is adjacent to the sidewall of the first dielectric layer, wherein the bottom electrode comprises a seed layer and a conductive layer. A second dielectric layer is adjacent to a side of the bottom electrode opposite the sidewall of the first dielectric layer. A top electrode couples the bottom electrode through a phase change layer. | 2009-02-05 |
20090032795 | Schottky diode and memory device including the same - A Schottky diode and a memory device including the same are provided. The Schottky diode includes a first metal layer and an Nb-oxide layer formed on the first metal layer. | 2009-02-05 |
20090032796 | PHASE CHANGE MEMORY BRIDGE CELL - Memory devices are described along with manufacturing methods. An embodiment of a memory device as described herein includes a conductive bit line and a plurality of first electrodes. The memory device includes a plurality of insulating members, the insulating members having a thickness between a corresponding first electrode and a portion of the bit line acting as a second electrode. The memory device further includes an array of bridges of memory material having at least two solid phases, the bridges contacting respective first electrodes and extending across the corresponding insulating member to the bit line. The bridges define an inter-electrode path between the corresponding first electrode and the bit line defined by the thickness of the insulating member. | 2009-02-05 |
20090032797 | PHOTOCATHODE - When to-be-detected light is made incident from a support substrate | 2009-02-05 |
20090032798 | LIGHT EMITTING DIODE (LED) - A light-emitting diode (LED) includes a p-type layer, an n-type layer, and an active layer arranged between the p-type layer and the n-type layer. The active layer includes at least one quantum well adjacent to at least one modulation-doped layer. Alternatively, or in addition thereto, at least one surface of the n-type layer or the p-type layer is texturized to form a textured surface facing the active layer. | 2009-02-05 |
20090032799 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate having a first surface and a second surface not parallel to the first surface, and a light emission layer disposed over the second surface to emit light. The light emission layer has a light emission surface which is not parallel to the first surface. | 2009-02-05 |
20090032800 | PHOTONIC CRYSTAL LIGHT EMITTING DEVICE - There is provided a photonic crystal light emitting device including: a substrate; a plurality of nano rod light emitting structures formed on the substrate to be spaced apart from one another, each of the nano rod light emitting structures including a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer; and first and second electrodes electrically connected to the first and second conductivity type semiconductor layers, respectively, wherein the nano rod light emitting structures are arranged with a predetermined size and period so as to form a photonic band gap for light emitted from the active layer, whereby the nano rod light emitting structures define a photonic crystal structure. In the photonic crystal light emitting device, the nano rod light emitting structures are arranged to define a photonic crystal to enhance light extraction efficiency. | 2009-02-05 |
20090032801 | Approach to contacting nanowire arrays using nanoparticles - An in situ approach toward connecting and electrically contacting vertically aligned nanowire arrays using conductive nanoparticles is provided. The utility of the approach is demonstrated by development of a gas sensing device employing the nanowire assembly. Well-aligned, single-crystalline zinc oxide nanowires were grown through a direct thermal evaporation process at 550° C. on gold catalyst layers. Electrical contact to the top of the nanowire array was established by creating a contiguous nanoparticle film through electrostatic attachment of conductive gold nanoparticles exclusively onto the tips of nanowires. A gas sensing device was constructed using such an arrangement and the nanowire assembly was found to be sensitive to both reducing (methanol) and oxidizing (nitrous oxides) gases. This assembly approach is amenable to any nanowire array for which a top contact electrode is needed. | 2009-02-05 |
20090032802 | MOSFET DEVICE FEATURING A SUPERLATTICE BARRIER LAYER AND METHOD - A method of forming a semiconductor structure comprises forming a channel layer; forming a superlattice barrier layer overlying the channel layer, and forming a gate dielectric overlying the superlattice barrier layer. The superlattice barrier layer includes a plurality of alternating first and second layers of barrier material. In addition, the superlattice barrier layer is configured for increasing a transconductance of the semiconductor device by at least a factor of three over a semiconductor device absent such superlattice barrier layer. | 2009-02-05 |
20090032803 | METHOD AND APPARATUS FOR FABRICATING A CARBON NANOTUBE TRANSISTOR - A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions of the nanotube. In a further embodiment, the method includes forming at least one trench in the gate dielectric (e.g., a back gate dielectric) and back gate adjacent to the local gate electrode. Another aspect of the invention is a nanotube field-effect transistor fabricated using such a method. | 2009-02-05 |
20090032804 | Self-Aligned T-Gate Carbon Nanotube Field Effect Transistor Devices and Method for Forming the Same - A method is provided for forming a self-aligned carbon nanotube (CNT) field effect transistor (FET). According to one feature, a self-aligned source-gate-drain (S-G-D) structure is formed that allows for the shrinking of the gate length to arbitrarily small values, thereby enabling ultra-high performance CNT FETs. In accordance with another feature, an improved design of the gate to possess a “T”-shape, referred to as the “T-Gate,” thereby enabling a reduction in gate resistance and further providing an increased power gain. The self-aligned T-gate CNT FET is formed using simple fabrication steps to ensure a low cost, high yield process. | 2009-02-05 |
20090032805 | Microresonator systems and methods of fabricating the same - Various embodiments of the present invention are related to microresonator systems that can be used as a laser, a modulator, and a photodetector and to methods for fabricating the microresonator systems. In one embodiment, a microresonator system comprises a substrate having a top surface layer, at least one waveguide embedded within the substrate, and a microdisk having a top layer, an intermediate layer, a bottom layer, current isolation region, and a peripheral annular region. The bottom layer of the microdisk is in electrical communication with the top surface layer of the substrate and is positioned so that at least a portion of the peripheral annular region is located above the at least one waveguide. The current isolation region is configured to occupy at least a portion of a central region of the microdisk and has a relatively lower refractive index and relatively larger bandgap than the peripheral annular region. | 2009-02-05 |
20090032806 | POLYMER COMPOSITE P-N JUNCTION AND METHOD FOR MANUFACTURING SAME AND POLYMER COMPOSITE DIODE INCORPORATING SAME - The present polymer composite p-n junction includes an n-type polymer composite layer and a p-type polymer composite layer. The n-type composite polymer layer includes a first polymer material and a number of electrically conductive particles imbedded therein. The p-type composite polymer layer includes a second polymer material and a number of carbon nanotubes (CNTs) imbedded therein. A method for manufacturing the polymer composite p-n junction and a polymer composite diode incorporating the polymer composite p-n junction are also provided. | 2009-02-05 |
20090032807 | Method of Manufacturing Semiconductor Element, Semiconductor Element, Electronic Device, and Electronic Equipment - The object of the present invention is to provide a method of manufacturing a semiconductor element which can produce a semiconductor element provided with a semiconductor layer having a high carrier transport ability, a semiconductor element manufactured by the semiconductor element manufacturing method, an electronic device provided with the semiconductor element, and electronic equipment having a high reliability. In order to achieve the object, the present invention is directed to a method of manufacturing a semiconductor element having an anode, a cathode, and a hole transport layer provided between the anode and the cathode, the method comprising steps of: a first step for forming layers mainly comprised of a hole transport material having polymerizable groups X on the side of one surface of the anode and on the side of one surface of the cathode, respectively, and a second step for obtaining the hole transport layer by integrating the two layers together by polymerizing the hole transport materials via a polymerization reaction through their polymerizable groups in a state that the layer on the side of the anode and the layer on the side of the cathode are made contact with each other. | 2009-02-05 |
20090032808 | ENHANCING PERFORMANCE CHARACTERISTICS OF ORGANIC SEMICONDUCTING FILMS BY IMPROVED SOLUTION PROCESSING - Improved processing methods for enhanced properties of conjugated polymer films are disclosed, as well as the enhanced conjugated polymer films produced thereby. Addition of low molecular weight alkyl-containing molecules to solutions used to form conjugated polymer films leads to improved photoconductivity and improvements in other electronic properties. The enhanced conjugated polymer films can be used in a variety of electronic devices, such as solar cells and photodiodes. | 2009-02-05 |
20090032809 | Organic thin film transistor and method of manufacturing the same - Disclosed are an organic thin film transistor and a method of manufacturing the same, in which a crystalline organic binder layer is on the surface of an organic insulating layer and source/drain electrodes or on the surface of the source/drain electrodes. The organic thin film transistor may be improved in two-dimensional geometric lattice matching and interface stability at the interface between the organic semiconductor and the insulating layer or at the interface between the organic semiconductor layer and the electrode, thereby improving the electrical properties of the device. | 2009-02-05 |
20090032810 | ORGANIC TRANSISTOR AND ACTIVE-MATRIX SUBSTRATE - An organic transistor includes a gate electrode having a predetermined length, source and drain electrodes overlapping the gate electrode in plan view, a channel region formed of the organic semiconductor between the source and drain electrodes, and a functional portion disposed on a first side of the gate electrode in a length direction thereof and connected to the drain electrode through a strip-like connection wiring line. A strip-like dummy connection wiring line is connected to the drain electrode so as to extend toward a second side of the gate electrode in the length direction thereof and has a width that is less than twice the width of the connection wiring line. The connection wiring line extends to or beyond an edge of the gate electrode on the first side, and the dummy connection wiring line extends to or beyond an edge of the gate electrode on the second side. | 2009-02-05 |
20090032811 | FUNCTIONALIZATION OF POLY(ARYLENE-VINYLENE) POLYMERS FOR ELECTRONIC DEVICES - A method is provided for modifying a poly(arylene vinylene) or poly(heteroarylene vinylene) precursor polymer having dithiocarbamate moieties by reacting it with an acid and further optionally reacting the acid-modified polymer with a nucleophillic agent. Also provided are novel polymers and copolymers bearing nucleophillic side groups which are useful as components of electronic devices, e.g. in the form of thin layers. | 2009-02-05 |
20090032812 | Microelectronic device - A microelectronic device includes a thin film transistor having an oxide semiconductor channel and an organic polymer passivation layer formed on the oxide semiconductor channel. | 2009-02-05 |
20090032813 | Test Wafer, Manufacturing Method Thereof and Method for Measuring Plasma Damage - Embodiments of the present invention provide a test wafer capable of analyzing plasma damage, a manufacturing method thereof, and a method for measuring plasma damage using the same. A test wafer according to an embodiment includes a transistor device having at least one probe contact and a gate insulating film comprising a charging trap layer. The plasma process in the process for manufacturing the semiconductor device can be optimized by using the test wafer to determine plasma damage, making it possible to inhibit defect occurrence and malfunction of the semiconductor device and extend the life of the gate insulating layer. | 2009-02-05 |
20090032814 | SiGe DIAC ESD protection structure - A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors. | 2009-02-05 |
20090032815 | PIXEL WELL ELECTRODES - A multi-level mandrel is used to locate an electrode in a pixel well. A display includes an electrode recessed in a floor of a pixel well. | 2009-02-05 |
20090032816 | PIXEL WELL ELECTRODE - Various apparatus and methods relating to pixel wells and electrodes that are at least partially concurrently formed are disclosed. | 2009-02-05 |
20090032817 | Back-To-Back Metal/Semiconductor/Metal (MSM) Schottky Diode - A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage. | 2009-02-05 |
20090032818 | THIN FILM TRANSISTOR ARRAY PANEL AND LIQUID CRYSTAL DISPLAY INCLUDING THE PANEL - A gate wire including a gate line and a gate electrode is formed on an insulating substrate of a TFT array panel. A semiconductor pattern made of amorphous silicon is formed on the gate insulating layer covering the gate wire. A data wire including a data line, a source electrode, and a drain electrode is formed on the semiconductor pattern or the gate insulating layer covering the gate wire. A part of the semiconductor pattern extends under the data line, and a light blocking member overlapping the semiconductor pattern under the data line is formed using the same layer as the gate wire. The light blocking member is to prevent light incident upon the substrate from a backlight from entering the amorphous silicon layers; therefore, the stripes of different brightness and waterfall phenomenon in which the stripes move up and down can be removed in an LCD using a backlight driven by a rectangular wave of ON/OFF signals outputted from inverter. | 2009-02-05 |
20090032819 | Array substrate for liquid crystal display device and method of fabricating the same - An array substrate for a liquid crystal display device, including: a substrate; a gate line on the substrate; a data line crossing the gate line to define a pixel region; a thin film transistor connected to the gate line and the data line, the thin film transistor including a gate electrode connected to the gate line, a semiconductor layer whose boundary is within the gate electrode, a source electrode connected to the data line and a drain electrode spaced apart from the source electrode; a passivation pattern covering the data line and the thin film transistor; and a pixel electrode extending from the drain electrode. | 2009-02-05 |
20090032820 | Reliable Normally-Off III-Nitride Active Device Structures, and Related Methods and Systems - A field-effect transistor includes a first gate, a second gate held at a substantially fixed potential in a cascode configuration, and a semiconductor channel. The semiconductor channel has an enhancement mode portion and a depletion mode portion. The enhancement mode portion is gated to be turned on and off by the first gate, and has been modified to operate in enhancement mode. The depletion mode portion is gated by the second gate, and has been modified to operate in depletion mode and that is operative to shield the first gate from voltage stress. | 2009-02-05 |
20090032821 | SEMICONDUCTOR DEVICE AND ELECTRICAL CIRCUIT DEVICE USING THEREOF - A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N | 2009-02-05 |
20090032822 | HIGH POWER LIGHT EMITTING DIODE - A high power light emitting diode, The high power light emitting diode comprises a light emitting diode chip, a main module, two first electrode pins, two second electrode pins, and at least one heat dissipation board. The main module has a concave and the light emitting diode chip is positioned in the concave. The first electrode pins are connected to a first side of the main module and also electrically connected to the light emitting diode chip. The second electrode pins are arranged on a second side of the main module that is relative to the first electrode pins wherein the second electrode pins and the first electrode pins are electrically opposite. The second electrode pins are electrically connected to the light emitting diode chip. The heat dissipation board is connected to a part of the main module between the first electrode pin and the second electrode pin. | 2009-02-05 |
20090032823 | Photo sensor and light emitting display having the same - A photo sensor includes a light incidence unit including a plurality of light incidence layers, the light incidence unit having a varying light transmittance with respect to external light, and a photo sensing unit including a plurality of photo sensing elements, the photo sensing unit being configured to output electrical signals in accordance with an amount of light transmitted through the light incidence unit to determine intensity of the external light, each of the photo sensing elements being configured to output electrical signals in accordance with light transmitted through a respective light incidence layer. | 2009-02-05 |
20090032824 | Image displaying device - An image displaying device having multiple photosensing devices have successfully suppressed a leakage current from each photosensing device and improved the S/N ratio. In the image displaying device, pixels and photosensing devices are disposed as pairs in a matrix pattern on a substrate. Each of the pixels and each of the photosensing devices are driven independently. Each photosensing device includes a semiconductor layer that is a photoelectric conversion layer connected to at least a first electrode and a second electrode. The contact surfaces of the first and second electrodes with respect to the semiconductor layer are disposed so that their center axes are separated from each other. | 2009-02-05 |
20090032825 | Structure Of LED-Based Display Module And Method For Manufacturing The Same - The display module contains a circuit board, a heat-resistant and transparent protective layer, and a transparent and waterproofing enclosing member. The circuit board has a number of LED devices configured on the front surface and at least a terminal on the back surface. The LED devices are electrically and signally wired to the terminal so that electricity and video signals are fed to the LED devices via the terminal. The protective layer is coated on the outer surfaces of the LED devices and the circuit board so as to protect the wiring, the soldering contacts, and the electrical components of the circuit board from being damaged by the high temperature during the process of forming the enclosing member. The enclosing member wraps the circuit board and the LED devices entirely within and exposes only the terminal. | 2009-02-05 |
20090032826 | MULTI-CHIP LIGHT EMITTING DIODE PACKAGE - A multi-chip light emitting diode (LED) package having a plurality of LED chips, a substrate, and a plurality of conductive paste layers is provided. The substrate has at least two hollow areas with conductive patterns formed on a bottom surface thereon. The conductive paste layers are pasted on the bottom surfaces of the hollow areas respectively for fixing the LED chips and having the LED chips electrically connected to the conductive patterns. The LED chips in the different hollow areas are electrically connected in serial. | 2009-02-05 |
20090032827 | Concave Wide Emitting Lens for LED Useful for Backlighting - Lenses for LEDs are described that efficiently create a substantially uniform light emission across a surface of a backlight box. The backlight may illuminate an LCD. A wide-emitting lens refracts light emitted by an LED die to cause a peak intensity to occur within 35-65 degrees off the die's center axis, normal to the die's top surface, and an intensity along the center axis to be between 40% and 90% of the peak intensity. The lens is concave over the die and has smooth edges that transition into the lens sidewalls. The direct emissions of the lenses from a plurality of LEDs arranged on a base surface in a backlight box combine together to uniformly illuminate a light output surface of the backlight box. | 2009-02-05 |
20090032828 | III-Nitride Device Grown on Edge-Dislocation Template - A semiconductor light emitting device includes a wurtzite III-nitride semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A template layer and a dislocation bending layer are grown before the light emitting layer. The template layer is grown such that at least 70% of the dislocations in the template layer are edge dislocations. At least some of the edge dislocations in the template layer continue into the dislocation bending layer. The dislocation bending layer is grown to have a different magnitude of strain than the template layer. The change in strain at the interface between the template layer and the dislocation bending layer causes at least some of the edge dislocations in the template layer to bend to a different orientation in the dislocation bending layer. Semiconductor material grown above the bent edge dislocations may exhibit reduced strain. | 2009-02-05 |
20090032829 | LED Light Source with Increased Thermal Conductivity - A light source and method for making the same are disclosed. The light source includes a substrate, a plurality of dies and a transparent layer of encapsulant. The substrate includes an insulating layer having top and bottom surfaces, the top surface having a first metal patterned layer thereon, and the bottom surface having a second metal patterned layer thereon. The first metal patterned layer has a plurality of die mounting areas thereon, and the second metal patterned layer includes a first contact layer that underlies the die mounting area, the die mounting area and the first contact layer being connected by metal lined vias at each of the die mounting areas. The transparent encapsulant covers the plurality of dies and is bonded to the first metal patterned layer and the top surface of the insulating layer. | 2009-02-05 |
20090032830 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light-emitting diode and the manufacturing method thereof are disclosed. The manufacturing method comprises the steps of: sequentially forming a refraction dielectric layer, a bonding layer, an epitaxy structure and a first electrode on a permanent substrate, wherein the epitaxy structure comprises a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer stacked in sequence; and forming a second electrode on the portion surface of the second conductivity type semiconductor layer. Therefore the light-emitting diode is achieved. | 2009-02-05 |
20090032831 | Optical waveguide apparatus and method for manufacturing the same - An optical waveguide apparatus having a very simple structure that can modulate a signal light guided through an optical waveguide is provided. A photoresist | 2009-02-05 |
20090032832 | LIGHT EMITTING DIODE STRUCTURE - A light emitting diode structure has a silicon substrate, a conductive layer, and a light emitting diode. The top surface of the silicon substrate has a cup-structure like paraboloid, and the bottom of the cup-structure has a plurality of through-holes penetrating the silicon substrate. The conductive layer fills up the through-holes and protrudes out from the through-holes. The light emitting diode is disposed on the top of the conductive layer protruding out from the through-holes and is located at the focus of the cup-structure. | 2009-02-05 |
20090032833 | LIGHT EMITTING DIODE HAVING ALGAN BUFFER LAYER AND METHOD OF FABRICATING THE SAME - The present invention relates to a light emitting diode having an Al | 2009-02-05 |
20090032834 | HIGHLY EFFICIENT LED WITH MICROCOLUMN ARRAY EMITTING SURFACE - A highly efficient light emitting diode with microcolumn array emitting surface, wherein the microcolumn array is prepared on the emitting surface of the light emitting diode, and can be formed with a two-dimensional periodic or non-periodic structure, the length and height of each microcolumn are in the same order of magnitude as, more specifically are from half to a few of, the wavelength of the emitting light. This invention utilizes a strong diffraction effect of the microcolumn array to increase the luminous efficiency of the light emitting diode. The distribution of light emitting is uniform. Compared with the conventional two-dimensional photonic crystal light emitting diode, the manufacturing process of this invention is simple, and the manufacturing cost is low. Compared with the conventional porous surface light emitting diode, the luminous efficiency of the light emitting diode according to this invention is high. | 2009-02-05 |
20090032835 | III-NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - The present disclosure provides a III-nitride semiconductor light emitting device, including: a plurality of III-nitride semiconductor layers including an active layer for generating light by recombination of electrons and holes; and a substrate used to grow the plurality of III-nitride semiconductor layers, and including a protrusion with two opposite sides rounded. | 2009-02-05 |
20090032836 | SEMICONDUCTOR LIGHT EMITTING DIODE THAT USES SILICON NANO DOT AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor light emitting diode that uses a silicon nano dot and a method of manufacturing the same. The semiconductor light emitting diode includes a light emitting layer that emits light; a hole injection layer formed on the light emitting layer; an electron injection layer formed on the light emitting layer to face the hole injection layer; a metal layer that comprises a metal nano dot and is formed on the electron injection layer; and a transparent conductive electrode formed on the metal layer. Amorphous silicon nitride that includes the silicon nano dot is used as the light emitting layer. | 2009-02-05 |
20090032837 | ASYMMETRIC BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER - The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier. | 2009-02-05 |
20090032838 | SYMMETRIC BIDIRECTIONAL SILICON-CONTROLLED RECTIFIER - The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas. | 2009-02-05 |
20090032839 | Semiconductor Device and Its Driving Method - A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth semiconductor region of the first conductivity type (anode gate AG) are formed in the top layer of a first semiconductor region; fifth semiconductor region of the first conductivity type (cathode CA) and sixth semiconductor region of the second conductivity type (cathode gate CG) are formed in the top layer of a second semiconductor region; a gate insulating film and gate electrode MG are formed on the second semiconductor region. When the thyristor is turned off from the on state, a higher potential than that on the anode is applied to the anode gate, and a diode made up of the anode and the anode gate inside the thyristor is made to conduct so as to control the potential of the anode during driving. | 2009-02-05 |
20090032840 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE - A semiconductor device and method of manufacture and, more particularly, a semiconductor device having strain films and a method of manufacture. The device includes an embedded SiGeC layer in source and drain regions of an NFET device and an embedded SiGe layer in source and drain regions of a PFET device. The PFET device is subject to compressive strain. The method includes embedding SiGe in source and drain regions of an NFET device and implanting carbon in the embedded SiGe forming an SiGeC layer in the source and drain regions of the NFET device. The SiGeC is melt laser annealed to uniformly distribute the carbon in the SiGeC layer, thereby counteracting a strain generated by the embedded SiGe. | 2009-02-05 |
20090032841 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material. | 2009-02-05 |
20090032842 | NANOMEMBRANE STRUCTURES HAVING MIXED CRYSTALLINE ORIENTATIONS AND COMPOSITIONS - The present nanomembrane structures include a multilayer film comprising a single-crystalline layer of semiconductor material disposed between two other single-crystalline layers of semiconductor material. A plurality of holes extending through the nanomembrane are at least partially, and preferably entirely, filled with a filler material which is also a semiconductor, but which differs from the nanomembrane semiconductor materials in composition, crystal orientation, or both. | 2009-02-05 |
20090032843 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, and a MIS type FET provided on the semiconductor substrate, the MIS type FET includes a gate insulating film provide on the semiconductor substrate, a gate electrode provided on the gate insulating film, a channel region provided in the semiconductor substrate and being isolated from the gate electrode by the gate insulating film, source/drain layers sandwiching the channel region, the source/drain layers including semiconductor layers having lattice spacing which is different from that of the semiconductor substrate and having uniform height, and a metal silicide layer provided on a region including a top surfaces of the source/drain layers and failing to provide on the channel region. | 2009-02-05 |
20090032844 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device has forming a transistor including a source and a drain, forming a mixed crystal layer over the source and the drain, forming a silicide layer over the mixed crystal layer, forming a first insulating film and a second insulating film over the silicide layer, forming a contact hole, performing an oxygen plasma treatment, and forming a conductive plug in the contact hole. | 2009-02-05 |
20090032845 | SOI FIELD EFFECT TRANSISTOR HAVING ASYMMETRIC JUNCTION LEAKAGE - A source trench and a drain trench are asymmetrically formed in a top semiconductor layer comprising a first semiconductor in a semiconductor substrate. A second semiconductor material having a narrower band gap than the first semiconductor material is deposited in the source trench and the drain trench to form a source side narrow band gap region and a drain side narrow band gap region, respectively. A gate spacer is formed and source and drain regions are formed in the top semiconductor layer. A portion of the boundary between an extended source region and an extended body region is formed in the source side narrow band gap region. Due to the narrower band gap of the second semiconductor material compared to the band gap of the first semiconductor material, charge formed in the extended body region is discharged through the source and floating body effects are reduced or eliminated. | 2009-02-05 |
20090032846 | POWER AND GROUND SHIELD MESH TO REMOVE BOTH CAPACITIVE AND INDUCTIVE SIGNAL COUPLING EFFECTS OF ROUTING IN INTEGRATED CIRCUIT DEVICE - A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid. A similar embodiment represents grid routing technique where the signals are routed between layers N and N+1. Another embodiment enables signals to be shielded by opposite power and ground grids on left, right, top and bottom. Additional embodiments also include utilization of similar mesh utilized in standard cell and/or in the gate array routing area or any other area where any other signal line is to be shielded. | 2009-02-05 |
20090032847 | SEMICONDUCTOR WAFER AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor wafer and a manufacturing method for a semiconductor device are provided, which prevent peeling-off of films and pattern skipping in a wafer edge portion. A silicone substrate has formed thereon gate structures in active regions isolated by a trench isolation film; a contact interlayer film; and a multilayer interconnection structure formed by alternate laminations of low-k via interlayer films, i.e., V layers, and low-k interconnect interlayer films, i.e., M layers. In a Fine layer ranging from first to fifth interlayer films, the M layers are removed from the wafer edge portion, but the V layers are not removed therefrom. Further, the contact interlayer film is not removed from the wafer edge portion. | 2009-02-05 |
20090032848 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SAME - A method for manufacturing a semiconductor device. The method includes providing a semiconductor body of a conductivity type, wherein the semiconductor body comprises a first surface. At least one buried region of a second conductivity type is formed in the semiconductor body and at least a surface region of the second conductivity type is formed at the first surface of the semiconductor body, wherein the buried region and the surface region are formed such that they are spaced apart from each other. The buried region is formed by deep implantation of a first dopant of the second conductivity type. | 2009-02-05 |
20090032849 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a cylindrical main pillar that is formed on a substrate and of which a central axis is perpendicular to the surface of the substrate, source and drain diffused layers that are formed in a concentric shape centered on the central axis at upper and lower portions of the main pillar and made from a first-conduction-type material, a body layer that is formed at an intermediate portion of the main pillar sandwiched between the source and drain diffused layers and made from the first-conduction-type material, and a front gate electrode that is formed on a lateral face of the main pillar while placing a gate insulating film therebetween. Moreover, a back gate electrode made from a second-conduction-type material is formed in a pillar shape penetrating from an upper portion to a lower portion on an inner side of the main pillar. | 2009-02-05 |
20090032850 | N-channel MOS Transistor Fabricated Using A Reduced Cost CMOS Process - An NMOS transistor includes a semiconductor substrate of a first conductivity type, first and second well regions of a second conductivity type formed spaced apart in the substrate, a conductive gate formed over the region between the spaced apart first and second well regions where the region of the substrate between the spaced apart first and second well regions forms the channel region, dielectric spacers formed on the sidewalls of the conductive gate, first and second heavily doped source and drain regions of the second conductivity type formed in the semiconductor substrate and being self-aligned to the edges of the dielectric spacers. The first and second well regions extend from the respective heavily doped regions through an area under the spacers to the third well region. The first and second well regions bridge the source and drain regions to the channel region of the transistor formed by the third well. | 2009-02-05 |
20090032851 | Method for Producing a Semiconductor Body Having a Recombination Zone, Semiconductor Component Having a Recombination Zone, and Method for Producing Such a Semiconductor Component - In a method for producing a semiconductor body, impurities which act as recombination centers in the semiconductor body and form a recombination zone are introduced into the semiconductor body during the process of producing the semiconductor body. In a semiconductor component, comprising a semiconductor body having a front surface and an opposite rear surface, and also a recombination zone formed by impurities between the front and rear surfaces, wherein the impurities act as recombination centres, the surface state density at the front and rear surfaces of the semiconductor body is just as high as the surface state density at a front and rear surface of an identical semiconductor body without a recombination zone. | 2009-02-05 |
20090032852 | CMOS image sensor - A CMOS (Complementary Metal-Oxide Semiconductor) image sensor is provided. A CMOS image sensor includes a first light-receiving unit converting light into charge, a first floating diffusion region, in which a first potential corresponding to the converted amount of charge is generated and a second floating diffusion region, to which the charge in the first floating diffusion region is transmitted, and in which a second potential is generated, wherein a wide dynamic range signal is acquired from the first floating diffusion region, a high-sensitively signal is acquired from the second floating diffusion region, and the acquired signals are synthesized and output. | 2009-02-05 |
20090032853 | CMOS image sensors and methods of fabricating the same - CMOS image sensors and methods of fabricating the same. The CMOS image sensors include a pixel array region having an active pixel portion and an optical block pixel portion which encloses the active pixel portion. The optical block pixel portion includes an optical block metal pattern for blocking light. The optical block metal pattern may be connected to a ground portion. | 2009-02-05 |
20090032854 | IMAGE SENSOR AND SENSOR UNIT - This image sensor is so formed as to control at least either the potential of a portion of a transfer channel corresponding to a third electrode or the potential of another portion of the transfer channel corresponding to a fourth electrode to be lower than the potentials of portions of the transfer channel corresponding to a first electrode and a second electrode respectively in a signal charge transferring operation and a signal charge increasing operation. | 2009-02-05 |
20090032855 | METHOD FOR FORMING A DEEP TRENCH IN AN SOI DEVICE BY REDUCING THE SHIELDING EFFECT OF THE ACTIVE LAYER DURING THE DEEP TRENCH ETCH PROCESS - By providing a conductive connection between the active semiconductor layer and the substrate material in an SOI device during the anisotropic etch process for forming a deep trench portion in the substrate material, the uniformity of the etch conditions may be increased, thereby enabling greater etch depth and enhanced controllability with respect to the shape of the deep trench portion. | 2009-02-05 |
20090032856 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a volatile memory device is provided. The manufacturing method includes steps as follows. A sacrificial layer is formed in an area which is predetermined for forming a metal gate. Then, a thermal treatment process or other high temperature processes are performed in a peripheral circuit region. Next, a fabricating process of the metal gate is performed. Thus, the volatile memory device which has a lower contact resistance and a higher driving ability of the device can be produced, and thereby poor thermal stability and pollution of metal diffusion can be avoided. | 2009-02-05 |
20090032857 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers ( | 2009-02-05 |
20090032858 | LAYOUT AND STRUCTURE OF MEMORY - A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on. | 2009-02-05 |
20090032859 | FINFET FLASH MEMORY DEVICE WITH AN EXTENDED FLOATING BACK GATE - A floating gate is formed on one side of the semiconductor fin on a floating gate dielectric. A control gate dielectric is formed on the opposite side of the semiconductor fin and on the floating gate. A gate conductor is formed on the control gate dielectric across the semiconductor fin. A gate spacer reaching above a gate cap layer and the control gate dielectric thereupon is formed by a conformal deposition of a dielectric layer and a reactive ion etch. The control gate dielectric and the material of the floating gate are removed from exposed portions of the semiconductor fin. The gate spacer is thereafter removed and source and drain regions are formed in the semiconductor fin. The overlap between the drain and the floating gate is extended by the thickness of the gate spacer, resulting in an enhanced efficiency in charge trapping in the floating gate. | 2009-02-05 |
20090032860 | PROGRAMMABLE MEMORY, PROGRAMMABLE MEMORY CELL AND THE MANUFACTURING METHOD THEREOF - A programmable memory structure includes a substrate, an active area, a common-source and a common-drain respectively disposed on each side of the active area, a first and a second source contact electrically connected to the common-source, a first and a second drain contact electrically connected to the common-drain, and between the first and the second source contact and the first and the second drain contact a plurality of programmable memory cells including a first and a second dielectric layer respectively encapsulating a first and a second floating gate. | 2009-02-05 |
20090032861 | NONVOLATILE MEMORIES WITH CHARGE TRAPPING LAYERS CONTAINING SILICON NITRIDE WITH GERMANIUM OR PHOSPHORUS - A nonvolatile memory has a charge trapping layer which includes a layer ( | 2009-02-05 |
20090032862 | Non-volatile memory cell and non-volatile memory device using said cell - A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near where the programming voltages were applied to. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and to either the right or the left region while the other region is grounded. Two bits are able to be programmed and read due to a combination of relatively low gate voltages with reading in the reverse direction. This greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region associated with each of the bits. In addition, both bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and either left or right regions so as to cause electrons to be removed from the corresponding charge trapping region of the nitride layer. | 2009-02-05 |
20090032863 | Nitridation oxidation of tunneling layer for improved SONOS speed and retention - A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O | 2009-02-05 |
20090032864 | SELF-ALIGNED CHARGE STORAGE REGION FORMATION FOR SEMICONDUCTOR DEVICE - Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film. | 2009-02-05 |