05th week of 2016 patent applcation highlights part 63 |
Patent application number | Title | Published |
20160035757 | SEMICONDUCTOR DEVICE - A semiconductor device capable of maintaining data during instantaneous power reduction or interruption. The semiconductor device includes first to sixth transistors. The first and fourth transistors are p-channel transistors. The second and fifth transistors are n-channel transistors. In the third and sixth transistors, an oxide semiconductor layer includes a channel formation region. A high voltage is applied to one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor. A low voltage is applied to one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor. | 2016-02-04 |
20160035758 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a pixel portion having a first thin film transistor and a driver circuit having a second thin film transistor. Each of the first thin film transistor and the second thin film transistor includes a gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer. Each of the layers of the first thin film transistor has a light-transmitting property. Materials of the gate electrode layer, the source electrode layer and the drain electrode layer of the first thin film transistor are different from those of the second transistor, and each of the resistances of the second thin film transistor is lower than that of the first thin film transistor. | 2016-02-04 |
20160035759 | FLEXIBLE DISPLAY DEVICE WITH WIRE HAVING REINFORCED PORTION AND MANUFACTURING METHOD FOR THE SAME - There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display. | 2016-02-04 |
20160035760 | ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - The invention belongs to the field of display technology, and particularly provides an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and a thin film transistor and driving electrodes provided on the base substrate, the thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain, the driving electrodes include a slit-shaped electrode and a plate-shaped electrode which are located in different layers and at least partially overlap with each other in the orthographic projection direction, the source, the drain and the active layer are formed so that part of their bottom surfaces are located in the same plane, and a resin layer is further provided between the thin film transistor and the plate-shaped electrode. | 2016-02-04 |
20160035761 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device including a substrate including a display area and a non-display area, a common electrode line in the non-display area, and a protective layer coating at least a part of an end portion of the common electrode line. | 2016-02-04 |
20160035762 | Methods for Manufacturing RFID Tags and Structures Formed Therefrom - Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g., improved electrical characteristics) as compared to tags containing organic electronic devices. | 2016-02-04 |
20160035763 | PROCESSING SUBSTRATES USING A TEMPORARY CARRIER - A technique comprising: securing a device substrate ( | 2016-02-04 |
20160035764 | PROCESSING SUBSTRATES USING A TEMPORARY CARRIER - A technique comprising: securing a device substrate ( | 2016-02-04 |
20160035765 | METHOD OF FABRICATING METAL WIRING AND THIN FILM TRANSISTOR SUBSTRATE - A method of fabricating metal wiring, including: sequentially forming first and second conductive layers on a substrate; forming a first photosensitive film pattern on the first and second conductive layers; forming first and second conductive patterns by etching parts of the first and second conductive layers by using the first photosensitive film pattern as a mask; forming a second photosensitive film pattern positioned inside the first photosensitive film pattern by a predetermined interval by ashing the first photosensitive film pattern; etching an exposed first conductive pattern by using the second photosensitive film pattern as a mask; and removing the second photosensitive film pattern. | 2016-02-04 |
20160035766 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device such as, for example an imaging sensor, includes a semiconductor layer in which, for example, a photodiode may be formed. An insulation film is disposed on a surface of the semiconductor layer. The insulation film includes one or more wirings or wiring layers formed therein. A semiconductor support substrate is disposed on the insulation film. The semiconductor support substrate includes a first layer (or region) and a second layer (or region) that is between the insulation film and the first layer. The first layer has a bulk micro defect density that is higher than a bulk micro defect density of the second layer. | 2016-02-04 |
20160035767 | PHOTOELECTRIC TRANSDUCER AND IMAGING SYSTEM - A photoelectric transducer includes a wiring structure and a photoelectric conversion section provided on a substrate. The photoelectric conversion section includes a first electrode and a photoelectric conversion layer provided on the first electrode. The wiring structure includes a first wiring layer including a wiring pattern. The distance between the bottom face of the first electrode and the substrate is shorter than the distance between the bottom face of the wiring pattern and the substrate. | 2016-02-04 |
20160035768 | IMAGE PICKUP APPARATUS, IMAGE PICKUP SYSTEM, AND METHOD FOR MANUFACTURING IMAGE PICKUP APPARATUS - An image pickup apparatus includes a first pixel electrode connected to a pixel circuit, a second pixel electrode adjoining the first pixel electrode and connected to the pixel circuit, a photoelectric conversion film continuously covering the first and second pixel electrodes, and an opposite electrode facing the first and second pixel electrodes via the film. The film includes a recessed portion recessed toward a portion between the first and second pixel electrodes on a surface opposite to the first and second pixel electrodes. The depth of the recessed portion is greater than the first pixel electrode's thickness, and a distance from the first pixel electrode to the recessed portion is greater than a distance from the first pixel electrode to the second pixel electrode. The opposite electrode is provided continuously along the surface via the film, and the recessed portion surrounds a part of the opposite electrode. | 2016-02-04 |
20160035769 | IMAGING APPARATUS AND IMAGING SYSTEM - The present invention reduces the leakage of the electric charge, which occurs at an end of a pixel electrode. An imaging apparatus includes: a plurality of pixel electrodes arranged separately from each other; an insulating film arranged on the pixel electrode; a pixel isolating film of an insulating member arranged between the pixel electrodes; and a photoelectric conversion film arranged on the insulating film, wherein the pixel isolating film contacts the pixel electrode. | 2016-02-04 |
20160035770 | IMAGE SENSOR FOR REDUCING CROSSTALK CHARACTERISTIC AND METHOD OF MANUFACTURING THE SAME - An image sensor includes a plurality of photoelectric detectors, a plurality of color filters, and at least one pixel isolation region between adjacent ones of the photoelectric detectors. The color filters include a white color filter, and the color filters correspond to respective ones of the photoelectric detectors. The at least one pixel isolation region serves to physically and at least partially optically separate the photoelectric detectors from one another. | 2016-02-04 |
20160035771 | Image Sensor Device and Method - A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration. | 2016-02-04 |
20160035772 | IMAGING DEVICE AND IMAGING SYSTEM - An imaging device includes a plurality of pixels arranged in a pixel region, each of the plurality of pixels including a photoelectric conversion element including a first electrode provided above a substrate, a second electrode provided above the first electrode and a photoelectric conversion layer provided between the first electrode and the second electrode, an interconnection layer provided between the substrate and the first electrode, the interconnection layer including a first conductive member extending in a first direction, and a second conductive member arranged at a level lower than the first conductive member and extending in a second direction intersecting the first direction, a first contact portion provided in the pixel region, the first contact portion electrically connecting the second electrode and the first conductive member, and a second contact portion electrically connecting the first conductive member and the second conductive member. | 2016-02-04 |
20160035773 | SEMICONDUCTOR IMAGE SENSORS HAVING CHANNEL STOP REGIONS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a light-receiving element which outputs electric charges in response to incident light, and a drive transistor which is gated by an output of the light-receiving element to generate a source-drain current in proportion to the incident light, wherein the drive transistor include a first gate electrode, a first channel region which is disposed under the first gate electrode, first source-drain regions which are disposed at respective ends of the first channel region and that have a first conductivity type, and a first channel stop region which is disposed on a side of the first channel region, and that separates the light-receiving element and the first channel region, the first channel stop region having a second conductivity type that is different from the first conductivity type. | 2016-02-04 |
20160035774 | IMAGE SENSORS AND METHODS OF FABRICATING THE SAME - An image sensor includes a photoelectric conversion element in a substrate, a first storage region spaced apart from the photoelectric conversion element in the substrate, a gate on the first storage region, a light shielding layer covering the gate, a dielectric layer disposed between the gate and the light shielding layer and extending onto a top surface of the substrate, an interlayer insulating structure covering the light shielding layer, and a micro-lens overlapping with the photoelectric conversion element on the interlayer insulating structure. The light shielding layer includes a first portion covering a sidewall of the gate, and a second portion on a top surface of the gate. The first portion has a first thickness corresponding to a vertical height from a bottom surface of the first portion to a top surface of the first portion, and the first thickness is greater than a second thickness of the second portion. | 2016-02-04 |
20160035775 | IMAGE SENSOR HAVING A METAL PATTERN BETWEEN COLOR FILTERS - An image sensor includes an inorganic color filter, an organic color filter, and a metal pattern. The inorganic color filter is on a support substrate. The organic color filter is on the support substrate. The organic color filter is spaced apart from the inorganic color filter. The metal pattern is between the inorganic color filter and the organic color filter. | 2016-02-04 |
20160035776 | METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND SOLID-STATE IMAGING DEVICE - Certain embodiments provide a method for manufacturing a solid-state imaging device, including thinning a semiconductor substrate, forming a plurality of masking patterns, and forming a groove having inclined surfaces that are inclined relative to a front surface of the semiconductor substrate at a back surface of the semiconductor substrate. A plurality of light receiving sections are provided in a lattice pattern at the front surface of the semiconductor substrate to be thinned. A wiring layer including metal wirings is provided on the front surface of the semiconductor substrate to be thinned. The plurality of masking patterns are arranged in a lattice pattern on the back surface of the thinned semiconductor substrate. The groove is formed by etching the semiconductor substrate between the masking patterns using an etchant having an anisotropic etching property. | 2016-02-04 |
20160035777 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other. | 2016-02-04 |
20160035778 | Thin Active Layer Fishbone Photodiode With A Shallow N+ Layer and Method of Manufacturing the Same - The present invention is directed toward a detector structure, detector arrays, and a method of detecting incident radiation. The present invention comprises a photodiode array and method of manufacturing a photodiode array that provides for reduced radiation damage susceptibility, decreased affects of crosstalk, reduced dark current (current leakage) and increased flexibility in application. | 2016-02-04 |
20160035779 | IMAGING APPARATUS AND IMAGING SYSTEM - Provided is an imaging apparatus includes: a substrate; a photoelectric conversion unit configured to generate a signal charge by photoelectric conversion; a contact wiring of a conductor electrically connected to the photoelectric conversion unit; a transistor including a control electrode, a first main electrode electrically connected to the contact wiring, and a second main electrode; a charge accumulating unit provided in the substrate and electrically connected to the second main electrode of the transistor; and a first switching unit configured to switch connection and disconnection between the control electrode and the first main electrode of the transistor. | 2016-02-04 |
20160035780 | SOLID-STATE IMAGE SENSING ELEMENT AND IMAGING SYSTEM - Each of a plurality of pixels arranged in two dimensions includes a photoelectric conversion unit including a pixel electrode, a photoelectric conversion layer provided above the pixel electrode, and a counter electrode provided so as to sandwich the photoelectric conversion layer between the counter electrode and the pixel electrode, and a microlens arranged above the photoelectric conversion unit. The plurality of pixels includes a first pixel and a plurality of second pixels. At least either the pixel electrodes of the plurality of second pixels are smaller than the pixel electrode of the first pixel or the counter electrodes of the plurality of second pixels are smaller than the counter electrode of the first pixel, and a configuration between the counter electrode and the microlens of the first pixel is the same as a configuration between the counter electrode and the microlens of each of the plurality of second pixels. | 2016-02-04 |
20160035781 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC INSTRUMENT - A solid-state imaging device including, a first semiconductor region of the first conduction type, a photoelectric conversion part having a second semiconductor region of the second conduction type formed in the region separated by the isolation dielectric region of the first semiconductor region, pixel transistors formed in the first semiconductor region, a floating diffusion region of the second conduction type which is formed in the region separated by the isolation dielectric region of the first semiconductor region, and an electrode formed on the first semiconductor region existing between the floating diffusion region and the isolation dielectric region and is given a prescribed bias voltage. | 2016-02-04 |
20160035782 | SHALLOW TRENCH TEXTURED REGIONS AND ASSOCIATED METHODS - Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation. The textured region can be formed from a series of shallow trench isolation features. | 2016-02-04 |
20160035783 | LOW NOISE HYBRIDIZED DETECTOR USING CHARGE TRANSFER - A low noise infrared photodetector has an epitaxial heterostructure that includes a photodiode and a transistor. The photodiode includes a high sensitivity narrow bandgap photodetector layer of first conductivity type, and a collection well of second conductivity type in contact with the photodetector layer. The transistor includes the collection well, a transfer well of second conductivity type that is spaced from the collection well and the photodetector layer, and a region of first conductivity type between the collection and transfer wells. The collection well and the transfer well are of different depths, and are formed by a single diffusion. | 2016-02-04 |
20160035784 | UNIT PIXEL OF IMAGE SENSOR, IMAGE SENSOR INCLUDING THE SAME AND METHOD OF MANUFACTURING IMAGE SENSOR - Provided are a unit pixel, an image sensor including the same, a portable electronic device including the same, and a method of manufacturing the same. The method of manufacturing includes: forming a photoelectric conversion region in a substrate; forming, in the substrate, a first floating diffusion region spaced apart from the photoelectric conversion region of the substrate, and a second floating diffusion region spaced apart from the first floating diffusion region; forming a first recess spaced apart from the first floating diffusion region and the second floating diffusion region by removing a portion of the substrate from a first surface of the substrate; filling the first recess to form a dual conversion gain (DCG) gate that extends perpendicularly or substantially perpendicularly from the first surface of the substrate; and forming a conductive layer to fill an inside of the first recess. | 2016-02-04 |
20160035785 | METHOD OF FORMING A LOW PROFILE IMAGE SENSOR PACKAGE - An image sensor package, and method of making same, that includes a printed circuit board having a first substrate with an aperture extending therethrough, one or more circuit layers, and a plurality of first contact pads electrically coupled to the one or more circuit layers. A sensor chip mounted to the printed circuit board and disposed at least partially in the aperture. The sensor chip includes a second substrate, a plurality of photo detectors formed on or in the second substrate, and a plurality of second contact pads formed at the surface of the second substrate which are electrically coupled to the photo detectors. Electrical connectors each electrically connect one of the first contact pads and one of the second contact pads. A lens module is mounted to the printed circuit board and has one or more lenses disposed for focusing light onto the photo detectors. | 2016-02-04 |
20160035786 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device, including grinding a first surface of a first semiconductor layer to generate a damage layer in a surface region of the first surface of the first semiconductor layer, polishing the damage layer to remove a portion with predetermined thickness of the damage layer; and etching the damage layer and the first semiconductor layer to remove the first semiconductor layer from a third surface of a second semiconductor layer, the third surface contacting to a second surface opposed to the first surface in the first semiconductor layer. | 2016-02-04 |
20160035787 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To protect a plurality of semiconductor chips of a sawn wafer housed in a shipping case. | 2016-02-04 |
20160035788 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Active patterns spaced apart from each other by an isolation layer are formed in a substrate. Gate structures extending in the isolation layer through the active patterns are formed. Each active pattern is divided into a central portion and a peripheral portion facing the central portion by the gate structures. A protrusion of at least one of active pattern is formed. The protrusion is exposed from a top surface of the isolation layer, and transformed into silicide such that a first silicide ohmic pad is formed at the central portion of the active pattern and a second silicide ohmic pad is formed at the peripheral portion of the active pattern. A conductive line structure electrically connected to the first silicide ohmic pad is formed. A conductive contact electrically connected to the second silicide ohmic pad is formed. A data storage unit electrically connected to the conductive contact is formed. | 2016-02-04 |
20160035789 | Method Of Manufacturing Semiconductor Device And Semiconductor Device Having Unequal Pitch Vertical Channel Transistors - A semiconductor device comprises a set of selection transistors, such as in a three-dimensional memory structure or stack having resistance change memory cells arranged along vertical bit lines. Each selection transistor has a non-shared control gate and a shared control gate. The transistor bodies may have an unequal pitch and a common height. Some of the transistor bodies can be misaligned with the vertical bit lines to fit the transistors to the stack. A method for programming the three-dimensional memory structure includes forming one or two channels in a transistor body to provide a current to selected memory cells. Programming can initially use one channel and subsequently use two channels based on a programming progress. A method for fabricating a semiconductor device includes etching a gate conductor material so that shared and non-shared control gates have a common height. | 2016-02-04 |
20160035790 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased. The semiconductor device of the present invention comprises a first pillar-shaped semiconductor layer, a gate insulating film formed around the first pillar-shaped semiconductor layer, a gate electrode made of a metal and formed around the gate insulating film, a gate line made of a metal and connected to the gate electrode, a second gate insulating film formed around an upper portion of the first pillar-shaped semiconductor layer, a first contact made of a second metal and formed around the second gate insulating film, a second contact which is made of a third metal and which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer, a second diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer, a pillar-shaped insulating layer formed on the second contact, a resistance-changing film formed around an upper portion of the pillar-shaped insulating layer, a lower electrode formed around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film, a reset gate insulating film that surrounds the resistance-changing film, and a reset gate that surrounds the reset gate insulating film. | 2016-02-04 |
20160035791 | RESISTANCE VARIABLE MEMORY CELL STRUCTURES AND METHODS - Resistance variable memory cell structures and methods are described herein. A number of embodiments include a first resistance variable memory cell comprising a number of resistance variable materials in a super-lattice structure and a second resistance variable memory cell comprising the number of resistance variable materials in a homogeneous structure. | 2016-02-04 |
20160035792 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a substrate including a major surface; a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface; a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; and a plurality of storage films provided in crossing sections of the first films and the second films. | 2016-02-04 |
20160035793 | IMAGE SENSORS AND ELECTRONIC DEVICES INCLUDING THE SAME - Image sensors, and electronic devices including the image sensors, include a first photoelectronic device including at least one of a blue photoelectronic device sensing light in a blue wavelength region, a red photoelectronic device sensing light in a red wavelength region, and a green photoelectronic device sensing light in a green wavelength region, and a second photoelectronic device stacked on one side of the first photoelectronic device without being interposed by a color filter, wherein the second photoelectronic device senses light in an infrared region. | 2016-02-04 |
20160035794 | PHOTOCHARGE STORAGE ELEMENT AND DEVICES INCLUDING THE SAME - A photocharge storage element includes a gate insulator formed on a gate electrode, a channel formed on the gate insulator between a source electrode and a drain electrode, and an organic photoelectric conversion element formed on the channel. The organic photoelectric conversion element generates photocharges in response to light. The channel accumulates the photocharges generated by the organic photoelectric conversion element. The photocharges accumulated in the channel are read out from the channel in response to a voltage between the source electrode and the drain electrode. | 2016-02-04 |
20160035795 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS - An organic light emitting display apparatus wherein a shift of white light caused by a viewing angle is reduced by adjusting an offset distance between one end of a corresponding emission region and one end of the black matrix adjacent to the one end of the corresponding emission region, thereby preventing a white color shift phenomenon at various viewing angles. Accordingly, a certain image is produced regardless of a use environment of a user's viewing angle. | 2016-02-04 |
20160035796 | Light-Emitting Element and Display Device - There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided. | 2016-02-04 |
20160035797 | DISPLAY DEVICE - Display of a display device is made less likely to appear divided when a plurality of display panels are used as one screen. Provided is a display device including two display units and a foldable housing that includes a joint portion between the two display units and supports the two display units. Each display unit includes a display panel including a display region and a non-display region and a support having a first surface overlapped with the display region and a second surface that meets the first surface and is overlapped with the non-display region. The two display units are placed in the housing in an opened state such that the first surfaces of the supports face the same direction and the second surfaces of the supports face each other. | 2016-02-04 |
20160035798 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate, a coupling unit and an organic light emitting unit. The coupling unit includes a first conductive layer, a first light emitting layer and a second conductive layer. The first conductive layer is located on the substrate. The first light emitting layer is located between the first conductive layer and the second conductive layer. The organic light emitting unit is located adjacent to the second conductive layer. | 2016-02-04 |
20160035799 | DISPLAY UNIT OF DISPLAY PANEL - A display unit of a display panel includes three pixels having different colors. Each pixel has a color sub-pixel and a transparent sub-pixel, both approximately arranged in one column along a first direction. Each pixel has a ratio defined by the area of the color sub-pixel divided by the area of the corresponding transparent sub-pixel. The three pixels are arranged in one row along a second direction, and the ratios of the three pixels are different from each other. Thus, the light transmittance of the display unit can be increased, and the area of the color sub-pixel for each pixel can be adjusted according to lighting efficiency. | 2016-02-04 |
20160035800 | FLEXIBLE DISPLAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a flexible display substrate and a method for manufacturing the same which can avoid break and peeling of film layers disposed on a flexible base and further reduce degree of a warpage occurred in the flexible base when separating the support substrate from the flexible base located above the support substrate. The flexible display substrate comprises the flexible base, a first buffer layer and a second buffer layer disposed on an upper surface and a lower surface of the flexible base, respectively, and a plurality of display modules disposed on the first buffer layer, each display module includes at least one thin film transistor and at least one electrode corresponding to the thin film transistor. | 2016-02-04 |
20160035801 | FLEXIBLE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A flexible display device including a substrate; a driving element layer including a plurality of thin film transistors on the substrate; a display element layer including organic light-emitting diodes electrically connected to the thin film transistors on the driving element layer; a light transmissive layer on the display element layer and configured to adjust a neutral plane of the flexible display device to lie at the driving element layer and the display element layer when the flexible display device is bent; and a back plate film attached to a back side of the substrate and having a cut portion formed in a center region where the flexible display device is bent. | 2016-02-04 |
20160035802 | LIGHT-EMITTING DEVICE, ARRAY SUBSTRATE, DISPLAY DEVICE AND MANUFACTURING METHOD OF LIGHT-EMITTING DEVICE - The present invention discloses a light-emitting device, array substrate, display device and manufacturing method of light-emitting device. The light-emitting device comprises a substrate and a pixel define layer provided on the substrate, the pixel define layer defines at least one pixel unit, each of which comprises a plurality of first electrodes, an organic layer provided on the plurality of first electrodes, and a second electrode provided on the organic layer. The light-emitting device, array substrate, display device and manufacturing method provided by the present invention can allow the formed film of the organic layer on the first electrodes to have good flatness and allow portions of the organic layer on different first electrodes to have substantially the same thickness, thus flatness and uniformity of the formed film of the organic layer in the light-emitting device is improved and further display quality of the light-emitting device is improved. | 2016-02-04 |
20160035803 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting display device according to an embodiment includes a lower substrate; a bank layer disposed on the lower substrate; a connection assistance unit disposed on the bank layer; a cathode disposed on the lower substrate so as to cover the bank layer; an auxiliary electrode disposed on the bank layer and electrically connected with the cathode; and an upper substrate provided to face the lower substrate. | 2016-02-04 |
20160035804 | ELECTROLUMINESCENCE DISPLAY DEVICE AND FABRICATION METHOD THEREOF - Embodiments of the disclosure disclose an electroluminescence display device and a fabrication method thereof The electroluminescence display device comprises an opposed substrate ( | 2016-02-04 |
20160035805 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS - An organic light emitting display apparatus includes a first pixel and a second pixel. The first pixel includes a first data line, a first driving thin film transistor (TFT), and a first contact metal connected to the first driving TFT and in a layer at a same level as a layer of the first data line. The second pixel includes a second data line, a second driving TFT, and a second contact metal connected to the second driving TFT and in a layer at a same level as a layer of the second data line. The first gap between the first driving TFT and the first contact metal is different from a second gap between the second driving TFT and the second contact metal. | 2016-02-04 |
20160035806 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display includes a substrate including a penetrated portion positioned in a display area for displaying an image and a light emission region neighboring the penetrated portion. The OLED display also includes an OLED positioned on the light emission region of the substrate. | 2016-02-04 |
20160035807 | OLED PIXEL STRUCTURE AND OLED DISPLAY DEVICE - The present invention belongs to the technical field of display, and specifically relates to an OLED pixel structure and an OLED display device. The OLED pixel structure comprises a thin film transistor and an OLED device, the thin film transistor being provided with a driving electrode for controlling whether the OLED device emits light or not, wherein the pixel structure comprises a transmission region and a reflection region in which a reflection layer formed by extending the driving electrode is provided. The beneficial advantages are that the OLED pixel structure can effectively improve the utilization of the light source and the utilization of the display panel. | 2016-02-04 |
20160035808 | ORGANIC LIGHT EMITTING DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - Provided are an organic light emitting display panel and a method of manufacturing the same. The organic light emitting display panel includes: a pixel defined by an intersection of one of a plurality of data lines and one of a plurality of gate lines, the pixel including: a transistor, a storage capacitor including: a first electrode, and a second electrode, and a semiconductor layer, a first plate partially overlapping the semiconductor layer in the pixel, the first plate including: a gate portion of the transistor, and a capacitor-forming portion including the first electrode of the storage capacitor, and a second plate on the first plate in the pixel, the second plate including the second electrode of the storage capacitor, the second plate not overlapping the semiconductor layer. | 2016-02-04 |
20160035809 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a substrate, a first insulating layer, a power supply electrode, a second insulating layer, a first electrode, an emission layer, and a second electrode. The substrate has a display region and a transparent region. The first insulating layer is disposed on the substrate. The power supply electrode is disposed on the first insulating layer. The second insulating layer is disposed on the power supply electrode such that an edge portion of the power supply electrode is free from overlap with the second insulating layer. The first electrode is disposed on the second insulating layer and in contact with the edge portion of the power supply electrode. The emission layer is disposed on the first electrode. The second electrode is disposed on the emission layer. | 2016-02-04 |
20160035810 | ORGANIC LIGHT EMITTING DISPLAY - An organic light emitting display can include a substrate, a first capacitor formed on the substrate, the first capacitor including a first capacitor lower electrode, a first capacitor upper electrode, and a gate insulating layer between the first capacitor lower upper electrodes, a first passivation layer over the first capacitor, a second capacitor on the first passivation layer, the second capacitor including a second capacitor lower electrode, a second capacitor upper electrode, and a second passivation layer interposed between the second capacitor lower upper electrodes, an organic insulating layer over the second capacitor, a pixel electrode on the organic insulating layer, an organic layer on the pixel electrode, the organic layer including at least a light emitting layer, and an opposite electrode on the organic layer, and the width of the second capacitor lower electrode is greater than that of the second capacitor upper electrode. | 2016-02-04 |
20160035811 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - Discussed is an organic light emitting display device that may include a first pixel on a substrate; a switching transistor with a first active layer provided inside the first pixel; a driving transistor with a second active layer provided inside the first pixel; a first light shielding layer overlapping the second active layer; and a second light shielding layer overlapping the first active layer, wherein the first light shielding layer is connected with the driving transistor, and the second light shielding layer is electrically insulated from the first light shielding layer. | 2016-02-04 |
20160035812 | FLEXIBLE DISPLAY DEVICE WITH WIRE HAVING REINFORCED PORTION AND MANUFACTURING METHOD FOR THE SAME - There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display. | 2016-02-04 |
20160035813 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus includes: a substrate; a thin film transistor formed on the substrate; a pixel electrode connected to at least one of the source or drain electrodes; a pixel-defining layer having a first opening exposing at least a portion of the pixel electrode and a second opening adjacent to the first opening; an intermediate layer formed on the pixel electrode, including an organic emission layer, and having a first hole corresponding to the second opening; an opposite electrode formed on the intermediate layer; and first and second auxiliary electrodes formed below the pixel-defining layer, at least portions of the first and second auxiliary electrodes are exposed through the second opening, where ends of the first and second auxiliary electrodes are spaced apart from each other, and where the opposite electrode contacts the ends of the and second first auxiliary electrodes which are exposed through the first hole. | 2016-02-04 |
20160035814 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting device includes a switching transistor and a driving transistor. A semiconductor layer is commonly used by the switching and driving transistors. The portion of semiconductor layer corresponding to the driving transistor is curved. A gate insulating layer is located between a channel region and gate electrode of the switching transistor, and between the channel region and the gate electrode of the driving transistor. The gate insulating layer has substantially a same plane shape as the switching gate electrode and the driving gate electrode. An edge of the gate insulating layer and an edge of the switching and driving gate electrodes at least partially overlap. | 2016-02-04 |
20160035815 | DISPLAY UNIT, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A display unit includes: a display layer including a pixel electrode; a semiconductor layer provided in a layer below the display layer, the semiconductor layer including a wiring layer that includes a material removable by an etchant by which the pixel electrode is also removable; and a terminal section configured to electrically connect the semiconductor layer to an external circuit, the terminal section including a first electrically-conductive layer made of a material same as a material of the wiring layer. | 2016-02-04 |
20160035816 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure is provided. The semiconductor structure includes a substrate; and a plurality of parallel first conductive layers formed on the substrate. The semiconductor structure also includes a composite magnetic structure having a plurality of magnetic layers and a plurality of insulation layers with a sandwich arrangement formed on a portion of the substrate and portions of surfaces of the plurality of first conductive layers. Further, the semiconductor structure includes a plurality of first conductive vias and a plurality of second conductive vias formed on the first conductive layers at both sides of the composite magnetic structure. Further, the semiconductor structure also includes a plurality of second conductive layers formed on a top surface of the composite magnetic structure, top surfaces of the first conductive vias, and top surfaces of the second conductive vias to form at least one coil structure wrapping around the composite magnetic structure. | 2016-02-04 |
20160035817 | Process to Improve Performance for Metal-Insulator-Metal (MIM) Capacitors - Some embodiments relate to a metal-insulator-metal (MIM) capacitor, which includes a capacitor a capacitor bottom metal (CBM) electrode, a high k dielectric layer arranged over the CBM electrode, and a capacitor top metal (CTM) electrode arranged over the high k dielectric layer. In some embodiments, the MIM capacitor comprises CTM protective sidewall regions, which extend along vertical sidewall surfaces of the CTM electrode, and protect the CTM electrode from leakage, premature voltage breakdown, or burn out, due to metallic residue or etch damage formed on the sidewalls during one or more etch process(es) used to form the CTM electrode. In some embodiments, the MIM capacitor comprises CBM protective sidewall regions, which extend along vertical sidewall surfaces of the CBM electrode. In some embodiments, the MIM capacitor comprises both CBM and CTM protective sidewall regions. | 2016-02-04 |
20160035818 | FORMING A VERTICAL CAPACITOR AND RESULTING DEVICE - Methods for forming a vertical capacitance structure and the resulting devices are disclosed. Embodiments may include forming fins on a substrate; conformally forming a first metal layer over the fins; conformally forming an insulation layer over the first metal layer; and forming a second metal layer over the insulation layer. | 2016-02-04 |
20160035819 | LOW-TEMPERATURE POLYSILICON MEMBRANE AND PREPARATION METHOD THEREOF, THIN-FILM TRANSISTOR AND DISPLAY DEVICE - A method for preparing an LTPS membrane, including: forming an amorphous silicon (a-Si) layer (S | 2016-02-04 |
20160035820 | UNIAXIALLY-STRAINED FD-SOI FINFET - Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance. | 2016-02-04 |
20160035821 | Power Semiconductor Device - A semiconductor device includes an active region and a semiconductor substrate layer having a lower part semiconductor layer of a second conductivity type. The active region includes a drift region formed by at least a part of the substrate layer, a body region of the second conductivity type formed on at least a part of the drift region, a source region of a first conductivity type disposed in the body region, and a first doped region of the first conductivity type at least partially disposed under the body region. A groove extends downward from a top of the substrate layer and contains a shielding electrode. A depth of the groove is greater than that of the first doped region. A gate at least partially formed above at least a part of the source region and the body region is electrically insulated from the shielding electrode. | 2016-02-04 |
20160035822 | High Voltage Semiconductor Devices and Methods for their Fabrication - Semiconductor devices include: (a) a semiconductor substrate containing a source region and a drain region; (b) a gate structure supported by the semiconductor substrate between the source region and the drain region; (c) a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range; and (d) a well region in the semiconductor substrate, wherein the well region has a second conductivity type and wherein the well region is configured to form a channel therein under the gate structure during operation of the semiconductor device. Methods for the fabrication of semiconductor devices are described. | 2016-02-04 |
20160035823 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed in the substrate at two respectively sides of the gate, a first well region formed in the substrate, and a plurality of first doped islands formed in the source region. The drain region and the source region include a first conductivity, and the first well region and the first doped islands include a second conductivity. The source region is formed in the first well region, and the first doped islands are spaced apart from the first well region. | 2016-02-04 |
20160035824 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND POWER MODULE - A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer. | 2016-02-04 |
20160035825 | SUPER JUNCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions. | 2016-02-04 |
20160035826 | SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD - A method for manufacturing a semiconductor device may include forming a semiconductor portion, forming a doped portion, and forming a dielectric member. A side of the dielectric member abuts each of the semiconductor portion and the doped portion. A first half of the doped portion is positioned between the semiconductor portion and a second half of the doped portion. A dopant concentration of the second half of the doped portion is greater than a dopant concentration of the first half of the doped portion. | 2016-02-04 |
20160035827 | Fin Structure of Semiconductor Device - A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFET, as compared to a FinFET including fins that do not include a dielectric disposed within a furrow. | 2016-02-04 |
20160035828 | COMPOUND SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING SAME, AND RESIN-SEALED TYPE SEMICONDUCTOR DEVICE - In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture. | 2016-02-04 |
20160035829 | ULTRA-LONG SILICON NANOSTRUCTURES, AND METHODS OF FORMING AND TRANSFERRING THE SAME - Under one aspect, a plurality of silicon nanostructures is provided. Each of the silicon nanostructures includes a length and a cross-section, the cross-section being substantially constant along the length, the length being at least 100 microns. Under another aspect, a method of making nanostructures is provided that includes providing a silicon wafer including a thickness and first and second surfaces separated from one another by the thickness; forming a patterned layer of metal on the first surface of the silicon wafer; generating a current through the thickness of the silicon wafer, the metal oxidizing the silicon wafer in a region beneath the patterned layer of the metal; and exposing the silicon wafer to an etchant in the presence of the current, the etchant removing the oxidized region of the silicon wafer so as to define a plurality of nanostructures. Methods of transferring nanowires also are provided. | 2016-02-04 |
20160035830 | THIN FILM TRANSISTOR AND DISPLAY DEVICE USING THE SAME - A display panel including an oxide thin film transistor is disclosed. In the oxide thin film transistor, a part of the active layer between a source region and a drain region is covered with an etch stopper layer, and the etch stopper layer is partially covered by the first electrode and the second electrode of the oxide thin film transistor. The length in which the etch stopper layer is overlapped by the second electrode is greater than the length in which the etch stopper layer is overlapped by the first electrode to suppress threshold voltage shift in the oxide thin film transistor. | 2016-02-04 |
20160035831 | CHANNEL REGION DOPANT CONTROL IN FIN FIELD EFFECT TRANSISTOR - A dummy gate structure straddling at least one semiconductor fin is formed on a substrate. Active semiconductor regions and raised active semiconductor regions may be formed. A planarization dielectric layer is formed over the at least one semiconductor fin, and the dummy gate structure is removed to provide a gate cavity. Electrical dopants in the channel region can be removed by outgassing during an anneal, thereby lowering the concentration of the electrical dopants in the channel region. Alternately or additionally, carbon can be implanted into the channel region to deactivate remaining electrical dopants in the channel region. The threshold voltage of the field effect transistor can be effectively controlled by the reduction of active electrical dopants in the channel region. A replacement gate electrode can be subsequently formed in the gate cavity. | 2016-02-04 |
20160035832 | TRANSISTOR DESIGN - Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel. In some embodiments, a counter-doped layer underlies the delta-doped layer configured to reduce leakage within the semiconductor substrate, and includes dopant impurities of a second impurity type, which is opposite the first impurity type. | 2016-02-04 |
20160035833 | TRAP RICH LAYER FOR SEMICONDUCTOR DEVICES - An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer. | 2016-02-04 |
20160035834 | SMART SEMICONDUCTOR SWITCH - A semiconductor device comprises a semiconductor substrate doped with dopants of a first type and a vertical transistor composed of one or more transistor cells. Each transistor cell has a first region formed in the substrate and doped with dopants of a second type, and the first regions form first pn-junctions with the surrounding substrate. At least a first well region is formed in the substrate and doped with dopants of a second type to form a second pn-junction with the substrate. The first well region is electrically connected to the first regions of the vertical transistor via a semiconductor switch. The semiconductor device comprises a detection circuit, which is integrated in the substrate and configured to detect whether the first pn-junctions are reverse biased. The switch is opened when the first pn-junctions are reverse biased and the switch is closed when the first pn-junctions are not reverse biased. | 2016-02-04 |
20160035835 | SMART SEMICONDUCTOR SWITCH - A semiconductor device comprises semiconductor substrate including vertical transistor and with dopants of a first type. Each transistor cell of transistor has body region formed in substrate and with dopants of second type. The body regions form first pn-junctions with substrate. A first well region is formed in substrate and with dopants of a second type forming a second pn-junction with substrate. Switch connects this first well region to body regions. A second well region is formed in the substrate and with dopants of a second type to form third pn-junction with substrate. Detection circuit is integrated in the second well region and to detect whether the first pn-junctions are reverse biased. The switch connects or disconnects the first well region(s) and the body regions of the transistor cell, and is opened, when the first pn-junctions are reverse biased, and dosed, when the first pn-junctions are not reverse biased. | 2016-02-04 |
20160035836 | SILICON CARBIDE POWER BIPOLAR DEVICES WITH DEEP ACCEPTOR DOPING - In a general aspect, a power semiconductor device can include a collector region disposed on a substrate, the collector region can include n-type silicon carbide (SiC). The power semiconductor device can also include a base region disposed on the collector region. The base region can include p-type SiC doped with gallium. The power semiconductor device can include an emitter region disposed on the base region. The emitter region can include n-type SiC carbide. | 2016-02-04 |
20160035837 | FREQUENCY MULTIPLIER BASED ON A LOW DIMENSIONAL SEMICONDUCTOR STRUCTURE - A frequency multiplier based on a low dimensional semiconductor structure, including an insulating substrate layer, a semiconductor conducting layer arranged on the surface of the insulating substrate layer, an insulating protective layer arranged on the surface of the semiconductor conducting layer, an insulating carving groove penetrating the semiconductor conducting layer, an inlet electrode arranged on the side surface of the semiconductor conducting layer, and an outlet electrode arranged on the side surface corresponding to the access electrode is provided. The semiconductor conducting layer comprises two two-dimensional, quasi-one-dimensional, or one-dimensional current carrying channels near to and parallel to each other. The frequency multiplier has advantages that the structure is simple, the process is easy to implement, no extra filter circuit needs to be added, dependence on material characteristics is little, and the selection range of materials is wide. | 2016-02-04 |
20160035838 | NANO-STRUCTURE ASSEMBLY AND NANO-DEVICE COMPRISING SAME - Provided are a nano-structure assembly including an insulating substrate; and a nano-structure formed on the insulating substrate, and a nano-device including the same. | 2016-02-04 |
20160035839 | COMPOUND SEMICONDUCTOR STACK AND SEMICONDUCTOR DEVICE - There is provided a compound semiconductor stack including a substrate ( | 2016-02-04 |
20160035840 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer provided in a portion on the first semiconductor layer, a first insulating layer provided on the first semiconductor layer on a terminal region side of the second semiconductor layer, a third semiconductor layer provided on the first semiconductor layer on the terminal region side of the first insulating layer, a second insulating layer provided on the first semiconductor layer on the terminal region side of the third semiconductor layer, a fourth semiconductor layer provided between the first semiconductor layer and the second insulating layer, and a plurality of field plate electrodes provided inside an inter-layer insulating film, the plurality of field plate electrodes having mutually-different distances from the first semiconductor layer. | 2016-02-04 |
20160035841 | MULTI-COMPOSITION GATE DIELECTRIC FIELD EFFECT TRANSISTORS - A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric. | 2016-02-04 |
20160035842 | Semiconductor Device Including a Trench at Least Partially Filled with a Conductive Material in a Semiconductor Substrate and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a semiconductor substrate and a first trench extending into or through the semiconductor substrate from a first side. The first trench is at least partially filled with a conductive material and electrically connected to the semiconductor substrate via a doped semiconductor layer at a sidewall of the first trench. A semiconductor layer adjoins the semiconductor substrate at the first side, and caps the first trench at the first side. A contact is disposed at a second side of the semiconductor substrate opposite to the first side. A method of manufacturing the semiconductor device is also provided. | 2016-02-04 |
20160035843 | CMOS IN SITU DOPED FLOW WITH INDEPENDENTLY TUNABLE SPACER THICKNESS - A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions. | 2016-02-04 |
20160035844 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device with enhanced reliability in which a gate electrode for a trench-gate field effect transistor is formed through a gate insulating film in a trench made in a semiconductor substrate. The upper surface of the gate electrode is in a lower position than the upper surface of the semiconductor substrate in an area adjacent to the trench. A sidewall insulating film is formed over the gate electrode and over the sidewall of the trench. The gate electrode and the sidewall insulating film are covered by an insulating film as an interlayer insulating film. | 2016-02-04 |
20160035845 | Vertical Semiconductor Device having Semiconductor Mesas with Side Walls and a PN-Junction Extending between the Side Walls - A vertical semiconductor device includes a semiconductor body having a backside and extending, in a peripheral area and in a vertical direction substantially perpendicular to the backside, from the backside to a first surface of the semiconductor body, the body including in an active area spaced apart semiconductor mesas extending, in the vertical direction, from the first surface to a main surface arranged above the first surface, in a vertical cross-section the peripheral area extending between the active area and an edge that extends between the back-side and the first surface, in the vertical cross-section each of the mesas including first and second side walls, a first pn-junction extending between the first and second side walls, and a conductive region in Ohmic contact with the mesa and extending from the main surface into the mesa. Gate electrodes are arranged between adjacent mesas and extend across the first pn-junctions. | 2016-02-04 |
20160035846 | HIGH DENSITY MOSFET ARRAY WITH SELF-ALIGNED CONTACTS ENHANCEMENT PLUG AND METHOD - A semiconductor substrate comprises epitaxial region, body region and source region; an array of interdigitated active nitride-capped trench gate stacks (ANCTGS) and self-guided contact enhancement plugs (SGCEP) disposed above the semiconductor substrate and partially embedded into the source region, the body region and the epitaxial region forming the trench-gated MOSFET array. Each ANCTGS comprises a stack of a polysilicon trench gate embedded in a gate oxide shell and a silicon nitride spacer cap covering the top of the polysilicon trench gate; each SGCEP comprises a lower intimate contact enhancement section (ICES) in accurate registration to its neighboring ANCTGS; an upper distal contact enhancement section (DCES) having a lateral mis-registration (LTMSRG) to the neighboring ANCTGS; and an intervening tapered transitional section (TTS) bridging the ICES and the DCES; a patterned metal layer atop the patterned dielectric region atop the MOSFET array forms self-guided source and body contacts through the SGCEP. | 2016-02-04 |
20160035847 | GATE WITH SELF-ALIGNED LEDGED FOR ENHANCEMENT MODE GaN TRANSISTORS - An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively. | 2016-02-04 |
20160035848 | METHOD OF FORMING SPLIT GATE MEMORY WITH IMPROVED RELIABILITY - A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions. | 2016-02-04 |
20160035849 | Strained Channel of Gate-All-Around Transistor - The disclosure relates to a semiconductor device. An exemplary structure for a nanowire structure comprises a first semiconductor material having a first lattice constant and a first linear thermal expansion constant; and a second semiconductor material having a second lattice constant and a second linear thermal expansion constant surrounding the first semiconductor material, wherein a ratio of the first lattice constant to the second lattice constant is from 0.98 to 1.02, wherein a ratio of the first linear thermal expansion constant to the second linear thermal expansion constant is greater than 1.2 or less than 0.8. | 2016-02-04 |
20160035850 | Semiconductor Device and Manufacturing Method - A semiconductor device includes a trench extending into a semiconductor body from a first surface. At least one of a ternary carbide and a ternary nitride is in the trench. | 2016-02-04 |
20160035851 | Epitaxial metallic transition metal nitride layers for compound semiconductor devices - A method for integrating epitaxial, metallic transition metal nitride (TMN) layers within a compound semiconductor device structure. The TMN layers have a similar crystal structure to relevant semiconductors of interest such as silicon carbide (SiC) and the Group III-Nitrides (III-Ns) such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and their various alloys. Additionally, the TMN layers have excellent thermal stability and can be deposited in situ with other semiconductor materials, allowing the TMN layers to be buried within the semiconductor device structure to create semiconductor/metal/semiconductor heterostructures and superlattices. | 2016-02-04 |
20160035852 | METAL SILICIDE, METAL GERMANIDE, METHODS FOR MAKING THE SAME - In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD. | 2016-02-04 |
20160035853 | SEMICONDUCTOR DEVICE - In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer. | 2016-02-04 |
20160035854 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region. | 2016-02-04 |
20160035855 | Organic-Inorganic Hybrid Multilayer Gate Dielectrics for Thin-Film Transistors - Disclosed are organic-inorganic hybrid self-assembled multilayers that can be used as electrically insulating (or dielectric) materials. These multilayers generally include an inorganic primer layer and one or more bilayers deposited thereon. Each bilayer includes a chromophore or “π-polarizable” layer and an inorganic capping layer composed of zirconia. Because of the regularity of the bilayer structure and the aligned orientation of the chromophore resulting from the self-assembly process, the present multilayers have applications in electronic devices such as thin film transistors, as well as in nonlinear optics and nonvolatile memories. | 2016-02-04 |
20160035856 | SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR AND METHOD FOR THE FORMATION THEREOF - An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region. The logic transistor includes a gate dielectric and a gate electrode. An input/output transistor is provided at the input/output transistor region. The input/output transistor includes a gate dielectric and a gate electrode. The gate dielectric of the input/output transistor has a greater thickness than the gate dielectric of the logic transistor. A ferroelectric transistor is provided at the ferroelectric transistor region. The ferroelectric transistor includes a ferroelectric dielectric and a gate electrode. The ferroelectric dielectric is arranged between the ferroelectric transistor region and the gate electrode of the ferroelectric transistor. | 2016-02-04 |