02nd week of 2009 patent applcation highlights part 59 |
Patent application number | Title | Published |
20090013113 | Methods and systems for interprocessor message exchange between devices using only write bus transactions - Systems and methods for reducing or eliminating use of read transactions by a message consuming device coupled through a shared bus to a message producing device to transfer a message from the producing device to the consuming device. Features and aspects hereof provide for use of only write transactions on the bus issued by the devices to transfer messages directly into the data memory of the consuming device. A memory manager on the producing device may manage allocation and freeing of buffer space within the data memory of the consuming device. The producing device notifies the consuming device when a message transfer is completed. | 2009-01-08 |
20090013114 | Master Slave Interface - Implementations related to systems, devices, and methods that make use of a master slave arrangement are described. | 2009-01-08 |
20090013115 | BUS COMMUNICATION APPARATUS THAT USES SHARED MEMORY - The present invention improves bus transfer efficiency in bus communication that uses a shared memory. A communication origin master | 2009-01-08 |
20090013116 | DATA COMMUNICATION METHOD, DATA TRANSMISSION AND RECEPTION DEVICE AND SYSTEM | 2009-01-08 |
20090013117 | SYSTEM AND METHOD FOR GENERATING INTERRUPT - A system and a method for generating an interrupt are provided. In the interrupt generating method, a time-out mechanism is executed by a second network component of a computer system after a packet processing action is finished. An interrupt is generated by the second network component only if a first network component of the computer system does not execute a polling action during a predefined period after the time-out mechanism is processed. Thus, it is not necessary to generate the interrupt every time after processing a network packet, so that less interrupts are generated and accordingly the loading of the computer system is reduced. Moreover, the reaction time of the computer system is kept to ensure the efficiency of the computer system. | 2009-01-08 |
20090013118 | PRIORITIZATION OF INTERRUPTS IN A STORAGE CONTROLLER BASED ON INTERRUPT CONTROL DIRECTIVES RECEIVED FROM HOSTS - A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive. | 2009-01-08 |
20090013119 | PRIORITIZATION OF INTERRUPTS IN A STORAGE CONTROLLER BASED ON INTERRUPT CONTROL DIRECTIVES RECEIVED FROM HOSTS - A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive. | 2009-01-08 |
20090013120 | Method for Operating a Tachograph and Tachograph for Carrying Out the Method - In a method for transferring data from a tachograph ( | 2009-01-08 |
20090013121 | USB COMPUTER SWITCHING DEVICE - The present invention describes a device and circuit for attaching at least two computers to a one or more computer peripheral such as a projector in a classroom situation. The peripheral can be switched easily between the computers without difficult toggling by means of a button which activates a relay between the two computers. A default position indicates the position the switch can start in. | 2009-01-08 |
20090013122 | Transaction Method for Managing the Storing of Persistent Data in a Transaction Stack - A transaction method manages the storing of persistent data to be stored in at least one memory region of a non-volatile memory device before the execution of update operations that involve portions of the persistent data. Values of the persistent data are stored in a transaction stack that includes a plurality of transaction entries before the beginning of the update operations so that the memory regions involved in such an update are restored in a consistent state if an unexpected event occurs. A push extreme instruction reads from the memory cells a remaining portion of the persistent data that is not involved in the update operation, and stores the remaining portion in a subset of the transaction entries. The push extreme instruction is executed instead of a push instruction when the restoring of the portion of persistent data is not required after the unexpected event. The restoring corresponds to the values that the persistent data had before the beginning of the update operations. | 2009-01-08 |
20090013123 | Storage Bridge and Storage Device and Method Applying the Storage Bridge - A storage bridge includes a flash memory register unit for temporarily storing data and for storing data of a storage unit when a host unit stores data to the storage unit, and a transmission interface control unit coupled to the flash memory register unit for controlling operations of the flash memory register unit. | 2009-01-08 |
20090013124 | ROM CODE PATCH METHOD - The present invention relates to a method of replacing a sequence of one or more commands from a routine in a ROM of a device using a RAM. The method allows replacing part of a routine, for example a single command, while continuing to use the rest of the commands of the routine from the ROM. In an exemplary embodiment of the invention, a single command is replaced by adding only two additional commands or four additional commands as overhead in the replacement process. | 2009-01-08 |
20090013125 | MEMORY CARD - A memory device is provided which is connected to operate with power and clocks supplied from a host apparatus. The memory device includes external terminals, a flash memory chip to store data, an IC chip to process data; and a controller chip connected with the external terminals, the flash memory chip and the IC chip. The flash memory chip, the IC chip and the controller chip are discrete chips. The controller chip writes data inputted from the host apparatus into the flash memory chip or the IC chip and transfers data read from the flash memory chip or the IC chip to the host apparatus, based upon commands from the host apparatus. | 2009-01-08 |
20090013126 | METHOD AND DEVICES FOR COMPRESSING DELTA LOG USING FLASH TRANSACTIONS - Each received piece of configuration data is added at a next currently free location in a volatile buffer. The contents of the volatile buffer are compressed after adding each received piece of configuration data. The compression result is stored in a non-volatile flash memory. If the compression result was shorter than a limit, it is allowed to be overwritten in the flash memory by a next compression result. If the compression result was longer than the limit, it is stored in the flash memory and the next compression result is directed to a different location in the flash memory. | 2009-01-08 |
20090013127 | Systems and Methods for Determining Refresh Rate of Memory Based on RF Activities - Systems and methods for determining a refresh rate of volatile memory are provided. In this regard, a representative system, among others, includes a radio frequency (RF) device; a computing device that communicates with the RF device, the computing device including a refresh manager that monitors activities of the RF device; and volatile memory that communicates with the refresh manager of the computing device, wherein the refresh manager determines a refresh rate of the volatile memory based on the monitored activities of the RF device. A representative method, among others, for determining the refresh rate of volatile memory, includes monitoring activities of a radio frequency (RF) device; and adjusting a refresh rate of volatile memory based on the monitored activities of the RF device. | 2009-01-08 |
20090013128 | Runtime Machine Supported Method Level Caching - A computer system includes a disk space comprising at least one type of memory and an operating system for controlling allocations and access to the disk space. A runtime machine runs applications through at least one of the operating system or directly on at least one processor of the computer system. In addition, the runtime machine manages a selected runtime disk space allocated to the runtime machine by the operating system and manages a separate method cache within the selected virtual disk space. The virtual machine controls caching within the method cache of a separate result of at least one method of the application marked as cache capable. For a next instance of the method detected by the runtime machine, the runtime machine accesses the cached separate result of the method in lieu of executing the method again. | 2009-01-08 |
20090013129 | COMMONALITY FACTORING FOR REMOVABLE MEDIA - Systems and methods for commonality factoring for storing data on removable storage media are described. The systems and methods allow for highly compressed data, e.g., data compressed using archiving or backup methods including de-duplication, to be stored in an efficient manner on portable memory devices such as removable storage cartridges. The methods include breaking data, e.g., data files for backup, into unique chunks and calculating identifiers, e.g., hash identifiers, based on the unique chunks. Redundant chunks can be identified by calculating identifiers and comparing identifiers of other chunks to the identifiers of unique chunks previously calculated. When a redundant chunk is identified, a reference to the existing unique chunk is generated such that the chunk can be reconstituted in relation to other chunks in order to recreate the original data. The method further includes storing one or more of the unique chunks, the identifiers and/or the references on the removable storage medium. | 2009-01-08 |
20090013130 | MULTIPROCESSOR SYSTEM AND OPERATING METHOD OF MULTIPROCESSOR SYSTEM - According to one aspect of embodiments, a multiprocessor system includes a plurality of processors, cache memories corresponding respectively to the processors, and a cache access controller. The cache access controller accesses at least one of the cache memories except one of the cache memories corresponding to one of the processors that issued the indirect access instruction in response to an indirect access instruction from each of the processors. Accordingly, even when one processor accesses data stored in a cache memory of another processor, data transfer between the cache memories is not required. Therefore, latency of an access to the data shared by the plurality of processors can be reduced. Moreover, since the communication between the cache memories is performed only at the time of executing the indirect access instructions, the bus traffic between the cache memories can be reduced. | 2009-01-08 |
20090013131 | LOW POWER SEMI-TRACE INSTRUCTION CACHE - A semi-trace cache combines elements and features of an instruction cache and a trace cache. An ICache portion of the semi-trace cache is filled with instructions fetched from the next level of the memory hierarchy while a TCache portion is filled with traces gleaned either from the actual stream of retired instructions or predicted before execution. | 2009-01-08 |
20090013132 | Cache memory - A cache memory comprises a first set of storage locations for holding syllables and addressable by a first group of addresses; a second set of storage locations for holding syllables and addressable by a second group of addresses; addressing circuitry operable to provide in each addressing cycle a pair of addresses comprising one from the first group and one from the second group, thereby accessing a plurality of syllables from each set of storage locations; and selection circuitry operable to select from said plurality of syllables to output to a processor lane based on whether a required syllable is addressable by an address in the first or second group. | 2009-01-08 |
20090013133 | CACHE LINE MARKING WITH SHARED TIMESTAMPS - Embodiments of the present invention provide a system that marks cache lines using shared timestamps. During operation, the system starts a transaction for a thread, wherein starting the transaction involves recording the value of an active timestamp and incrementing a transaction or overflow counter (TO_counter) corresponding to the recorded value. The system then places load-marks on cache lines which are loaded during the transaction. While placing the load-marks, the system writes the recorded value into metadata corresponding to the cache lines. Upon completing the transaction for the thread, the system decrements the TO_counter corresponding to the recorded value and resumes non-transactional execution for the thread without removing the load-marks from cache lines which were load-marked during the transaction. | 2009-01-08 |
20090013134 | MEMORY APPARATUS AND PROTECTING METHOD THEREOF - A memory apparatus and method for protecting the memory apparatus are provided. The memory apparatus includes a memory unit, a memory control unit, a switch and a control circuit. The memory control unit is used for reading from or writing to the memory unit and has a build-in protection unit. The switch has a lock end and a normal end. The control circuit is coupled between the switch and the memory control unit and is used for detecting the position of the switch. Once the switch is switched to the lock end and the memory apparatus receives a working voltage, the protection unit is automatically enabled by the control circuit to inhibit the memory control unit from reading data from or writing data to the memory unit. | 2009-01-08 |
20090013135 | UNORDERED LOAD/STORE QUEUE - A method and processor for providing full load/store queue functionality to an unordered load/store queue for a processor with out-of-order execution. Load and store instructions are inserted in a load/store queue in execution order. Each entry in the load/store queue includes an identification corresponding to a program order. Conflict detection in such an unordered load/store queue may be performed by searching a first CAM for all addresses that are the same or overlap with the address of the load or store instruction to be executed. A further search may be performed in a second CAM to identify those entries that are associated with younger or older instructions with respect to the sequence number of the load or store instruction to be executed. The output results of the Address CAM and Age CAM are logically ANDed. | 2009-01-08 |
20090013136 | De-Interleaving and Interleaving for Data Processing - Among others, techniques and apparatus are described for de-interleaving. A data processing apparatus includes a buffer to store interleaved data; an interleaving index producing unit to produce an interleaving index of the interleaved data; and an output control unit to output the data stored in the buffer using the interleaving index. | 2009-01-08 |
20090013137 | STORAGE SYSTEM AND POWER CONSUMPTION REDUCTION METHOD, AND INFORMATION PROCESSING APPARATUS - In a storage system including: plural information processing apparatuses each of which copies data sent from a host computer to create archive data in accordance with redundancy sent from the host computer; and a storage apparatus having physical disks that store the archive data, the storage apparatus includes a management unit that manages power state information that is information on whether or not the power state of each of the physical disks is “on,” and the information processing apparatuses each include an acquisition unit that acquires the power state information managed by the management unit and a determination unit that determines an information processing apparatus targeted for reading or writing the archive data from among the information processing apparatuses based on the power state information acquired by the acquisition unit. | 2009-01-08 |
20090013138 | Backup archive management - Apparatus, systems, and methods may operate to taking a snapshot of an origin volume in conjunction with a backup process in response to receiving a snapshot request by a snapshot service. A persistent time stamp associated with the creation time of the snapshot may be recorded on the origin volume. The persistent time stamp is accessible to the file system process associated with the origin volume in most embodiments. If access to a file is requested, the time the file was last modified may be compared with the persistent time stamp, and if the file modified time is earlier than the persistent time stamp, the file's archive bit can be reset. Otherwise, the archive bit is not reset. Additional apparatus, systems, and methods are disclosed. | 2009-01-08 |
20090013139 | APPARATUS AND METHOD TO PREVENT DATA LOSS IN NONVOLATILE MEMORY - An apparatus for preventing data loss of a nonvolatile memory device and a method thereof are presented The apparatus includes a nonvolatile memory including a memory cell which writes bit information to a first page and a second page included in a first block using plural states which are implemented using at least 2 bits, and a data-processing unit which writes the bit information of the first page to a second block in the nonvolatile memory while the bit information is written to the second page after the bit information is written to the first page. | 2009-01-08 |
20090013140 | HARDWARE ACCELERATION OF COMMONALITY FACTORING WITH REMOVABLE MEDIA - Systems and methods for commonality factoring for storing data on removable storage media are described. The systems and methods allow for highly compressed data, e.g., data compressed using archiving or backup methods including de-duplication, to be stored in an efficient manner on portable memory devices such as removable storage cartridges. The methods include breaking data, e.g., data files for backup, into unique chunks and calculating identifiers, e.g., hash identifiers, based on the unique chunks. Redundant chunks can be identified by calculating identifiers and comparing identifiers of other chunks to the identifiers of unique chunks previously calculated. When a redundant chunk is identified, a reference to the existing unique chunk is generated such that the chunk can be reconstituted in relation to other chunks in order to recreate the original data. The method further includes storing one or more of the unique chunks, the identifiers and/or the references on the removable storage medium. The acceleration hardware and/or software can reside in multiple devices, depending on the embodiment. For example, hardware and/or software for the chunking and/or hashing functions can reside in one or more of a host computer, a removable storage device, a removable cartridge holder and the removable storage cartridge. | 2009-01-08 |
20090013141 | Information leakage detection for storage systems - A storage system compares content of new data received from a host computer with content of existing data already stored in the storage system. If the content of the new data matches the content of the existing data, the storage system determines whether the computer that sent the new data is a registered owner of the new data by determining who the registered owners are of the existing data that has the matching content. If the computer that sent the new data is not a registered owner, unauthorized information sharing is assumed to have taken place. The storage system sends a notification or takes other specified action when the computer that sent the new data is not a registered owner. An administrator or monitoring agent may thus be notified of any unauthorized file sharing or data leakage within the storage system. | 2009-01-08 |
20090013142 | DIGITAL BROADCASTING CONTENTS MOVE FUNCTION - To provide a move function that can restore copy-once contents even if the contents are failed to be moved midway, an information storage device | 2009-01-08 |
20090013143 | SYSTEM AND METHOD FOR READ SYNCHRONIZATION OF MEMORY MODULES - A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing. | 2009-01-08 |
20090013144 | INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT SYSTEM - A main LSI includes a plurality of master circuits that transmit access requests to an SDRAM, an input interface that receives an access request from a master circuit in a sub LSI, an arbitration circuit that receives the access requests from the internal master circuits and from the input interface, sequentially selects, in accordance with a predetermined arbitration rule, a master circuit to be allowed to access the SDRAM, and determines output timings for addresses pertaining to the data transfers from the sequentially selected master circuits, and an access signal generation circuit that causes the sequentially selected master circuits to access the SDRAM in accordance with the corresponding output timings. | 2009-01-08 |
20090013145 | SYSTEM AND METHOD FOR FINDING KERNEL MEMORY LEAKS - The invention provides a system and method for tracking memory information associated with dynamically loaded kernel modules with the help of a tracking system. The tracking system defines its own kernel memory allocation functions. Whenever, a dynamic kernel module is loaded/unloaded into/from the kernel space, these newly defined functions are called in response to kernel memory allocation/de-allocation requests from the kernel module. The newly defined functions are responsible for allocating and de-allocating kernel memory, as well as, keeping track of information relating to the kernel memory allocations/de-allocations. The tracked information may be used to identify the source of kernel memory leaks. | 2009-01-08 |
20090013146 | METHOD TO CREATE A UNIFORMLY DISTRIBUTED MULTI-LEVEL CELL (MLC) BITSTREAM FROM A NON-UNIFORM MLC BITSTREAM - A method, system, and computer software product for operating a collection of memory cells. Each memory cell in the collection of memory cells is configured to store a binary multi-bit value delimited by characteristic parameter bands. In one embodiment, a transforming unit transforms an original collection of data to a transformed collection of data using a reversible mathematical operator. The original collection of data has binary multi-bit values arbitrarily distributed across the binary multi-bit values assigned to the characteristic parameter bands and the transformed collection of data has binary multi-bit values substantially uniformly distributed across the binary multi-bit values assigned to the characteristic parameter bands. | 2009-01-08 |
20090013147 | COMPUTER SYSTEM FOR PERFORMING ERROR MONITORING OF PARTITIONS - A computer system for performing error monitoring of partitions. A partition status buffer (PSB) denotes a status (GOOD, BAD, NOCARE) of each partition of at least two partitions. The BAD status denotes that the partition has encountered at least one error that is currently unrepaired. A global supervisor mapping (GSM) associates each partition (designated as a supervised partition) with a supervisor partition in a one-to-one mapping. The supervisor partition determines its supervised partition from the GSM and ascertains the status of its supervised partition from the PSB. If the status of the supervised partition is BAD then the supervisor partition performs a recovery procedure. The recovery procedure: obtains a grant of access to physical and logical resources of the supervised partition which contains error data of the supervised partition; gathers the error data; sets the status of the supervised partition to the NOCARE status. | 2009-01-08 |
20090013148 | BLOCK ADDRESSING FOR PARALLEL MEMORY ARRAYS - Apparatus and methods provide associative mapping of the blocks of two or more memory arrays such that data, such as pages of data, from the good blocks of the two or more memory arrays can be read in an alternating manner for speed or can be read in parallel for providing data to relatively wide data channels. This obviates the need for processor intervention to access data and can increase the throughput of data by providing, where configured, the ability to alternate reading of data from two or more arrays. For example, while one array is loading data to a cache, the memory device can be providing data that has already been loaded to the cache. | 2009-01-08 |
20090013149 | METHOD AND APPARATUS FOR CACHING OF PAGE TRANSLATIONS FOR VIRTUAL MACHINES - A method for caching of page translations for virtual machines includes managing a number of virtual machines using a guest page table of a guest operating system, which provides a first translation from a guest-virtual memory address to a first guest-physical memory address or an invalid entry, and a host page table of a host operating system, which provides a second translation from the first guest-physical memory address to a host-physical memory address or an invalid entry, and managing a cache page table, wherein the cache page table selectively provides a third translation from the guest-virtual memory address to the host-physical memory address, a second guest-physical memory address or an invalid entry. | 2009-01-08 |
20090013150 | SIMD MICROPROCESSOR AND DATA TRANSFER METHOD FOR USE IN SIMD MICROPROCESSOR - A disclosed SIMD microprocessor includes plural processor elements each having n arithmetic circuits and n registers configured to temporarily store data pieces to be input to the arithmetic circuits, n being a natural number equal to or greater than 2, and; a control circuit configured to determine an arrangement order of the processor elements and an arrangement order of the arithmetic circuits in the processor elements and determine whether to use the n arithmetic circuits as a single arithmetic circuit or as n arithmetic circuits. Each processor element further includes n shifter pairs each including a PE shifter and a bit shifter; and n shift data selection circuits configured to select arbitrary data pieces from the data pieces in the shifter pairs, perform bit extension on the data pieces, and transfer the data pieces to the arithmetic circuits. | 2009-01-08 |
20090013151 | SIMD TYPE MICROPROCESSOR - An SIMD type microprocessor is disclosed. The SIMD type microprocessor includes plural PEs (processor elements) each of which provides an ALU (arithmetic and logic unit) for lower-order bits, an ALU for upper-order bits, a control circuit for lower-order bits, a control circuit for upper-order bits, a range determining circuit for lower-order bits, and a range determining circuit for upper-order bits. The SIMD type microprocessor further includes a global processor, a range designation bus for lower-order bits which connects the global processor to the range determining circuit for lower-order bits, and a range designation bus for upper-order bits which connects the global processor to the range determining circuit for upper-order bits. The global processor instructs the range determining circuits to designate corresponding ranges to be operated on by the corresponding ALUs via the corresponding range designation buses so that the ALU for lower-order bits and the ALU for upper-order bits can be operated separately. | 2009-01-08 |
20090013152 | COMPUTING UNIT AND IMAGE FILTERING DEVICE - A processor capable of performing a filter processing in a high speed is provided. A computing unit comprises a computer for performing a filter processing. Data supply to the computer is performed by an internal register configured by a flip-flop. Data read from the internal register is outputted to a shift register and the data is supplied to the computer per cycle. And, the computing unit comprises a mechanism for changing a filter computing direction according to a motion vector, thereby preventing performance lowering due to branched command by performing a horizontal filtering and a vertical filtering by a same command. | 2009-01-08 |
20090013153 | PROCESSOR EXCLUSIVITY IN A PARTITIONED SYSTEM - A computer system including a plurality of physical processors (CPs) having physical processor performances (PCPs), a plurality of logical processors (LCPs), a plurality of logical partitions (LPARs) where each partition includes one or more of the logical processors (LCPs), and a system assist processor having a control element. The control element controls the virtualization of the physical processors (CPs), the logical partitions (LPARs) and the logical processors (LCPs) and allocates the physical processor performances (PCPs) to the logical partitions (LPARs). The control element operates to exclusively bind logical processors (LCPs) to the physical processors (CPs). For a logical processor (LCP) exclusively bound to a physical processor (CP), the logical processor (LCP) has exclusive use of the underlying physical processor (CP) and no other logical processor (LCP) can be dispatched on the underlying physical processor (CP) even if the underlying physical processor (CP) is otherwise available. | 2009-01-08 |
20090013154 | MULTILAYER DISTRIBUTED PROCESSING SYSTEM - The independencies of a plurality of layers executing dividingly a transaction can be easily enhanced. Anode ( | 2009-01-08 |
20090013155 | System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor - An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array. | 2009-01-08 |
20090013156 | PROCESSOR COMMUNICATION TOKENS - The invention provides a method of transmitting messages over an interconnect between processors, each message comprising a header token specifying a destination processor and at least one of a data token and a control token. The method comprises: executing a first instruction on a first one of the processors to generate a data token comprising a byte of data and at least one additional bit to identify that token as a data token, and outputting the data token from the first processor onto the interconnect as part of one of the messages. The method also comprises executing a second instruction on said first processor to generate a control token comprising a byte of control information and at least one additional bit to identify that token as a control token, and outputting the control token from the first processor onto the interconnect as part of one of the messages. | 2009-01-08 |
20090013157 | Management of Software Implemented Services in Processor-Based Devices - A service management system for devices with embedded processor systems manages use of memory by programs implementing the services by assigning services to classes and limiting the number of services per class that can be loaded into memory. Classes enable achieving predictable and stable system behavior, defining the services and service classes in a manifest that is downloaded to embedded devices operating on a network, such as a cable or satellite television network, telephone or computer network, and permit a system operator, administrator, or manager to manage the operation of the embedded devices while deploying new services implemented with applications downloaded from the network when the service is requested by a user. | 2009-01-08 |
20090013158 | System and Method for Assigning Tags to Control Instruction Processing in a Superscalar Processor - A tag monitoring system for assigning tags to instructions embodied in software on a tangible computer-readable storage medium. A source supplies instructions to be executed by a functional unit. A queue having a plurality of slots containing tags which are used for tagging instructions. A register file stores information required for the execution of each instruction at a location in the register file defined by the tag assigned to that instruction. A control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, the information for each instruction can be read out of the register file in program order. | 2009-01-08 |
20090013159 | Queue Processor And Data Processing Method By The Queue Processor - A queue processor and its data processing method are provided. It can do high-speed data processing and decreases the electric energy consumption. | 2009-01-08 |
20090013160 | DYNAMICALLY COMPOSING PROCESSOR CORES TO FORM LOGICAL PROCESSORS - A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved. | 2009-01-08 |
20090013161 | PROCESSOR FOR MAKING MORE EFFICIENT USE OF IDLING COMPONENTS AND PROGRAM CONVERSION APPARATUS FOR THE SAME - A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by a first functional unit that executes instructions stored in the first instruction slot, and a second functional unit that executes instructions stored in the second instruction slot. An instruction stored in the second instruction slot is executed in parallel by a third functional unit that executes instructions stored in the second instruction slot. | 2009-01-08 |
20090013162 | Managing a deployment of a computing architecture - Embodiments are provided to deploy a number of computing devices based in part on a deployment file, but the embodiments are not so limited. In an embodiment, a dispatch application can be used to deploy a number of computing devices, wherein the deployment includes a number deployment parameters and functions associated with a configuration of the number of computing devices. The dispatch application can be used to deploy a number of computing devices, including virtual devices, logical devices, and other devices and systems. Other embodiments are available. | 2009-01-08 |
20090013163 | METHOD AND SYSTEM FOR MONITORING AND ADAPTIVELY PRE-LOADING CRUCIAL DYNAMIC LINK LIBRARIES - The invention provides a system and method for adaptively loading frequently loaded dynamic link libraries. The system comprises: a monitor for monitoring loading events of dynamic link libraries while an operating system is running, and logging a name and related loading information of the corresponding dynamic link library into a log file in response to the loading events; and an invoker for automatically loading at least one of the most frequently loaded dynamic link libraries logged in the log file upon a subsequent startup of the operating system. By using the system and method, startup performance of the most frequently used applications can be greatly improved. | 2009-01-08 |
20090013164 | Computer system and method of using power button to switch from one BIOS to another - A computer system, using a power button to switch from one BIOS to another, includes a power button, a detection device and a switch circuit. The power button is electrically coupled to the computer system. The detection device is electrically coupled to the power button, and outputs a switch signal and a boot signal when the power button is continuously pushed for a switch time value, in which the boot signal is used to execute a boot procedure in the computer system. The switch circuit is electrically coupled to the detection device, and switches from a first BIOS to a second BIOS used for the boot procedure, in accordance with the switch signal. A method of using a power button to switch from one BIOS to another is also disclosed. | 2009-01-08 |
20090013165 | PORTABLE USB DEVICE THAT BOOTS A COMPUTER AS A SERVER - Techniques for booting a host computer from a portable storage device with customized settings have been described herein. According to one embodiment, in response to detecting a portable storage device inserted into a first host computer having a first operating environment provided by a first operating system (OS) installed in the first host computer, rebooting the first host computer into a second operating environment using a second OS image stored in the portable device. In addition, a personal configuration file stored in the portable device is extracted to configure the second operating environment of the first host computer, such that the user of the portable storage device can operate the second host computer in view of the personal working environment. Other methods and apparatuses are also described. | 2009-01-08 |
20090013166 | ROM BIOS BASED TRUSTED ENCRYPTED OPERATING SYSTEM - There is disclosed a device, system, and method for a ROM BIOS based trusted encrypted operating system for use in a gaming environment. The gaming device includes a ROM storing a BIOS, a secure loader, an encrypted operating system, and a decryption key for decrypting the encrypted operating system. The decryption key is partitioned and scattered about the secure loader. The method includes initializing the BIOS, locating the decryption key, decrypting the encrypted operating system with the encryption key, verifying a plurality of check codes, and transferring control to the operating system. The check codes are verified responsive to decrypting the encrypted operating system. The check codes are dispersed about the operating system and are unrelated to the operating system. Control is transferred to the operating system responsive to verifying the check codes. | 2009-01-08 |
20090013167 | COMPUTER DEVICE, METHOD FOR BOOTING THE SAME, AND BOOTING MODULE FOR THE SAME - A method for booting a computer device can be applied to a basic input/output system (BIOS). Whether backup data of a master boot record (MBR) is stored in the BIOS is first determined. When the backup data of the MBR is not stored in the BIOS, actual data of the MBR is backed up to the BIOS; when the backup data of the MBR is stored in the BIOS, the actual data of the MBR is compared with the backup data of the MBR. Then the backup data is restored to MBR when the actual data is different from the backup data. | 2009-01-08 |
20090013168 | SYSTEMS AND METHODS FOR AUTOMATIC PROVISIONING OF STORAGE AND OPERATING SYSTEM INSTALLATION - A method for provisioning a blade server is provided. The method includes creating a server boot image for a blade server, where the boot image includes an operating system image created from a donor server. Then, the method includes inserting the blade server into a chassis of an enclosure that is capable of receiving multiple blade servers. Then, staring the blade server from a pre-boot execution environment (PXE). The PXE loading an image that prompts a user to install a new operating system from a pre-existing target computer of the enclosure. The method then installs the new operating system. The installing includes creation of a new iSCSI target for the inserted blade server, and partitioning of the iSCSI target. The also includes restarting the inserted blade server. The restarting is configured to boot using the iSCSI target of the inserted blade server, so that the inserted blade server becomes a provisioned blade server. The provisioning is accomplished without a hardware iSCSI initiator for an iSCSI boot. | 2009-01-08 |
20090013169 | Method And System For Migrating Information Between Information Handling Systems - A system for migrating information includes a first information handling system (IHS). The first IHS is for, in response to a first boot event, booting from a computer readable medium, bypassing the first IHS user authentication requirement, and establishing a connection between the first IHS and a second IHS. The system for migrating information also includes the second IHS, coupled to the first IHS. The second IHS is for, in response to a second boot event, booting from a storage device of the second IHS, establishing the connection between the first IHS and the second IHS, and migrating information from the first IHS to the second IHS. | 2009-01-08 |
20090013170 | Control Device With Configurable Hardware Modules - A control device for controlling components in a vehicle with an interface to an external databus is described. The device includes a hardware module and a memory for making available the data necessary for the data processing. Controller processes are executed by control processes which can be actuated chronologically in parallel with one another, as a result communicating directly via an interface to the databus or with sensors/actuators in order to control components of vehicle. The control device has at least two configurable hardware modules which carry out a plurality of control processes in parallel on the basis of the messages from the databus or on the basis of the control instructions of the control device. A distribution unit is provided for assigning the controller processes which run in parallel to the hardware modules. After the assignment of a controller process to a hardware module, a hardware configuration is firstly loaded into the hardware module in order to newly configure its hardware, and after the allocation of the input data for the controller process, the newly configured hardware module performs the control of the assigned component. | 2009-01-08 |
20090013171 | COMPUTER DOCKING SYSTEM USING HARDWARE ABSTRACTION - One embodiment uses a virtual machine layer between software and hardware on both a portable computing device and on a docking station used by the portable computing device. A first virtual machine layer on the portable device is used to save the state of the portable device upon intermediate shutdown. Upon docking the portable device with the docking station, a second virtual machine layer on the docking station is loaded with the state of the first virtual machine. The second virtual machine layer is aware of the resources in the docking station and is programmed to utilize the docking station resources (and the portable computing device resources, as desired) to restore and continue the state while allowing the operating system, application programs and other software and hardware to utilize the resources of the docking station. | 2009-01-08 |
20090013172 | METHOD AND DEVICES FOR REPRODUCING ENCRYPTED CONTENT AND APPROVING REPRODUCTION - A reproduction method capable of immediately revoking a leaked device key by dividing the device key into a first partial key and a second partial key is provided. The reproduction method includes the operations of receiving encrypted content to be reproduced, requesting a token for decrypting the received content from an external device containing a first partial key of a device via a network, receiving the requested token from the external device, and decrypting the received token by using a second partial key contained in the device, thereby preventing content encrypted and distributed before revocation of an illegally copied device from being reproduced, and minimizing damage due to key leakage. | 2009-01-08 |
20090013173 | Portable cross platform database accessing method and system - A user manages a database or other application through a remote graphical user interface on a server device through a client device. A cross platform database translation module resides on the client device. The client device may also store cross platform authentication, configuration, and report generating modules for validating a user id and presenting database results in a desirable format. The modules on the client device request applications from a server device, may request validation from an authorization server, may configure embedded devices, and may query a database. The database may reside on a server, on the client device, or on another device. | 2009-01-08 |
20090013174 | METHODS AND SYSTEMS FOR HANDLING DIGITAL RIGHTS MANAGEMENT - Systems and methods according to the present invention address this need and others by providing methods and systems for translating media encrypted by various Digital Rights Management (DRM) techniques. This allows end user equipment to receive media in an IMS/IPTV environment when the end user equipment uses a DRM that is different from the media server which is providing the desired media in both unicast and multicast applications. | 2009-01-08 |
20090013175 | METHOD AND APPARATUS FOR CONTROLLING THE FLOW OF DATA ACROSS A NETWORK INTERFACE - The present invention performs “flow control” based on the remaining encryption capacity of an encrypted outbound network interface link of a network routing device, such as a router or switch. As the encrypted link begins to run low on encryption key material, this invention begins to discard datagrams queued for transit across that link, in order to signal distant host computers that they should slow down the rate at which they are sending datagrams. The invention, which is particularly useful in cryptographically protected networks that run the TCP/IP protocol stack, allows fine-grained flow control of individual traffic classes because it can determine, for example, how various classes of data traffic (e.g., voice, video, TCP) should be ordered and transmitted through a network. Thus, the invention can be used to implement sophisticated flow control rules so as to give preferential treatment to certain people, departments or computers. | 2009-01-08 |
20090013176 | APPLICATION LEVEL INTEGRATION IN SUPPORT OF A DISTRIBUTED NETWORK MANAGEMENT AND SERVICE PROVISIONING SOLUTION - An integrated data network management and data service provisioning environment is provided. The integrated environment includes legacy software application code and current software application code each augmented with code portions enabling exchange of information therebetween via an interworking layer. A facility for participation in and interacting with the integrated environment is also provided. A man-machine interface is integrated across different applications which themselves may be executed on different computers to provide a seamless exchange of information. The advantages are derived from enhanced usage efficiencies in providing data network management and service provisioning solutions. The interworking layer also provides for security enforcement across applications participating in the integrated environment. | 2009-01-08 |
20090013177 | LICENSE MANAGEMENT SYSTEM AND METHOD - A license-management system and method is provided. A method of issuing a proxy certificate includes transmitting a proxy-certificate-issuance-request message to a license server in order for the local license manager to acquire an authority to issue a license by a local license manager; enabling the license server to verify the proxy-certificate-issuance-request message; if the proxy-certificate-issuance-request message is valid, transmitting a proxy certificate to the local license manager by the license server, the proxy certificate including information regarding the authority to issue a license; and verifying the proxy certificate by the local license manager. | 2009-01-08 |
20090013178 | Integrated circuit for the authentication of a consumable storage device - An integrated circuit for the authentication of a consumable storage device by an apparatus includes a memory space which contains encrypted data defined by a message authentication code (MAC) applied to data relating to a consumable stored by the device and by at least one secret key (K) shared by the apparatus for decryption of the data. The MAC is a construction of a cryptographic function. | 2009-01-08 |
20090013179 | Controlling With Rights Objects Delivery Of Broadcast Encryption Content For A Network Cluster From A Content Server Outside The Cluster - Methods, systems, and products are disclosed for delivering broadcast encryption content. Embodiments of the present invention typically include receiving in a cluster broadcast encryption content; receiving in a cluster a rights object defining device-oriented digital rights for broadcast encryption content; and administering the broadcast encryption content on one or more network devices in the cluster in dependence upon the digital rights. In some embodiments, administering the broadcast encryption content on one or more network devices in the cluster in dependence upon the digital rights include mapping the device-oriented digital rights to digital rights supported in the cluster, excluding device-oriented rights not supported in the cluster. In some embodiments, mapping the device-oriented digital rights to digital rights supported in the cluster includes supporting in the cluster only those device-oriented digital rights having direct analogs in the cluster. | 2009-01-08 |
20090013180 | Method and Apparatus for Ensuring the Security of an Electronic Certificate Tool - The present invention discloses a method and apparatus for ensuring the security of an electronic certificate tool, the method comprising: A: inputting business information by using the input or confirmation function set up in the electronic certificate tool; and step B: encrypting, attaching signature to or/and authenticating the inputted business information by the electronic certificate tool and sending the processed business information over the Internet via a computed connected to the Internet to make business dealing or/and payment. The method and apparatus ensure the security of the electronic certificate tool and are convenient and easy to use. | 2009-01-08 |
20090013181 | METHOD AND ATTESTATION SYSTEM FOR PREVENTING ATTESTATION REPLAY ATTACK - Provided are a method and an attestation system for preventing an attestation replay attack. The method for preventing an attestation replay attack in an attestation system including an attestation target system and an attestation request system, the method including: measuring associated components when an event that affects the integrity of the attestation target system occurs; perceiving own identity information and verifying the perceived identity information; extending the measured component and the identity information into a register and logging the measured component and the identity information; generating an attestation response message including values of the log and the register when an attestation request message is received from the attestation request system; and transmitting the generated attestation response message to the attestation request system. Therefore, the method and an attestation system may be useful to provide an additional simple mathematical operation in verifying an attestation message by preventing an attestation replay attack, and thus to minimize performance degradation in the attestation system, compared to the conventional attestation processing mechanisms. | 2009-01-08 |
20090013182 | Centralized Identification and Authentication System and Method - A method and system is provided by a Central-Entity, for identification and authorization of users over a communication network such as Internet. Central-Entity centralizes users personal and financial information in a secure environment in order to prevent the distribution of user's information in e-commerce. This information is then used to create digital identity for the users. The digital identity of each user is dynamic, non predictable and time dependable, because it is a combination of user name and a dynamic, non predictable and time dependable secure code that will be provided to the user for his identification. The user will provide his digital identity to an External-Entity such as merchant or service provider. The External-Entity is dependent on Central-Entity to identify the user based on the digital identity given by the user. The External-Entity forwards user's digital identity to the Central-Entity for identification and authentication of the user and the transaction. The identification and authentication system provided by the Central-Entity, determines whether the user is an authorized user by checking whether the digital identity provided by the user to the External-Entity, corresponds to the digital identity being held for the user by the authentication system. If they correspond, then the authentication system identifies the user as an authorized user, and sends an approval identification and authorization message to the External-Entity, otherwise the authentication system will not identify the user as an authorized user and sends a denial identification and authorization message to the External-Entity. | 2009-01-08 |
20090013183 | Confidential Information Processing Method, Confidential Information Processor, and Content Data Playback System - In order to maintain the confidentiality of information at a high level even in cases where a confidential information processor in which multiple types of decryption sequences are applicable is used, decryption is performed according to the value of content decryption information | 2009-01-08 |
20090013184 | Method, System And Apparatus For Protecting A BSF Entity From Attack - A method, system and apparatus for protecting a bootstrapping service function (BSF) entity from attack includes: obtaining a first temporary identity and a second temporary identity after a user equipment (UE) performing mutual authentication with the BSF entity, where the first temporary identity is different from the second temporary identity; by the UE, originating a re-authentication request to the BSF entity through the first temporary identity; and originating a service request to a NAF entity through the second temporary identity. The present disclosure prevents attackers from intercepting the temporary identity at the Ua interface and using the temporary identity to originate a re-authentication request at the Ub interface, thus protecting the BSF entity from attack and avoiding unnecessary load on the BSF entity and saving resources. | 2009-01-08 |
20090013185 | COMPATIBLE SYSTEM OF DIGITAL RIGHTS MANAGEMENT AND METHOD FOR OPERATING THE SAME - Disclosed is a compatible system of digital rights management which enables the reproduction of the same contents between apparatuses each employing a different digital rights management system. The compatible system of digital rights management comprises: a user server including a first authentication document of a first apparatus; a second apparatus connected to the first apparatus and outputting a contents request signal and a second authentication document to reproduce substantially the same contents; and a provider server forming a virtual safe channel with the user server based on the contents request signal to receive the first authentication document, and generating first and second licenses encrypted through the first and second authentication documents to transmit the same to the second apparatus. | 2009-01-08 |
20090013186 | METHOD AND SYSTEM FOR THE AUTHORIZATION MANAGEMENT - A method is provided for the authorization management of digital contents between at least one owner of authorizations with a first electronic work environment and at least one user of the contents with a second electronic work environment. The owner of the authorizations provides the digital contents to the user of the contents by means of the first electronic work environment at a defined scope of authorizations and the user of the contents is entitled to use the provided digital contents on the second electronic work environment only at the defined scope of authorization. The digital contents are encoded with encryption, the encoded contents are exchanged between the first electronic work environment and the second electronic work environment and the encoded contents are subsequently decoded by means of decryption pertaining to the digital contents. | 2009-01-08 |
20090013187 | Secure Storage Device For Transfer Of Digital Camera Data - A secure storage device with the external dimensions of a PCMCIA card, for securing digital camera data at the acquisition stage. Original digital camera data is saved in the memory of the secure storage device which has the capability of performing one or more security functions, including encryption, creation of an authentication file, adding data to the image data such as fingerprinting, and adding secure annotations such as separate data included in an image-header. The device prepares original authentication data from original digital camera data, and encrypts and stores both the original authentication data and the original image data. The use of the device includes downloading the original image data to a first computer, and encrypted original authentication data to a second computer. The second computer can be programmed with software whereby the encrypted original authentication data can be decrypted by a user having a key. The software then allows the user to prepare corresponding second authentication data from second image data of questionable authenticity. If the second authentication data is the same as the original authentication data, the questionable second image data is deemed to be an accurate copy of the original image data. | 2009-01-08 |
20090013188 | Search for a Watermark in a Data Signal - The invention relates to a method of searching for a watermark in a data signal, and to a watermark detector, such as a copy-control watermark detector. The search is conducted in order to find a watermark in content which possibly has been attacked and/or altered. The search is conducted by the steps of determining or setting a search space for the data signal, selecting a subspace of the search space, and searching for the presence of the watermark in the subspace. The subspace may be selected from a multitude of regions, the selection e.g. being based on a deterministic or probabilistic function. | 2009-01-08 |
20090013189 | Method and devices for video processing rights enforcement - A system for protection against unauthorized modifications of digital content, in particular image content, in which a content processing system retrieves content, a fingerprint for the content and at least one modification limit expressing authorized modifications to the content. The content may then be modified, but before saving or exportation is allowed, a second fingerprint is calculated, and the difference between the fingerprints is compared with the at least one modification limit. If the difference is within the allowed bounds, then saving or exportation is allowed; if not, it is prevented. Also provided are a method and a content consumer device performing essentially the same steps before allowing rendering of the content. | 2009-01-08 |
20090013190 | SECURE MEMORY DEVICE FOR SMART CARDS - A secure memory device which can be used for multi-application smart cards for secure identification in data transfer, or for component verification in a computer system, without the requirement of an internal microprocessor. The secure memory device features a dual authentication protocol in which the memory and host authenticate each other. The secure memory device also includes an encrypted password feature, as well as using stream encryption to encrypt the data. | 2009-01-08 |
20090013191 | MULTISYSTEM BIOMETRIC TOKEN - An apparatus and a method for generating a unique user identification code for a user of a biometric security system is presented. No biometric information is stored either within the security system or on a device, and process enables a unique user identification code to be generated to allow multi-system identification of the same user. | 2009-01-08 |
20090013192 | INTEGRITY CHECK METHOD APPLIED TO ELECTRONIC DEVICE, AND RELATED CIRCUIT - An integrity check method applied to an electronic device includes: fetching at least one portion of external data into a specific memory, where the external data is stored within the electronic device; during fetching the portion of the external data into the specific memory, checking whether the size of the fetched data in the specific memory reaches a predetermined value, where the predetermined value is less than the total size of the external data; and when the size of the fetched data in the specific memory reaches the predetermined value, enabling an integrity check of the fetched data. | 2009-01-08 |
20090013193 | Circuit Building Device - The present invention provides an apparatus for securely acquiring a circuit configuration information set corresponding to a new cryptosystem without increasing the number of reconfigurable circuits. A content playback apparatus | 2009-01-08 |
20090013194 | TECHNIQUE FOR PROTECTING A DATABASE FROM AN ONGOING THREAT - A system for stopping an ongoing threat to a database is described. During operation, if an ongoing threat to the database is detected, the system modifies a threat-assessment condition. Then, the system selectively restricts access to one or more cryptographic keys for the database based on the threat-assessment condition. Next, the system selectively activates decryption of requested encrypted information based on the threat-assessment condition. Note that both the selective restriction of access to the one or more cryptographic keys and the selective activation of decryption can be used to stop the ongoing threat from accessing the encrypted information in the database. | 2009-01-08 |
20090013195 | Data Storing Method, Data Playback Method, Data Recording Device, Data Playback Device, and Recording Medium - Provided is a method for performing high-speed search for a content key associated with encrypted content in the case of a key-separation-type content management method where content keys and their respective pieces of encrypted content are correlated by ID information and stored in different recording media. An external recording medium is used to store a plurality of content files that contain: their respective pieces of encrypted content that are encrypted with different encryption keys; and their respective content IDs, each being associated with a corresponding piece of the encryption content, and a semiconductor recording medium is used to store a list that contains: pieces of encryption key storage location information, each indicating where a corresponding one of the encryption keys is stored; and the content IDs, the list being sorted in accordance with the content IDs. When encrypted content is played back, the list is searched to find encryption key storage location information associated with a content ID that matches the content ID of the encrypted content, and the encryption key is read based on the encryption key storage location information. | 2009-01-08 |
20090013196 | Secure Processing Device, Method and Program - A secure processing device having a power saving mode, which is used for built-in apparatuses, calculates a hash value of secure data that needs to be saved when switching to the power saving mode, stores the calculated hash value in a protection storage unit whose data is not lost even in the power saving mode, encrypts the secure data and stores the encrypted data in an external memory when switching to the power saving mode. When switching back to the normal power mode, the secure processing device decrypts the encrypted data, calculates a hash value of the decrypted data and compares the hash value with the hash value stored in the protection storage unit. The decrypted data is restored to the protection storage unit when the hash values are identical, but discarded together with the encrypted data stored in the external memory when the hash values are not identical. | 2009-01-08 |
20090013197 | Method and Apparatus for Trusted Branded Email - A trusted branded email method and apparatus in one aspect detects branded electronic messages and performs validation before it is sent to a recipient. In another aspect, an electronic messages is branded by embedding branding assets and validation signatures. Algorithms that generate validation signatures are dynamically selected to further strengthen the security aspects. Branding assets are presented to a user using a distinct indicia that represents to the user that the branding assets are secure. | 2009-01-08 |
20090013198 | ELECTRONIC APPARATUS WITH IMPROVED MEMORY POWER MANAGEMENT - An electronic apparatus includes a battery holder, a detector detecting a battery, a non-volatile memory storing a program for initialization, a volatile memory, a first power supply for the non-volatile memory, a second power supply for the volatile memory, a power switch, a power supply controller activating the first power supply and the second power supply after the battery is detected or after the power switch is turned on, and a management circuit sending the program from the non-volatile memory to the volatile memory if the first and the second power supplies are activated and before the program is fully sent to the volatile memory, causing the power supply controller to deactivate the first power supply after sending the program, and causing the program in the volatile memory to run after the power switch is turned on. | 2009-01-08 |
20090013199 | DIGITAL POWER SUPPLY CONTROLLER WITH INTEGRATED MICROCONTROLLER - A digital power supply controller is disclosed for controlling the operation of a switched power supply. The controller is contained within an integrated circuit package enclosing an integrated circuit chip. A plurality of inputs are provided on the package for interfacing with the switched power supply for receiving sensed inputs therefrom. A plurality of outputs provide switch control signals for turning on and off switches in the switched power supply. An integrated digital controller on the chip receives the inputs and generates the outputs, and includes an integrated instruction based processing engine for providing a portion of the digital control of the digital controller. A memory associated with the processing engine stores instructions for the processing engine. | 2009-01-08 |
20090013200 | DATA PROCESSING APPARATUS AND DATA PROCESSING APPARATUS CONTROL METHOD - A data processing apparatus includes a receiving unit configured to receive data, a first processing unit configured to perform predetermined processing on the received data, a second processing unit configured to perform the predetermined processing on the received data, a first control unit configured to perform control so that the data processing apparatus operates in one of a first operation mode for supplying power to both the first processing unit and the second processing unit and a second operation mode for discontinuing a supply of power to the first processing unit while supplying power to the second processing unit, and a second control unit configured to perform control so that the first processing unit performs the predetermined processing if the data processing apparatus operates in the first operation mode and that the second processing unit performs the predetermined processing if the data processing apparatus operates in the second operation mode. | 2009-01-08 |
20090013201 | Method for Reducing Power Consumption of Processor - A method for reducing power consumption of a processor is disclosed comprising steps of applying time-frequency transformation to a plurality of load values of the processor to obtain the feature sampling cycle of the processor, and adjusting the voltage/frequency of the processor based on said feature sampling cycle. With the method of the present invention, the processor load value in next time interval can be accurately predicted, and thus the voltage/frequency of the processor in the next time interval can be adjusted on the basis of the load value. | 2009-01-08 |
20090013202 | Portable Information Processing Apparatus And Method Of The Same - The present invention relates to a portable information apparatus which can realize electrical power for a longer period of time. Under the condition that the suspending mode is set, when an exclusive key is manipulated, a switch monitoring circuit detects this condition and issues an interruption to the CPU. In this timing, the CPU supplies the necessary electrical power to the CD-ROM controller, CD-ROM drive and audio circuit which are required for reproduction of CD. Thereby, a CD can be reproduced under the suspending mode. | 2009-01-08 |
20090013203 | Method and apparatus for power saving mode in hard disk drive - A method for implementing a power saving mode in a hard disk drive. The method includes the steps of flying a head over a data track of a disk that is covered with a lubricant. The speed of the disk is reduced. A voltage is applied to a heating element of the head to move the head closer to the disk. The fly height of the head is then determined. The voltage can be incrementally varied until the head makes contact with the disk. The voltage is terminated and the head is allowed to fly over the data track. The head is also moved to adjacent tracks on either side of the data track. A pressure gradient of the flying head moves the lubricant about the disk to mitigate a modulated wear pattern caused by the reduction in disk speed. The disk speed is then increased in a normal operating mode. | 2009-01-08 |
20090013204 | INFORMATION PROCESSING DEVICE AND MOBILE PHONE - An information processing device, for use in a mobile terminal unable to obtain power consumption information from an external source, which can estimate, based on an actual performance value, a battery life, power consumption for processing that changes depending on the usage by the user, and so on, and ensures execution of processing specified by the user for a specified period of time, the information processing device comprising a power consumption calculating unit which calculates, for each processing executed by the information processing device, power consumption information concerning an amount of power consumed by executing each processing; a request generating unit which compares the amount of power indicated by the power consumption information and a remaining amount of power of the information processing device, and generates a request to execute predetermined processing according to a result of the comparison; and a request processing unit which executes the predetermined processing in response to the generated request. | 2009-01-08 |
20090013205 | Information Leakage Prevention Apparatus and Information Leakage Prevention Method - A clock signal extractor ( | 2009-01-08 |
20090013206 | Efficient Utilization of a Multi-Source Network of Control Logic to Achieve Timing Closure in a Clocked Logic Circuit - A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit. | 2009-01-08 |
20090013207 | PREDICTING MICROPROCESSOR LIFETIME RELIABILITY USING ARCHITECTURE-LEVEL STRUCTURE-AWARE TECHNIQUES - A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms. | 2009-01-08 |
20090013208 | REAL TIME AUTOMATED EXCEPTION NOTIFICATION AND REPORTING SOLUTION - A closed loop, autonomic exception notification and resolution system enables an application to proactively collect and forward exception information to developers with no user intervention; in some cases before the user is even aware that an exception has occurred. A notification process ensures that the appropriate resources can be applied to exception resolution, increasing error resolution by decreasing duplicate or misdirected efforts. An error coding scheme ensures that errors are uniquely and consistently reported while allowing duplicate issues to be grouped, further reducing duplicated efforts and improving resolution time. The use of an Exception Object which is automatically populated ensures that all information that is necessary to resolve the exception is provided to developers, thereby reducing debug time. Error resolutions are stored in a centralized database which can be accessed to quickly leverage previously generated solutions. | 2009-01-08 |
20090013209 | APPARATUS FOR CONNECTION MANAGEMENT AND THE METHOD THEREFOR - An apparatus and method for scheduling data distributions to or results information from, or collectively, “jobs” a plurality of data processing systems via a network. A connection to a target system is created. For each distribution, a session, which is an independent thread, is allocated from one of a plurality of pool of sessions and launched to effect execution of the job. Each pool corresponds to a predetermined priority level, and the session is allocated from the pool having the same priority level as the priority level of the job being scheduled. A connection supports a multiplicity of independent threads. In the event of an error, the session is released, and the scheduling of the aborted job is retried after a predetermined retry interval expires. After expiry of the retry interval, a callback method is invoked when the target system on which the scheduled job is executed becomes accessible. | 2009-01-08 |
20090013210 | Systems, devices, agents and methods for monitoring and automatic reboot and restoration of computers, local area networks, wireless access points, modems and other hardware - An embodiment of the invention is a client on a local area network that periodically and automatically evaluates its physical connectivity with the local area network, exercises local-network services such as DHCP, and verifies Internet connectivity and function by pinging one or more numerically specified IP addresses and by pinging one or more IP addresses specified by an FQDN (Fully Qualified Domain Name) known to the assigned DNS servers. An embodiment of the invention may include a plurality of client elements monitoring one or more networks. Functionality according to embodiments of the invention can send notices, automatically initiate action, and otherwise assist in, among other things, remote monitoring and administration of networks, and particularly wireless networks. | 2009-01-08 |
20090013211 | MEMORY CHANNEL WITH BIT LANE FAIL-OVER - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 2009-01-08 |
20090013212 | System and Method for Computer Data Recovery - The invention consists of a method of data recovery for a computer system, the steps comprising: a) initializing hardware associated with the computer system, the hardware including a hard drive, and a minimum of 32 MB of RAM; b) initializing network devices and connections associated with the computer system; c) scanning and identifying partitions on any hard drives connected to the computer system; d) recovering data from the hard drives by making all the data on the computer system available over the network as a network share resembling a file server; and e) copying the recovered data over the network connection to a recovery hard drive. | 2009-01-08 |