Entries |
Document | Title | Date |
20100275176 | Method for Time-Evolving Rectilinear Contours Representing Photo Masks - Photomask patterns are represented using contours defined by level-set functions. Given target pattern, contours are optimized such that defined photomask, when used in photolithographic process, prints wafer pattern faithful to target pattern. Optimization utilizes “merit function” for encoding aspects of photolithographic process, preferences relating to resulting pattern (e.g. restriction to rectilinear patterns), robustness against process variations, as well as restrictions imposed relating to practical and economic manufacturability of photomasks. | 10-28-2010 |
20110010677 | METHOD AND SYSTEM FOR LITHOGRAPHIC SIMULATION AND VERIFICATION - Methods and systems for lithographic simulation and verification comprising a process in the frequency domain or in the spatial domain of calculating intensity at a location (x, y) for a number of defocus values. In addition, evaluating the intensity calculation result to determine if the intensity level will result in the mask pattern being written onto a wafer. The verification process may be calculated in the spatial domain or in the frequency domain. The calculations may be done such that full focus window calculations may be obtained by isolating the defocus parameter “z” in the calculations. | 01-13-2011 |
20110016436 | Digitally Obtaining Contours of Fabricated Polygons - The present invention provides a method for digitally obtaining contours of fabricated polygons. A GDS polygon described in a Geographic Data System (GDS) file is provided. Based on the GDS polygon, a plurality of identical polygons is fabricated with the same fabrication process such that shapes of the plurality of identical polygons are altered by optical effects in the same or similar way. The plurality of identical polygons forms poly-silicon gates of a plurality of test transistors. The position of source and drain islands along a length of a poly-silicon gate for each of the plurality of test transistors is different. Using Automated Test Equipment (ATE), a digital test is performed on a circuit including the plurality of test transistors to obtain test responses, the test responses being raw digital data. The test responses may be displayed in a histogram reflecting a contour of the plurality of identical polygons or post-processed to reconstruct a contour of the plurality of identical polygons. | 01-20-2011 |
20110016437 | METHOD AND APPARATUS FOR MEASURING OF MASKS FOR THE PHOTO-LITHOGRAPHY - The invention relates to a method and an apparatus for measuring masks for photolithography. In this case, structures to be measured on the mask on a movable mask carrier are illuminated and imaged as an aerial image onto a detector, the illumination being set in a manner corresponding to the illumination in a photolithography scanner during a wafer exposure. A selection of positions at which the structures to be measured are situated on the mask is predetermined, and the positions on the mask in the selection are successively brought to the focus of an imaging optical system, where they are illuminated and in each case imaged as a magnified aerial image onto a detector, and the aerial images are subsequently stored. The structure properties of the structures are then analyzed by means of predetermined evaluation algorithms. The accuracy of the setting of the positions and of the determination of structure properties is increased in this case. | 01-20-2011 |
20110029937 | PATTERN EVALUATING METHOD, PATTERN GENERATING METHOD, AND COMPUTER PROGRAM PRODUCT - A pattern evaluating method includes generating a proximity pattern that affects a resolution performance of a circuit pattern around a lithography target pattern of the circuit pattern to be formed on the substrate, generating distribution information on a distribution of an influence degree to the resolution performance of the circuit pattern by using the lithography target pattern, calculating the influence degree to the resolution performance of the circuit pattern by the proximity pattern as a score by comparing the distribution information with the proximity pattern, and evaluating whether the proximity pattern is placed at an appropriate position in accordance with the circuit pattern based on the score. | 02-03-2011 |
20110041104 | Semiconductor circuit pattern design method for manufacturing semiconductor device or liquid crystal display device - A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected. | 02-17-2011 |
20110047519 | Layout Content Analysis for Source Mask Optimization Acceleration - The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign. In further implementations, the difficult-to-print sections may be subjected to a source mask optimization process. Subsequently, the entire layout design may receive a conventional resolution enhancement treatment using the optimized source. | 02-24-2011 |
20110047520 | Partition Response Surface Modeling - A group of models are developed to predict printed contour deviations relative to the corresponding layout edges for different classes of layout topologies. A plurality of calibration layouts with topologies belonging to a class of layout topologies are used to generate a model for the class of layout topologies. A standard least square regression is modified for model creation. The model error may be monitored dynamically. | 02-24-2011 |
20110055776 | METHOD OF DESIGNING SEMICONDUCTOR DEVICE - This is a method of designing a semiconductor device. The method includes: arranging cells used for an electric circuit and wirings respectively connected to gates of the cells in a coordinate region to create chip layout data including the cells, gates and wirings; checking whether each gate included in the chip layout data is in antenna violation; storing antenna violation information in an error-remaining portion library, the antenna violation information representing an antenna violation gate group, in which gates in the antenna violation are contained, in the gates included in the chip layout data; performing lithography simulation for the chip layout data to create predicted layout data after photoresist exposure; selecting the antenna violation gate group from the gates included in the predicted layout data, with reference to the error-remaining library; calculating a calculated value representing a ratio of an area of an wiring of the wirings with respect to an area of a gate of the antenna violation gate group connected to the wiring, for each gate of the antenna violation group; and adjusting a size of the gate of the antenna violation gate group, when the calculated value of the antenna violation group included in the predicted layout data is in a range between a first and second setting value. | 03-03-2011 |
20110072401 | Model-Based Fill - Various aspects of this disclosure relate to increasing pattern density in a circuit layout design of a circuit layer so as to control the thickness of material in a manufactured integrated circuit. For example, a layer in circuit design may be divided into separate areas, and a target thickness range may be established for all of the tiles in the integrated circuit design. Each area may be analyzed to determine if it has a sufficient pattern density for a thickness estimation model to accurately estimate its expected material thickness upon manufacture. Each tile may be analyzed to determine if the expected thickness for that tile is within the target thickness range. | 03-24-2011 |
20110078638 | LAYOUT DECOMPOSITION FOR DOUBLE PATTERNING LITHOGRAPHY - The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs. | 03-31-2011 |
20110107279 | METHOD FOR CORRECTING IMAGE RENDERING DATA, METHOD FOR RENDERING IMAGE, METHOD FOR MANUFACTURING WIRING BOARD, AND IMAGE RENDERING SYSTEM - A method for correcting image rendering data includes preparing image rendering data having position coordinates that determine an image rendering region and base position coordinates that show the position of a base point arranged in the image rendering region; obtaining a displacement state of position coordinates on an image rendering object; based on the obtained displacement state of position coordinates on the image rendering object, correcting the base position coordinates; and based on the corrected base position coordinates, correcting the position coordinates of the image rendering region while the shape of the image rendering region is maintained. | 05-05-2011 |
20110119643 | SUM OF COHERENT SYSTEMS (SOCS) APPROXIMATION BASED ON OBJECT INFORMATION - A method for determining kernels in a sum of coherent systems (SOCS) approximation is provided. Information for an object to be simulated in a manufacturing process is determined. For example, information based on geometries that are included in a layout or mask is determined. A set of kernels from a transmission cross coefficient (TCC) matrix are also determined. The set of kernels may be weighted by importance values in an order of importance. The kernels may then be re-ordered based on the information for the object. These kernels are then re-ordered in the SOCS series to reflect their order of importance. The SOCS series of kernels is then truncated at the number of kernels desired. Accordingly, by re-ordering the kernels that may be more relevant to the object to include higher weights, when the truncation occurs, the kernels that are most relevant may be included in the SOCS approximation. | 05-19-2011 |
20110119644 | METHODS OF ARRANGING MASK PATTERNS AND ASSOCIATED APPARATUS - Methods and apparatus are disclosed that arrange mask patterns in response to the contribution of a second pattern to image intensity. In some methods of arranging mask patterns, a distribution of functions h(ξ−x) is obtained which represents the contribution of a second pattern to image intensity on a first pattern. Neighboring regions of the first pattern are discretized into finite regions, and the distribution of the functions h(ξ−x) is replaced with representative values | 05-19-2011 |
20110154273 | METHOD OF GENERATING MASK PATTERN, MASK PATTERN GENERATING PROGRAM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, in process simulation, it is verified whether sidewall patterns formed on sidewalls of a core material pattern or a transfer pattern formed by transferring the core material pattern form a closed loop. When it is determined as a result of the verification that the sidewall patterns form a closed loop, the mask pattern is changed. When it is determined as a result of the verification that the sidewall patterns do not form a closed loop, the mask pattern is adopted. | 06-23-2011 |
20110161893 | LITHOGRAPHIC PLANE CHECK FOR MASK PROCESSING - The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired. | 06-30-2011 |
20110179392 | LAYOUT DETERMINING FOR WIDE WIRE ON-CHIP INTERCONNECT LINES - A method for determining the layout of an interconnect line is provided including: providing a required width for the interconnect line; determining a layout of the interconnect line including slotting the interconnect line to provide two or more fingers extending along the interconnect line with an elongate slot separating adjacent fingers; and determining a number of elongate apertures to be arranged across the width of the interconnect line by comparing the required width with a maximal width for a solid metal feature, and a minimal elongate aperture width. The two or more fingers and elongate slot may be of constant width and equally spaced across the interconnect line width. The method may include selecting the number of fingers and the width of the slots to optimize the layout for a given layer technology. | 07-21-2011 |
20110185323 | Stacked Integracted Circuit Verification - Techniques for performing physical verification processes for stacked integrated circuit devices. An interface between a first two-dimensional integrated circuit device and a second two-dimensional integrated circuit device is identified. The design data for the identified layers in the first and second two-dimensional integrated circuit devices are then combined and physically verified as a single set of interface design data. The design data for the first two-dimensional integrated circuit device and the second two-dimensional integrated circuit device are then separately physically verified. Once the interface design data, the first two-dimensional integrated circuit device design data and the second two-dimensional integrated circuit device design data have been physically verified, the verified design can be recombined to form verified design data corresponding to a stacked integrated circuit device. | 07-28-2011 |
20110191725 | FAILURE ANALYSIS USING DESIGN RULES - The use of design rule checks for failure analysis of semiconductor chips is described. The smaller geometries of recent semiconductor devices lead to a much higher level of sensitivity of devices to photolithography related systematic problems. Failure analysis to date has focused on physical, randomly distributed defects of devices rather than systematic problems caused by the mask manufacturing or mask application process. Methods and systems are described which allow for online searches of a layout database for geometric features defined by a set of rules. The rules may be defined as two-dimensional Boolean operations including shape or distance based as well as any kind of combination. The result is graphically and interactively presented. | 08-04-2011 |
20110191726 | Selective Optical Proximity Layout Design Data Correction - After layout design data has been modified using an OPC process, a repair flow is initiated. This repair flow includes analyzing the modified data to identify any remaining or new potential print errors in the layout data. Regions then are formed around the identified potential print errors, and a subsequent OPC process is performed only on the data within these regions using a different set of process parameters from the process parameters employed by the initial OPC process. This repair flow is iteratively repeated, where a different set of process parameter values for the subsequent OPC process is used during each iteration. | 08-04-2011 |
20110202890 | DESIGN SYSTEM FOR SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE AND METHOD FOR BONDING SUBSTRATES - The terminals that oppose each other when substrates are bonded are designed to be reliably joined. Comprised in a semiconductor device design system are a numerical value acquiring part, which acquires the respective numerical values of a plurality of calculation parameters, a junction estimating part, which, in the case in which a plurality of substrates has been pressed at a prescribed pressure so that the bump front end faces come into contact, estimates whether or not the respective mutually opposing bumps will be joined based on the respective numerical values of the calculation parameters acquired by the numerical value acquiring part, and a change processing part, which, in the case in which it has been estimated by the junction estimating part that any of the bumps will not be joined, gives a warning or performs processing so as to change the numerical value of at least one calculation parameter among the plurality of calculation parameters. | 08-18-2011 |
20110202891 | EVALUATING THE QUALITY OF AN ASSIST FEATURE PLACEMENT BASED ON A FOCUS-SENSITIVE COST-COVARIANCE FIELD - One embodiment of the present invention provides a system that determines an assist feature placement within a post-optical proximity correction (post-OPC) mask layout. During operation, the system receives a set of target patterns which represent a set of polygons in a pre-OPC mask layout. The system then constructs a focus-sensitive cost function based on the target patterns, wherein the focus-sensitive cost function represents an amount of movement of post-OPC contours of the target patterns in response to changes in focus condition of the lithography system. Note that the contours of the target patterns substantially coincide with the edges of set of the polygons. Next, the system computes a cost-covariance field (CCF field) based on the focus-sensitive cost function, wherein the CCF field is a two-dimensional (2D) map representing changes to the focus-sensitive cost function due to an addition of a pattern at a given location within the post-OPC mask layout. Finally, the system generates assist features for the post-OPC mask layout based on the CCF field. | 08-18-2011 |
20110219342 | Design Rule Optimization in Lithographic Imaging Based on Correlation of Functions Representing Mask and Predefined Optical Conditions - Methods, computer program products and apparatuses for optimizing design rules for producing a mask are disclosed, while keeping the optical conditions (including but not limited to illumination shape, projection optics numerical aperture (NA) etc.) fixed. A cross-correlation function is created by multiplying the diffraction order functions of the mask patterns with the eigenfunctions from singular value decomposition (SVD) of a TCC matrix. The diffraction order functions are calculated for the original design rule set, i.e., using the unperturbed condition. ILS is calculated at an edge of a calculated image of a critical polygon using the cross-correlation results and using translation properties of a Fourier transform. The use of the calculated cross-correlation of the mask and the optical system, and the translation property of the Fourier transform for perturbing the design reduces the computation time needed for determining required changes in the design rules. Once an optimum separation is calculated, it is incorporated into the design rule to optimize the mask layout for improved ILS throughout the mask, including critical and non-critical portions of the mask. | 09-08-2011 |
20110225554 | Method for the Reproducible Determination of the Position of Structures on a Mask with a Pellicle Frame - A method for the reproducible determination of the positions of structures ( | 09-15-2011 |
20110265047 | Mask data processing method for optimizing hierarchical structure - Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree. | 10-27-2011 |
20110302539 | METHOD FOR DESIGNING MASKS USED TO FORM ELECTRONIC COMPONENTS - A method for designing masks adapted to the forming of integrated circuits, including the steps of: (a) forming a first test file including a set of configurations of integrated circuit elements; (b) forming a second test file comprising the elements of the first test file, less the elements corresponding to configurations forbidden by design rule manuals; (c) trans-forming the second test file by means of a set of logical operations implemented by computing means to obtain a mask file; (d) testing the mask file and, if the test is negative, modifying the design rule manuals; and (e) repeating steps (a) to (d) until the test of step (d) is positive. | 12-08-2011 |
20110307844 | Model-Based Fill - Various aspects of this disclosure relate to increasing pattern density in a circuit layout design of a circuit layer so as to control the thickness of material in a manufactured integrated circuit. For example, a layer in circuit design may be divided into separate areas, and a target thickness range may be established for all of the tiles in the integrated circuit design. Each area may be analyzed to determine if it has a sufficient pattern density for a thickness estimation model to accurately estimate its expected material thickness upon manufacture. Each tile may be analyzed to determine if the expected thickness for that tile is within the target thickness range. | 12-15-2011 |
20110320986 | METHOD FOR DESIGNING OVERLAY TARGETS AND METHOD AND SYSTEM FOR MEASURING OVERLAY ERROR USING THE SAME - A method for designing an overlay target comprises selecting a plurality of overlay target pairs having different overlay errors or offsets, calculating a deviation of the simulated diffraction spectrum for each overlay target pair, selecting a plurality of sensitive overlay target pairs by taking the deviation of the simulated diffraction spectrum into consideration, selecting an objective overlay target pair from the sensitive overlay target pairs by taking the influence of the structural parameters to the simulated diffraction spectrum into consideration, and designing the overlay target pair based on the structural parameter of the objective overlay target pair. | 12-29-2011 |
20120005633 | CONSISTENCY CHECK IN DEVICE DESIGN AND MANUFACTURING - A method of forming a device is disclosed. The method includes providing at least one original artwork file having front end and back end information. The original artwork file includes an original artwork file format. A modified artwork file corresponding to the original artwork file is provided in a first modified artwork file format. The modified artwork file contains back end information. The method also includes checking to ensure that the original and modified artwork files are consistent. | 01-05-2012 |
20120017183 | System and Method for Creating a Focus-Exposure Model of a Lithography Process - A system and a method for creating a focus-exposure model of a lithography process are disclosed. The system and the method utilize calibration data along multiple dimensions of parameter variations, in particular within an exposure-defocus process window space. The system and the method provide a unified set of model parameter values that result in better accuracy and robustness of simulations at nominal process conditions, as well as the ability to predict lithographic performance at any point continuously throughout a complete process window area without a need for recalibration at different settings. With a smaller number of measurements required than the prior-art multiple-model calibration, the focus-exposure model provides more predictive and more robust model parameter values that can be used at any location in the process window. | 01-19-2012 |
20120023464 | AUTOMATIC IDENTIFICATION OF SYSTEMATIC REPEATING DEFECTS IN SEMICONDUCTOR PRODUCTION - A method includes capturing an image of the pattern using one or more scans across a surface of the partially completed wafer. The method includes processing information associated with the captured image of the pattern in a first format (e.g., pixel domain) into a second format, e.g., transform domain. The method includes determining defect information associated with the image of the pattern in the second format and processing the defect information (e.g., wafer identification, product identification, layer information, x-y die scanned) to identify at least one defect associated with a spatial location of a repeating pattern on the partially completed wafer provided by a reticle. The method includes identifying the reticle associated with the defect and a stepper associated with the reticle having the defect and ceasing operation of the stepper. The damaged reticle is replaced, and the process resumes using a replaced reticle. | 01-26-2012 |
20120047472 | DUMMY-METAL-LAYOUT EVALUATING DEVICE AND DUMMY-METAL-LAYOUT EVALUATING METHOD - A dummy-mesh-information creating unit separates a group of dummy metal blocks that are arranged in a pattern regularly staggered with respect to a direction of a wire object into meshes so that each mesh has the same layout of dummy metal blocks. An overlap determining unit determines whether a dummy metal block within a dummy mesh overlaps with the wire object. A dummy-information calculating unit calculates dummy information after any dummy metal block that is determined to be overlapped with the wire object is removed. An information integrating unit integrates the dummy information with information about the wire object, thereby generating a dummy-fill circuit layout. An evaluating unit evaluates whether the dummy-fill circuit layout satisfies the design criteria. | 02-23-2012 |
20120066651 | Technique for Repairing a Reflective Photo-Mask - During a calculation technique, a modification to a reflective photo-mask is calculated. In particular, using information associated with different types of analysis techniques a group of one or more potential defects in the reflective photo-mask is determined. Then, the modification to the reflective photo-mask is calculated based on at least a subset of the group of potential defects using an inverse optical calculation. In particular, during the inverse optical calculation, a cost function at an image plane in a model of the photolithographic process is used to determine the modification to the reflective photo-mask at an object plane in the model of the photolithographic process. | 03-15-2012 |
20120072874 | DISSECTION SPLITTING WITH OPTICAL PROXIMITY CORRECTION AND MASK RULE CHECK ENFORCEMENT - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC. | 03-22-2012 |
20120072875 | Composition Based Double-Patterning Mask Planning - Layout design data is analyzed to identify both potential geometric element cuts in the design and instances of an application of a separation directive. Each of the identified separation directive instances and the identified cuts are assigned an analysis value, such as a weight value. The separation directive instances and the identified cuts then are ordered in a single list according to their analysis values. Each item on the list is then analyzed, to determine if the item can be implemented in the layout design data without creating a conflict in complementary pattern sets for using in a double-patterning lithographic technique. If a list item (either separation directive instance or identified cut) cannot be implemented without creating a conflict in one of the complementary patterns, then it is discarded from the list. After each of the list items has been analyzed, the remaining items are implemented in the design layout data. | 03-22-2012 |
20120110521 | Split-Layer Design for Double Patterning Lithography - A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker. | 05-03-2012 |
20120124528 | METHOD AND DEVICE FOR INCREASING FIN DEVICE DENSITY FOR UNALIGNED FINS - A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. A plurality of elongate mandrels is defined in a plurality of active regions. Where adjacent active regions are partially-parallel and within a specified minimum spacing, connective elements are added to a portion of the space between the adjacent active regions to connect the mandrel ends from one active region to another active region. | 05-17-2012 |
20120137260 | Virtual Photo-Mask Critical-Dimension Measurement - A technique for reconstructing a mask pattern corresponding to a photo-mask using a target mask pattern (which excludes defects) and an image of at least a portion of the photo-mask is described. This image may be an optical inspection image of the photo-mask that is determined using inspection optics which includes an optical path, and the reconstructed mask pattern may include additional spatial frequencies than the image. Furthermore, the reconstructed mask pattern may be reconstructed based on a characteristic of the optical path (such as an optical bandwidth of the optical path) using a constrained inverse optical calculation in which there are a finite number of discrete feature widths allowed in the reconstructed mask pattern, and where a given feature has a constant feature width. Consequently, the features in the reconstructed mask pattern may each have the constant feature width, such as an average critical dimension of the reconstructed mask pattern. | 05-31-2012 |
20120137261 | METHOD AND APPARATUS FOR DETERMINING MASK LAYOUTS FOR A SPACER-IS-DIELECTRIC SELF-ALIGNED DOUBLE-PATTERNING PROCESS - Methods and apparatuses are described for determining mask layouts for printing a design intent on a wafer using a spacer-is-dielectric self-aligned double-patterning process. A system can determine whether a graph corresponding to a design intent is two-colorable. If the graph is not two-colorable, the system can merge one or more pairs of shapes in the design intent to obtain a modified design intent, so that a modified graph corresponding to the modified design intent is two-colorable. The system can then determine a two-coloring for the modified graph. Next, the system can place one or more core shapes in a mandrel mask layout which correspond to vertices in the modified graph that are associated with a selected color in the two-coloring. The system can then place one or more shapes in a trim mask layout for separating the shapes in the design intent that were merged. | 05-31-2012 |
20120144349 | HIGH PERFORMANCE DRC CHECKING ALGORITHM FOR DERIVED LAYER BASED RULES - Roughly described, a design rule data set includes rules on derived layers. The rules are checked by traversing the corners of physical shapes, and for each corner, populating a layout topology database with values gleaned from that corner location, including values involving derived layers. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations, including violations of design rules defined on derived layers. Violations are reported in real time during manual editing of the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, scanning in the direction of the edge orientations. Scans stop only at corner positions on physical layers, and populate the layout topology database with what information can be gleaned based on the current scan line, including information about derived layers. The scans need not reach corners simultaneously. | 06-07-2012 |
20120144350 | GATE MODELING FOR SEMICONDUCTOR FABRICATION PROCESS EFFECTS - In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates parametric variation factors that may occur in the photolithographic process. An adjusted width and adjusted length of the object is then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor using the adjusted width and adjusted length. | 06-07-2012 |
20120144351 | ANALYSIS OPTIMZER - A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer. | 06-07-2012 |
20120174045 | ACCEPTANCE DETERMINING METHOD OF BLANK FOR EUV MASK AND MANUFACTURING METHOD OF EUV MASK - According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective. | 07-05-2012 |
20120180006 | GENERATING CUT MASK FOR DOUBLE-PATTERNING PROCESS - Aspects of the invention include a computer-implemented method of designing a photomask. In one embodiment, the method comprises: simulating a first photomask patterning process using a first photomask design to create simulated contours; comparing the simulated contours to a desired design; identifying regions not common to the simulated contours and the desired design; creating desired target shapes for a second photomask patterning process subsequent to the first photomask patterning process based upon the identified regions; and providing the desired target shapes for forming of a second photomask design based upon the desired target shapes. | 07-12-2012 |
20120185807 | METHOD FOR IMPROVING ACCURACY OF PARASITICS EXTRACTION CONSIDERING SUB-WAVELENGTH LITHOGRAPHY EFFECTS - The present disclosure involves a method. The method includes decomposing a layout of a circuit into a plurality of patterns. The method includes generating a plurality of contours to represent the plurality of patterns after the patterns have been subjected to a manufacturing process. The method includes generating a plurality of polygons that approximate geometries of the contours, respectively. The method includes associating each of the polygons with a respective one of a plurality of pattern elements in a pattern library, wherein the pattern elements each include a shape that resembles the associated polygon and electrical parameters extracted from the shape. The method includes calculating electrical performance of the circuit based on the pattern elements associated with the polygons. | 07-19-2012 |
20120204134 | METHODS FOR FABRICATING AN ELECTRICALLY CORRECT INTEGRATED CIRCUIT - A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a logical design for the semiconductor device and comparing an element in the logical design to a library of element patterns. The library of element patterns is derived by identifying layout patterns having electrical properties that deviate from modeled properties; the library also includes a quantitative measure of deviation from the modeled properties. In response to the comparing and with consideration of the quantitative measure, a determination is made as to whether the element is acceptable in the logical design. A mask set is generated that implements the logical design using either the element or a modified element if the element is not acceptable, and the mask set is employed to implement the logical design in and on a semiconductor substrate. | 08-09-2012 |
20120210278 | SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR FORMING PHOTOMASKS WITH REDUCED LIKELIHOOD OF FEATURE COLLAPSE, AND PHOTOMASKS SO FORMED - At least one pattern of a photomask is identified that has a likelihood of causing collapse of a microelectronic device feature that is formed using the photomask, due to surface tension of a solution that is applied to the feature during manufacture of the microelectronic device. The patterns of the photomask are then modified to reduce the likelihood of the collapse. The photomask may be formed and the photomask may be used to manufacture microelectronic devices. Related methods, systems, devices and computer program products are described. | 08-16-2012 |
20120216155 | CHECKING METHOD FOR MASK DESIGN OF INTEGRATED CIRCUIT - A method for checking mask design of an integrated circuit, wherein the integrated circuit includes a plurality of functional elements arranged at different positions, the method includes generating implant layer data of each functional element of the integrated circuit according to characteristics of each functional element; generating mask design data of the integrated circuit according to circuit design of the integrated circuit; generating a block diagram of the integrated circuit according to the mask design data; determining a corresponding position of the functional element in the block diagram according to the implant layer data; and comparing the implant layer data of the functional element with the mask design data at the corresponding position. | 08-23-2012 |
20120216156 | Method of Pattern Selection for Source and Mask Optimization - The present invention relates to a method of selecting a subset of patterns from a design, to a method of performing source and mask optimization, and to a computer program product for performing the method of selecting a subset of patterns from a design. According to certain aspects, the present invention enables coverage of the full design while lowering the computation cost by intelligently selecting a subset of patterns from a design in which the design or a modification of the design is configured to be imaged onto a substrate via a lithographic process. The method of selecting the subset of patterns from a design includes identifying a set of patterns from the design related to the predefined representation of the design. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes a similar predefined representation of the design as the set of patterns. | 08-23-2012 |
20120227014 | METHOD AND APPARATUS FOR MINIMIZING OVERLAY ERRORS IN LITHOGRAPHY - The invention relates to a method for minimizing errors of a plurality of photolithographic masks, the plurality of photolithographic masks serving for successively processing a substrate, the method comprises determining a reference displacement vector field, the reference displacement vector field correlates displacement vectors of the errors of the plurality of photolithographic masks, determining for each of the photolithographic mask a difference displacement vector field as a difference between the reference displacement vector field and the displacement vectors of the errors of the respective photolithographic mask, and correcting the errors for each of the photolithographic masks using the respective difference displacement vector field. | 09-06-2012 |
20120227015 | PERTURBATIONAL TECHNIQUE FOR CO-OPTIMIZING DESIGN RULES AND ILLUMINATION CONDITIONS FOR LITHOGRAPHY PROCESS - A process of generating design rules, OPC rules and optimizing illumination source models for an integrated circuit layout, to form short lines, terminated lines and crossovers between adjacent parallel route tracks, may include the steps of generating a set of template structures which use a set of characteristic design rules, and performing a plurality of source mask optimization (SMO) operations on the set of template structures with different values for the design rules in each SMO operation. In a first embodiment, the SMO operations are run using a predetermined set of values for each of the design rules, spanning a desired range of design rule values. In a second embodiment, the SMO operations are performed in a conditional iterative process in which values of the design rules are adjusted after each iteration based on results of the iteration. | 09-06-2012 |
20120227016 | CIRCUIT SIMULATION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT - The present disclosure provides a method of performing circuit simulation of electrical characteristics of a transistor formed on a semiconductor substrate using calculators, each of which includes a memory. A first calculator receives mask layout data and distance-dependent data indicating a distance from the target transistor. Then, a second calculator calculates an area ratio of a layout pattern of a predetermined mask from the received mask layout data, and calculates a parameter α based on the area ratio and the distance-dependent data. Then, the second calculator B calculates a change ΔP in the electrical characteristics of the transistor based on the parameter α. This configuration provides highly accurate circuit simulation of the electrical characteristics of the transistor, which depend on variations in temperature distribution of the semiconductor substrate during heat treatment due to the mask layout pattern around the transistor. | 09-06-2012 |
20120246601 | PATTERN CORRECTING METHOD, MASK FORMING METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area. | 09-27-2012 |
20120254811 | SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT RC EXTRACTION NETLIST - A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium. | 10-04-2012 |
20120254812 | SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN - A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles. | 10-04-2012 |
20120260222 | MASK FABRICATION SUPPORTING METHOD, MASK BLANK PROVIDING METHOD, AND MASK BLANK DEALING SYSTEM - A mask blank is provided by forming a plurality of films, including at least a thin film to be a transfer pattern, on a board. At the time of patterning a resist film of the mask blank according to pattern data, film information to check with a pattern is obtained for each of a plurality of the films. | 10-11-2012 |
20120266110 | DUAL-PATTERN COLORING TECHNIQUE FOR MASK DESIGN - A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment. | 10-18-2012 |
20120266111 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 10-18-2012 |
20120266112 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 10-18-2012 |
20120266113 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 10-18-2012 |
20120266114 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 10-18-2012 |
20120278768 | SYSTEMS AND METHODS FOR STOCHASTIC MODELS OF MASK PROCESS VARIABILITY - Systems and methods are disclosed for a stochastic model of mask process variability of a photolithography process, such as for semiconductor manufacturing. In one embodiment, a stochastic error model may be based on a probability distribution of mask process error. The stochastic error model may generate a plurality of mask layouts having stochastic errors, such as random and non-uniform variations of contacts. In other embodiments, the stochastic model may be applied to critical dimension uniformity (CDU) optimization or design rule (DR) sophistication. | 11-01-2012 |
20120278769 | Gradient-Based Search Mechanism for Optimizing Photolithograph Masks - A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of α | 11-01-2012 |
20120290990 | Pattern Measuring Condition Setting Device - When setting a measurement position, on the basis of a defect coordinate, on a sample, which is arranged with a complex pattern or a plurality of patterns and which has a pattern in which the influence of the optical proximity effect needs to be evaluated, the measurement position is set so as to improve work efficiency. Provided is a device for setting a first measurement position and a second measurement position, wherein: a reference line comprising a plurality of line segments is superimposed on a two-dimensional region set by a pattern layout data; the first measurement position is set on the inside of a contour which indicates a pattern in which a defect coordinate on the layout data exists, and between the intersecting points of the reference line and said contour; and a second measurement position is set outside of said contour, and either on said contour and another portion of said contour or between the intersecting points of said contour and another portion of said contour. | 11-15-2012 |
20120297349 | METHOD OF DESIGNING A SEMICONDUCTOR DEVICE - In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data. | 11-22-2012 |
20120311511 | MASK INSPECTION METHOD, MASK PRODUCTION METHOD, SEMICONDUCTOR DEVICE PRODUCTION METHOD, AND MASK INSPECTION DEVICE - A mask inspection method according to the embodiments, original data corresponding to a semiconductor integrated circuit pattern to be formed on a substrate is created. After that, original production simulation which mocks an original production process is performed on the original data to derive information relating to an original pattern shape in the case of forming an original pattern corresponding to the original data on an original. After that, whether or not the information relating to an original pattern shape satisfies a predetermined value decided based on the original production process is determined. | 12-06-2012 |
20120317523 | Reducing Through Process Delay Variation in Metal Wires - A mechanism is provided for reducing through process delay variation in metal wires by layout retargeting. The mechanism performs initial retargeting, decomposition, and resolution enhancement techniques. For example, the mechanism may perform optical proximity correction. The mechanism then performs lithographic simulation and optical rules checking. The mechanism provides retargeting rules developed based on coupling lithography simulation and resistance/capacitance (RC) extraction. The mechanism performs RC extraction to capture non-linear dependency of RC on design shape dimensions. If the electrical properties in the lithographic simulation are within predefined specifications, the mechanism accepts the retargeting rules; however, if the electrical properties from RC extraction are outside the predefined specifications, the mechanism modifies the retargeting rules and repeats resolution enhancement techniques. | 12-13-2012 |
20120331425 | MANUFACTURABILITY ENHANCEMENTS FOR GATE PATTERNING PROCESS USING POLYSILICON SUB LAYER - A method for designing a mask set including at least one mask includes the implementation of at least one design rule from a set of design rules. The design rules include rules relating to allowable spacing between adjacent features, overlap of features defined by different masks in the mask set, and other characteristics of the mask set. | 12-27-2012 |
20120331426 | CELL ARCHITECTURE AND METHOD - A method includes selecting a cell stored in a non-transient computer readable storage medium, arranging a plurality of the cells on a model of a semiconductor device, and creating a mask for the semiconductor device based on the model of the semiconductor device. The cell is designed according to a design rule in which a first power-supply-connection via satisfies a criterion from the group consisting of: i) the first power-supply-connection via is spaced apart from a second power-supply-connection via by a distance that is greater than a threshold distance such that the cell can be fabricated by a single-photolithography single-etch process, or ii) the first power-supply-connection via is coupled to first and second substantially parallel conductive lines that extend along directly adjacent tracks. | 12-27-2012 |
20120331427 | IN-SITU SCANNER EXPOSURE MONITOR - A method for predicting pattern critical dimensions in a lithographic exposure process includes defining relationships between critical dimension, defocus, and dose. The method also includes performing at least one exposure run in creating a pattern on a wafer. The method also includes creating a dose map. The method also includes creating a defocus map. The method also includes predicting pattern critical dimensions based on the relationships, the dose map, and the defocus map. | 12-27-2012 |
20120331428 | METHOD FOR DESIGNING OPTICAL LITHOGRAPHY MASKS FOR DIRECTED SELF-ASSEMBLY - A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate. | 12-27-2012 |
20130007674 | RESOLVING DOUBLE PATTERNING CONFLICTS - A mechanism is provided for resolving patterning conflicts. The mechanism performs decomposition with stitches at all candidate locations to find the solution with the minimum number of conflicts. The mechanism then defines interactions between a layout of a first mask and a layout of a second mask through design rules, as well as interactions of mask | 01-03-2013 |
20130019211 | Optimizing lithographic mask for manufacturability in efficient mannerAANM Sakamoto; MasaharuAACI YamatoAACO JPAAGP Sakamoto; Masaharu Yamato JPAANM Rosenbluth; Alan E.AACI Yorktown HeightsAAST NYAACO USAAGP Rosenbluth; Alan E. Yorktown Heights NY USAANM Szeto-Millstone; Marc AlanAACI SeattleAAST WAAACO USAAGP Szeto-Millstone; Marc Alan Seattle WA USAANM Inoue; TadanobuAACI YamatoAACO JPAAGP Inoue; Tadanobu Yamato JPAANM Tian; KehanAACI Hopewell JunctionAAST NYAACO USAAGP Tian; Kehan Hopewell Junction NY USAANM Waechter; AndreasAACI Yorktown HeightsAAST NYAACO USAAGP Waechter; Andreas Yorktown Heights NY USAANM Lee; JonathanAACI Yorktown HeightsAAST NYAACO USAAGP Lee; Jonathan Yorktown Heights NY USAANM Melville; David OsmondAACI Yorktown HeightsAAST NYAACO USAAGP Melville; David Osmond Yorktown Heights NY US - Mask layout data of a lithographic mask includes polygons that each include horizontal and vertical edges. Each of a number of target edge pairs is defined by two edges of one or more of the polygons. A search box having a boundary coincident with a given edge of the edges of the polygons is specified. Whether the search box includes at least one edge of the edges of the polygons in addition to the given edge is determined. Where the search box includes at least one edge, at least one of the target edge pairs is specified as including the given edge and one of the at least one edge. For each target edge pair that has been specified, a manufacturability penalty value is determined. A dynamic manufacturability constraint table and a non-zero multiplier table are maintained. | 01-17-2013 |
20130019212 | Method And Apparatus For The Position Determination Of Structures On A Mask For Microlithography - A method and an apparatus for determining the position of a structure on a mask for microlithography, in which the position is determined by comparing an aerial image, measured by a recording device, of a portion of the mask with an aerial image determined by simulation. The position determination includes carrying out a plurality of such comparisons which differ from one another with regard to the input parameters of the simulation. | 01-17-2013 |
20130024822 | DOUBLE PATTERNING METHODOLOGY - Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process. | 01-24-2013 |
20130024823 | METHOD AND APPARATUS FOR DESIGNING PATTERNING SYSTEM BASED ON PATTERNING FIDELITY - A method which directly incorporates patterning fidelity into the design of a patterning system is provided. A production result of a target pattern is simulated according to a set of design parameters to obtain a simulated pattern. The target pattern is compared with the simulated pattern to obtain a patterning fidelity, and the values of the set of design parameters of the patterning system are adjusted according to a target patterning fidelity to optimize the values of the set of design parameters of the patterning system. | 01-24-2013 |
20130031518 | Hybrid Hotspot Detection - Aspects of the invention relate to hybrid hotspot detection techniques. The hybrid hotspot detection techniques combine machine learning classification, pattern matching and process simulation. A machine learning model, along with false hotspots and false non-hotspots for pattern matching, is determined based on training patterns. The determined machine learning model is then used to classify patterns in a layout design into three categories: preliminary hotspots, preliminary non-hotspots and potential hotspots. Pattern matching is then employed to identify false positives and false negatives in the first two categories. Process simulation is employed to identify boundary hotspots in the last category. | 01-31-2013 |
20130031519 | YIELD ENHANCEMENT BY MULTIPLICATE-LAYER-HANDLING OPTICAL CORRECTION - Potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region. Multiplicate layers are generated for each design shape in that lithographic level in each marked region. Each multiplicate layer includes a different type of variant for each design shape in the lithographic level. The different types of variants correspond to different design environments. Lithographic simulation is performed with each type of variants under the constraint of long range effects, such as pattern density, provided by adjacent shapes in the lithographic level. In each marked region, the results of lithographic simulations are evaluated to determine an optimal type among the variants. The optimal type is retained for the lithographic level in each marked region, thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization. | 01-31-2013 |
20130055172 | ORIGINAL PLATE EVALUATION METHOD, COMPUTER READABLE STORAGE MEDIUM, AND ORIGINAL PLATE MANUFACTURING METHOD - According to one embodiment, an original plate evaluation method is disclosed. The original plate includes a substrate and N patterns differing from one another in shape. The method includes selecting N1 patterns from the N patterns based on first criterion, obtaining measured values for the N1 patterns, performing a decision whether the obtained measured values satisfy first specification value, selecting N2 patterns from the N patterns based on second criterion, predicting shapes of transfer patterns corresponding to N2 patterns, performing a decision whether the predicted shapes satisfy second specification value, and evaluating the plate based on the decision. | 02-28-2013 |
20130061183 | Multiple Patterning Layout Decomposition for Ease of Conflict Removal - A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction, The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features, The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors. | 03-07-2013 |
20130061184 | AUTOMATED LITHOGRAPHIC HOT SPOT DETECTION EMPLOYING UNSUPERVISED TOPOLOGICAL IMAGE CATEGORIZATION - A method for proactively preventing lithographic problems is disclosed, which employs information generated from layout patterns including hot spots in a first technology node to identify hot spots in a second technology node employing a scaled down minimum dimension. In this proactive approach, problematic patterns or complex product geometries are identified in a chip design layout of the second technology node based on detection, in the chip design layout, of topological features that are similar to topological features of known hot spots in the first technology node. The identified patterns are potential hot spots in the chip design layout for the second technology node. Known hot spots in layout patterns in the first technology node are topologically categorized to provide a database for performing the fault detection and diagnosis on the chip design layout. | 03-07-2013 |
20130074016 | METHODOLOGY FOR PERFORMING POST LAYER GENERATION CHECK - There is provided a method comprising receiving data corresponding to a layout design for a plurality of input mask layers and generating a layout design for at least one generated mask layer. The relationship between a first geometric element in a first layout pattern comprising one or more of the generated mask layers and a second geometric element in a second layout pattern is then determined and verified to check if they comply with predetermined rules. If the relationship does not conform with the predetermined rules the design of at least one of the generated mask layers associated with the first or second layout pattern is modified. | 03-21-2013 |
20130074017 | Illumination-Source Shape Definition in Optical Lithography - A method and system are described for determining lithographic processing conditions for a lithographic process. After obtaining input, a first optimization is made for illumination source and mask design under conditions of allowing non-rectangular sub-resolution assist features. Thereafter, mask design is optimized in one or more further optimizations for which only rectangular sub-resolution assist features are allowed. The latter results in good lithographic processing while limiting the complexity of the mask design. | 03-21-2013 |
20130080980 | METHOD FOR CHECKING AND FIXING DOUBLE-PATTERNING LAYOUT - A method including receiving layout data representing the plurality of patterns, the layout data including a plurality of layers and identifying spaces between adjacent patterns in at least one layer of the plurality of layers which violate a G | 03-28-2013 |
20130111418 | METHOD, SYSTEM AND SOFTWARE FOR ACCESSING DESIGN RULES AND LIBRARY OF DESIGN FEATURES WHILE DESIGNING SEMICONDUCTOR DEVICE LAYOUT | 05-02-2013 |
20130125070 | OPC Checking and Classification - A technique for selecting a subset of determined defects in a mask pattern is described. In this technique, defects in the mask pattern may be determined based on differences between a pattern produced at an image plane in a photolithographic process, when the mask pattern, illuminated by an associated source pattern, is at an object plane in the photolithographic process, and a target pattern that excludes the defects. These defects may be classified by associating them with types of geometric features in the target pattern and/or the mask pattern. Moreover, the subset may be selected by filtering the defects associated with the types of geometric features. For example, the subset may defects corresponding to the differences that exceed filtering values that are associated with the types of geometric features. | 05-16-2013 |
20130139117 | Model-Based Fill - Various aspects of this disclosure relate to increasing pattern density in a circuit layout design of a circuit layer so as to control the thickness of material in a manufactured integrated circuit. For example, a layer in circuit design may be divided into separate areas, and a target thickness range may be established for all of the tiles in the integrated circuit design. Each area may be analyzed to determine if it has a sufficient pattern density for a thickness estimation model to accurately estimate its expected material thickness upon manufacture. Each tile may be analyzed to determine if the expected thickness for that tile is within the target thickness range. | 05-30-2013 |
20130152026 | SPATIAL MAP OF MASK-PATTERN DEFECTS - A technique for providing information about defects in a mask pattern is described. In this technique, defects in the mask pattern may be determined based on differences between a calculated pattern produced at an image plane in the photolithographic process, when the mask pattern, illuminated by an associated source pattern, is at an object plane in the photolithographic process, and a target pattern that excludes the defects. Then the defect information may be provided to the user, such as a spatial map of the determined defects, where the spatial map is associated with at least the portion of the mask pattern. | 06-13-2013 |
20130152027 | METHOD FOR COMPENSATING FOR VARIATIONS IN STRUCTURES OF AN INTEGRATED CIRCUIT - A method of for compensating for variations in structures of an integrated circuit. The method includes (a) selecting a mask design shape and selecting a region of the mask design shape; (b) applying a model-based optical proximity correction to all of the mask design shape; and after (b), (c) applying a rules-based optical proximity correction to the selected region of the mask design shape. | 06-13-2013 |
20130159943 | MACHINE LEARNING APPROACH TO CORRECT LITHOGRAPHIC HOT-SPOTS - A method, system, and computer program product for machine learning approach for detecting and correcting lithographic hot-spots in an integrated circuit (IC) design are provided in the illustrative embodiments. A layout corresponding to the IC design is received at a machine learning model (ML model). At the ML model using a hardware component, a set of input objects is identified corresponding to a target shape in the layout. A retargeting value is predicted for the target shape using the set of input objects, such that applying the retargeting value to the target shape in the layout causes the target shape to be modified into a modified target shape, wherein printing the modified target shape instead of the target shape eliminates a lithographic hot-spot that would otherwise occur from printing the target shape in a printed circuit corresponding to the IC design. | 06-20-2013 |
20130159944 | FLARE MAP CALCULATING METHOD AND RECORDING MEDIUM - A flare map calculating method of an embodiment calculates an optical image intensity distribution in each division region set in a pattern region. Furthermore, an average value of the optical image intensity distribution is calculated in each division region. A pattern or plural patterns, which has a pattern density corresponding to the average value, is calculated as a corresponding density pattern in each division region. Furthermore, a density map, which represents a pattern density distribution within the pattern region, is generated based on the corresponding density pattern, and a flare map representing a flare intensity distribution within the pattern region is calculated by convolution integral of the density map and a point spread function. | 06-20-2013 |
20130159945 | LAYOUT DECOMPOSITION FOR DOUBLE PATTERNING LITHOGRAPHY - The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs. | 06-20-2013 |
20130174102 | INTELLIGENT DEFECT DIAGNOSIS METHOD - An intelligent defect diagnosis method for manufacturing fab is provided. The intelligent defect diagnosis method comprises: receiving pluralities of defect data, design layouts and fabrication data; analyzing the defect data, design layouts, and the fabrication data by a defect analysis system, wherein the analyzing step further contains the sub-steps: segmenting and grouping the design layouts into pluralities of multi-pattern group cells to construct LPG cell based pattern groups; introducing the defect data; segmenting defect image into pluralities of defect and pattern contours; mapping the defect data to each multi-pattern group cell to form the LPG based defect composite pattern group; performing coordinate conversion and pattern match between image contour and design layout for coordinate correction; fulfilling CAA with defect contour, pattern contour and design layout, and obtaining corresponding defect yield; classifying the defect type of defect data through defect image classification analysis. | 07-04-2013 |
20130191792 | Sub-Resolution Assist Feature Repair - After layout design data has been modified using a resolution enhancement process, a repair flow is initiated. This repair flow includes checking a layout design altered by a resolution enhancement process for errors. A repair process is performed to correct detected sub-resolution assist feature errors. The repair process may employ a rule-based sub-resolution assist feature technique, a model-based sub-resolution assist feature technique, an inverse lithography-based sub-resolution assist feature technique, or any combination thereof. | 07-25-2013 |
20130191793 | DUAL-PATTERN COLORING TECHNIQUE FOR MASK DESIGN - A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment. | 07-25-2013 |
20130205263 | SUBSTRATE-TOPOGRAPHY-AWARE LITHOGRAPHY MODELING - Described herein is a method for simulating an image formed within a resist layer on a substrate resulting from an incident radiation, the substrate having a first feature and a second feature underlying the resist layer, the method comprising: simulating a first partial image using interaction of the incident radiation and the first feature without using interaction of the incident radiation and the second feature; simulating a second partial image using the interaction of the incident radiation and of the second feature without using the interaction of the incident radiation and the first feature; computing the image formed within the resist layer from the first partial image, and the second partial image; wherein the interaction of the incident radiation and the first feature is different from the interaction of the incident radiation and the second feature. | 08-08-2013 |
20130212543 | LENS HEATING AWARE SOURCE MASK OPTIMIZATION FOR ADVANCED LITHOGRAPHY - A computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus comprising an illumination source and projection optics, the method including computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, at least some of the design variables being characteristics of the illumination source and the design layout, the computing of the multi-variable cost function accounting for lens heating effects; and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied. | 08-15-2013 |
20130219347 | METHODS FOR DECOMPOSING CIRCUIT DESIGN LAYOUTS AND FOR FABRICATING SEMICONDUCTOR DEVICES USING DECOMPOSED PATTERNS - Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate. | 08-22-2013 |
20130219348 | METHOD FOR PROCESS WINDOW OPTIMIZED OPTICAL PROXIMITY CORRECTION - One embodiment of a method for process window optimized optical proximity correction includes applying optical proximity corrections to a design layout, simulating a lithography process using the post-OPC layout and models of the lithography process at a plurality of process conditions to produce a plurality of simulated resist images. A weighted average error in the critical dimension or other contour metric for each edge segment of each feature in the design layout is determined, wherein the weighted average error is an offset between the contour metric at each process condition and the contour metric at nominal condition averaged over the plurality of process conditions. A retarget value for the contour metric for each edge segment is determined using the weighted average error and applied to the design layout prior to applying further optical proximity corrections. | 08-22-2013 |
20130232453 | NON-DIRECTIONAL DITHERING METHODS - A method of data preparation in lithography processes is described. The method includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, converting the IC layout design GDS grid to a first exposure grid, applying a non-directional dither technique to the first exposure, coincident with applying dithering to the first expose grid, applying a grid shift to the first exposure grid to generate a grid-shifted exposure grid and applying a dither to the grid-shifted exposure grid, and adding the first exposure grid (after receiving dithering) to the grid-shifted exposure grid (after receiving dithering) to generate a second exposure grid. | 09-05-2013 |
20130239070 | RC EXTRACTION FOR SINGLE PATTERNING SPACER TECHNIQUE - A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns. | 09-12-2013 |
20130263061 | Global Landmark Method For Critical Dimension Uniformity Reconstruction - Data associated with a substrate can be processed by measuring a property of at least a first type of specific features and a second type of specific features on a substrate. The first type of specific features is measured at a first plurality of locations on the substrate to generate a first group of measured values, and the second type of specific features is measured at a second plurality of locations on the substrate to generate a second group of measured values, in which the first and second groups of measured values are influenced by critical dimension variations of the substrate. A combined measurement function is defined based on combining the at least first and second groups of measured values. At least one group of measured values is transformed prior to combining with another group or other groups of measured values, in which the transformation is defined by a group of coefficients. Variations in the critical dimension across the substrate are determined based on the combined measurement function and a predetermined relationship between the measured values and the critical dimension. | 10-03-2013 |
20130268901 | Structure and Method for E-Beam Writing - The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced. | 10-10-2013 |
20130283216 | METHOD AND SYSTEM FOR CRITICAL DIMENSION UNIFORMITY USING CHARGED PARTICLE BEAM LITHOGRAPHY - A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized. | 10-24-2013 |
20130290912 | METHOD AND APPARATUS FOR MONITORING MASK PROCESS IMPACT ON LITHOGRAPHY PERFORMANCE - The present disclosure is directed generally to a method and apparatus for monitoring mask process impact on lithography performance. A method including receiving a physical wafer pattern according to a mask, extracting a mask contour from the mask, and extracting a deconvolution pattern based on the mask contour. A lithography process is simulated to create a virtual wafer pattern based on the deconvolution pattern. The virtual wafer pattern is then compared to the physical wafer pattern. | 10-31-2013 |
20130298088 | System and Method for Combined Intraoverlay and Defect Inspection - A method and system for measuring layer overlay and for inspecting a mask for defects unrelated to overlay utilizing a singe comprehensive tool is disclosed. An exemplary method includes receiving a mask design database that corresponds to a mask and has a die area with a mask database feature. A mask image of the mask is received, and a comprehensive inspection system compares the mask image to the mask design database in order to detect mask defects that are not related to layer alignment. The system produces mask defect information corresponding to the mask defects. The comprehensive inspection system also compares the mask image to the mask design database to determine a database-to-mask offset. From the database-to-mask offset, a mask overlay characteristic is determined. | 11-07-2013 |
20130298089 | METHOD FOR INCREASING THE ROBUSTNESS OF A DOUBLE PATTERNING ROUTER USED TO MANUFACTURE INTEGRATED CIRCUIT DEVICES - A method for increasing the robustness of a double patterning router used in the manufacture of integrated circuit devices that includes providing a set of original color rules defining an original color rule space, providing a set of integrated circuit designs defining a design space, providing a router processing engine, perturbing the original color rules to define a perturbed color rule space, applying the perturbed color rule space and the design space to the router processing engine to expose double pattern routing odd cycle decomposition errors, and feeding back the exposed decomposition errors to enhance router processing engine development by reconfiguring the router processing engine in accordance with the exposed decomposition errors. | 11-07-2013 |
20130305194 | Validation of Integrated Circuit Designs Built With Encrypted Silicon IP Blocks - A method and system for validating integrated circuit designs that are built with encrypted silicon IP blocks decrypts the encrypted silicon IP blocks in the integrated circuit designs with the keys from IP providers. After decryption, various validation checks on the integrated circuit designs are done, such as design rule check (DRC), layout versus schematic (LVS) check, parasitic resistor capacitor (RC) extraction, circuit simulation, signal electro migration (EM) and voltage drop check, signal integrity (SI) check and static timing check, etc. After validation, any confidential data from the checking results related to the encrypted silicon IP blocks are themselves encrypted to protect the proprietary silicon IP blocks. The method and system work with silicon IP encryption technology to establish a low cost silicon IP usage and verification platform, and to enable a more cost efficient silicon IP business model. | 11-14-2013 |
20130305195 | ANALYSIS OPTIMIZER - A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer. | 11-14-2013 |
20130326434 | INTEGRATED CIRCUIT DESIGN METHOD WITH DYNAMIC TARGET POINT - The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a pattern, assigning target points to segments of the pattern, and producing first a simulated contour of the pattern based on the assigned target points. The method further includes reassigning the target points to the segments of the pattern based on the first simulated contour of the pattern; producing a second simulated contour of the pattern based on the reassigned target points, and after producing the second simulated contour of the pattern, producing a modified IC design layout. | 12-05-2013 |
20130326435 | Distance Metric For Accurate Lithographic Hotspot Classification Using Radial and Angular Functions - An dual function distance metric for pattern matching based hotspot clustering is described. The dual function distance metric can handle patterns containing multiple polygons, is easy to compute, and is tolerant of small variations or shifts of the shapes. Compared with an XOR distance metric pattern clustering, the dual function distance metric can achieve up to 37.5% accuracy improvement with 2×-4× computational cost in the context of cluster analysis. The dual function distance metric is reliable and accurate for characterizing clips (e.g. hotspots), thereby making it desirable for industry applications. | 12-05-2013 |
20130326436 | METHOD FOR CHECKING DIE SEAL RING ON LAYOUT AND COMPUTER SYSTEM - The invention is directed to a method for checking a die seal ring on a layout. The method comprises steps of receiving a digital database of a layout corresponding to at least a device with a text information corresponding to the layout. Tape-out information corresponding to the layout is received. A checking process is performed according to the digital database of the layout and the tape-out information and, meanwhile, a mask design procedure for designing a mask pattern corresponding to the layout is performed by using the digital database of the layout, the text information and the tape-out information. A result of the checking process is recorded in an inspection table corresponding to the layout. | 12-05-2013 |
20130339910 | IN-SITU SCANNER EXPOSURE MONITOR - A method for predicting pattern critical dimensions in a lithographic exposure process includes defining relationships between critical dimension, defocus, and dose. The method also includes performing at least one exposure run in creating a pattern on a wafer. The method also includes creating a dose map. The method also includes creating a defocus map. The method also includes predicting pattern critical dimensions based on the relationships, the dose map, and the defocus map. | 12-19-2013 |
20140007024 | Pattern Recognition For Integrated Circuit Design | 01-02-2014 |
20140013286 | METHOD FOR MANUFACTURING A MASK - A target pattern and a mask pattern are provided. The target pattern is segmented into a plurality of segments. Each segment includes at least one evaluation point. A first contour of a structure based on the mask pattern is simulated. A distortion between the first contour and the target pattern is evaluated at the evaluation point. At least one of the plurality of segments having a distortion exceeding a threshold value is identified. The identified segment is dissected into at least two sub-segments. | 01-09-2014 |
20140026106 | SYSTEMS AND METHODS FOR STOCHASTIC MODELS OF MASK PROCESS VARIABILITY - Systems and methods are disclosed for a stochastic model of mask process variability of a photolithography process, such as for semiconductor manufacturing. In one embodiment, a stochastic error model may be based on a probability distribution of mask process error. The stochastic error model may generate a plurality of mask layouts having stochastic errors, such as random and non-uniform variations of contacts. In other embodiments, the stochastic model may be applied to critical dimension uniformity (CDU) optimization or design rule (DR) sophistication. | 01-23-2014 |
20140040836 | GRADED DUMMY INSERTION - Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example. | 02-06-2014 |
20140040837 | METHOD OF OPTICAL PROXIMITY CORRECTION ACCORDING TO COMPLEXITY OF MASK PATTERN - A method of optical proximity correction (OPC) includes the following steps. At first, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into at least a first region and at least a second region. Then, several iterations of OPC calculations are performed to the layout pattern, and a total number of OPC calculations performed in the first region is substantially larger than a total number of OPC calculations performed in the second region. Afterwards, a corrected layout pattern is outputted through the computer system onto a mask. | 02-06-2014 |
20140047396 | P AND N REGION DIFFERENTIATION FOR IMAGE-TO-CAD ALIGNMENT - In one embodiment, a method for aligning an image of a semiconductor device with a bitmap representation thereof includes receiving diffusion layer information of at least a portion of the semiconductor device, receiving implant layer information of the at least a portion of the semiconductor device, deriving distinct p- and n-doped region information from the received diffusion and implant layer information, generating the bitmap representation, including a differentiation between the distinct p- and n-doped regions, and performing an alignment operation of the image of the semiconductor device with generated bitmap representation. | 02-13-2014 |
20140053117 | TECHNIQUES FOR PHASE TUNING FOR PROCESS OPTIMIZATION - Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning. | 02-20-2014 |
20140053118 | COMPRESSION METHOD AND SYSTEM FOR USE WITH MULTI-PATTERNING - A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data. | 02-20-2014 |
20140059502 | PATTERN DATA GENERATION METHOD, PATTERN VERIFICATION METHOD, AND OPTICAL IMAGE CALCULATION METHOD - According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected. | 02-27-2014 |
20140068528 | BALANCING MASK LOADING - Among other things, one or more techniques for balancing mask loading are provided herein. In some embodiments, a dummy mask assignment is assigned to a dummy within a mask layout based on an area of a polygon within the mask layout. In some embodiments, the dummy mask comprising the dummy mask assignment is inserted in the mask layout. In some embodiments, a window is created such that dummies within the window receive dummy mask assignments. In some embodiments, a halo is created such that the area of the polygon is determined based on the halo. Additionally, in some examples, the window and halo are shifted around the mask layout. In this manner, balanced mask loading is provided, thus enhancing a yield associated with the mask layout, for example. | 03-06-2014 |
20140075397 | PITCH-AWARE MULTI-PATTERNING LITHOGRAPHY - A method, system, and computer program product for improving printability of a design of an integrated circuit (IC) using pitch-aware coloring for multi-patterning lithography (MPL) are provided in the illustrative embodiments. A first shape is identified in a layout of the IC corresponding to the design as being apart by a first distance from a second shape. The first distance is a forbidden distance and at least equal to a minimum distance requirement of a lithography system. A determination is made that the first shape and the second shape are colored using a first color. The first shape is changed to a second color, such that even though the first distance is at least equal to the minimum distance requirement of the lithography system, the first and the second shapes are placed on different masks to print the design, thereby improving the printability of the design. | 03-13-2014 |
20140089868 | AUTOMATED REPAIR METHOD AND SYSTEM FOR DOUBLE PATTERNING CONFLICTS - A method of performing double patterning (DPT) conflict repairs is described. In this method, even cycles adjacent to odd cycles in a layout can be identified (also called adjacent even/odd cycles herein). The identifying can include forming graph constructs of the layout. Route guidances for break-link operations and split-node operations can be prioritized for the adjacent even/odd cycles. A list including the route guidances for the break-link operations and the split-node operations can be generated. The list can be ordered based on the prioritizing. | 03-27-2014 |
20140089869 | LAYOUT METHOD OF SEMICONDUCTOR CIRCUIT STRUCTURE - A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns. | 03-27-2014 |
20140101622 | PERTURBATIONAL TECHNIQUE FOR CO-OPTIMIZING DESIGN RULES AND ILLUMINATION CONDITIONS FOR LITHOGRAPHY PROCESS - A process of generating design rules, OPC rules and optimizing illumination source models for an integrated circuit layout, to form short lines, terminated lines and crossovers between adjacent parallel route tracks, may include the steps of generating a set of template structures which use a set of characteristic design rules, and performing a plurality of source mask optimization (SMO) operations on the set of template structures with different values for the design rules in each SMO operation. In a first embodiment, the SMO operations are run using a predetermined set of values for each of the design rules, spanning a desired range of design rule values. In a second embodiment, the SMO operations are performed in a conditional iterative process in which values of the design rules are adjusted after each iteration based on results of the iteration. | 04-10-2014 |
20140101623 | METHOD OF MERGING COLOR SETS OF LAYOUT - A method includes determining one or more potential merges corresponding to a color set A | 04-10-2014 |
20140123082 | COMPENSATION FOR PATTERNING DEVICE DEFORMATION - A method for improving a lithographic process for imaging a design layout onto a substrate using a lithographic projection apparatus comprising a patterning device, wherein the patterning device deforms from a first state to a second state, the method comprising: determining a deformation of the patterning device from the first state to the second state; determining a compensatory design layout from the design layout and the deformation; wherein the compensatory design layout is such that when the compensatory design layout is generated on the patterning device in the first state, the deformation of the patterning device deforms the compensatory design layout to the design layout. | 05-01-2014 |
20140143739 | POLYGON RECOVERY FOR VLSI MASK CORRECTION - Embodiments relate to polygon recovery from a +1/−1 description of a plurality of polygons of a very large scale integrated (VLSI) mask for production of a VLSI semiconductor device. An aspect includes receiving a set of data comprising the +1/−1 description of the plurality of polygons of the VLSI mask, the +1/−1 description comprising a plurality of corners. Another aspect includes determining a 4-directional data structure, a Mm value comprising a first limit value, and a Mp value comprising a second limit value for each of the plurality of corners. Another aspect includes recovering the plurality of polygons from the set of data by assigning each of the plurality of corners to a single polygon based on the 4-directional data structure, the Mm value, and the Mp value of each of the plurality of corners, and determining an order of the respective corners of each polygon. | 05-22-2014 |
20140143740 | POLYGON RECOVERY FOR VLSI MASK CORRECTION - A computer-implemented method for polygon recovery from a +1/−1 description of a plurality of polygons includes receiving, by a computer, a set of data comprising the +1/−1 description of the plurality of polygons, the +1/−1 description comprising a plurality of corners; determining a 4-directional data structure, a Mm value, and a Mp value for each of the plurality of corners; and recovering the polygons by assigning each of the plurality of corners to one of the plurality of polygons based on the 4-directional data structure, the Mm value, and the Mp value for each of the plurality of corners, and, for each of the plurality of polygons, determining an order of the polygon's respective corners. | 05-22-2014 |
20140149952 | TRENCH SILICIDE MASK GENERATION USING DESIGNATED TRENCH TRANSFER AND TRENCH BLOCK REGIONS - A method for designating TT and TB regions utilizing designated TS regions, without fully generating TT and TB features, and thereafter fabricating TS regions utilizing the designated TT and TB regions, is disclosed. Embodiments include: determining a TS having a placement and shape, the TS shape having a first horizontal dimension and a first vertical dimension; determining an active region including the TS; determining an extended TS including the TS and an extension portion in the horizontal and vertical directions, adjacent each edge of the TS; and determining a TB region based on the active region and the extended TS. | 05-29-2014 |
20140157213 | METHOD OF GENERATING A SET OF DEFECT CANDIDATES FOR WAFER - A method of generating a set of defect candidates for a wafer includes generating a filtration area according to a graph operation of one or more of a plurality of layout areas. The wafer includes at least one die manufactured according to a mask, and the mask is prepared by combining the plurality of layout areas. The method further includes generating the set of defect candidates by omitting a subset of initial defect candidates having positions within the filtration area. | 06-05-2014 |
20140173533 | LOCALLY OPTIMIZED COLORING FOR CLEANING LITHOGRAPHIC HOTSPOTS - Approaches for cleaning/resolving lithographic hotspots (e.g., during a simulation phase of semiconductor design) are provided. Typically, a hotspot will be identified in a first polygon (having a first color) of a lithographic pattern or contour. Once a hotspot has been identified, a location (e.g., another portion of the first polygon or in a second polygon of the lithographic pattern having the first color) proximate the hotspot will be identified to place a stitch marker. Once the location has been identified, a stitch marker will be placed at that location. Then, a color of the stitch marked location will be changed to a second color, and the resulting lithographic pattern can be further processed to clean/resolve the hotspot. | 06-19-2014 |
20140181761 | IDENTIFYING CIRCUIT ELEMENTS FOR SELECTIVE INCLUSION IN SPEED-PUSH PROCESSING IN AN INTEGRATED CIRCUIT, AND RELATED CIRCUIT SYSTEMS, APPARATUS, AND COMPUTER-READABLE MEDIA - Embodiments of the disclosure include identifying circuit elements for selective inclusion in speed-push processing and related circuit systems, apparatus, and computer-readable media. A method for altering a speed-push mask is provided, including analyzing a circuit design comprising a plurality of cells to which a speed-push mask is applied to identify at least one of the plurality of cells as having performance margin. The speed-push mask is altered such that the at least one of the plurality of cells having performance margin may be fabricated as a non-speed-pushed cell. Additionally, a method for creating a speed-push mask is provided, including analyzing a circuit design comprising a plurality of cells to identify at least one of the plurality of cells below a performance threshold. A speed-push mask is created such that the at least one of the plurality of cells below the performance threshold may be fabricated as a speed-pushed cell. | 06-26-2014 |
20140181762 | LITHOGRAPHY AWARE LEAKAGE ANALYSIS - A method for performing leakage analysis includes receiving information specifying an integrated circuit. A neighborhood of shapes associated with the integrated circuit is then determined Leakage information associated with the integrated circuit is generated based on the neighborhood of shapes. The neighborhood of shapes may be determined by determining a first set of spacings to a boundary of a first cell from an internal shape. A second set of spacings may be determined from the boundary of the first cell to a shape of a second cell. A lithography process may be characterized using the first and second set of spacings. | 06-26-2014 |
20140189611 | Method Of Decomposable Checking Approach For Mask Alignment In Multiple Patterning - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a first plurality of features defined in a first layer and a second plurality of features defined in a second layer; converting the IC design layout to a topological diagram having nodes, chains and arrows; and identifying alignment conflict based on the topological diagram using rules associated with loop and path count. | 07-03-2014 |
20140189612 | TEST COVERAGE OF INTEGRATED CIRCUITS WITH MASKING PATTERN SELECTION - A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference. | 07-03-2014 |
20140189613 | VOLTAGE-RELATED ANALYSIS OF LAYOUT DESIGN DATA - Disclosed are representative embodiments of methods, apparatus, and systems for voltage-related analysis of layout design data. According to embodiments of the disclosed technology, voltage association data objects are generated for drawn layers in a net of a layout design and voltage values or ranges of voltage values associated with the net are collected. The voltage values or ranges of voltage values are then associated with the voltage association data objects. A voltage-related analysis may be performed by searching the voltage association data objects according to a predetermined criterion. | 07-03-2014 |
20140201691 | LAYOUT DECOMPOSITION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE APPLYING THE SAME - A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system. | 07-17-2014 |
20140215414 | Mask Rule Checking Based on Curvature - Aspects of the invention relate to techniques for mask rule checking based on curvature information. The curvature information comprises convex curvature information and concave curvature information. The convex curvature information for a vertex of a mask feature may comprise a convex curvature value derived based on the size of a circle that passes through the vertex, is tangent to an edge and does not cross any other edges. The concave curvature information for the vertex may comprise a concave curvature value derived based on the size of a circle that is tangent to two edges that form the vertex and does not cross any other edges, and of which distance from the vertex measured from the nearest point is no more than a predetermined number. The generated curvature information is compared with threshold curvature information to determine mask rule violations. | 07-31-2014 |
20140215415 | AUTOMATED DESIGN LAYOUT PATTERN CORRECTION BASED ON CONTEXT-AWARE PATTERNS - A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout. | 07-31-2014 |
20140223389 | SYSTEM AND METHOD TO DESIGN AND TEST A YIELD SENSITIVE CIRCUIT - A method includes identifying at least a portion of a design of a semiconductor device to be fabricated as a yield sensitive circuit. The method also includes, in response to identifying the yield sensitive circuit, forming a scan chain. Forming the scan chain includes inserting the yield sensitive circuit between a pair of flip flops and connecting the yield sensitive circuit to the pair of flip flops. | 08-07-2014 |
20140223390 | RETARGETING SEMICONDUCTOR DEVICE SHAPES FOR MULTIPLE PATTERNING PROCESSES - A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features. | 08-07-2014 |
20140223391 | RECOGNITION OF TEMPLATE PATTERNS WITH MASK INFORMATION - Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons. | 08-07-2014 |
20140237435 | LAYOUT METHOD AND SYSTEM FOR MULTI-PATTERNING INTEGRATED CIRCUITS - A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node. | 08-21-2014 |
20140245238 | METHODS INVOLVING PATTERN MATCHING TO IDENTIFY AND RESOLVE POTENTIAL NON-DOUBLE-PATTERNING-COMPLIANT PATTERNS IN DOUBLE PATTERNING APPLICATIONS - One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout. | 08-28-2014 |
20140245239 | DETECTION AND REMOVAL OF SELF-ALIGNED DOUBLE PATTERNING ARTIFACTS - Mask design techniques for detection and removal of undesirable artifacts in SADP processes using multiple patterns are disclosed. Artifacts or spurs result from lithographic and chemical processing of semiconducting wafers. The spurs are undesirable because they can cause unwanted connections or act as electrical antennas. Spurs are detected using rule-based techniques and reduced by modifying lithographic masks. The severity of the detected spurs is determined, again using rule-based techniques. The effects of detected spurs can be reduced by modifying the decomposition of the drawn patterns into the two masks used for lithography. Mandrel masks are modified by add dummy mandrel material, and trim masks are modified by removing trim material. The resulting multi-pattern arrangement is used to fabricate the critical design elements that make up the semiconductor wafers. | 08-28-2014 |
20140282291 | SOURCE-MASK OPTIMIZATION FOR A LITHOGRAPHY PROCESS - Systems and methods for optimizing a source shape and a mask shape for a lithography process are disclosed. One such method includes performing a mask optimization for the lithography process in accordance with a set of parameters including at least one variable representation, at least one objective and problem constraints. Further, a light source optimization for the lithography process is performed in accordance with the set of parameters. In addition, a joint light source-mask optimization is performed in accordance with the set of parameters. The method further includes iterating at least one of the mask optimization or the light source optimization by changing at least one of the variable representation, the objective or the problem constraints to maximize a common process window for the lithography process. | 09-18-2014 |
20140282292 | SURFACE TOPOGRAPHY ENHANCED PATTERN (STEP) MATCHING - A design or lithographic enhancement process, a method for forming a device based on the lithographic enhancement process and a system for pattern enhancement are presented. The process includes processing a design data file. The design data file includes information of design layers in an integrated circuit (IC). Processing the design data file includes analyzing the design data file and patterns in the design data file are enhanced taken into consideration topography information of design layers corresponding to masks of the IC. | 09-18-2014 |
20140282293 | EDA TOOL AND METHOD FOR CONFLICT DETECTION DURING MULTI-PATTERNING LITHOGRAPHY - A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing. | 09-18-2014 |
20140282294 | METHOD, SYSTEM AND SOFTWARE FOR ACCESSING DESIGN RULES AND LIBRARY OF DESIGN FEATURES WHILE DESIGNING SEMICONDUCTOR DEVICE LAYOUT - Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout. | 09-18-2014 |
20140289684 | BALANCING MASK LOADING - Among other things, techniques for balancing mask loading are provided for herein. In some embodiments, one or more windows are defined within a layout. Based upon polygons comprised within respective windows, a localized mask loading is computed for the layout. In some embodiments, a global mask loading is also computed for the layout. Using the localized mask loading and the global mask loading, if computed, a loading effect of a plurality of mask pattern schemes is evaluated to identify a mask pattern scheme having a desired loading effect. | 09-25-2014 |
20140310662 | PATTERN INSPECTION METHOD - In accordance with one aspect of this invention, a pattern inspection method includes acquiring optical images regarding figure patterns arranged in each of frame regions, for each of the plurality of frame regions; measuring linewidth dimensions of the figure patterns, for each of the frame regions; operating an average value of each linewidth dimension shift between linewidth dimensions of figure patterns in a reference image corresponding to the frame region concerned and the linewidth dimensions of the figure patterns in the optical image, for each of the frame regions; extracting a specific frame from the frame regions by comparing the average value of the frame region concerned, with average values of frame regions around the frame region concerned, for each of the frame regions; and inspecting the specific frame for dimensional defects of linewidth dimensions. | 10-16-2014 |
20140344769 | METHOD FOR CORRECTING ELECTRONIC PROXIMITY EFFECTS USING THE DECONVOLUTION OF THE PATTERN TO BE EXPOSED BY MEANS OF A PROBABILISTIC METHOD - A method of lithography by radiation having critical dimensions of the order of some ten nanometers makes it possible to carry out the correction of the proximity effects by joint optimization of the dose modulation and geometric corrections. Accordingly, a deconvolution of the pattern to be etched is carried out by an iterative procedure modeling the interactions of the radiation with the resined support by a joint probability distribution. Advantageously, when the support exposure tool is of formed-beam type, the pattern to be etched is split into contrasted levels and then the deconvolved image is vectorized and fractured before carrying out the exposure step. In an advantageous embodiment, the method is applied to at least two character cells which are exposed in a multi-pass cells projection method. | 11-20-2014 |
20140372958 | TRIPLE-PATTERN LITHOGRAPHY LAYOUT DECOMPOSITION - Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium. | 12-18-2014 |
20150012895 | DOUBLE PATTERNING TECHNOLOGY (DPT) LAYOUT ROUTING - One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues. | 01-08-2015 |
20150020037 | Method and System for Design of a Reticle to be Manufactured Using Variable Shaped Beam Lithography - A method for optical proximity correction (OPC) is disclosed, in which a set of VSB shots is determined, where the set of shots can approximately form a target reticle pattern that is an OPC-compensated version of an input pattern. The set of shots is simulated to create a simulated reticle pattern. A substrate image is calculated, based on using the simulated reticle pattern in an optical lithographic process to form the substrate image. A system for OPC is also disclosed. | 01-15-2015 |
20150026650 | INTEGRATED CIRCUIT MANUFACTURE USING DIRECT WRITE LITHOGRAPHY - Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step is varied in dependence upon those performance characteristics. Accordingly, the performance of an individual integrated circuit, wafer of integrated circuits or batch of wafers may be altered. | 01-22-2015 |
20150026651 | PREVENTING DOUBLE PATTERNING ODD CYCLES - A method, system or computer usable program product for preventing odd cycles caused by design modifications to a double patterning layout including utilizing a processor to identify a set of double patterning cycles in the layout for storage in a memory; receiving a set of design modifications to the layout; utilizing the processor to identify from the set of double patterning cycles a subset of double patterning cycles affected by the set of design modifications; utilizing the processor to identify from the set of design modifications a subset of design modifications which may cause odd cycles in the subset of double patterning cycles; and providing a notification of the subset of design modifications. | 01-22-2015 |
20150046887 | RETARGETING SEMICONDUCTOR DEVICE SHAPES FOR MULTIPLE PATTERNING PROCESSES - A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features. | 02-12-2015 |
20150052489 | LONG-RANGE LITHOGRAPHIC DOSE CORRECTION - A method of quantifying a lithographic proximity effect and determining a lithographic exposure dosage is disclosed. In an exemplary embodiment, the method for determining an exposure dosage comprises receiving a design database including a plurality of features intended to be formed on a workpiece. A target region of the design database is defined such that the target region includes a target feature. A region of the design database proximate to the target region is also defined. An approximation for the region is determined, where the approximation represents an exposed area within the region. A proximity effect of the region upon the target feature is determined based on the approximation for the region. A total proximity effect for the target feature is determined based on the determined proximity effect of the region upon the target feature. | 02-19-2015 |
20150052490 | DETECTING AND DISPLAYING MULTI-PATTERNING FIX GUIDANCE - A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable. | 02-19-2015 |
20150058813 | MULTI-MODEL METROLOGY - Disclosed are apparatus and methods for characterizing a plurality of structures of interest on a semiconductor wafer. A plurality of models having varying combinations of floating and fixed critical parameters and corresponding simulated spectra is generated. Each model is generated to determine one or more critical parameters for unknown structures based on spectra collected from such unknown structures. It is determined which one of the models best correlates with each critical parameter based on reference data that includes a plurality of known values for each of a plurality of critical parameters and corresponding known spectra. For spectra obtained from an unknown structure using a metrology tool, different ones of the models are selected and used to determine different ones of the critical parameters of the unknown structure based on determining which one of the models best correlates with each critical parameter based on the reference data. | 02-26-2015 |
20150067616 | CELL LAYOUT DESIGN AND METHOD - A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell. | 03-05-2015 |
20150067617 | Method and System for Overlay Control - A method for overlay monitoring and control is introduced in the present disclosure. The method comprises forming resist patterns on one or more wafers in a lot by an exposing tool; selecting a group of patterned wafers in the lot using a wafer selection model; selecting a group of fields for each of the selected group of patterned wafers using a field selection model; selecting at least one point in each of the selected group of fields using a point selection model; measuring overlay errors of the selected at least one point on a selected wafer; forming an overlay correction map using the measured overlay errors on the selected wafer; and generating a combined overlay correction map using the overlay correction map of each selected wafer in the lot. | 03-05-2015 |
20150067618 | INTEGRATED CIRCUIT LAYOUT DESIGN METHODOLOGY WITH PROCESS VARIATION BANDS - A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions. | 03-05-2015 |
20150074619 | METHODS AND SYSTEM FOR MODEL-BASED GENERIC MATCHING AND TUNING - The present invention relates to a method for tuning lithography systems so as to allow different lithography systems to image different patterns utilizing a known process that does not require a trial and error process to be performed to optimize the process and lithography system settings for each individual lithography system. According to some aspects, the present invention relates to a method for a generic model-based matching and tuning which works for any pattern. Thus it eliminates the requirements for CD measurements or gauge selection. According to further aspects, the invention is also versatile in that it can be combined with certain conventional techniques to deliver excellent performance for certain important patterns while achieving universal pattern coverage at the same time. | 03-12-2015 |
20150082258 | Method for Forming Circular Patterns on a Surface - A method for fracturing or mask data preparation is disclosed, in which a set of shots is determined, where each shot will direct a circular or nearly-circular dosage pattern to a surface, where each shot comprises a shot dosage, and in which the set of shots is output. A method for forming patterns on a surface using charged particle beam lithography is also disclosed, in which a stencil is provided comprising one or more circular apertures, and where a plurality of circular patterns of different sizes are formed on the surface using a single aperture, by varying the shot dosage. | 03-19-2015 |
20150089457 | Hierarchical Approach to Triple Patterning Decomposition - A mechanism is provided in a data processing system for hierarchical triple patterning decomposition. The mechanism receives an integrated circuit design. The mechanism enforces boundary conditions on three-color mapping of shapes in a layer of the integrated circuit design at the cell level. The mechanism places cells in the layer of the integrated circuit design. The mechanism identifies post placement coloring conflicts and resolves the post placement coloring conflicts with two-color flipping in coloring runs containing one or more conflicts. | 03-26-2015 |
20150089458 | SYSTEMS AND METHODS FOR MITIGATING PRINT-OUT DEFECTS - The present disclosure provides methods and systems for mitigating print-out defects that result during semiconductor simulation and/or fabrication. One of the methods disclosed herein includes steps of receiving a first desired sub-layout and a second desired sub-layout and of optimizing the first desired sub-layout and the second desired sub-layout to generate a first optimized sub-layout and a second optimized sub-layout. The method further includes simulating the first optimized sub-layout and the second optimized sub-layout and of identifying one or more print-out defects in the simulated first optimized sub-layout and the simulated second optimized sub-layout. By comparing the simulated first optimized sub-layout and the simulated second optimized sub-layout it may be determined whether or not print-out defects in the simulated second optimized sub-layout are covered by the first desired sub-layout such that the first optimized sub-layout may be used to pattern material layers. | 03-26-2015 |
20150095857 | METHOD AND SYSTEM FOR MULTI-PATTERNING LAYOUT DECOMPOSITION - A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations. | 04-02-2015 |
20150095858 | METHOD, PROGRAM PRODUCT AND APPARATUS FOR PERFORMING DOUBLE EXPOSURE LITHOGRAPHY - A method of generating complementary masks based on a target pattern having features to be imaged on a substrate for use in a multiple-exposure lithographic imaging process. In embodiments, the invention provides a double exposure lithography method which trims (i.e., removes) unwanted SB residues from the substrate, that is suitable for use, for example, when printing 65 nm or 45 nm node devices or less. According to certain aspects, the present invention provides the ability to utilize large SBs due to the mutual trimming of SBs that results from the process of the present invention. Specifically, in the given process, both the H-mask and the V-mask contain circuit features and SBs, but they are in different corresponding orientations, and therefore, there is a mutual SB trimming for the H-mask and V-mask during the two exposures. | 04-02-2015 |
20150106772 | Method For Fracturing And Forming A Pattern Using Shaped Beam Charged Particle Beam Lithography - In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. A method for forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed. | 04-16-2015 |
20150113484 | METHODS OF GENERATING CIRCUIT LAYOUTS THAT ARE TO BE MANUFACTURED USING SADP ROUTING TECHNIQUES - One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern. | 04-23-2015 |
20150113485 | PATTERN DATA GENERATION METHOD, PATTERN VERIFICATION METHOD, AND OPTICAL IMAGE CALCULATION METHOD - According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected. | 04-23-2015 |
20150121317 | MULTI-PATTERNING SYSTEM AND METHOD - A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by multipatterning. The mask assignment information includes, for each of the plurality of patterns, a mask assignment identifying which of a plurality of masks is to be used to form that pattern, and a mask assignment lock state for that pattern. User inputs setting the mask assignment of at least one of the plurality of patterns, and its mask assignment lock state are received. A new mask assignment is generated for each of the plurality of patterns having an “unlocked” mask assignment lock state. | 04-30-2015 |
20150128098 | Method and System for Repairing Wafer Defects - A method of lithographic defect detection and repair is disclosed. In an exemplary embodiment, the method of patterning a workpiece comprises receiving a mask for patterning a workpiece. The mask is inspected for defects, and a mask defect is identified that is repairable in the workpiece. The workpiece is lithographically exposed using the mask, and a defect is repaired within the workpiece based on the identified mask defect. The method may further comprise comparing defects across the workpiece to determine repeating defects and determining a spacing between repeating defects. A distance between a first focal point and a second focal point of a lithographic system may be configured to correspond to the spacing between repeating defects. Thus, a first repeating defect and a second repeating defect may be repaired concurrently. | 05-07-2015 |
20150149969 | LAYOUT DESIGN FOR ELECTRON-BEAM HIGH VOLUME MANUFACTURING - The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step. In some embodiments a routing grid is refined to rule out interactions between a subset of design constructs and the layout grid. Remaining design shape placement is then optimized along the routing grid relative to the stitching lines. | 05-28-2015 |
20150302136 | Methods for Layout Verification for Polysilicon Cell Edge Structures in FinFET Standard Cells Using Filters - Methods for verifying the layout for standard cells using finFET standard cell structures with polysilicon on cell edges. Standard cells are defined using finFET transistors. Polysilicon dummy structures are formed on the edges of the active areas of the standard cells. Where two standard cells abut a single polysilicon dummy structure is formed. In a design flow, a pre-layout netlist schematic for the standard cells is formed that does not include devices corresponding to the polysilicon dummy structures. After an automated place and route process forms a device layout using the standard cells, a post layout netlist schematic is extracted including MOS devices corresponding to the polysilicon dummy structures. A layout versus schematic comparison is then performed, but during the comparison MOS devices corresponding to the polysilicon dummy structures are filtered from the post-layout netlist and are not compared. Additional methods are disclosed. | 10-22-2015 |
20150302137 | Expanded Canonical Forms Of Layout Patterns - Aspects of the disclosed technology relate to techniques for determining expanded canonical forms of layout patterns. Coordinates of vertices of geometric elements in a window of a layout design are first transformed into new coordinates of the vertices, wherein the coordinates of vertices do not comprise clipped coordinates and the transforming comprises: performing a translation on the coordinates of vertices based on differences between maximum and minimum X/Y coordinate values of the vertices. Based on sums of X/Y coordinate values of the new coordinates of the vertices, a canonical form of the geometric elements is determined. The canonical form coordinates of the vertices for a plurality of windows may then be determined. The plurality of windows comprise the window, are centered in the same location as the window, and have different sizes. | 10-22-2015 |
20150339428 | MASK-AWARE ROUTING AND RESULTING DEVICE - Methods for routing a metal routing layer based on mask design rules and the resulting devices are disclosed. Embodiments may include laying-out continuous metal lines in a semiconductor design layout, and routing, by a processor, a metal routing layer using the continuous metal lines according to placement of cut or block masks based on cut or block mask design rules. | 11-26-2015 |
20150339429 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING GENERATING PHOTOMASKS FOR DIRECTED SELF-ASSEMBLY (DSA) USING DSA TARGET PATTERNS - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern overlying a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes identifying placement of DSA target patterns in a design layout. The DSA target patterns are grouped into groups including a first group and a first group boundary is defined around the first group. The method further includes determining if a neighboring DSA target pattern to the first group boundary is at least a predetermined minimal keep-away distance from an adjacent DSA target pattern that is within the first group boundary. The method also includes determining if the DSA target patterns in the first group are DSA compatible. An output mask pattern is generated using the first group boundary. | 11-26-2015 |
20150347660 | Compensation of Dose Inhomogeneity Using Overlapping Exposure Spots - An exposure pattern is computed which is used for exposing a desired pattern on a target by means of a particle beam and a blanking aperture array in a particle-optical lithography apparatus, taking into account a non-uniform current dose distribution as generated by the beam over the positions of the apertures of the blanking aperture array: From the desired pattern a nominal exposure pattern is calculated as a raster graphics comprising nominal dose values for the pixels of the raster graphics; based on a map of the current dose distribution, which correlates each aperture with a current factor describing the current dose of the beam at the location of the aperture, a compensated dose value is calculated for each pixel, by dividing its nominal dose value by the compensation factor corresponding to the current factor of the corresponding aperture(s); and for each pixel, a discrete value is determined by selecting a value from a discrete gray scale so as to approximate the compensated dose value. | 12-03-2015 |
20150356228 | PHOTOMASK ERROR CORRECTION - Design errors generated employing a mask rule check (MRC) program are indexed and examined one by one by an automated computer program connected to a false error pattern database that contains previously known waivered patterns, a real error pattern database that contains previously known pairs of an error-containing pattern and a corresponding error-free pattern, and optionally a mask house rule database. A waiver is applied to each design error for which a matching pattern is found in the false error pattern database. Each design error for which a match is found in the real error pattern database is modified to substitute an error-free pattern for an error-containing pattern therein. The output of the automated program includes a list of design errors for which no solution is found by the automated program. | 12-10-2015 |
20150356232 | Method and System for Generating a Circuit Design, Method for Calibration of an Inspection Apparatus and Method for Process Control and Yield Management - A method for generating a circuit design of an integrated circuit, the circuit design comprising a functional area (FA) and a non-functional area is provided. The method comprises the steps of providing a description of a test cell (TC) to an electronic design automation (EDA) tool and inserting the test cell (TC) into the circuit design. Therein, the description of the test cell (TC) comprises a description of a test structure (HS) and the test structure (HS) is designed to be sensitive to variations of a manufacturing process. Furthermore, the test cell (TC) is inserted into a non-functional area and the inserting is performed automatically by the EDA tool. The test structure (HS) is intentionally designed to be sensitive to variations of the manufacturing process, in contrast to regular structures within the circuit description. | 12-10-2015 |
20150356234 | FAST FREEFORM SOURCE AND MASK CO-OPTIMIZATION METHOD - The present disclosure relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present disclosure significantly speeds up the convergence of the optimization by allowing direct computation of gradient of the cost function. According to other aspects, the present disclosure allows for simultaneous optimization of both source and mask, thereby significantly speeding the overall convergence. According to still further aspects, the present disclosure allows for free-form optimization, without the constraints required by conventional optimization techniques. | 12-10-2015 |
20150363534 | METHOD AND APPARATUS FOR POST-OPC VERIFICATION - A method for post-OPC verification including of several steps is provided. First, a pre-OPC layout of an integrated circuit (IC) is received. Then, a first OPC procedure is performed to obtain a post-OPC layout of the IC. After that, a first extraction process is performed on the pre-OPC layout and a second extraction process is performed on the post-OPC layout to respectively obtain a first netlist and a second netlist by using a processor. Next, a verification process is performed by using the processor to determine whether an electrical network of the first netlist and an electrical network of the second netlist are identical. The verification process is then terminated if the electrical network of the first netlist and the electrical network of the second netlist are identical. An apparatus for post-OPC verification is also provided. | 12-17-2015 |
20150363541 | EDA TOOL AND METHOD FOR CONFLICT DETECTION DURING MULTI-PATTERNING LITHOGRAPHY - A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing. | 12-17-2015 |
20150379189 | TRIPLE-PATTERN LITHOGRAPHY LAYOUT DECOMPOSITION - Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium. | 12-31-2015 |
20150379190 | MEMS Modeling System and Method - A system and method for modeling microelectromechanical devices is disclosed. An embodiment includes separating the microelectromechanical design into separate regions and modeling the separate regions separately. Parametric parameters or parametric equations may be utilized in the separate models. The separate models may be integrated into a MEMS device model. The MEMS device model may be tested and calibrated, and then may be used to model new designs for microelectromechanical devices. | 12-31-2015 |
20160012175 | Method for Modeling a Photoresist Profile | 01-14-2016 |
20160019330 | THERMAL UNIFORMITY COMPENSATING METHOD AND APPARATUS - The invention provides a thermal uniformity compensating method and apparatus. The steps of the method includes: respectively measuring a plurality of first resistances of a plurality of hot spot patterns of a chip over an hot spot effect, wherein a plurality of pattern densities of the hot spot patterns are different; respectively measuring a plurality of second resistances of each of the hot spot patterns of the chip by a plurality of test keys over the hot spot effect, wherein a plurality of distances between the test keys and the corresponding hot spot pattern are different; establishing a look-up information according to the first and second resistances; analyzing a layout data of the chip for obtaining a pattern density information; and generating a calibrated layout data according to the pattern density information and the look-up information. | 01-21-2016 |
20160019333 | METHOD OF DETERMINING WHETHER A LAYOUT IS COLORABLE - A method of determining whether a layout is colorable includes assigning nodes to polygon features of the layout. The method includes designating nodes as being adjacent nodes for nodes separated by less than a minimum pitch. The method includes iteratively removing nodes having less than three adjacent nodes from consideration to identify a node arrangement, wherein all nodes in the node arrangement have at least three adjacent nodes. The method includes determining whether the layout is colorable based on the node arrangement. Determining whether the layout is colorable includes independently assessing each internal node of node arrangement to determine whether each internal node of the node arrangement is colorable. The method includes generating a colored layout design for fabrication of the semiconductor device if each internal node of the node arrangement is colorable; and modifying the layout if at least one internal node of the node arrangement is not colorable. | 01-21-2016 |
20160026744 | LAYOUT DESIGN METHODS AND LAYOUT DESIGN SYSTEMS FOR PERFORMING THE LAYOUT DESIGN METHODS - A layout design method may include receiving predetermined values related to first to third normal fin designs extending in a first direction and arranged in parallel in a second direction perpendicular to the first direction, generating dummy fin designs based on the predetermined values, generating mandrel candidate designs based on the first to third normal fin designs and the dummy fin designs, decomposing the mandrel candidate designs to first and second mandrel mask designs, and generating a final mandrel mask design using one of the first and second mandrel mask designs that satisfies a predetermined condition. A first interval distance in the second direction between the first normal fin design and the second normal fin design may be different from a second interval distance in the second direction between the second normal fin design and the third normal fin design. | 01-28-2016 |
20160026748 | MULTI-POLYGON CONSTRAINT DECOMPOSITION TECHNIQUES FOR USE IN DOUBLE PATTERNING APPLICATIONS - One illustrative method disclosed herein involves, among other things, decomposing an initial circuit layout into first and second mask patterns, for the first mask pattern, identifying a first four-polygon pattern in the first mask pattern that violates a multi-polygon constraint rule, wherein the first four-polygon pattern comprises four polygons positioned side-by-side in the first mask pattern, and recoloring one or two of the polygons in the first four-polygon pattern in the first mask pattern to the second mask pattern to eliminate the first four-polygon pattern from the first mask pattern without introducing any design rule violations in the initial circuit layout. | 01-28-2016 |
20160026750 | PATTERN SELECTION FOR FULL-CHIP SOURCE AND MASK OPTIMIZATION - The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result. | 01-28-2016 |
20160063169 | METHOD OF DETERMINING COLORABILITY OF A LAYOUT AND SYSTEM FOR IMPLEMENTING THE SAME - A method of determining colorability of a layout includes generating a conflict diagram based on circuit information. The conflict diagram includes a plurality of nodes, each node of the plurality of nodes is connected to at least another node of the plurality of nodes by a link, and each node of the plurality of nodes has a degree equal to a number of links connected to the node. The method includes setting a degree of each anchor node within the conflict diagram to a value of n, where n is equal to a number of mask usable to manufacture the layout. The method further includes excluding, using a processor, nodes having a degree less than n from the conflict diagram. The method further includes performing a color status check on the conflict diagram after the excluding; and determining whether the layout is colorable based on the performed color status check. | 03-03-2016 |
20160063170 | MEMORY REDUNDANCY REDUCTION - A method includes designing, at a computer, a first version of a memory device that includes first main memory and first redundant memory. The method further includes modifying a design of the first version of the memory device to produce a second version of the memory device when an error rate associated with fabrication of the first version of the memory device is below a threshold. The second version of the memory device includes second main memory that is logically identical to the first main memory, and the second version of the memory device includes less redundant memory than the first redundant memory. | 03-03-2016 |
20160063173 | Optical Proximity Correction Verification System and Verification Method Thereof - The optical proximity correction verification method includes loading a layout data to be verified to a processor, loading a reference layout data to the processor. The processor performs a first stage Boolean operation on the layout data to be verified to generate a first verified data. The processor performs a layout versus layout verification on the first verified data by using a user-defined verification tool of optical proximity correction data in a database to generate second verified data according to the reference layout data. The processor performs a second stage Boolean operation on the second verified data to generate a third verified data if the layout versus layout verification is successfully performed. The processor performs a Boolean check on the third verified data to generate fourth verified data using the reference layout data. | 03-03-2016 |
20160070848 | METHOD OF DECOMPOSING LAYOUT OF SEMICONDUCTOR DEVICE FOR QUADRUPLE PATTERNING TECHNOLOGY PROCESS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction. | 03-10-2016 |
20160085905 | PROCESS WINDOW IDENTIFIER - Disclosed herein is a computer-implemented method for determining an overlapping process window (OPW) of an area of interest on a portion of a design layout for a device manufacturing process for imaging the portion onto a substrate, the method comprising: obtaining a plurality of features in the area of interest; obtaining a plurality of values of one or more processing parameters of the device manufacturing process; determining existence of defects, probability of the existence of defects, or both in imaging the plurality of features by the device manufacturing process under each of the plurality of values; and determining the OPW of the area of interest from the existence of defects, the probability of the existence of defects, or both. | 03-24-2016 |
20160098512 | HIERARCHICAL FILL IN A DESIGN LAYOUT - This application discloses a computing system implementing one or more tools or mechanism configured to capture a hierarchy of a circuit design layout generated by a downstream tool. The hierarchy can include multiple cells that identify corresponding portions of the circuit design layout. The tools or mechanism can be further configured to modify the circuit design layout based, at least in part, on the captured hierarchy, which alters the portions of the circuit design layout identified by the cells separately from other portions of the circuit design layout. | 04-07-2016 |
20160103948 | RESISTIVE CAPACITANCE DETERMINATION METHOD FOR MULTIPLE-PATTERNING-MULTIPLE SPACER INTEGRATED CIRCUIT LAYOUT - A method includes generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions includes a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a first spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the first spacing values. | 04-14-2016 |
20160117432 | METHOD AND APPARATUS FOR ASSISTED METAL ROUTING - A method and apparatus for an assisted metal routing is disclosed. Embodiments may include: determining an initial block mask having a first inner vertex for forming a metal routing layer of an integrated circuit (IC); adding an assistant metal portion within the metal routing layer; and determining a modified block mask based on the assistant metal portion for forming the metal routing layer. | 04-28-2016 |
20160125117 | INTEGRATED CIRCUIT AND METHOD OF DESIGNING LAYOUT THEREOF - A method of designing a layout of an integrated circuit (IC), which is implemented by a computer system or a processor, includes receiving input layout data, and performing a design rule check with regard to a plurality of patterns. The method includes, merging, from among a first pattern and a second pattern against the design rule, the first pattern with a third pattern connected to a same net as the first pattern, and generating output layout data. | 05-05-2016 |
20160125120 | DRC-Based Hotspot Detection Considering Edge Tolerance And Incomplete Specification - A range-pattern-matching-type DRC-based process hotspot detection is provided that considers edge tolerances and incomplete specification (“don't care”) regions in foundry-provided hotspot patterns. First, all possible topological patterns are enumerated for the foundry-provided hotspot pattern. Next, critical topological features are extracted from each pattern topology and converted to critical design rules using Modified Transitive Closure Graphs (MTCGs). Third, the extracted critical design rules are arranged in an order that facilitates searching space reduction techniques, and then the DRC process is sequentially repeated on a user's entire layout pattern for each critical design rule in a first group, then searching space reduction is performed to generate a reduced layout pattern, and then DRC process is performed for all remaining critical design rules using the reduced layout pattern. Candidate locations are then identified using the DRC results, and then the true hotspot locations are confirmed using longest common subsequence and linear scan techniques. | 05-05-2016 |
20160140287 | Template Creation Device for Sample Observation Device, and Sample Observation Device - A template creation device for a sample observation device for creating a template for image processing using design data includes a storage unit for storing process information in which information concerning a plurality of process processings is defined, and a template creation unit for processing the design data using the process information and creating the template for the image processing. | 05-19-2016 |
20160147933 | METHOD OF RESOLVING COLOR CONFLICTS FOR CELL-BASED DESIGNS WITH MULTI-PATTERN LITHOGRAPHY - According to one general aspect, a method may include receiving a data file that includes placement data regarding a plurality of circuit cells. The circuit cells may include respective layout portions. The layout portions may be associated with a plurality of respective lithographic colors. The method may include determining if a violating circuit cell is to be re-colored. The method may include indicating that, via at least one shape on a color swap layer in the data file, the violating circuit cell is to be at least partially re-colored. A color swap layer shape may cause a mask generator to re-color the portion of the violating circuit cell indicated by the color swap layer shape. | 05-26-2016 |
20160161845 | METHOD OF OPERATING A MICROLITHOGRAPHIC PROJECTION APPARATUS - A method of operating a microlithographic projection exposure apparatus includes, in a first step, providing a projection objective that includes a plurality of real manipulators. In a second step, a virtual manipulator is defined that is configured to produce preliminary control signals for at least two of the real manipulators. In a third step, performed during operation of the apparatus, a real image error of the projection objective is determined. In a fourth step, a desired corrective effect is determined. In a fifth step, first virtual control signals for the virtual manipulator are determined. In a sixth step, second virtual control signals for the real manipulators are determined. | 06-09-2016 |
20160162628 | GENERIC DESIGN RULE CHECKING (DRC) TEST CASE EXTRACTION - A computer-aided testing is provided for design verification of integrated circuits. More specifically, a method of generating a test case in design rule checking is provided for that includes extracting coordinates of an error marker for a first error identified in an integrated circuit design. The method further includes identifying a first rectangle that encloses the error marker. The method further includes generating a first test case based on data of the integrated circuit design contained within the rectangle. The method further includes determining whether the first test case is representative of the first error. The method further includes in response to determining the first test case is not representative of the first error, identifying a second rectangle that is between the first rectangle and a third rectangle. The method further includes generating a second test case based on data of the integrated circuit design contained within the second rectangle. | 06-09-2016 |
20160171149 | METHODS AND APPARATUS FOR AUTOMATED DESIGN OF SEMICONDUCTOR PHOTONIC DEVICES | 06-16-2016 |
20160180005 | SYSTEM AND TECHNIQUE FOR RASTERIZING CIRCUIT LAYOUT DATA | 06-23-2016 |
20160195805 | Method and System for Design of Enhanced Edge Slope Patterns for Charged Particle Beam Lithography | 07-07-2016 |
20160196379 | METROLOGY TARGET INDENTIFICATION, DESIGN AND VERIFICATION | 07-07-2016 |
20160378902 | GENERATIVE LEARNING FOR REALISTIC AND GROUND RULE CLEAN HOT SPOT SYNTHESIS - Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable. | 12-29-2016 |
20160378906 | METHODS OF DESIGN RULE CHECKING OF CIRCUIT DESIGNS - Methods for performing design rule checking of a circuit design are provided. The methods include, for instance: providing a circuit design for an integrated circuit layer, in which the circuit design includes a plurality of design lines oriented in a particular direction; and automatically performing a design rule check of the circuit design, which may include forming a verification pattern for the circuit design, the verification pattern comprising a plurality of verification lines and a plurality of verification regions, wherein one or more verification regions are associated with and connected to one verification line of the plurality of verification lines, and checking the verification pattern for any verification line overlapping a verification region. The circuit design may be considered to fail the design rule check if an end of one verification line overlaps any verification region associated with another verification line of the verification pattern. | 12-29-2016 |
20170235217 | A PHOTOMASK STRUCTURE WITH AN ETCH STOP LAYER THAT ENABLES REPAIRS OF DRTECTED DEFECTS THEREIN AND EXTREME ULTRAVIOLET(EUV) PHOTOLITHOGRAPY METHODS USING THE PHOTOMASK STRUCTURE | 08-17-2017 |
20190147134 | METHOD OF POST OPTICAL PROXIMITY CORRECTION (OPC) PRINTING VERIFICATION BY MACHINE LEARNING | 05-16-2019 |