Class / Patent application number | Description | Number of patent applications / Date published |
714600130 | Isolating failed storage location (e.g., sector remapping, etc.) | 74 |
20110016352 | PROGRAMMABLE MEMORY REPAIR SCHEME - The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element. | 01-20-2011 |
20110083039 | MEMORY SYSTEMS AND METHODS OF DETECTING DISTRIBUTION OF UNSTABLE MEMORY CELLS - A circuit is operated to detect unstable memory cells from among a plurality of memory cells in at least one page. A determination is made from an initial status of data stored in a memory cell whether no read error occurs when the data is read at a standard read voltage level, whether a read error occurs and the read error is correctable, and whether a read error occurs and the read error is uncorrectable. Responsive to determining that a read error occurs that is correctable, a further determination is made as to whether the memory cell is correctable by reading the data stored in the memory cell at a correction read voltage level, which has a different voltage level from the standard read voltage level, and by determining whether a read error occurring in the data read at the correction read voltage level is correctable or uncorrectable. | 04-07-2011 |
20110113282 | METHOD OF STORING A DATA SET IN A DISTRIBUTED STORAGE SYSTEM, DISTRIBUTED STORAGE SYSTEM AND COMPUTER PROGRAM PRODUCT FOR USE WITH SAID METHOD - The present invention is directed to a method of storing a data set in a storage system. Said storage system comprises a plurality of storage entities. The method comprises the following steps. A step of forming at least one data set block from said data set using a fragmentation entity. A step of encoding said at least one data set block by means of an encoding entity, wherein said encoding entity provides a plurality of encoded blocks based on said at least one data set block at an output of said encoding entity. And a step of distributing said encoded blocks amongst at least two of said storage entities using a distribution entity for storage thereof by said storage entities. Said encoding entity uses a rateless erasure encoding algorithm based on rateless codes for encoding said at least one data set block. The invention is further directed to a storage system and a computer program product. | 05-12-2011 |
20110219260 | DEFECTIVE MEMORY BLOCK REMAPPING METHOD AND SYSTEM, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME - A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address. | 09-08-2011 |
20120011395 | BOOT METHOD UNDER BOOT SECTOR FAILURE IN HARD DISK AND COMPUTER DEVICE USING THE SAME - A boot method under a boot sector failure in a hard disk is provided, which includes the following steps. First, a detection unit is utilized to determine whether a boot sector in the hard disk fails. After determining that the boot sector fails, the detection unit utilizes a second boot file stored in a solid state disk (SSD) for booting. Meanwhile, the detection unit drives a pickup head in the hard disk to skip the failed boot sector and move to a normal sector in the hard disk, so as to boot a computer and enable the hard disk to operate normally. | 01-12-2012 |
20120023365 | METHODS AND SYSTEMS FOR MONITORING WRITE OPERATIONS OF NON-VOLATILE MEMORY - Systems and methods are disclosed for monitoring the time it takes to perform a write operation, and based on the time it takes, a determination is made whether to retire a block that is a recipient of the write operation. The time duration of the write operation for a page or a combination of pages may indicate whether any block or blocks containing the page or combination of pages is experiencing a physical failure. That is, if the time duration of the write operation for a particular page exceeds time threshold, this may indicate that this page requires a larger number of program cycles than other pages. The longer programming cycle can be an indication of cell leakage or a failing block. | 01-26-2012 |
20120060054 | METHOD FOR USING BAD BLOCKS OF FLASH MEMORY - A method is provided for using bad blocks in flash memory. The method includes placing in a replacement area of the flash memory a special bad block that meets a “still usable” condition from the bad blocks of the flash memory. The method also includes receiving a use request for using the special bad block in the replacement area to store user data, writing the user data into the special bad block, and determining whether the user data is successfully written into the special bad block. Further, the method includes placing the special bad block back into the replacement area for a next use request when it is determined that the user data is not successfully written into the special bad block. | 03-08-2012 |
20120084600 | METHOD AND SYSTEM FOR DATA RECONSTRUCTION AFTER DRIVE FAILURES - Methods and systems for data reconstruction following drive failures may include: storing data across two or more drives in one or more data stripes, each data stripe including two or more drive extents; detecting a degradation of a drive containing a drive extent associated with a first data stripe; assigning a reconstruction priority to the drive extent associated with the first data stripe; detecting a degradation of a drive containing a drive extent associated with a second data stripe; and assigning a reconstruction priority to the drive extent associated with the second data stripe. | 04-05-2012 |
20120131382 | MEMORY CONTROLLER AND INFORMATION PROCESSING SYSTEM - A information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, causes the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions. | 05-24-2012 |
20120137168 | METHOD FOR PROTECTING DATA IN DAMAGED MEMORY CELLS BY DYNAMICALLY SWITCHING MEMORY MODE - A method for protecting data in damaged memory cells by dynamically switching memory mode is provided. The method is adapted to an electronic device having a memory, which has a memory controller and at least one memory module, each of which is consisted of a plurality of memory cells, and the memory cells are divided into a plurality of pages. A power-on self test is executed and a mirror memory mode is activated to protect the data in the memory modules. An uncorrectable error of each page of the memory modules is detected by the memory controller when an operating system reads the memory. If the uncorrectable error in one page is detected, the memory module having the page is determined as a damaged memory module, and the mirror memory mode is switched to a spare memory mode, so as to protect the data in the memory modules. | 05-31-2012 |
20120137169 | METHOD OF DETERMINING DEFECTS IN INFORMATION STORAGE MEDIUM, RECORDING/REPRODUCING APPARATUS USING THE SAME, AND INFORMATION STORAGE MEDIUM - A method of determining whether a defect exists on an information storage medium is provided along with a recording/reproducing apparatus using the same. Such a method comprises: seeking a defect entry whose state information indicates that a defect block or a replacement block has been re-initialized without certification from a defect list for managing an information storage medium and including state information of the defect block and state information of the replacement block, wherein the medium includes a spare area for recording the replacement block to replace the defect block occurring in a user data area on the medium; and certifying the defect block or the replacement block registered in the sought defect entry. As a result, defect information can be effectively rearranged for quick re-initialization without certification in order to improve the performance of a drive system. | 05-31-2012 |
20120151252 | Memory Management to Accommodate Non-Maskable Failures - Methods of memory management are described which can accommodate non- maskable failures in pages of physical memory. In an embodiment, when an impending non-maskable failure in a page of memory is identified, a pristine page of physical memory is used to replace the page containing the impending failure and memory mappings are updated to remap virtual pages from the failed page to the pristine page. When a new page of virtual memory is then allocated by a process, the failed page may be reused if the process identifies that it can accommodate failures and the process is provided with location information for impending failures. In another embodiment, a process may expose information on failure-tolerant regions of virtual address space such that a physical page of memory containing failures only in failure-tolerant regions may be used to store the data instead of using a pristine page. | 06-14-2012 |
20120239969 | BLOCKING WRITE ACCESS TO MEMORY MODULES OF A SOLID STATE DRIVE - Described are embodiments of an invention for blocking write access to memory modules of a solid state drive. The solid state drive includes a controller access module or a memory access module that controls write access to the solid state drive and the memory modules of the solid state drive. Upon determining that a memory module has failed, the failed memory module or the entire solid state memory device is configured to be read only to prevent an errant write of data over critical data. Further, a failed memory module, or solid state device memory having a failed memory module, may be replaced upon failure. | 09-20-2012 |
20120254656 | METHOD, APPARATUS AND SYSTEM FOR PROVIDING MEMORY SPARING INFORMATION - Techniques for implementing memory sparing with a memory controller. In an embodiment, a memory controller stores memory sparing information which is specific to a first line of memory in a memory coupled to and controller by the memory controller. In another embodiment, the memory controller includes a second memory line which is to operate as a spare for the first line of memory, where accessing the second memory line is to be a substitute for accessing the first memory line. | 10-04-2012 |
20120266016 | MEMORY ADDRESS REMAPPING ARCHITECTURE AND REPAIRING METHOD THEREOF - A memory address remapping architecture is applied to execute an address remapping method for repairing a main memory. A valid flag and an essential flag in a TCAM corresponding to at least one subcube address in a spare memory are initialized, and the main memory is checked to find out some faulty cell addresses. The Hamming distance between the subcube address and the faulty cell address is calculated, and the faulty cell address is merged into the subcube address by a masked bits concentrator when the Hamming distance is not larger than an address-width degree of the subcube address and the merged number of the subcube address is not larger than a threshold value. | 10-18-2012 |
20120311380 | CACHE LOCKING CONTROL - Each cache line of a cache has a lockout state that indicates whether an error has been detected for data accessed at the cache line, and also has a data validity state, which indicates whether the data stored at the cache line is representative of the current value of data stored at a corresponding memory location. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. In response to a cache invalidation event, the state of the lockout indicators for each cache line can be maintained so that locked out cache lines remain in the locked out state even after a cache invalidation. This allows memory error management software executing at the data processing device to robustly manage the state of the lockout indicators. | 12-06-2012 |
20130061088 | INFORMATION STORAGE DEVICE AND INFORMATION STORAGE METHOD - An information storage device includes a semiconductor memory divided into storage regions and a management unit. The management unit manages the storage regions so that any storage region which caused read or write errors a predetermined threshold number of times, which may be two or more, is made unavailable for storing data. | 03-07-2013 |
20130073898 | ERROR DETECTION/CORRECTION BASED MEMORY MANAGEMENT - The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith. | 03-21-2013 |
20130086417 | Systems and Methods for Retiring and Unretiring Cache Lines - The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure. | 04-04-2013 |
20130151890 | Methods and Systems for Repairing Memory - In accordance with embodiments of the present disclosure, a method may comprise identifying one or more portions of the memory having defects. The method may also include storing one or more addresses in the memory defect list, each of the one or more addresses associated with a portion of the one or more identified portions. The method may further include indicating to components of an information handling system that the one or more identified portions are unusable such that the other components are prevented from allocating and using the one or more identified portions. | 06-13-2013 |
20130173954 | METHOD OF MANAGING BAD STORAGE REGION OF MEMORY DEVICE AND STORAGE DEVICE USING THE METHOD - A method of managing a bad storage region of a memory device may include detecting a bad page of a selected data block that has failed in one of a program operation, a read operation, and an erase operation on the memory device; and performing a mapping process so that the detected bad page is excluded from a storage region to which data is to be programmed, wherein remaining pages of the selected data block excluding the bad page are allowed to be used as a storage region in a garbage collection operation. | 07-04-2013 |
20130212427 | RECLAIMING DISCARDED SOLID STATE DEVICES - Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced. | 08-15-2013 |
20130227342 | SYSTEMS AND METHODS FOR STORING AND RETRIEVING A DEFECT MAP IN A DRAM COMPONENT - In accordance with the present disclosure, a dynamic random access memory (DRAM) component is described. The DRAM component may comprise an integrated circuit, with the integrated circuit including an array of volatile memory cells. A first volatile memory cells of the array of volatile memory cells may be defective. The integrated circuit may also include non-volatile memory, and the non-volatile memory may contain a reference to the first volatile memory cell. | 08-29-2013 |
20130227343 | Circuits and Methods for Replacing Defective Instructions - An address selector replaces an address pointing to a defective instruction in a built-in firmware. The address selector includes a comparing unit and a multiplexer. The comparing unit provides a comparison result by comparing a current address received from a processor with a predetermined address pointing to the defective instruction. The multiplexer coupled to the comparing unit receives a backup address pointing to a backup instruction, and the current address and if the current address matches the predetermined address, selects the backup address such that the current address is replaced by the backup address | 08-29-2013 |
20130232377 | METHOD FOR REUSING RESOURCE AND STORAGE SUB-SYSTEM USING THE SAME - In a storage sub-system adopting a redundant configuration for preventing data loss and continuing processing during failure, when failure occurs, a controller unit in which failure has occurred is blocked so as not to affect the normal controller unit, so that the performance of the storage sub-system is deteriorated and the redundancy thereof is lost until maintenance and component replacement is performed. According to the present invention, self diagnosis of the blocked area is executed and a failure area is isolated. Then, the blocked area is reconnected to the storage sub-system, so as to prevent deterioration of performance and overload of the device until maintenance and replacement is performed, and to reduce the time of failure analysis during maintenance by specifying the detailed failure area via self diagnosis. | 09-05-2013 |
20130246839 | DYNAMIC HIGHER-LEVEL REDUNDANCY MODE MANAGEMENT WITH INDEPENDENT SILICON ELEMENTS - A Solid-State Disk (SSD) controller enables dynamic higher-level redundancy mode management with independent silicon elements to provide graceful degradation as non-volatile (e.g. flash) memory elements fail during operation of an SSD implemented by the controller. Higher-level error correction provides correction of lower-level uncorrectable errors. If a failure of one of the non-volatile memory elements is detected, then the higher-level error correction is dynamically transitioned from operating in a current mode to operating in a new mode. The transition includes one or more of reducing free space available on the SSD, rearranging data storage of the SSD, recovering/storing failed user data (if possible), and determining/storing revised higher-level error correction information. Operation then continues in the new mode. If another failure of the non-volatile memory elements is detected, then another transition is made to another new mode. | 09-19-2013 |
20130326268 | REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - A repair control circuit and a semiconductor integrated circuit using the same, which can reduce test time, are provided. The semiconductor integrated circuit includes a plurality of memory blocks in which a plurality of word lines are arranged, a plurality of word line drivers driving one or more of the plurality of word lines in response to a plurality of memory block selection signals, and a repair control circuit determining whether to perform a repair through comparison of repair addresses generated in response to surplus addresses and the plurality of memory block selection signals with external addresses. | 12-05-2013 |
20130326269 | APPARATUS, SYSTEM AND METHOD FOR MANAGING SOLID-STATE RETIREMENT - A storage controller is configured to determine a reliability metric of a storage division of a solid-state storage medium based on one or more test read operations. The storage division may be retired based on the reliability metric and/or the age of the data on the storage division. A storage division comprising aged data may be marked for post-write reliability testing, which may comprise determining a post-write reliability metric in response to grooming and/or reprogramming the storage division. The storage controller may project the reliability metric of the storage division to the end of a predetermined data retention period. Portions of a storage divisions that exhibit poor reliability may be removed to improve the reliability of the storage division without taking the entire storage division out of service. | 12-05-2013 |
20130332769 | IN-FIELD BLOCK RETIRING - Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed. | 12-12-2013 |
20130339785 | DYNAMIC CACHE CORRECTION MECHANISM TO ALLOW CONSTANT ACCESS TO ADDRESSABLE INDEX - A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold. | 12-19-2013 |
20140006848 | BAD BLOCK MANAGEMENT MECHANISM | 01-02-2014 |
20140006849 | FAULT-AWARE MAPPING FOR SHARED LAST LEVEL CACHE (LLC) | 01-02-2014 |
20140059377 | DYNAMIC Y-BUFFER SIZE ADJUSTMENT FOR RETAINED SECTOR REPROCESSING - Aspects of the disclosure pertain to a system and method for providing dynamic y-buffer size adjustment for retained sector reprocessing (RSR). The system and method implement dynamic y-buffer size adjustment for RSR for promoting improved Sector Failure Rate (SFR) performance of the system. The system is a read channel system. | 02-27-2014 |
20140089727 | ESTIMATING A PERFORMANCE PARAMETER OF A JOB HAVING MAP AND REDUCE TASKS AFTER A FAILURE - A job profile includes characteristics of a job to be executed, where the characteristics of the job profile relate to map tasks and reduce tasks of the job, and where the map tasks produce intermediate results based on input data, and the reduce tasks produce an output based on the intermediate results. In response to a failure in a system, numbers of failed map tasks and reduce tasks of the job based on a time of the failure are computed, and numbers of remaining map tasks and reduce tasks are computed. A performance model is provided, and a performance parameter of the job is estimated using the performance model. | 03-27-2014 |
20140115383 | MULTIPLE LEVEL CELL MEMORY DEVICE WITH SINGLE BIT PER CELL, RE-MAPPABLE MEMORY BLOCK - A system having a non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Blocks can operate in either a multiple bit per cell mode or a single bit per cell mode. A processor controls the system and selects blocks to operate in the multiple bit per cell mode and single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode. | 04-24-2014 |
20140122923 | Sector Failure Prediction Method and Related System - A method and system is disclosed for identification and removal of a memory sector prone to failure. The method performs satisfaction checks on the memory sector and monitors and stores returned Unsatisfied Checks (USC) for analysis by a pattern recognition algorithm. Once a first global iteration is pattern matched with a second global iteration from the sector, the method determines the period of the repetitive pattern. The method then identifies, as the sector prone to failure, the sector having the defined pattern and period. Once identified, the method uses a power management scheme to remove the sector prone to failure from further use by the memory system and displays to a user the details of the action taken. | 05-01-2014 |
20140136885 | ISOLATING AND CORRECTING VPD DATA MISMATCH AND/OR CORRUPTION - Disclosed is a method of detecting a product data error in a storage system. First and second vital product data (VPD) EEPROMs are read. Indicators of whether wither or both reads failed are received. Based on these indicators, the contents of the VPD EEPROMs may be compared. Based on a result of the comparing indicating a match, an arbitrary one of the VPD EEPROMS is used. Based on an indicator indicating an error with the first VPD EEPROM, the second VPD EEPROM is used. | 05-15-2014 |
20140143593 | MEMORY SEGMENT REMAPPING TO ADDRESS FRAGMENTATION - The techniques discussed herein identify failed segments of memory in a memory region. The techniques may then manage the failed segments of memory by logically clustering the failed segments of memory at an outlying portion of the memory region using a remapping process. The remapping process may include creating and storing remapping metadata defining segment remapping entries for the memory region. Accordingly, the failure clustering logically eliminates or reduces the memory fragmentation so that a system can allocate larger portions of contiguous memory for object storage. | 05-22-2014 |
20140157045 | Memory controller, memory system including the memory controller, and operating method performed by the memory controller - Provided are a memory controller, a memory system including the memory controller, and an operating method performed by the memory controller. The operating method includes operations of queuing a first command in a first queue, detecting a fail of a first address that corresponds to the first command, when the first address is determined as a fail address, queuing a second address and a second command in the first queue, wherein the second address is obtained by remapping the first address and the second command corresponds to the second address, and outputting the second command and the second address from the first queue. | 06-05-2014 |
20140164824 | ERROR DETECTION/CORRECTION BASED MEMORY MANAGEMENT - The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith. | 06-12-2014 |
20140181576 | MEMORY ALLOCATION FOR VIRTUAL MACHINES USING MEMORY MAP - Apparatuses and methods associated with memory allocations for virtual machines are disclosed. In embodiments, an apparatus may include a processor; a plurality of memory modules; and a memory controller configured to provide a layout of the memory modules. The apparatus may further include a VMM configured to be operated by the processor to manage execution of a VM by the processor including selective allocation of the memory modules to the VM using the layout of the memory modules provided to the VMM by the memory controller. Other embodiments may be described and claimed. | 06-26-2014 |
20140181577 | SYSTEMATIC MITIGATION OF MEMORY ERRORS - A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system. | 06-26-2014 |
20140237286 | MEMORY SYSTEM PERFORMING ADDRESS MAPPING ACCORDING TO BAD PAGE MAP - A memory system comprises a nonvolatile memory comprising a memory block having multiple pages, and a controller configured to control the nonvolatile memory to store data in the memory block according to a command and logical address received from an external source. The controller is configured to determine whether the logical address is currently mapped to a bad page of the memory block by referring to a bad page map, and as a consequence of determining that the logical address corresponds to the bad page, remaps the logical address to a different page and stores dummy data in the bad page. | 08-21-2014 |
20140281687 | PERFORMANCE OF A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for improving performance of a system having non-volatile memory (“NVM”). The system can vertically re-vector defective blocks of a user region of the NVM to other blocks having the same plane or die's plane (“DIP”) but corresponding to a dead region of the NVM. Then, the system can select any band with more than one defective block and vertically re-vector one of its defective blocks to a band that has no defective blocks. At run-time, the system can monitor the number of vertical re-vectors per DIP. If at least one vertical re-vector has been performed on all DIPs of the NVM, a band of the user region can be allocated for the dead region. | 09-18-2014 |
20140298088 | DATA CONDITIONING TO IMPROVE FLASH MEMORY RELIABILITY - Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data from a first number of pages or blocks of memory cells having a first density, performing a data handling operation on the read first data to generate second data, and writing the second data to a second number of pages or blocks of memory cells having a second density, wherein the second density is different than the first density, and wherein the second number is different than the first number. | 10-02-2014 |
20140325260 | SLICE MIGRATION IN A DISPERSED STORAGE NETWORK - A dispersed storage unit includes a physical memory and a storage unit control module. The physical memory is transferred to a receiving dispersed storage unit from a transferring dispersed storage unit, which used the transferred physical memory to store encoded data slices prior to the at least one physical memory being transferred. The encoded data slices stored on the transferred physical memory have addresses falling within a first address range. The storage control unit is configured to detect installation of the transferred physical memory, and to notify a dispersed storage network that data slices within the first address range are to be received by and retrieved from the receiving dispersed storage unit. | 10-30-2014 |
20140351629 | MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING - A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error. | 11-27-2014 |
20140372792 | METHOD FOR HEALING RESET ERRORS IN A MAGNETIC MEMORY - A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error; identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state. | 12-18-2014 |
20150033066 | PARTIAL WRITE ERROR RECOVERY - A data storage device may have at least a qualifier circuit that is configured to recognize a write error during a write operation for a single user data sector on a data storage medium and resume the write operation from the location of the write error by skipping at least one user data sub-sector to provide multiple separate original user data sub-sectors that collectively form the single user data sector. | 01-29-2015 |
20150052387 | SYSTEMS AND METHODS UTILIZING A FLEXIBLE READ REFERENCE FOR A DYNAMIC READ WINDOW - A memory system having a flexible read reference is disclosed. The system includes a memory partition, a failcount component, and a controller. The memory partition includes a plurality of memory cells. The failcount component is configured to generate failcounts in response to read operations of the memory partition. The controller is configured to calibrate a reference value for the memory partition by utilizing the failcounts. | 02-19-2015 |
20150127972 | METHOD AND APPARATUS FOR NON-VOLATILE RAM ERROR RE-MAPPING - A memory module comprising a non-volatile cell array and a re-mapper. A page map table is stored in the non-volatile cell array, and includes mappings of old page addresses to new page addresses. The re-mapper is configured to direct memory operations referencing an old page address to the new page address that the old page address is mapped to. The mappings are created when a memory cell is determined to be in a failure state. | 05-07-2015 |
20150127973 | APPARATUS AND METHODS FOR PROVIDING DATA INTEGRITY - The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors. | 05-07-2015 |
20150143166 | SECURITY KEY ENTRY USING ANCILLARY INPUT DEVICE - A physical, non-human readable representation of a digital key may be in a physical key article. The key article may enable a person to generate a signal representing the digital key from a user interface device in communication with a computer by physical manipulation of the key article. Access to digital content via the computer may be unlocked in response to receiving the signal. In addition, a key may be represented by a pattern of unreadable errors in a computer-readable medium. | 05-21-2015 |
20150149818 | DEFECT MANAGEMENT POLICIES FOR NAND FLASH MEMORY - Systems and methods of managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible. The disclosed systems and methods can monitor a plurality of trigger events for detecting possible defects in one or more nonvolatile memory (NVM) devices included in the nonvolatile storage systems, and apply one or more defect management policies to the respective NVM devices based on the types of trigger events that resulted in detection of the possible defects. Such defect management policies can be used proactively to retire memory in the nonvolatile storage systems with increased granularity, focusing the retirement of memory on regions of nonvolatile memory that are likely to contain a defect. | 05-28-2015 |
20150293822 | SYSTEMS AND METHODS FOR RECOVERING FROM UNCORRECTED DRAM BIT ERRORS - Systems, methods, and computer programs are disclosed for recovering from dynamic random access memory (DRAM) defects. One method comprises determining that an uncorrected bit error has occurred for a physical codeword address associated with a dynamic random access memory (DRAM) device coupled to a system on chip (SoC). A kernel page associated with a DRAM page comprising the physical codeword address is identified as a bad page. Recovery from the uncorrected bit error is provided by rebooting a system comprising the SoC and the DRAM device. In response to the rebooting, the identified kernel page is excluded from being allocated for DRAM operation. | 10-15-2015 |
20150317225 | REPAIR CONTROL LOGIC FOR SAFE MEMORIES HAVING REDUNDANT ELEMENTS - Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array. | 11-05-2015 |
20150332736 | Stacked Memory Device Control - A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus. | 11-19-2015 |
20150332789 | SEMICONDUCTOR MEMORY DEVICE PERFORMING SELF-REPAIR OPERATION - A semiconductor memory device includes a memory cell array including a main cell array and a repair cell array, a command controller that controls an input/output operation of the memory cell array, an address generator that stores a repair address, and generates an internal address according to an external address requested to be read or written, an ECC that performs a parity operation for data input/output to the memory cell array, an address table that associates an address, at which a fail has occurred when the fail has occurred in the ECC, with a number of times of occurrence of the fail, and a repair controller that selects a repair address according to the number of times of the occurrence of the fail stored in the address table, and controls the address generator to allow information of the selected repair address to be stored. | 11-19-2015 |
20150347254 | MEMORY ERROR PROPAGATION FOR FASTER ERROR RECOVERY - A method for managing a corrupted memory block. The method includes detecting the corrupted memory block, and removing, after detecting the corrupted memory block, references to the corrupted memory block. The method further includes identifying, after detecting the corrupted memory block, an uncorrupted memory block and analyzing each cache line. The method further includes determining, while analyzing each cache line, that a first cache line includes an uncorrectable error and creating, based on determining the first cache line includes the uncorrectable error, a second cache line including an artificial error, and migrating the second cache line to the uncorrupted memory block, where a layout of the corrupted memory block is maintained. | 12-03-2015 |
20150364218 | Non-Volatile Memory Module with Physical-To-Physical Address Remapping - The various embodiments described herein include systems, methods and/or devices used to enable physical-to-physical address remapping in a storage module. In one aspect, the method includes, for each of a sequence of two or more units of non-volatile memory, determining a validity state of a respective unit of memory. In accordance with a determination that the validity state of the respective unit of memory is an invalid state, the method includes storing, in a table, a second address assigned to the respective unit of memory. At least a portion of the second address is a physical address portion corresponding to a physical location of a second unit of memory. In accordance with a determination that the validity state of the respective unit of memory is a valid state, the method includes forgoing assignment of the second address corresponding to the unit of memory. | 12-17-2015 |
20150380109 | APPARATUSES AND METHODS FOR MEMORY TESTING AND REPAIR - Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information. | 12-31-2015 |
20160041878 | Failure Mapping in a Storage Array - A storage cluster is provided. The storage cluster includes a plurality of storage nodes within a chassis. The plurality of storage nodes has flash memory for storage of user data and is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the storage nodes is configured to generate at least one address translation table that maps around defects in the flash memory on one of a per flash package basis, per flash die basis, per flash plane basis, per flash block basis, per flash page basis, or per physical address basis. Each of the plurality of storage nodes is configured to apply the at least one address translation table to write and read accesses of the user data. | 02-11-2016 |
20160077939 | RECOVERING FROM UNCORRECTED MEMORY ERRORS - A method for recovering from uncorrected memory errors may include receiving, at an operating system, a correctable error (CE) associated with a first memory page. The correctable error is marked in a page table entry describing the first memory page. The first memory page is then migrated, by the operating system, to a second memory page based on the received correctable error. | 03-17-2016 |
20160077941 | IDENTIFYING A DEFECT IN A DATA-STORAGE MEDIUM - An embodiment of a data-read path includes a defect detector and a data-recovery circuit. The defect detector is operable to identify a defective region of a data-storage medium, and the data-recovery circuit is operable to recover data from the data-storage medium in response to the defect detector. For example, such an embodiment may allow identifying a defective region of a data-storage disk caused, e.g., by a scratch or contamination, and may allow recovering data that was written to the defective region. | 03-17-2016 |
20160085612 | HEALTH MANAGEMENT OF NON-VOLATILE MEMORY - An apparatus for controlling programming of a non-volatile memory including at least one block partitioned into a plurality of physical sections, each of the physical sections comprising a plurality of memory cells, the apparatus including a controller configured to access a table including information corresponding to individual ones of the plurality of physical sections. The controller is configured to identify a first programming method for a first physical section of the plurality of physical sections and identify a second programming method for a second physical section of the plurality of physical sections according to information in the table corresponding to the first and second physical sections. The controller is also configured to program the first and second physical sections according to the first and second programming methods for the first and section physical sections, respectively. | 03-24-2016 |
20160093404 | METHOD AND APPARATUS FOR REVERSE MEMORY SPARING - An apparatus and method are described for performing forward and reverse memory sparing operations. For example, one embodiment of a processor comprises memory sparing logic to perform a first forward memory sparing operation at a first level of granularity in response to detecting a memory failure; the memory sparing logic to perform a reverse memory sparing operation in response to a determination of an improved sparing state having a second level of granularity; and the memory sparing logic to responsively perform a second forward memory sparing operation at the second level of granularity. | 03-31-2016 |
20160132406 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device includes memory devices including respective main regions and respective virtual regions, and a processor suitable for forming a super page by selecting main pages from the respective main regions, wherein when a main page of a main region in a memory device is a bad region, the processor forms a virtual super page by selecting a virtual page from a virtual region in the memory device instead of the main page. | 05-12-2016 |
20160140004 | APPARATUS, SYSTEM, AND METHOD FOR CONDITIONAL AND ATOMIC STORAGE OPERATIONS - An apparatus, system, and method are disclosed for implementing conditional storage operations. Storage clients access and allocate portions of an address space of a non-volatile storage device. A conditional storage request is provided, which causes data to be stored to the non-volatile storage device on the condition that the address space of the device can satisfy the entire request. If only a portion of the request can be satisfied, the conditional storage request may be deferred or fail. An atomic storage request is provided, which may comprise one or more storage operations. The atomic storage request succeeds if all of the one or more storage operations are complete successfully. If one or more of the storage operations fails, the atomic storage request is invalidated, which may comprise deallocating logical identifiers of the request and/or invalidating data on the non-volatile storage device pertaining to the request. | 05-19-2016 |
20160147623 | RANK AND PAGE REMAPPING LOGIC IN A VOLATILE MEMORY - Embodiments of the inventive concept include a plurality of memory ranks, a buffer chip including a rank remap control section configured to remap a rank from among the plurality of memory ranks of the volatile memory module responsive to a failure of the rank, and a dynamic serial presence detect section configured to dynamically update a stated total capacity of the volatile memory module based at least on the remapped rank. In some embodiments, a memory module includes a plurality of memory ranks, an extra rank in addition to the plurality of memory ranks, the extra rank being a spare rank configured to store a new page corresponding to a failed page from among the plurality of ranks, and a buffer chip including a page remap control section configured to remap the failed page from among the plurality of ranks to the new page in the extra rank. | 05-26-2016 |
20160147624 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device and a method of operating the same are provided. The method includes determining the degree of deterioration of a selected memory block, performing a program operation of the selected memory block in a first program operating condition when it is determined that the selected memory block is not deteriorated and performing the program operation of the selected memory block in a second program operating condition when it is determined that the selected memory is deteriorated, and updating the program operating time of the selected memory block. | 05-26-2016 |
20160162375 | DATA STORAGE DEVICE FOR SELF-DETECTING ERROR AND LOGGING OPERATION AND METHOD OF OPERATING THE SAME - A method of operating a data storage device which is provided with an operating voltage from a host and communicates with the host is provided. The method includes converting an operation mode of the data storage device into a debugging mode in response to a log start command transmitted from the host, receiving a first operation command from the host and executing the first operation command, generating first log information corresponding to a result of executing the first operation command, storing the first log information in a first storage area of memory of the data storage device, and copying at least part of the first log information from the first storage area to a second storage area of the memory of the data storage device when an event occurs according to the result of executing the first operation command. | 06-09-2016 |
20160179609 | Bad Sector Repair Method and Apparatus | 06-23-2016 |
20160179645 | SYSTEMS AND METHODS FOR FINE GRANULARITY MEMORY SPARING | 06-23-2016 |
20160378620 | REMAPPING OF MEMORY IN MEMORY CONTROL ARCHITECTURES - In accordance with embodiments disclosed herein, there is provided systems and methods for remapping of memory in memory control architectures. A processing device includes a processing core and a platform controller hub (PCH) coupled to the processing core. The PCH is to receive an indication of a failure associated with a first memory region of a plurality of memory regions residing in a memory. The PCH is also to interrupt an operating system to prompt for a reboot. Upon the reboot, the PCH is to remap a memory address range associated with the first memory region to a second memory region of the plurality of regions. | 12-29-2016 |