Entries |
Document | Title | Date |
20100271057 | Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit - A test setup for estimating the critical charge of a circuit under test (CUT) uses a charge injection circuit having a switched capacitor that is selectively connected to a node of the CUT. A voltage measurement circuit measures the voltage at a tap in the charge injection circuit before and after the charge is injected. When the injected charge causes an upset in the logical state of the CUT, the critical charge is calculated as the product of the voltage difference and the known capacitance of the capacitor. In one embodiment, (NMOS drain strike simulation) the amount of charge injected is controlled by a variable pulse width generator gating the switch of the charge injection circuit. In another embodiment (PMOS drain strike simulation) the amount of charge injected is controlled by a variable voltage supply selectively connected to the charge storage node. | 10-28-2010 |
20110084717 | CORRECTED OPTICAL SPECTRAL RESPONSES FOR PHOTOELECTRIC DEVICES - A system for measuring an optical spectral response of a photoelectric device under test (DUT) includes a spectrally programmable light source including in optically coupled sequence a broadband light source for emitting light, a dispersive element for dispersing light, and a spatial light modulator for controlling an intensity and a spectra of the light to provide a spectrally programmable light beam. A light distributing device having at least one input portion is coupled to receive the spectrally programmable light beam and includes a light distributing structure for distributing the spectrally programmable light beam in a known ratio to a first area and at least a second area. A reference detector having a reference output positioned at the first area, and the DUT is positioned at the second area. Data acquisition electronics and a processor can receive simultaneously generated output signals from the DUT and the reference detector to correct for intensity variation in the spectrally programmable light beam in determining the optical spectral response of the DUT. | 04-14-2011 |
20110102004 | METHOD FOR TESTING A LABORATORY DEVICE AND CORRESPONDINGLY EQUIPPED LABORATORY DEVICE - The invention relates to devices for liquid level detection (LLD). It relates to a laboratory device having an electronic circuit for detecting a liquid level in a liquid container, a feeler, which can be advanced, and which is connected to an input side of the electronic circuit, and having a movement device, which allows the feeler to be advanced in the direction of the liquid in the liquid container. Upon the immersion of the feeler in the liquid, a capacitance change is caused in the electronic circuit, which triggers a signal in the circuit. The laboratory device comprises a reference circuit, which is connected to the input side of the circuit, and which specifies an effective capacitance on the input side of the circuit. A sequence controller is used, which causes the triggering of a test by the application of a control signal to the reference circuit, the control signal causing an increase of the effective capacitance through a switching procedure. The processing of the corresponding capacitance change is monitored by the sequence controller, for example. | 05-05-2011 |
20110109334 | Method for Detecting Component Defects of an Analog Signal Processing Circuit, Especially for a Measurement Transmitter - A method for detecting component defects of an analog signal processing circuit, especially for a measurement transmitter. A test signal TS is generated at a first test point TP | 05-12-2011 |
20110128020 | TEST APPARATUS AND POWER SUPPLY APPARATUS - Provided is a test apparatus that tests a device under test, comprising a plurality of capacitors that are each charged to a predetermined voltage; a switching section that switches which of the capacitors charged to a predetermined voltage supplies power to the device under test; and a judging section that judges acceptability of the device under test based on an operational result of the device under test. Also provided is a test apparatus that selects one of a plurality of capacitors and a corresponding one of a plurality of power supply units, according to content of a test performed after a test that uses another of the capacitors to supply power to the device under test. | 06-02-2011 |
20110133763 | CIRCUIT FOR SIMULATING AN ELECTRICAL LOAD - A circuit for simulating an electrical load at a terminal of a test circuit having at least one first switch and at least one second switch includes a third switch connected to the first switch of the test circuit via a first external connection point. A fourth switch is connected to the second switch of the test circuit via a second external connection point. The first switch and the second switch are connected via a shared, first internal connection point to the terminal of the test circuit and the third switch and the fourth switch are connected via a shared, second internal connection point such that that the first switch, the second switch, the third switch and the fourth switch form an H-bridge circuit. A voltage source is configured to provide the first and second external connection points with a supply voltage. A controllable voltage source is connected in a transverse bridge branch between the terminal and the second internal connection point. An inductance is active in the transverse bridge branch. A current-control unit is operable on the controllable voltage source so as to adjust, to a predetermined setpoint current, an actual current flowing over the terminal of the test circuit and over the transverse bridge branch. | 06-09-2011 |
20110148444 | CIRCUIT FOR TESTING INTERNAL VOLTAGE OF SEMICONDUCTOR MEMORY APPARATUS - An internal voltage test circuit of a semiconductor memory apparatus includes a comparing unit for comparing a level of internal voltage with a level of external voltage to output a comparison result as an output signal during a test mode, and an output selecting unit for outputting the output signal to a data output pad during the test mode, and outputting a data signal to the data output pad during a normal operation mode. | 06-23-2011 |
20110156729 | TEST APPARATUS AND TEST METHOD - A test apparatus and a test method with which a circuit size can be decreased are provided. A recovered clock generating circuit generates a recovered clock of which phase is approximately the same as a phase of output data output by a device under test (DUT). The recovered clock generating circuit includes a phase comparator that compares a phase of the output data of the DUT to a phase of the recovered clock to generate a phase difference signal, a binary counter of which output value is incremented or decremented based on the phase difference signal, a control signal generating section that generates a control signal based on an output value of the binary counter, and a phase shifter that shifts the phase of the reference clock based on the control signal. | 06-30-2011 |
20110163771 | TEST APPARATUS AND DRIVER CIRCUIT - A test apparatus includes: a driver circuit that supplies, to a device under test, a test signal corresponding to an input signal; and a judging section that judges pass/fail of the device under test, based on the load voltage or the load current supplied to the device under test when supplying a test signal of a constant current or a constant voltage to the device under test from the driver circuit, where the driver circuit includes: a driver section that outputs the test signal; a supply current detecting section that detects a supply current supplied to the driver section; and an output control section that controls a voltage or a current of the test signal outputted from the driver section to the predetermined value, based on the supply current detected by the supply current detecting section. | 07-07-2011 |
20110204906 | Wideband I-V probe and method - Low loss current and voltage probes are integrated in parallel plate airlines (slablines) to be used either as separate modules inserted between tuner and DUT in load pull test setups, or integrated in the impedance tuners themselves. The probes are inserted orthogonally at exactly the same reference plane relative to the DUT, maximizing bandwidth and the minimizing deformation of the detected electric and magnetic fields. The probes are used to detect the actual voltage and current waveforms and feed into an amplitude-and-phase calibrated high speed oscilloscope, including several harmonic frequencies. The actual real time voltage and current time domain waves are transformed into the frequency domain using fast Fourier transformation (FFT), de-embedded to the DUT reference plane and inverse transformed into the time domain using inverse Fourier transformation (FFT | 08-25-2011 |
20110204907 | METHOD AND SYSTEM FOR LOW-POWER THREE-PHASE DETECTION - A method and a system for three-phase detection of a three-phase electric device are provided. The system includes a testing circuit and a comparison module. The testing circuit generates two reference voltages by using the three phase voltages of the three-phase electric device. The two reference voltages are the first and second phase voltages with reference to the third phase voltage, respectively. Three-phase detection is performed by comparing the two reference voltages for a determined number of times. After testing is completed, the testing circuit is switched off by the comparison module, to save power. | 08-25-2011 |
20110227592 | Method And Arrangement For Through-Line Mismatch RF Testing - The present invention relates to a method and an arrangement of facilitating through-line mismatch RF testing using an air-isolated coaxial line ( | 09-22-2011 |
20110248733 | TEST APPARATUS AND TEST METHOD - A test apparatus that tests a device under test having a plurality of blocks operating asynchronously, based on a signal received from outside, the test apparatus comprising a plurality of domain test units corresponding respectively to the blocks; and a main body unit that controls the domain test units. The main body unit includes a reference operation clock generating section that generates a reference operation clock supplied to each domain test unit, and a test start signal generating section that generates a test start signal instructing each domain test unit to start the testing. Each domain test unit includes a test clock generating section that generates a test clock based on the reference operation clock, and generates a test signal for testing the corresponding block based on the test clock obtained by the test clock generating section, and each domain test unit starts generating the test signal on a condition that the test start signal is received. | 10-13-2011 |
20110267081 | METHOD AND SYSTEM TO VERIFY THE RELIABILITY OF ELECTRONIC DEVICES - To verify robustness with respect to electrical overstresses of an electronic circuit under test, the latter is exposed to electrical overstresses, and the behavior thereof is monitored. In particular, both the testing of the electronic circuit in dynamic conditions is performed by causing it to be traversed by the currents that characterize operation thereof, and by exposing at least one supply line of the electronic circuit under test to electrical overstresses and the testing of the electronic circuit under test in static conditions, without causing it to be traversed by the currents that characterize operation thereof, and by exposing to electrical overstresses both the supply and the input and/or output lines of the electronic circuit under test. The device for generating the overstresses can be mounted on a circuit board, which can be coupled as daughter board to a mother board, on which the electronic circuit under test is mounted. | 11-03-2011 |
20110291679 | TESTING INTEGRATED CIRCUITS - A method of testing integrated circuits is provided. The method includes establishing at least one first physical communication channel between a test equipment and a respective group of integrated circuits under test by having probes of the test equipment contacting at least one corresponding physical contact terminal of each integrated circuit of the respective group. The method further includes having the test equipment exchanging, over the at least one first physical communication channel, the same test stimuli with each integrated circuit of the group. The method still further includes having each integrated circuit of the group establishing a corresponding second physical communication channel with the test equipment by having at least one physical contact terminal of the integrated circuit contacted by a corresponding probe of the test equipment. The method further includes having each integrated circuit of the group exchanging, over the second physical communication channel, a corresponding test response signal based on the received test stimuli with the test equipment. The test stimuli are exchanged by modulating at least one first carrier wave based on the test stimuli; the at least one first carrier wave has at least one first frequency. The test response signals of each integrated circuit of the group are exchanged by modulating at least one respective second carrier wave based on the test response signals; each second carrier wave have at least one respective second frequency. | 12-01-2011 |
20110298483 | TESTER HAVING DEVICE UNDER TEST POWER SUPPLY - A tester includes a device under test (DUT) power supply (DPS) with and input and output includes an amplifier configured to set an output voltage of the DPS output equal to an input voltage for the DPS. The DPS has a first output stage coupled to the amplifier and configured to source and sink current at the output of the DPS between a first voltage rail and a third voltage rail. The | 12-08-2011 |
20110304348 | Apparatus for Driving Placing Table - Disclosed is an apparatus for driving a placing table that contributes to saving a space and reducing the weight of an inspecting apparatus. The apparatus for driving a placing table according to an exemplary embodiment of the present disclosure includes a horizontal driving mechanism that horizontally moves a placing table in an inspecting chamber, a base that supports horizontal driving mechanism, a placing table lifting mechanism (for example, air bearing) that lifts placing table from support, using compressed air in inspecting chamber, a connecting mechanism that connects horizontal driving mechanism with placing table, and a case that accommodates the horizontal driving mechanism and the base. | 12-15-2011 |
20120019272 | PIN CARD AND TEST APPARATUS USING THE SAME - A DUT is connected to an I/O terminal. An AC test unit performs an AC test operation for the DUT. A DC test unit performs a DC test operation for the DUT. An optical semiconductor switch is arranged such that a first terminal thereof is connected to the AC test unit and a second terminal thereof is connected to the I/O terminal. The optical semiconductor switch | 01-26-2012 |
20120032694 | IN-PROCESS ELECTRICAL CONNECTOR - Characteristics of partially assembled photovoltaic modules can be determined using electrical connection apparatuses and methods. | 02-09-2012 |
20120062255 | TEST CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME - A test circuit is capable of easily testing the standby function of an interface block. The test circuit is used for the interface block disposed on a semiconductor integrated circuit which is switched between a standby mode and a non-standby mode and conducting interfacing between the semiconductor integrated circuit and the outside in the non-standby mode, generating a fixed voltage and outputting the same to a corresponding signal line in the standby mode. The test circuit is disposed on the semiconductor integrated circuit and generates a current in accordance with the voltage level of the signal line in the standby mode. | 03-15-2012 |
20120081137 | TESTING METHOD FOR SEMICONDUCTOR INTEGRATED ELECTRONIC DEVICES AND CORRESPONDING TEST ARCHITECTURE - A testing method is described of at least one device provided with an integrated testing circuit and in communication with at least one tester where messages/instructions/test signals/information are exclusively sent from the tester to the device . A testing architecture is also described for implementing this testing method. | 04-05-2012 |
20120092033 | MEASUREMENT OF ELECTRICAL AND MECHANICAL CHARACTERISTICS OF LOW-K DIELECTRIC IN A SEMICONDUCTOR DEVICE - Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer. | 04-19-2012 |
20120098556 | Zero Ampere Level Current Data Correction for a Power Device Under Test - An apparatus and method corrects for zero ampere level current fluctuations in a current signal. First and second acquisition circuitry generate respective current and voltage data samples of the current signal. Current fluctuation data samples representative of zero ampere level deviations of the current signal are extracted corresponding to Off-periods of the current signal. The current fluctuation data samples of the Off-periods are interpolated to generate current fluctuation data samples representative of zero ampere level deviations of the On-periods of the current signal. The Off-period and On-period current fluctuation data samples are subtracted from the current data samples of the current signal to generate corrected zero ampere level current data samples. | 04-26-2012 |
20120119764 | TEST MODE CONTROL CIRCUIT OF SEMICONDUCTOR APPARATUS AND CONTROL METHOD THEREOF - Various embodiments of a test mode control circuit of a semiconductor apparatus and related methods are disclosed. In one exemplary embodiment, the test mode control circuit may include: a test mode control block configured to generate a plurality of control signal sets in response to a first address signal set and a second address signal set which are sequentially inputted; a test mode transfer block configured to transfer a plurality of test mode signals, which are generated according to a combination of the plurality of control signal sets, to a plurality of circuit blocks of the semiconductor apparatus; and a plurality of global lines configured to transmit the plurality of control signal sets to the test mode transfer block. | 05-17-2012 |
20120119765 | BATTERY SIMULATION SYSTEM HAVING FAULT SIMULATION - A battery emulation device for simulating a battery cell voltage at a terminal of a battery control unit in accordance with a setpoint value includes a control unit configured to determine the setpoint value and provide the determined setpoint value via a galvanically isolated interface; and at least one emulation channel, each including: a voltage source; an amplifier unit; connection lines for connecting the emulation channel; measurement lines; and a fault simulation device configured to simulate fault states. | 05-17-2012 |
20120126839 | METHOD AND DEVICE FOR MONITORING THE INSULATION OF UNGROUNDED DC AND AC VOLTAGE NETWORKS - The invention relates to a method and a device for monitoring the insulation of an ungrounded DC and/or AC voltage network. The method comprises the following steps: (a) generating a measurement DC voltage U | 05-24-2012 |
20120133380 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus comprising a plurality of testing sections and a synchronizing section that synchronizes operation of at least two testing sections among the plurality of testing sections. Each testing section transmits a synchronization standby command to the synchronizing section when a predetermined condition is fulfilled during execution of the corresponding program and the testing section enters a synchronization standby state, and on a condition that the synchronization standby commands have been received from all of one or more predetermined testing sections among the plurality of testing sections, the synchronizing section supplies a synchronization signal, which ends the synchronization standby state, in synchronization to two or more predetermined testing sections among the plurality of testing sections. | 05-31-2012 |
20120139566 | METHOD FOR PERFORMING BURN-IN TEST - Provided is a method for performing a burn-in test on an object under test in which a plurality of electrodes are provided in positions at different heights. The method comprising steps of: preparing an object under test in which an electrode in a higher position have a higher surface roughness among the plurality of electrodes; bringing a plurality of sheet-type probes into contact with the plurality of electrodes, respectively; and supplying an electric current with the plurality of electrodes through the plurality of sheet-type probes. By implementing the method, the sheet-type probes can be kept in stable contact with the electrodes because electrodes in a higher position have a higher surface roughness Ra than electrodes in a lower position. Consequently, stable and reliable burn-in test can be performed. | 06-07-2012 |
20120139567 | SWITCHING APPARATUS AND TEST APPARATUS - Provided is a switching apparatus that switches a connection state between two terminals, comprising a switch that switches the connection state between the two terminals according to a control voltage supplied thereto; a driving section that provides the switch with the control voltage corresponding to a control signal supplied thereto; and a changing section that changes the control voltage output from the driving section, according to a designated switching time. The changing section may change power supplied as a power supply to the driving section, according to the designated switching time. The changing section may change the control voltage output from the driving section prior to switching of the switch. | 06-07-2012 |
20120139568 | SEMICONDUCTOR DEVICE INCLUDING INTEGRATED CIRCUIT - A semiconductor device that can be manufactured with reduced costs and that includes a first connecting terminal, a second connecting terminal, a third connecting terminal, and a first circuit module configured to operate in response a first signal and a second signal. When a mode signal is in a first state, the first circuit module receives the first signal from the first connecting terminal and receives the second signal from the second connecting terminal. Otherwise, when the mode signal is in a second state, the first circuit module receives the first signal from the first connecting terminal and receives the second signal from the third connecting terminal. A memory module including at least one such memory device may also be provided. | 06-07-2012 |
20120153974 | TEST APPARATUS - Provided is a test apparatus that tests a device under test, comprising a power supply section that generates a power supply voltage to be supplied to the device under test; an inductive load section provided in a path between the power supply section and the device under test; a plurality of semiconductor switches connected in series in a path between the inductive load section and the device under test; and a control section that turns OFF the semiconductor switches when a supply of voltage to the device under test is stopped. | 06-21-2012 |
20120153975 | DRIVER CIRCUIT - A branch circuit branches an input signal to be transmitted into multiple paths. Each timing adjustment circuit applies a delay to at least one from among a positive edge and a negative edge of a signal to be transmitted, which has been branched into a corresponding path. A combining output circuit combines the output signals of the multiple timing adjustment circuits, and outputs the signal thus combined to a transmission line. | 06-21-2012 |
20120153976 | DEVICE WITH OVERVOLTAGE PROTECTION AND METHOD FOR ITS TESTING - Exemplary embodiments are directed to a device with overvoltage protection that includes a varistor which can be connected by a first connection via a first line to high-voltage potential in a circuit arrangement, while a second connection is connected to ground via a second line. Furthermore, an additional impedance is provided, which can be connected between the second connection and ground or the first connection and the high voltage, or is mounted fixed in this position. The corresponding line can be interrupted by a switching arrangement. In order to test the withstand voltage of the circuit arrangement, at least one of the first and second line is interrupted and an additional impedance is inserted. A test voltage is applied to the circuit arrangement. After the overvoltage test, the interruption in at least one of the first and second lines is removed again. | 06-21-2012 |
20120161800 | MEASUREMENT CIRCUIT AND TEST APPARATUS - Provided is a measurement circuit that measures a signal under measurement input thereto, comprising a level comparing section that outputs a logic value according to a comparison result between a signal level of the signal under measurement and a set threshold level; a logic comparing section that acquires the logic value output by the level comparing section at a comparison timing input thereto; and a timing adjusting section that adjusts relative phases of a signal output by the level comparing section and the comparison timing, based on the expected value pattern of the signal under measurement and the threshold level. | 06-28-2012 |
20120161801 | SOLAR PHOTOVOLTAIC POWER GENERATION MODULE AND INSPECTING METHOD - A solar photovoltaic power generation module includes: plural cells connected in series with one another, and generating electric powers in correspondence to lights received; and plural bypass portions bypassing the plural cells, respectively, in accordance with an operation made from an outside. | 06-28-2012 |
20120161802 | DIGITAL CIRCUIT TESTABLE THROUGH TWO PINS - A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin. | 06-28-2012 |
20120169359 | METHOD AND SYSTEM FOR TESTING AN ELECTRIC CIRCUIT - Embodiments include a method and system for testing an electric circuit. A carrier signal of a first frequency is modulated with a multi-tone signal to generate a test signal. The test signal is applied to an input of a circuit under test (CUT). A crest factor of an output signal that corresponds to the test signal received at an output of the CUT is measured. A crest factor differential between the measured crest factor and a reference crest factor is determined. If the crest factor differential exceeds a threshold value, the CUT is determined to be defective. | 07-05-2012 |
20120169360 | SYSTEM AND METHODS FOR TESTING ELECTRICAL POWER SYSTEM COMPONENTS - A power system includes a prime mover drivingly connected to an electric generator. The power system may also include an electric power load, an electrical energy storage device, and power-system controls. The power-system controls may be configured to selectively operate the prime mover and the electric generator to power the electric power load by supplying electricity at a first voltage. The power-system controls may also be configured to selectively supply electricity from the electrical energy storage device at a second voltage during testing of one or more electrical components of the power system with the electricity supplied at the second voltage. The second voltage may be lower than the first voltage. | 07-05-2012 |
20120182031 | Test apparatus and test method - Provided is a test apparatus that tests a device under test, comprising an inductance load section that is provided in a path through which test current flows to the device under test and that has an inductance component; a switching section that switches whether the test current is supplied to the device under test from the inductance load section; a cut-off control section that severs the path by switching the switching section according to a state of the device under test; and a voltage control section that controls voltage of the path between the inductance load section and the switching section to be no greater than a predetermined clamp voltage. | 07-19-2012 |
20120187967 | VOLTAGE LIMITING TEST SYSTEM AND ASSISTANT TEST DEVICE - A voltage limiting test system used to test limit voltage values of a memory includes a voltage limiting test device and an assistant test device connected to the voltage limiting test device. The voltage limiting test device includes a button to adjust a voltage of the memory. The assistant test device includes a first timer, and first and second relays. The first relay is used to receive a state signal of the motherboard, to determine whether the first timer is powered according to the state signal. The second relay is used to receive the pulse signal output by the first timer when the first timer is powered, to trigger the button to adjust the voltage of the memory per a reference time. When the motherboard stops working, the voltage value of the memory is a limit voltage value of the memory. | 07-26-2012 |
20120187968 | TEST APPRATUS - Provided is a test apparatus that tests a device under test, comprising a power supply section that supplies the device under test with power; a comparing section that detects a characteristic value indicating a state of the device under test and compares the characteristic value to a predetermined threshold value; a cutoff section that cuts off the power supplied from the power supply section to the device under test, based on a result of the comparison by the comparing section; and a control section that changes at least one of the threshold value of the comparing section and a detection timing at which the characteristic value is detected. | 07-26-2012 |
20120194206 | Measuring Apparatus - A test for connecting a transmitter and a receiver of a device under test with each other is carried out by a measurement device. The measurement device | 08-02-2012 |
20120194207 | METHOD AND SYSTEM FOR TESTING OF MEMS DEVICES - Some embodiments provide methods, process, systems and apparatus for use in testing multi-axis Micro Electro Mechanical Systems (MEMS) devices. In some embodiments, methods of testing are provided, comprising: selecting, according to a test specification and a test program, at least a first MEMS device on a substrate comprising a plurality of MEMS formed relative to the substrate and applying one or more electrical probes to the first MEMS device; providing power to the first MEMS device through the one or more electrical probes; measuring output signals of the first MEMS device; applying a force to the first MEMS device using a force actuator; measuring a set of output signals of the first MEMS device based on the applied force; and processing test data and generating output test results according to the test specification and test program. | 08-02-2012 |
20120194208 | Coaxial Four-Point Probe for Low Resistance Measurements - Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance. | 08-02-2012 |
20120212244 | Test Board and Method of Using Same - A test board is provided. The test board includes a test module configured to accommodate an integrated circuit (IC) device and first wirelessly enabled functional blocks located in the test module and configured to communicate with second wirelessly enabled functional blocks of the IC device. | 08-23-2012 |
20120217985 | TEST APPARATUS AND TEST METHOD - There is provided a test apparatus that is capable of applying, to a device under test, a current that rises within a short period. A test apparatus for testing a device under test, includes a current source that supplies the device under test with a current, a dummy load that has an electrical characteristic corresponding to an electrical characteristic of the device under test, and a switching section that switches whether the current source is connected to the dummy load or the device under test. Here, after connecting the current source to the dummy load, the switching section disconnects the current source from the dummy load and connects the current source to the device under test when a voltage applied to the dummy load reaches a voltage within a predetermined range. | 08-30-2012 |
20120242357 | AUTOMATIC FAULT INSERTION, CALIBRATION AND TEST SYSTEM - An automatic fault insertion and test (FIT) system provides an interface between a unit under test and test equipment that can be configured to allow for automatic fault insertion, testing and calibration of the test equipment. The FIT system includes an input connection terminal for connection to the UUT, an output connection terminal for connection to the test equipment and a plurality of bus circuit binding posts that can be connected to external devices. The FIT system includes a plurality of switch matrices and a plurality of common buses. Each switch matrix is connected to an input contact associated with the input connection terminal and an output contact associated with the output connection terminal, and each of the plurality of common buses. Selective control of the switches within each switch matrix allow the input contacts to be connected to the associated output contact, the input contacts to be connected to each of the four common buses, and the output contacts to be connected to each of the four common buses. | 09-27-2012 |
20120242358 | Method and Device for Performing Diagnostics of an Actuator, and Actuator Comprising One Such Device - A diagnostic method of an actuator comprising a coil and a control device of power supply of the coil, comprising the following steps:
| 09-27-2012 |
20120249169 | METHOD AND SYSTEM FOR TESTING TRANSPONDERS - The invention relates to a method and system for testing remote transponders. In the method, a radio-frequency transponder is excited with the aid of a first electromagnetic field and the response of the radio-frequency transponder is measured with the aid of a second electromagnetic field. According to the invention, one of said fields is a radiating field and the other of said fields is a reactive field. The invention eliminates the need to test transponders separately from other transponders and the need to inactivate or screen other transponders in the vicinity of the transponder being measured. | 10-04-2012 |
20120256648 | Method and Apparatus for In-Situ Health monitoring of Solar Cells in Space - Embodiments of the present invention describe an apparatus including an oscillator, a ramp generator, and an inverter. The oscillator is configured to generate a waveform comprising a low time and a high time. The inverter is configured to receive the waveform generated by the oscillator, and invert the waveform. The ramp generator is configured to increase a gate control voltage of a transistor connected to a solar cell, and rapidly decrease the gate control voltage of the transistor. During the low time, a measurement of a current and a voltage of the solar cell is performed. During the high time, a measurement of a current of a shorted cell and a voltage reference is performed. | 10-11-2012 |
20120274344 | TESTING SYSTEM FOR PRINTED CIRCUIT BOARD - A test system includes a testing power supply unit which includes a rectifier and filter circuit and a voltage output circuit, a dropping voltage circuit which includes a primary coil and a secondary coil, a PWM regulator, and a control circuit. The rectifier and filter circuit receives an AC voltage and converts the AC voltage into a square wave signal. The primary coil is connected to the rectifier and filter circuit and receives the square wave signal. The secondary coil is connected to the voltage output circuit. The PWM regulator is connected to the primary coil. The PWM regulator generates a pulse signal to turn on and turn off the primary coil periodically. The control circuit is connected to the PWM regulator. The control circuit controls a duty cycle of the pulse signal to adjust time of the primary coil being on in a cycle. | 11-01-2012 |
20120293195 | METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUITS - Aspects of the disclosure provide a testing method. The method includes supplying a power supply from a voltage regulator to a device under test (DUT). The DUT includes an adaptive voltage scaling module configured to generate a feedback signal in response to the power supply. Further, the method includes receiving the feedback signal from the DUT to the voltage regulator to regulate the power supply based on the feedback signal from the DUT, and determining whether the DUT meets a specified performance requirement while the voltage regulator regulates the power supply provided to the DUT based on the feedback signal received from the DUT. | 11-22-2012 |
20120299606 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, the test apparatus comprising a data acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal output by the device under test; a masking section that masks the acquisition of data by the data acquiring section, while the device under test is not outputting the clock signal; and a judging section that judges pass/fail of the device under test based on a result of a comparison between the data signal acquired by the data acquiring section and an expected value. | 11-29-2012 |
20120299607 | Testing of Defibrillator Electrodes - Systems and methods for testing defibrillator electrode conductivity. Connection for electrically connecting electrodes and defibrillation signal generator connected to the electrodes. Patient impedance measurement system comprising patient signal generator and patient signal receiver. A defibrillator controller connected to defibrillation signal generator and patient impedance measurement system. An electrode test system with control signal device connected to the patient signal receiver which generates at least one control signal causing the patient signal receiver to change from a patient signal receive state to an electrode test signal receive state, a test commence signal device connected to the patient signal generator which generates at least one test commence signal causing the patient signal generator to send a test signal to the electrodes and an electrode test signal device connected to the patient signal receiver which receives an electrode test signal and processes the signal to determine a test result. | 11-29-2012 |
20120306517 | Compensation Methods for Digital Source-Measure-Units (SMUs) - A source-measure unit (SMU) may be implemented with respective digital control loops for output voltage and output current. The output voltage and output current may be measured with dedicated ADCs (analog-to-digital converters). The readings obtained by the ADCs may be compared to a setpoint, which may be set in a digital loop controller. The digital loop controller may be used to produce an output to drive a DAC (digital-to-analog converter) until the output voltage and/or output current and/or a function thereof reach the respective desired levels. The digital loop controller may implement respective integrating functions for the respective digital control loops, and may also implement a compensation function featuring pole-zero pairs to stabilize the respective current/voltage outputs. Coefficients of the compensation function may be calculated based on user programmable parameters corresponding to the gain bandwidth product, compensation frequency, and ratio of the added pole-zero frequencies. | 12-06-2012 |
20120306518 | Fast Current Saturation Recovery for a Digital Source Measure Unit (SMU) - A source-measure unit (SMU) may be implemented with respective digital control loops for output voltage and output current. The output voltage and output current may be measured with dedicated ADCs (analog-to-digital converters). The readings obtained by the ADCs may be compared to a setpoint, which may be set in a digital loop controller (DLC). The DLC may be used to produce an output to drive a DAC (digital-to-analog converter) until the output voltage and/or output current and/or a function thereof reach the respective desired levels. The DLC may perform a threshold check to determine if the output current is outside a specified measurable range, and generate an override signal to drive the DAC to rapidly return the output current to the measurable range. Once the current is within the measurable range, the DAC may once again be driven according to the respective digital control loops for the output voltage and the output current. | 12-06-2012 |
20120306519 | METHOD FOR THE PHASE DIAGNOSIS OF A MULTIPHASE CONVERTER - A method for the phase diagnosis of a multiphase converter for detecting potential errors in individual converter phases is provided, wherein a symmetrical load distribution for the individual converter phases is regulated. During the operation of the converter, the distribution of the load prescribed for each individual phase of the converter is detected at least two different times, at different temperatures, and in any order. | 12-06-2012 |
20120313655 | ELECTRICAL TEST EQUIPMENT HAVING SWITCHABLE INTERMEDIATE-VOLTAGE LINE- LEAKAGE AND RUN TEST POWER SOURCE - An electrical test instrument includes a built-in, switchable intermediate-voltage power source that enables line-leakage and run testing to be carried-out under higher-than-normal DUT operating voltages. | 12-13-2012 |
20120319709 | HIGH SPEED CONTROLLABLE LOAD - A high speed controllable load uses a voltage waveform synthesizer and a driver circuit to dynamically control an electronically variable load to generate a current though an arc fault circuit interrupter (AFCI) device under test. Sensors may be used to monitor a source voltage and the output current to generate an arbitrary waveform have a range of voltage and current phase shifts. An optical isolation circuit allows separation of grounds between a control stage and the AFCI device under test. | 12-20-2012 |
20120326737 | METHOD OF MEASURING SCATTERING PARAMETERS OF DEVICE UNDER TEST - A method of measuring scattering parameters (S-parameters) of a device under test (DUT) is provided in the present disclosure. The S-parameters of the DUT with two connectors of different standards may be obtained without performing a full two-port calibration using an adapter kit. Two one-port calibrations are performed in the present disclosure to build two error models, the first one of which includes the characteristics of one-port of a network analyzer and a cable, the second one of which further includes the characteristics of the DUT. Therefore, the characteristics of the DUT may be obtained by removing the characteristics of the first error model from the second error model. | 12-27-2012 |
20120326738 | PATTERN SYNTHESIS APPARATUS AND SEMICONDUCTOR TEST SYSTEM HAVING THE SAME - A semiconductor test system includes a user device configured to operate a reference device in accordance with an interface signal based on a timing signal having a variable operating frequency, a pattern synthesis apparatus configured to measure an interval between adjacent edges of the timing signal transmitted from the user device, and extract a logic value of the interface signal in accordance with the timing signal so as to generate test pattern data, and a test device configured to receive the test pattern data, reconstruct the timing signal based on the measured interval, generate a test driving signal such that the logic value is extracted from a device under test (DUT) based on the reconstructed timing signal, and apply the test driving signal to the DUT so as to determine an operating state of the DUT. | 12-27-2012 |
20130002272 | FAULT MODE CIRCUITS - A test circuit and method for testing through-silicon-vias (TSVs) in three-dimensional integrated circuits (ICs) during each phase of manufacturing is disclosed. In one aspect, the method includes testing for faults in each individual TSV, TSV-under-test, shorts between a TSV-under-test, and TSVs in close proximity and for connections between the TSV-under-test and another tier in the ICs. A test circuit has three switchable current paths connected to a power supply via a pull-up resistor and switches: a calibration path, a short path, and a current measurement path. A power supply is connected to the measurement path, and the calibration path and the short path are connected to ground via respective pull-down resistors. For each TSV-under-test, the desired operation mode is selected by the closure of different combinations of switches. The current flowing through the pull-up resistor in each operation mode indicates whether the TSV-under-test has passed or failed the test. | 01-03-2013 |
20130002273 | SYSTEM AND METHOD FOR ELECTROSTATIC DISCHARGE TESTING OF DEVICES UNDER TEST - A system and method for electrostatic discharge (ESD) testing devices under test (DUTs) uses an ESD gun attached to a robotic arm to execute ESD tests. The system and method also uses cameras positioned around a DUT placed on a testing table to define at least one test point on a surface of the DUT. Using the defined test point, as well as settings on the ESD gun and a testing process scenario that includes actions to be executed by the system, the testing process is performed by the system. | 01-03-2013 |
20130002274 | AGING DEGRADATION DIAGNOSIS CIRCUIT AND AGING DEGRADATION DIAGNOSIS METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - Provided is an aging degradation diagnosis circuit, including: a first delay circuit including a gate array for allowing aging degradation to progress, the first delay circuit being configured to delay an input signal and output a first output signal; a second delay circuit including a gate array having the same number of stages as the first delay circuit, the second delay circuit being configured to delay an input signal and output a second output signal; and an arbitrary delay unit, which is capable of varying a delay period in the second delay circuit by a predetermined amount. A delay comparison unit outputs comparison information obtained by relatively comparing delays between the first output signal and the second output signal. An adjustment unit uses the comparison information, to thereby readjust the delay period in the second delay circuit. | 01-03-2013 |
20130027066 | TRANSISTOR TEST STRUCTURE - A test structure may characterize the properties of a transistor including a DC test structure for testing DC properties of the transistor, and an AC test structure for testing AC properties of the transistor. The DC and AC test structures may have common test pads. | 01-31-2013 |
20130027067 | DAMAGE REDUCTION METHOD AND APPARATUS FOR DESTRUCTIVE TESTING OF POWER SEMICONDUCTORS - A device and method for limiting damage to a semiconductor device under test when the semiconductor device fails during a high current, or high power test is provided. The occurrence of a failure of the device under test is detected, and power applied to the semiconductor device is diverted through a parallel path element upon detection of failure of the semiconductor device. | 01-31-2013 |
20130033276 | AUTOMATIC TESTING EQUIPMENT, AUTOMATIC TESTING SYSTEM AND METHOD FOR CONTROLLING AUTOMATIC TESTING THEREOF - An automatic testing equipment, an automatic testing system, an a method for controlling automatic testing thereof are disclosed. The automatic testing equipment is used for receiving a control signal to test a durability of a connecting port of a device under test (DUT). The automatic testing equipment includes a testing platform, a testing unit, and a power control unit. The testing platform is used for disposing the DUT. The testing unit includes a main body, an assembly unit, and a height adjustment unit. The assembly unit is used for assembling a test connector. The height adjustment unit is connected with the main body and works with the assembly unit to adjust a height of the assembly unit. The power control unit drives the testing unit to test the connecting port via the test connector after receiving the control signal. | 02-07-2013 |
20130043895 | FAN SPEED CONTROL DEVICE - A fan speed control device is applied to a fan including a speed control signal port and a speed signal port. The fan speed control device includes a speed regulating circuit. The speed regulating circuit includes a signal control unit electrically connected to the speed signal port of the fan, and an adjustable resistor is electrically connected between the signal control unit and the speed control signal port of the fan. The resistance of the adjustable resistor may be varied to change the voltage and current supplied to the fan, and the rotational speed of the fan changes according to the operating voltage and current supplied. The signal control unit obtains speed signals from the speed signal port and processes and displays the current testing parameters of the fan. | 02-21-2013 |
20130049779 | INTEGRATED CIRCUIT - An integrated circuit comprising a first pair ( | 02-28-2013 |
20130057305 | HYBRID CONSTRUCTION MACHINE AND METHOD FOR MEASURING CAPACITANCE OF ELECTRICITY STORAGE DEVICE OF HYBRID CONSTRUCTION MACHINE - A hybrid construction machine includes: a measurement unit configured to measure a capacitance of an electricity storage device; and a monitoring unit configured to monitor a first condition in which an engine is driven, a second condition in which an adjustment value of a fuel adjusting unit adjusting an amount of fuel supplied to the engine is a predetermined value, and a third condition in which an operation unit and/or an upper swing body are locked and transmit a control signal for starting a measurement of the capacitance of the electricity storage device to the measurement unit when all conditions of the first to third conditions are satisfied. | 03-07-2013 |
20130063169 | EVALUATION BOARD - An evaluation board for evaluating a power module including a power semiconductor device and a detecting unit for detecting characteristics of the power semiconductor device, comprises: a power source circuit supplying an electric power to the power module; a driving circuit driving the power semiconductor device; a display unit displaying a detected signal inputted from the detecting unit; and a substrate on which the power source circuit, the driving circuit, and the display unit are mounted. | 03-14-2013 |
20130076380 | METHOD AND APPARATUS FOR ELECTRICALLY ACCESSING PHOTOVOLTAIC MODULES - An apparatus and a method for testing and/or conditioning photovoltaic modules. The apparatus includes a set of contacts for contacting electrical conductors of the module and a testing and/or conditioning system for testing and/or conditioning of the module and measuring parameters associated therewith. | 03-28-2013 |
20130082724 | PV PANEL DIAGNOSIS DEVICE, DIAGNOSIS METHOD AND DIAGNOSIS PROGRAM - A PV panel diagnosis technology is provided which can surely find a deteriorated panel in a solar power generation system. A PV panel diagnosis device includes an adjusting unit that adjusts an impedance for a PV panel circuit connected with a plurality of PV panels, a measured-value storing unit that stores, as a measured value, a voltage or a current measured through the PV panel circuit in accordance with a change in the impedance, a change-amount determining unit that determines a change amount of the voltage or the current based on the measured value in accordance with the change in the impedance, and a specifying unit that specifies a deteriorated PV panel based on a comparison result of the change amount with a predetermined threshold. | 04-04-2013 |
20130082725 | POWER SWITCHING FOR ELECTRONIC DEVICE TEST EQUIPMENT - An apparatus, system and method are provided for testing a battery-powered electronic device-under-test in a transport frame engaged with a test fixture. A transport frame power supply is arranged to provide power to the DUT in a pre-testing stage. A switching circuit is arranged to switch from the transport frame power supply to a test fixture power supply in response to receiving a power switching signal indicating satisfaction of a pre-testing condition. Power from the test fixture power supply can then be switched back to the first transport frame, or to a second transport frame, to begin testing a second DUT. The ability to start a DUT test without having to wait for the DUT to boot-up in the test fixture reduces test time and increases efficiency of use of test equipment. | 04-04-2013 |
20130106450 | DRIVE CIRCUIT AND TEST APPARATUS | 05-02-2013 |
20130106451 | Apparatus for VLF-Voltage Testing of Cables | 05-02-2013 |
20130113508 | ELECTRONIC TEST SYSTEM AND ASSOCIATED METHOD - Electronic test system and associated method, including a first and a second connection terminals respectively coupled to two pins of a chip under test, a signal source terminal coupled to a signal generator, a first and a second measurement terminals coupled to a tester, a fifth switch, a seventh switch and a switch circuit which has a first and a fourth front terminals coupled to the signal source terminal, has a first and a fourth back terminals coupled to the first and second connection terminals, and controls conduction between the first front terminal and the first back terminal, as well as conduction between the fourth front terminal and the fourth back terminal. The fifth switch is coupled between the fourth back terminal and the first measurement terminal, and the seventh switch is coupled between the first connection terminal and the second measurement terminal. | 05-09-2013 |
20130120009 | APPARATUS AND METHOD FOR DETERMINING VARIATION IN A PREDETERMINED PHYSICAL PROPERTY OF A CIRCUIT - Apparatus and method for determining variation in a predetermined physical property of a circuit. The apparatus includes monitored circuitry for generating output pulses, and configured such that each output pulse has a pulse width which is indicative of the current value of the predetermined physical property. Circuitry is then configured to receive both the output pulses generated by the monitored circuitry and an oscillating timing reference signal. With reference to the oscillating timing reference signal, the counter circuitry produces for each output pulse an associated count value indicative of the pulse width of that output pulse. Circuitry then compares the associated count values for at least two output pulses, in order to produce a comparison result used to determine the variation in the predetermined physical property. This provides a flexible mechanism for monitoring variations in a physical property on the fly during use of a data processing circuit. | 05-16-2013 |
20130120010 | Power Measurement System for Battery Powered Microelectronic Chipsets - A measurement instrument includes selectable channels for simultaneously measuring current on a power rail/load of a device under test. Multiplexor circuitry can be controlled to select power rails/loads for measurement and to couple unselected power rails to bypass the measurement circuitry. Active loads are provided in the measurement circuitry to compensate for loading by the measurement circuitry. The active loads cause current on a source side of a selected power rail/load to match current measured on a load side of the selected power rail/load during power measurements. | 05-16-2013 |
20130141124 | TEST METHOD OF DRIVING APPARATUS AND CIRCUIT TESTING INTERFACE THEREOF - A circuit testing interface and test method are disclosed. The circuit testing interface may include a test current transmitting pad, a test voltage measuring pad, and at least one driving circuit comprising an output terminal. The output terminal of the at least one driving circuit may be coupled to a through-silicon via (TSV). The circuit testing interface may further include at least one switch module, coupled to (1) the output terminal of the driving circuit, (2) the test current transmitting pad, and (3) the test voltage measuring pad. | 06-06-2013 |
20130141125 | DEVICE AND METHOD FOR TESTING STABLITY OF ELECTRONIC DEVICES - A test device is connected to a plurality of electronic devices to test a stability of the electronic devices is provided. The test device includes a parameter setting module, a signal generating module, a communication module, and a monitoring module. The parameter setting module sets test parameters for a test in response to a user input. The signal generating module generates a control signal according to the test parameters set by the user to control the electronic devices to execute operations corresponding to the test parameters. The communication module transmits the control signal to the electronic devices. The monitoring module monitors whether the electronic devices are running in a normal state during the test to determine the stability of the electronic devices and further informs the monitoring result to the user. | 06-06-2013 |
20130147499 | TEST APPARATUS AND TEST METHOD - A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR. | 06-13-2013 |
20130147500 | Frequency Extension Methods and Apparatus for Low-Frequency Electronic Instrumentation - An electronic measuring system for extending the effective measurement input frequency range of an electronic measuring instrument includes an electronic measuring instrument and a plurality of downconverting frequency extenders from which two or more downconverting frequency extenders can be selected and configured in series between a test signal output of a device under test (DUT) and a measuring input of the electronic measuring instrument, to selectively and effectively extend the permissible input frequency range of the electronic measuring instrument. The electronic measuring system may optionally include a plurality of upconverting frequency extenders from which one or more upconverting frequency extenders can be selected to selectively and effectively extend the maximum output frequency range of a signal generator used to generate stimulus signals for the DUT. | 06-13-2013 |
20130154675 | SUBSTRATE HOLDING DEVICE AND METHOD, AND INSPECTION APPARATUS AND METHOD USING THE SUBSTRATE HOLDING DEVICE AND METHOD - Non-contact type displacement sensors which measure the height of a substrate surface are installed above the substrate in order to hold the upper surface of the substrate at a desired height or to maintain the flatness of the substrate. A substrate mounting device is such that a plurality of grooves and of barriers are provided on the upper surface of a table and air is supplied between the substrate and the table to enable the pressure of air to displace the substrate. In addition, the substrate mounting device has such a structure as to make it possible to deform the substrate into an arbitrary convex-concave shape or to make the substrate flat by feeding back the output of the displacement sensor. | 06-20-2013 |
20130154676 | CABLE FATIGUE MONITOR AND METHOD THEREOF - A monitor for determining the operation condition of at least one cable that suffers bending and/or twisting and constitutes an electrical loop and a method thereof are provided. The monitor comprises a test electrical signal generator ( | 06-20-2013 |
20130162273 | TESTING DEVICE - A testing device comprising a power unit, a storage unit, and a controlling unit is mentioned. The power unit is adapted to provide different voltages. The storage unit is adapted to store a power sequence table and a simulation signal generating table. The controlling unit couples with the power unit and the storage unit, wherein the controlling unit is adapted to provide power sequence controlling signals according to the power sequence table, and the power unit is adapted to provide the voltages to the unit under test according to the power sequence controlling signals. The controlling unit is adapted to provide a simulation signal to the unit under test according to the simulation signal generating table, and the controlling unit is adapted to receive state signals generated by the unit under test in response to the voltages and the simulation signal. | 06-27-2013 |
20130162274 | SEMICONDUCTOR INTEGRATED CIRCUIT AND TEST CONTROL METHOD THEREOF - A semiconductor integrated circuit includes a decoding circuit configured to decode one or more test source signals and generate a plurality of test decoding signals, a transmission circuit configured to transmit the plurality of test decoding signals as a plurality of test mode group signals in response to a test enable signal, wherein the transmission circuit outputs the test mode group signals with maintaining a previous output, when the test decoding signals different from each other are sequentially activated, and a test mode signal output circuit configured to output a plurality of test mode signals corresponding to test mode groups, respectively, in response to the plurality of test mode group signals and one or more test mode select signals. | 06-27-2013 |
20130181729 | TESTING PROTECTION SCHEMES OF A POWER CONVERTER - A system for testing the existing protection schemes of a power converter. The system simulates the voltage regulator producing a voltage level below an under-voltage threshold. The system simulates the voltage regulator producing a voltage level above an over-voltage threshold. The system simulates a short in the power converter pulling down the input bus. The system simulates a short in the power converter pulling down the output bus. The system measures the system responses to these simulations against responses of a properly operating system and determines if the power converter's protection schemes are operating correctly. | 07-18-2013 |
20130181730 | PULSED BEHAVIOR MODELING WITH STEADY STATE AVERAGE CONDITIONS - A method for pulsed behavior modeling of a device under test (DUT) using steady state conditions is disclosed. The method includes providing an automated test system (ATS) programmed to capture at least one behavior of the DUT. The ATS then generates a DUT input power pulse that transitions from a predetermined steady state level to a predetermined pulse level and back to the predetermined steady state level. At least one behavior of the DUT is then captured by the ATS while the input power is at the predetermined pulse level. The ATS then steps the predetermined pulse level to a different predetermined pulse level, and the above steps are repeated until a range of predetermined pulse levels is swept. The ATS then steps the predetermined steady state level to a different steady state level, and the above steps are repeated until a range of predetermined steady state levels is swept. | 07-18-2013 |
20130181731 | INVERTER - In a test of discharging a capacitor by electrically turning on a first switching element and a second switching element that are inserted in series in a conductor connecting a positive electrode and a negative electrode of the capacitor, a discharge current that passes through the first and second switching elements tend to apply stress on the first and second switching elements. In this discharge test, while a first control signal for putting the first switching element into a low resistance state is being applied to the first switching element, a second control signal increasing a voltage thereof over time is applied to the second switching element, and application of one of or both of the first and second control signals is stopped when a current detector detects a current. Since a discharge test ends when a limited discharge current starts flowing, stress associated with the discharge test is reduced. | 07-18-2013 |
20130193993 | METHOD AND APPARATUS FOR TESTING A DEVICE-UNDER-TEST - A method for testing a device-under-test includes receiving, from at least one test channel circuit dedicated to communicate with an input/output pin of the device-under-test by means of at least one hardware resource, at least one logical control command describing a desired operation of the at least one hardware resource, and converting, by means of a resource controller, the at least one logical control command into at least one dedicated control command for the at least one hardware resource, wherein the at least one dedicated control command is adapted to be received by a physical implementation of the at least one hardware resource. | 08-01-2013 |
20130193994 | SYSTEMS AND METHODS FOR TEST TIME OUTLIER DETECTION AND CORRECTION IN INTEGRATED CIRCUIT TESTING - Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner. | 08-01-2013 |
20130200908 | METHOD AND APPARATUS FOR ACCELERATING DEVICE DEGRADATION AND DIAGNOSING THE PHYSICAL CHANGES OF THE DEVICE DURING THE DEGRADATION PROCESS - Embodiments of the present invention comprise methods and apparatus for testing devices. In some embodiments, a method for testing a device includes operating the device in a stress inducing mode using a first set of conditions for a first period of time; determining a first value for a plurality of device parameters after the first period of time; operating the device in the stress inducing mode using the first set of conditions for a second period of time; determining a second value for the plurality of device parameters after the second period of time; and determining if one or more components of the device has at least one of failed or physically changed by comparing the first and second values for the plurality of device parameters. | 08-08-2013 |
20130214805 | SELF-TEST OF OVER-CURRENT FAULT DETECTION - A system for testing over-current fault detection includes a first switch to connect a voltage to a load, a capacitor connected between the first switch and ground, a monitor circuit that monitors a current from the first switch to the load, and a microcontroller configured to detect an over-current fault condition based upon input from the monitor circuit. The microcontroller controls the state of the first switch to connect voltage to the load and verifies over-current detection based upon current generated during charging of the capacitor. | 08-22-2013 |
20130214806 | SELF-TEST OF OVER-CURRENT FAULT DETECTION - A system for testing over-current fault detection includes a first switch to connect a voltage to a load and a capacitor; a first monitor circuit that monitors a current from the first switch to the load; a second monitor circuit that monitors a voltage across the capacitor; and a microcontroller configured to control a state of the first switch to connect voltage to the load and verifies over-current detection based upon current generated during charging of the capacitor. The microcontroller detects an over-current fault condition based upon input from the first monitor circuit and detects a short-circuit fault condition based upon input from the second monitor circuit during test of the first monitor circuit. | 08-22-2013 |
20130214807 | INTEGRATED CIRCUIT AND TESTING METHOD - An integrated circuit includes a register cell, a control unit and an oscillation detecting unit. The register cell stores a value of a signal input through an input pin. The control unit makes control such that the value of the signal input from the input pin is stored in the register cell, and the value stored in the register cell is output to an outside. The oscillation detecting unit receives a signal output from an oscillator through the input pin, and stores a predetermined value in the register cell when it is detected that the signal oscillates. | 08-22-2013 |
20130221999 | TESTING SYSTEM AND METHOD - A testing method implemented by a testing system connected to an electronic device includes testing whether the electronic device is successfully powered on in a powering on/off test according to pre-set test parameters; detecting if the electronic device is successfully powered on in the powering on/off test; generating a pause signal when the electronic device is successfully powered on; upon receiving the pause signal, preventing from entering into testing powering off of the electronic device, controlling to test whether certain components in the electronic device can successfully perform some functions; generating a continue signal to test powering off of the electronic device after testing the certain components performing some functions; and testing whether the electronic device is successfully powered off in the powering on/off test. The testing system is also provided. | 08-29-2013 |
20130222000 | LOAD CIRCUIT FOR TESTING USB PORTS - An exemplary load circuit includes a switch unit and a current dividing circuit. The switch unit includes a number of switches. The current dividing circuit includes a number of sub-circuits. A terminal of a resistance module of each of the sub-circuits is connected to both a power terminal and a terminal of a corresponding one of the switches. The other terminal of the resistance module of each of the sub-circuits is connected to a drain of a transistor of each of the sub-circuits. A source of the transistor is connected to ground. A gate of the transistor is connected to ground, and is also connected to another terminal of the corresponding switch. | 08-29-2013 |
20130229196 | VARIABLE PRESSURE FOUR-POINT COATED PROBE PIN DEVICE AND METHOD - A variable pressure probe pin device, including: a housing with a channel having a first longitudinal axis; a probe at least partially disposed in the channel and including a plurality of probe pins configured to measure a property of a conductive layer; and a fluid pressure system configured to supply pressurized fluid o the channel to control a position of the probe within the channel. The housing or the probe is displaceable such that the plurality of probe pins contact the conductive layer. | 09-05-2013 |
20130229197 | TEST APPARATUS - A main power supply is arranged such that its output terminal Po is connected to a power supply terminal of a DUT via a power supply line, and is configured to feedback control an output voltage V | 09-05-2013 |
20130229198 | METHODOLOGIES AND TEST CONFIGURATIONS FOR TESTING THERMAL INTERFACE MATERIALS - Methodologies and test configurations are provided for testing thermal interface materials and, in particular, methodologies and test configurations are provided for testing thermal interface materials used for testing integrated circuits. A test methodology includes applying a thermal interface material on a device under test. The test methodology further includes monitoring the device under test with a plurality of temperature sensors. The test methodology further includes determining whether any of the plurality of temperature sensors increases above a steady state. | 09-05-2013 |
20130234741 | Methods for Characterizing Tunable Radio-Frequency Elements - A wireless electronic device may contain at least one antenna tuning element for use in tuning the operating frequency range of the device. The antenna tuning element may include radio-frequency switches, continuously/semi-continuously adjustable components such as tunable resistors, inductors, and capacitors, and other load circuits that provide desired impedance characteristics. A test station may be used to measure the radio-frequency characteristics associated with the tuning element. The test station may provide adjustable temperature, power, and impedance control to help emulate a true application environment for the tuning element without having to place the tuning element within an actual device during testing. The test system may include at least one signal generator and a tester for measuring harmonic distortion values and may include at least two signal generators and a tester for measuring intermodulation distortion values. During testing, the antenna tuning element may be placed in a series or shunt configuration. | 09-12-2013 |
20130234742 | INTEGRATED CIRCUIT AND PRINTED CIRCUIT BOARD HAVING RECEIVER TESTING FUNCTION - A integrated circuit having a receiver testing function includes a signal generating circuit, a jitter output circuit, a signal mix circuit, a receiver, and an error counting circuit. The signal generating circuit outputs a reference signal to the signal mix circuit and the error counting circuit. The jitter output circuit outputs a jitter. The signal mix circuit injects the jitter into the reference signal, and outputs a testing signal that is a combination of the jitter and the reference signal. The receiver receives and then outputs the testing signal to the error counting circuit. The error counting circuit tests a performance of the receiver by determining whether a difference between a code information of the testing signal and a code information of the reference signal is within a predetermined difference range. | 09-12-2013 |
20130241583 | DEVICE FOR TESTING SHORT CIRCUIT PROTECTION FUNCTION OF POWER SUPPLY - A device for testing short circuit protection functions of a plurality power supply units of a power supply includes a short circuit control module, a controller and an oscilloscope. The short circuit control module includes a number of driving circuits and a number of short circuits corresponding to the driving circuits. Each driving circuit is electrically connected to one of the power supply units by the corresponding short circuit. The controller is electrically connected to the driving circuits. The controller controls one or more of the driving circuits to drive the corresponding short circuits to short-circuit the corresponding power supply units. The oscilloscope is electrically connected to each power supply unit. The oscilloscope displays waveforms of output voltage of the short-circuit power supply units. | 09-19-2013 |
20130241584 | POWER-ON TEST APPARATUS AND SYSTEM FOR TESTING ELECTRONIC DEVICE - A test apparatus for executing a power-on test of an electronic device includes a setting module, an activation module, a controller, and a USB connector. The setting module includes a plurality of input keys. The activation module activates a power supply-on pin of a motherboard of the electronic device. The controller is electronically connected to the input keys and the activation module, the controller drives the activation module to activate the power supply-on pin, and controls a number of times of activation of the power supply-on pin according to a predetermined number of power-on events. The USB connector electronically connects the controller to the electronic device, the USB connector receives power-on and power-off confirmation signals from the electronic device, and transmits the signals to the controller. | 09-19-2013 |
20130241585 | INVERTER TEST APPARATUS - There is provided an inverter test apparatus for testing an inverter interconnected with an alternating-current power system, the apparatus including an alternating-current power output unit configured to output alternating-current power, and an alternating-current power controller configured to control the alternating-current power output from the alternating-current power output unit to simulate an alternating-current load of the inverter. | 09-19-2013 |
20130249576 | POWER SUPPLY UNIT TESTING SYSTEM - A system for testing a PSU includes an input control module, a voltage regulating module, and a load adjusting module. The input control module includes a microcontroller and a plurality of key switches connected to the microcontroller. The microcontroller is configured to receive input instruction from the plurality of key switches and output a control signal according to the input instruction. The voltage regulating module is configured to receive the control signal and generate an output voltage with a voltage value associated with the control signal. The load adjusting module includes a motor coupled to the output voltage of the voltage regulating module. The motor is rotatable in opposite direction to adjust an output current of the PSU. A rotating speed of the motor is in direct proportion to the voltage value of the output voltage. | 09-26-2013 |
20130257466 | METHOD AND APPARATUS FOR TESTING A MEMORY DEVICE - In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data. | 10-03-2013 |
20130265066 | PIXEL ARRAY MODULE WITH SELF-TEST FUNCTION AND METHOD THEREOF - A pixel array module with a self-test function including a test circuit unit, a plurality of test lines, and a pixel array is provided. The test circuit unit provides the self-test function. The test lines are connected between the test circuit unit and the pixel array. The pixel array is connected to the test circuit unit through the test lines and includes a plurality of pixels. Each pixel includes a transistor. Each transistor has a first terminal and a second terminal. Regarding each of the pixels, a driving signal of the transistor is transmitted from the first terminal to the second terminal thereof under a normal mode, and a test signal of the transistor is transmitted from the second terminal to the first terminal thereof under a test mode. Furthermore, a self-test method of the foregoing pixel array module is also provided. | 10-10-2013 |
20130265067 | Three dimensional memory structure - The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method. | 10-10-2013 |
20130271166 | Dielectric Monitoring System and Method Therefor - A system and method for monitoring or testing dielectric material nondestructively and in situ within field-based electrical equipment or as samples in a laboratory environment. In exemplary embodiments the use of negative voltage test pulses and a ground plane electrode with a parabolic curve or ogive shape minimizes energy transferred to the dielectric material to avoid or minimize degradation of the material. The disclosed system and method are thus suitable, inter alia, for continuous or near-continuous monitoring of fluid-filled electrical equipment in the field. | 10-17-2013 |
20130293248 | METHOD AND APPARATUS FOR MONITORING A HIGH-VOLTAGE ELECTRICAL CIRCUIT INCLUDING A DISCHARGE CIRCUIT - A high-voltage discharge circuit diagnostic system includes a high voltage DC link with a positive DC link and a negative DC link, a first resistor selectably connectable between the positive DC link and the negative DC link, and a second resistor connected between the positive DC link and the negative DC link. A control module connects the first resistor between the positive DC link and the negative DC link until the high voltage DC link discharges to a first voltage after which the control module disconnects the first resistor from between the positive DC link and the negative DC link to permit continued discharge of the high voltage DC link through the second resistor to a second voltage through an elapsed time period. The control module diagnoses a fault in the second resistor based upon the first voltage, the second voltage, and the elapsed time period. | 11-07-2013 |
20130300442 | Chip Socket - The present document relates to chip sockets which for testing integrated circuit chips. A chip socket carries an integrated circuit chip comprising a plate for mounting onto a front side of a PCB, a plurality of electrical PCB connectors in a first area on a backside of the plate, wherein the plurality of electrical PCB connectors is adapted for electrically connecting the chip socket to a corresponding plurality of connectors on the PCB and a corresponding plurality of chip connectors on a front side of the plate, wherein the plurality of chip connectors is electrically connected to the plurality of electrical PCB connectors respectively; wherein the plurality of chip connectors connect the chip socket to a corresponding plurality of connectors of the integrated circuit chip, wherein the plate comprises a recess at its backside. | 11-14-2013 |
20130300443 | MODULATED TEST MESSAGING FROM DEDICATED TEST CIRCUITRY TO POWER TERMINAL - The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals. | 11-14-2013 |
20130307571 | AUTOMATIC TEST EQUIPMENT CONTROL DEVICE - A shutdown apparatus and method for use in conjunction with automatic test equipment (ATE) is provided. A unit under test (UUT) is inserted into an ATE receiver that couples the UUT to at least one electronic device during test and extracted from the ATE receiver after test. The shutdown apparatus comprises an electro-mechanical interface that inserts the UUT into the receiver prior to test and extracts the UUT from the receiver after test A shutdown module is coupled to the electronic device and to the electro-mechanical interface and connects the electronic device to the receiver after insertion of the UUT into the receiver and disconnects the electronic device from the receiver prior to extraction of the UUT from the receiver. | 11-21-2013 |
20130314111 | APPARATUS FOR TESTING THYRISTOR VALVE - An apparatus for testing a thyristor valve includes: a current source circuit that provides an electric current when a thyristor valve as a test target is turned on; a voltage source circuit that provides a reverse voltage or a forward voltage when the thyristor valve is turned off; and a first auxiliary valve provided between a connection point between the thyristor valve and the voltage source circuit and the current source circuit, and that insulates the current source circuit from the voltage source circuit to protect the current source circuit from a high voltage of the voltage source circuit. | 11-28-2013 |
20130321010 | DETECTION OF DEFECTS IN TOUCH SENSORS - Defects in a touch sensor are detected by coupling the sensor lines to a common signal line. Each of the sensor lines is tested by disconnecting the sensor line from the common signal line, connecting it to a voltage (e.g., ground) and comparing the voltage on the common signal line to a reference voltage. Detected defects include a short circuit between any two transmit and/or receive lines and a short between any transmit or receive line to ground. | 12-05-2013 |
20130321011 | TEST DEVICE, TEST SYSTEM, METHOD AND CARRIER FOR TESTING ELECTRONIC COMPONENTS UNDER VARIABLE PRESSURE CONDITIONS - A test device, a test system, a method and a carrier for testing electronic components under variable pressure conditions comprise: a first chamber half and a second chamber half, a first gasket and a second gasket, a carrier segment adapted to carry a plurality of electronic components, and a circular carrier section surrounding the carrier segment. The circular carrier section comprises a first side and a second side. The first gasket is placed between the first chamber half and the first side of the circular carrier section to form an airtight seal and the second gasket is placed between the second chamber half and the second side of the circular carrier section to form an airtight seal. | 12-05-2013 |
20130328581 | APPARATUS AND METHOD FOR AUTOMATED TESTING OF DEVICE UNDER TEST - An apparatus and a method for automated testing of electrostatic discharge of a Device Under Test (DUT) are provided. In the apparatus and the method, an electrostatic pulse is applied to the DUT, a malfunction type is detected from the DUT, and a control command is transmitted to the DUT to return a test mode of the DUT to a normal mode according to the detected malfunction type. | 12-12-2013 |
20130342228 | TEST METHOD FOR SENSE CIRCUIT - Embodiments are directed to coupling a first transformer to a first load, coupling a second transformer to a second load, applying a single phase power source to the first transformer, applying an inverted version of the power source to the second transformer, coupling a sensing circuit to the first and second transformers, and monitoring, by the sensing circuit, signal contributions associated with the first and second transformers. | 12-26-2013 |
20140002117 | SYSTEM FOR MEASURING SOFT STARTER CURRENT AND METHOD OF MAKING SAME | 01-02-2014 |
20140002118 | DEVICE FOR HIGH VOLTAGE TESTING OF SEMICONDUCTOR COMPONENTS | 01-02-2014 |
20140009179 | TESTING DEVICE - A testing device including a first connector, a control unit, a first detecting circuit and a memory controller is provided. The first connector is electrically connected to a first bus. The control unit generates a plurality of first control signals according to a first enable signal from the first connector. The first detecting circuit is electrically connected to a plurality of first transmission lines in the first bus, and sequentially conducts the first transmission lines to a ground according to the first control signals. The memory controller detects states of the signals transmitted by the first transmission lines and determines whether to generate a first abnormal indication signal according to a detecting result. The control unit controls a plurality of indication lights according to the first abnormal indication signal. | 01-09-2014 |
20140009180 | TOUCH TESTING SYSTEM AND TOUCH TESTING METHOD THEREOF - A touch testing system for a capacitive touch device and a method thereof are provided. The system includes a test fixture, at least one magnetization component, at least one magnetic induction component and a driving unit. The fixture is disposed on the touch device and has at least one chute on a position corresponding to the touching area. The magnetization component is disposed on the fixture and enabled by a driving signal to produce a magnetic force. The magnetic induction component is slidably disposed in the chute and inducts the magnetic force to slide along the chute, such that the sensing unit produces a touch testing information. The driving unit is coupled to the magnetization component and the sensing unit, provides the driving signal to enable the magnetization component and receives the touch testing information to feed back a testing result on the capacitive touch device accordingly. | 01-09-2014 |
20140015554 | INSPECTION APPARATUS - An inspection apparatus includes an insulating substrate, a socket in which a body portion having a through-hole in a wall thereof is integrally formed with a connection portion secured to the insulating substrate, and a contact probe detachably secured to the socket. | 01-16-2014 |
20140015555 | HARDWARE-IN-THE-LOOP GRID SIMULATOR SYSTEM AND METHOD - A hardware-in-the-loop (HIL) electrical grid simulation system and method that combines a reactive divider with a variable frequency converter to better mimic and control expected and unexpected parameters in an electrical grid. The invention provides grid simulation in a manner to allow improved testing of variable power generators, such as wind turbines, and their operation once interconnected with an electrical grid in multiple countries. The system further comprises an improved variable fault reactance (reactive divider) capable of providing a variable fault reactance power output to control a voltage profile, therein creating an arbitrary recovery voltage. The system further comprises an improved isolation transformer designed to isolate zero-sequence current from either a primary or secondary winding in a transformer or pass the zero-sequence current from a primary to a secondary winding. | 01-16-2014 |
20140043050 | METHOD AND SYSTEM FOR PERFORMING TESTING OF PHOTONIC DEVICES - A photonics system includes a transmit photonics module and a receive photonics module. The photonics system also includes a transmit waveguide coupled to the transmit photonics module, a first optical switch integrated with the transmit waveguide, and a diagnostics waveguide optically coupled to the first optical switch. The photonics system further includes a receive waveguide coupled to the receive photonics module and a second optical switch integrated with the receive waveguide and optically coupled to the diagnostics waveguide. | 02-13-2014 |
20140043051 | INSPECTION APPARATUS, INSPECTION SYSTEM AND INSPECTION METHOD - An inspection apparatus for inspecting target objects includes multiple inspection cells corresponding to target objects, respectively, and a test-pattern wiring formed between the inspection cells. Each of the inspection cell includes a test pattern memory device which temporarily stores a test pattern, an inspection signal driver device which transmits an inspection signal to a respective one of the target objects based on the test pattern, a comparator device which compares an output signal from the respective one of the target objects with an expected value corresponding to the test pattern such that a test result is obtained, and a test result memory device which temporarily stores the test result, and the test-pattern wiring transmits the test pattern to the test pattern memory device of each of the inspection cells from an upstream side to a downstream side in the order that the target objects are inspected. | 02-13-2014 |
20140084950 | CANCELLATION OF SECONDARY REVERSE REFLECTIONS IN A VERY-FAST TRANSMISSION LINE PULSE SYSTEM - An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider. | 03-27-2014 |
20140084951 | METHOD FOR DETECTING A DEVICE THAT GENERATES SPURIOUS SIGNALS IN AN ELECTRICAL NETWORK, AN ELECTRICAL SYSTEM AND AN AIRCRAFT - A method for detecting a device that generates spurious signals in an electrical network, to which several devices and at least one fault detection device are connected, includes the steps of monitoring the electrical network for electrical spurious signals, sequentially deactivating each device for a predetermined time T when an electrical spurious signal has been detected, and checking the electrical network for the disappearance of the respective spurious signal, and signaling as soon as the respective spurious signal has disappeared upon deactivating a respective device. This makes it possible to especially reliably detect a device in an electrical network that couples an undesired spurious signal into the network. | 03-27-2014 |
20140091818 | FINE PITCH INTERFACE FOR PROBE CARD - A probe card for testing integrated circuit devices. The probe card includes a first circuit having a plurality of traces disposed thereon. The probe card also includes a plurality of pins to couple to a device under test. An interface element interfaces a first set of pins of the plurality of pins with the plurality of traces on the first circuit. The interface element includes a conductive plane coupled to a second set of pins of the plurality of pins to provide power and ground to the device under test. | 04-03-2014 |
20140097858 | RING OSCILLATOR TESTING WITH POWER SENSING RESISTOR - A test circuit for a ring oscillator comprising a plurality of inverting stages includes a power supply, the power supply configured to provide a voltage to the plurality of inverting stages of the ring oscillator at a power output; and a power sensing resistor located between the power output of the power supply and direct current (DC) bias inputs of the inverting stages of the ring oscillator, wherein a signal from the power sensing resistor is configured to be monitored to determine a characteristic of the ring oscillator. | 04-10-2014 |
20140097859 | MULTIAXIAL MOTOR DRIVE SYSTEM AND MULTIAXIAL MOTOR DRIVE DEVICE - A multi-axis motor driving apparatus includes: a plurality of drivers individually connected to corresponding ones of the plurality of motors, for supplying electric power to the corresponding ones of the plurality of motors for driving; and an integrated controller for sequentially supplying electric power to the plurality of motors via the plurality of drivers, and based on detection signals of the encoders, determining for each driver whether or not there is miswiring of at least either of a motor wire that connects one of the plurality of drivers to one of the plurality of motors or a detector wire from the encoder. | 04-10-2014 |
20140103946 | Device for Actively Improved Impedance Synthesis - An impedance control device for tuning a device under test comprising: a first terminal port arranged for connecting a device under test, a second terminal port arranged for connecting a termination, a first signal path for a signal travelling between the first and the second terminal port, first coupling means arranged for picking up a part of the signal travelling in the first signal path, a second signal path arranged for receiving the part of the signal from the first coupling means, said second signal path comprising a correction circuit for adapting as a function of frequency the amplitude and phase of the received part of the signal, second coupling means arranged for coupling back into the first signal path an adapted signal outputted by the correction circuit, and an attenuator and phase shifter for applying attenuation and phase shifting on the signals travelling between the first and the second terminal port. | 04-17-2014 |
20140132290 | FLEXIBLE PERFORMANCE SCREEN RING OSCILLATOR WITHIN A SCAN CHAIN - Aspects of the invention provide for a flexible performance screen ring oscillator (PSRO) integrated within a scan chain. In one embodiment, a circuit structure to create the flexible PSRO includes: a plurality of programmable scan chain elements; and a forward test scan chain path through the plurality of scan chain elements; wherein each of the programmable scan chain elements includes additional circuitry for a backward path, such that the backward path and the forward test scan chain path are combined to create the PSRO. | 05-15-2014 |
20140139245 | SEMICONDUCTOR DEVICE DRIVING CIRCUIT AND METHOD OF TESTING THE SAME - A semiconductor device driving circuit includes: a driving circuit that drives a semiconductor device; an input circuit that gives a control signal to the driving circuit; a driving power source that drives output stages of the driving circuit; and a control power source provided independently of the driving power source, and which drives the input circuit. Only the driving voltage of the driving power source is reduced during a test and the current capability of the driving circuit is adjusted based on the current capabilities of the output stages in a pentode region. | 05-22-2014 |
20140145738 | DIGITALLY DISPLAYING INSPECTION SYSTEM FOR ESD PROTECTION CHIP - The present invention provides a digitally displaying inspection system for ESD protection chip, which includes an LVDS connector, a display system, first, second, and the third data lines, a power supply, and a resistor. The first, second, and third data lines each have an end electrically connected to the LVDS connector and an opposite end electrically connected to the display system. The display system includes a logic operation module and a digital display module electrically connected to the logic operation module. The logic operation module is electrically connected to the first, second, and third data lines. When an ESD protection chip is electrically connected to the LVDS connector, the logic operation module samples signals on the first, second, and third data lines and drive, after carrying out logic operations, the digital display module to display character signs, which can identify if the ESD protection chip is incorrectly connected. | 05-29-2014 |
20140152333 | ENVIRONMENTAL SENSOR - A device for monitoring a working environment in which electronic circuit boards are present includes: a) test circuit boards with pairs of traces and circuitry for determining the electrical resistance between the traces, the test boards being positioned in a pathway effective for directing air across the test traces; b) control elements for controlling the flow of air through the pathway and for controlling power applied to the test board traces; c) data storage for storing data relating to acceptable electrical resistance between test traces; d) circuitry for comparing measured electrical resistance between two test traces to a stored value for the acceptable electrical resistance between two test traces; and e) an output for communicating the results of the comparison between the measured electrical resistance between two test traces and the stored value for the acceptable electrical resistance between two test traces. | 06-05-2014 |
20140159755 | PARTIAL DISCHARGE CHARGE AMOUNT MEASURING METHOD AND DEVICE - A partial discharge charge amount measuring method includes generating a partial discharge in a sample by applying a voltage from a voltage impressing device connected to the sample, the voltage being higher than a partial discharge inception voltage, continuously measuring and recording terminal voltages of a capacitor connected in series between the sample and a ground at least until a breakdown of the sample occurs by alternately operating at least two data loggers connected to the capacitor at intervals of a predetermined time, calculating an amount of electric charge discharged from the sample and remaining in the capacitor by multiplying a difference in the recorded terminal voltages of the capacitor by a capacitance of the capacitor, and calculating an accumulated discharge amount by accumulating the discharged amount of electric charge at earliest until the breakdown of the sample occurs. | 06-12-2014 |
20140159756 | DETECTING DEVICE AND CURRENT SENSOR - A detecting device includes a detecting part configured to detect a change in an object to be detected so as to output a detection signal, an amplifying part configured to amplify the detection signal output from the detecting part to output a first amplification signal, a reference voltage supply part configured to supply a reference voltage to the amplifying part, the reference voltage being input to the amplifying part to be output as a second amplification signal, a switching part configured to switch a connection between the detecting part and the amplifying part or a connection between the amplifying part and the reference voltage supply part based on a control signal input thereto, and a comparing part configured to compare a predetermined amplification factor in the amplifying part, with an amplification factor obtained from the second amplification signal so as to output the comparison result as a comparison signal. | 06-12-2014 |
20140167792 | SCAN TESTING SYSTEM, METHOD AND APPARATUS - Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible. | 06-19-2014 |
20140167793 | Measurement System for Characterising a Device Under Test - The present invention relates to a measurement system for characterising a device under test (DUT) wherein impedance is controlled or varied over a set of measurement conditions and a parameter or a set of parameters measured for each measurement condition. The measurement system comprises
| 06-19-2014 |
20140184252 | OPEN POTENTIOMETER DETECTION SYSTEM - A system to detect whether a potentiometer is in an open circuit condition is disclosed. The system includes a potentiometer having a resistive element coupled between a voltage input and ground and an adjustable arm determining the resistance of the resistive element. A low pass filter is coupled to the adjustable arm. A controller has a first driver output coupled to the voltage input of the potentiometer and a second driver output coupled to the adjustable arm. The controller determines failure of the potentiometer by setting the first driver output coupled to the voltage input of the potentiometer to a high value. A first sample voltage from the adjustable arm is read and determined whether the first sample voltage is between a high threshold and a low threshold value. The first driver output coupled to the voltage input of the potentiometer is set to a low value. A voltage is applied to the adjustable arm via the second driver output. A second sample is read from the adjustable input and it is determined whether the second sample is below an arm threshold value. | 07-03-2014 |
20140210495 | LOAD TESTING MACHINE - A load testing machines includes: six resistance units; six cooling fans; insulators between the resistance units and the cooling fans; and connection cables, in which: each of the resistance units includes a plurality of steps of resistor groups arranged in a z-direction and each formed of a plurality of rod-shaped resistors parallel to a x-direction connected together in series arranged at predetermined intervals in a y-direction; the six cooling fans face the resistance units, respectively, in the z-direction; the connection cables are cables used for serially and detachably connecting resistor groups next to each other in the y-direction of two resistance units next to each other in the y-direction with an interval of not smaller than a second distance in between; and the insulators each have a size corresponding to the rated voltage of a target power supply of a power supply load test to be conducted using a resistance unit group. | 07-31-2014 |
20140232420 | Methods And Systems For Defective Phase Identification And Current Sense Calibration For Multi-Phase Voltage Regulator Circuits - Methods and systems are disclosed that may be implemented to complete individual phase current sense calibration of a multi-phase voltage regulator (VR) and/or to detect any and all individual bad phases of such a VR by utilizing the reconfiguration capability of a digital VR controller-based VR in conjunction with an improved test process. The disclosed systems and methods may be employed in one example to identify that all individual phases of the multi-phase VR are operational to contribute to the output of the multi-phase VR using a rotating single phase operation testing mode. Individual phase current sense calibration may also be additionally or alternatively completed while the VR is operating under the rotating single phase operation mode. | 08-21-2014 |
20140232421 | Probe card of low power loss - A probe card, which is used to transmit power signals and test signals from a tester to a DUT, includes a pin base, a plurality of signal pins, a signal conducting circuit and at least one power conducting circuit. The signal pins are made of conductive materials, and each contacts the DUT with an end thereof; the signal conducting circuit has a first resistance, and electrically connects the tester and the other end of one of the signal pin to transmit the test signals to the DUT; the power conducting circuit has a second resistance which is much less than the first resistance, and electrically connects the tester and the other end of one of the signal pin which is not connected with the signal conducting circuit to transmit the power signals to the DUT. | 08-21-2014 |
20140232422 | BUILT-IN SELF-TEST METHODS, CIRCUITS AND APPARATUS FOR CONCURRENT TEST OF RF MODULES WITH A DYNAMICALLY CONFIGURABLE TEST STRUCTURE - A testable integrated circuit chip ( | 08-21-2014 |
20140239986 | PROCESS CONTROL MONITORING FOR BIOCHIPS - The present disclosure provides a biosensor device wafer testing and processing methods, system and apparatus. The biosensor device wafer includes device areas separated by scribe lines. A number of test areas that allow fluidic electrical testing are embedded in scribe lines or in device areas. An integrated electro-microfluidic probe card includes a fluidic mount that may be transparent, a microfluidic channels in the fluidic mount in a testing portion, at least one microfluidic probe and a number of electronic probe tips at the bottom of the fluidic mount, fluidic and electronic input and output ports on the sides of the fluidic mount, and at least one handle lug on the fluidic mount. The method includes aligning a wafer, mounting the integrated electro-microfluidic probe card, flowing one or more test fluids in series, and measuring and analyzing electrical properties to determine process qualities and an acceptance level of the wafer. | 08-28-2014 |
20140247064 | INTEGRATED CIRCUIT TESTING - In some examples, a system, such as an integrated circuit device (IC), includes functional elements interspersed with access elements and associated test elements. The access elements and associated test elements may be used to determine a health status of the IC or an area of the IC. A health status determination can include, for example, identification of an area of the IC where performance may have degraded (e.g., has degraded or is about to degrade beyond desirable levels of performance). For example, a test element can be configured to generate a parametric output in response to an electrical stimulus, where the parametric output indicates a health status of one or more functional elements of the IC. | 09-04-2014 |
20140266270 | SMOOTH VI MODE CROSSOVER METHOD AT COMPLIANCE LIMIT THRESHOLD - Source measure units may operate as a voltage/current (V/I) source for a load, such as a device under test (DUT). Source measure units having a voltage controlled mode and a current controlled mode are described. The source measure units may have a suitable configuration to transition between the voltage controlled mode and current controlled mode in a smooth manner, and may be operated accordingly. | 09-18-2014 |
20140266271 | INJECTION PROTOCOL - An injection protocol for a cable includes selecting a cable for testing, selecting a pre-injection electrical discharge test for determining if electrical discharge activity occurs at or about operating voltage of the cable, configuring the cable for the pre-injection electrical discharge test; running the pre-injection electrical discharge test on the cable, and determining whether to inject the cable with a restorative fluid based upon electrical discharge activity detected at or about operating voltage of the cable. | 09-18-2014 |
20140292361 | Testing Integrated Circuit Packaging for Output Short Circuit Current - An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously connecting multiple output pins directly to ground in order to active a current limiter associated with each of the output pins. The pins are then connected to a resistive connection to ground via a set of resistors; the direct ground is then removed, such that the current limiter associated with each of the output pins remains activated. A voltage drop across each of the set of resistors is measured simultaneously. An output short circuit current fault is indicated when the voltage drop across any of the resistors exceeds a threshold value corresponding to a maximum output short circuit current value | 10-02-2014 |
20140347079 | SYSTEM AND METHOD FOR ELECTROSTATIC DISCHARGE TESTING OF DEVICES UNDER TEST - A system and method for electrostatic discharge (ESD) testing devices under test (DUTs) uses an ESD gun attached to a robotic arm to execute ESD testing processes. The system and method also uses a relay station to place a DUT after an ESD testing process is performed on one major side of the DUT so the ESD testing can be performed on the other major side of the DUT. | 11-27-2014 |
20140354310 | Capacitive Sensor Testing - Capacitive sensor testing techniques are described. In one or more implementations, a plurality of conductive pads of a test apparatus are caused to transition to a grounded state. The plurality of conductive pads is disposed proximal to one or more capacitive sensors of a device. An output is examined that describes a response of the one or more capacitive sensors of the device to the transition to the grounded state by the plurality of conductive pads to test operation of the one or more capacitive sensors of the device. | 12-04-2014 |
20140368225 | Electric Circuit Evaluation Method - The electric circuit evaluation method according to the present invention is characterized in that a designated electric circuit is placed inside a shield structure, a noise signal for a malfunction test is inputted to the designated electric circuit, a short-circuit is established between a ground of the shield structure and a ground of a noise source for inputting a noise signal for a malfunction test to the designated electric circuit, and the ground of the designated electric circuit and the ground of the shield structure are isolated. | 12-18-2014 |
20140368226 | SEMICONDUCTOR DEVICE AND TEST METHOD - A test voltage having a first voltage or a second voltage is applied to an output terminal of a complementary fuse that includes a first fuse to one end of which the first voltage is applied and the other end of which serves as the output terminal and a second fuse to one end of which the second voltage is applied and the other end of which is connected to the output terminal. The test voltage then stops being applied. In such a state, whether output data from the output terminal of the complementary fuse coincides with an expected value is determined. The result of determination is output as a test result. | 12-18-2014 |
20150008944 | TEST SYSTEM AND METHOD FOR TESTING HIGH-VOLTAGE TECHNOLOGY - The present invention relates to a test system for high-voltage technology devices, in particular shunt reactors, as defined in the preamble of independent patent claim | 01-08-2015 |
20150015283 | Method and Apparatus for Power Glitch Detection in Integrated Circuits - A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred. | 01-15-2015 |
20150042368 | AUTOMATIC TEST EQUIPMENT FOR TESTING AN OSCILLATING CRYSTAL AND METHOD FOR OPERATING THE SAME - Embodiments of the invention relate to automatic test equipment for testing a circuit having an oscillating crystal and to a method for operating such automatic test equipment. A generator generates a first signal comprising an oscillating part having at least one predetermined frequency. A first terminal couples the first signal to the oscillating crystal. At least one predetermined frequency is located inside a predetermined window around one of the resonance frequencies of the oscillating crystal. An analyzer has a second terminal coupled to the oscillating crystal for detecting a second signal and a rectifier connected in series with a low-pass filter for rectifying and filtering the second signal. A detector for detects a DC-signal at the output of the low-pass filter and for signals a valid test result for the oscillating crystal if the DC-signal exceeds a certain threshold value. | 02-12-2015 |
20150048855 | METHOD FOR TESTING A MULTI-CHIP SYSTEM OR A SINGLE CHIP AND SYSTEM THEREOF - A method for testing a multi-chip system including multiple ports is provided. The method comprises determining a test path formed by connecting the multiple ports, in which the test path is determined in such a way that the internal logic circuit of each chip in the multi-chip system is bypassed, injecting a test traffic to the test path, and receiving the test traffic from the test path. | 02-19-2015 |
20150054532 | TEST DEVICE AND TEST SYSTEM INCLUDING THE SAME - A test device includes a test unit and a voltage selection circuit. The test unit is configured to detect a voltage at a test pad of a semiconductor device under test by applying a test current to the test pad. The voltage selection circuit is configured to apply a selection voltage to a ground pad of the semiconductor device under test by selecting one of a plurality of voltages according to a test mode. | 02-26-2015 |
20150061707 | INTEGRATED CIRCUIT PROVIDING FAULT PREDICTION - The prediction of hardware failure is obtained by operating two redundant circuit modules while one circuit module is artificially aged. The output of the two circuit modules is compared and a discrepancy between outputs indicates a projected failure of the aged modules. Aging may be accomplished by one or a combination of lowering operating voltages and re-phasing a sampling clock to reduce slack time both of which provide increased sensitivity to gate delay. | 03-05-2015 |
20150084655 | SWITCHED LOAD TIME-DOMAIN REFLECTOMETER DE-EMBED PROBE - A de-embed probe, including two inputs configured to connect to a device under test, a memory, a signal generator configured to output a signal, a plurality of load components, a plurality of switches, and a controller. Each load component is configured to provide a different load. A first switch of the plurality of switches is associated with the signal generator and the other switches of the plurality of switches are each associated with one load component. The controller is configured to control the plurality of switches to connect combinations of the loads from the plurality of load components and the signal from the signal generator across the two inputs. | 03-26-2015 |
20150084656 | TWO PORT VECTOR NETWORK ANALYZER USING DE-EMBED PROBES - A test and measurement system including a device under test, two de-embed probes connected to the device under test, and a test and measurement instrument connected to the two de-embed probes. The test and measurement instrument includes a processor configured to determine the S-parameter set of the device under test based on measurements from the device under test taken by the two de-embed probes. | 03-26-2015 |
20150091594 | Apparatus and Method for Integrated Circuit Forensics - A test system including an embodiment having a sensor array adapted to test one or more devices under test in learning modes as well as evaluation modes. An exemplary test system can collect a variety of test data as a part of a machine learning system associated with known-good samples. Data collected by the machine learning system can be used to calculate probabilities that devices under test in an evaluation mode meet a condition of interest based on multiple testing and sensor modalities. Learning phases or modes can be switched on before, during, or after evaluation mode sequencing to improve or adjust machine learning system capabilities to determine probabilities associated with different types of conditions of interest. Multiple permutations of probabilities can collectively be used to determine an overall probability of a condition of interest which has a variety of attributes. | 04-02-2015 |
20150137838 | AUTOMATED TEST SYSTEM WITH EDGE STEERING - A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained. | 05-21-2015 |
20150137839 | FLEXIBLE TEST SITE SYNCHRONIZATION - A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations. | 05-21-2015 |
20150137840 | Solid State Wideband High Impedance Voltage Converter - A front-end converter circuit may allow devices, e.g. oscilloscopes and digitizers, to receive input signals having a wide range of possible amplitudes while maintaining a high standardized input impedance. The converter may selectively couple, using low-voltage switches, a selected input network of two or more input networks to a virtual ground node, and a selected feedback network of two or more feedback networks to a transconductance stage input. The selected input network and selected feedback network together define a respective input signal amplitude range. The converter may also controllably adjust an AC gain of the converter to match a DC gain of the converter, and selectively couple non-selected input networks to signal ground. Output referred integrated resistor thermal noise may be reduced to a desired value by lowering the value of the transconductance stage coupled across the input of the converter (through an input resistance) and the virtual ground node. | 05-21-2015 |
20150301104 | CIRCUITRY TO PROTECT A TEST INSTRUMENT - Controlling a test instrument may include: determining a first value corresponding to power output by the test instrument; determining a second value based on the first value, where the second value corresponds to an amount of energy consumed by the test instrument; and placing at least part of the test instrument in a high-impedance state when the second value exceeds a threshold. | 10-22-2015 |
20150309108 | CIRCUIT ARRANGEMENT WITH A THYRISTOR CIRCUIT, AS WELL AS A METHOD FOR TESTING THE THYRISTOR CIRCUIT - A thyristor circuit comprising at least one series circuit in which two or more thyristors are connected in series. Each thyristor is parallel-connected to an RC member. A control device can energize the thyristors individually and independently of each other by a control signal, so that each thyristor can be individually switched into its conducting condition. During a test sequence, the thyristors are switched successively into their conducting condition, wherein, in a series circuit and/or in the thyristor circuit, respectively only one thyristor is in its conducting condition. While a thyristor is conducting, the capacitor of the associate RC member discharges and produces a thyristor current. As a result, the conducting condition is maintained until the thyristor current falls below the holding current. The control device can use the thyristor voltage and/or the thyristor current to evaluate the function or the switching behavior of the thyristor. | 10-29-2015 |
20150316607 | SYSTEM AND METHOD FOR CONVERGING CURRENT WITH TARGET CURRENT IN DEVICE UNDER TEST - A test system measures parameters of a device under test (DUT), including a transistor. The test system includes a first voltage source unit for supplying a gate voltage; a second voltage source unit for supplying one of a drain voltage or a source voltage, the second voltage source having a current measurement device for detecting one of a drain current or a source current flowing through the transistor, respectively; a feedback unit for outputting a feedback current, based on the one of the drain or source currents; and an error amplifier for outputting a feedback control signal, based on comparison of the feedback current and a target current value. The first voltage source unit adjusts the gate voltage based on the feedback control signal so that the one of the drain or source currents converges to match the target current value. | 11-05-2015 |
20150331011 | MEASUREMENT DEVICE - A measurement device includes a stage for carrying an object to be measured, an insulating board having a through hole, a probe fixed on the undersurface of the insulating board, a side wall section in a shape surrounding the probe, a pressurizing section provided on the top surface of the insulating board, the pressuring section supplying a gas below the insulating board via the through hole, and a measurement section electrically connected to the probe to control the pressurizing section, wherein the measurement section measures an electric property of the object to be measured via the probe in a state where the pressurizing section is controlled to supply a gas to a measurement space located below the insulating board to increase a pressure in the measurement space, the measurement space surrounded by the stage, the side wall section, and the insulating board. | 11-19-2015 |
20150338454 | CIRCUIT TO DETECT PREVIOUS USE OF COMPUTER CHIPS USING PASSIVE TEST WIRES - A test structure and method to detect open circuits due to electromigration or burn-out in test wires and inter-level vias. Electromigration occurs when current flows through circuit wires leading to a circuit interruption within the wire. The test structure is a passive test wire arranged in one of several configurations within the circuit of a computer chip. The dimensions and resistances of test wires can vary according to the test structure configuration. Each test wire is measured for an electrical discontinuity after the computer chip is powered-on. If a wiring interruption is detected, it is concluded that the chip had been powered-on before. | 11-26-2015 |
20150346273 | BRANCH CIRCUIT MONITORING SYSTEM - The present disclosure provides a branch circuit monitoring (BCM) system that may include a first collector board with a first plurality of connector ports connected to a first plurality of branch circuits, and a second collector board with a second plurality of connector ports connected to a second plurality of branch circuits. Each of the first and second plurality of connector ports may receive a respective first and second plurality of connector plugs configured to be receivable in the respective first and second plurality connector ports. The first collector board may be coupled to an aggregator board such that the first plurality of current sensors may report branch circuit measurements to the aggregator board. The plugs may be connected to associated leads connected to respective first plurality and second plurality of current sensors. The first board and the second board may be in communication using a bus protocol. | 12-03-2015 |
20150355265 | METHOD AND APPARATUS FOR IDENTIFYING DEFECTS IN A CHEMICAL SENSOR ARRAY - An apparatus including an array of sensors including a plurality of chemical sensors and a plurality of reference sensors, each chemical sensor coupled to a corresponding reaction region for receiving at least one reactant, and each reference sensor comprising a field effect transistor having a gate coupled to a corresponding reference line and an access circuit for accessing the chemical sensors and the reference sensors and a controller to apply bias voltages to the reference lines to select corresponding reference sensors, acquire output signals from the selected reference sensors, and identify one or more defects in the access circuit based on differences between the acquired output signals and expected output signals. | 12-10-2015 |
20150355269 | METHOD AND APPARATUS FOR IDENTIFYING DEFECTS IN A CHEMICAL SENSOR ARRAY - In one implementation, a method for operating an apparatus is described. The method includes applying a bias voltage to place a transistor of a reference sensor in a known state, the reference sensor in an array of sensors that further includes a chemical sensor coupled to a reaction region for receiving at least one reactant. The method further includes acquiring an output signal from the reference sensor in response to the applied bias voltage, and determining a defect associated with the array if the output signal does not correspond to the known state. | 12-10-2015 |
20150362549 | MEASURING APPARATUS - A measuring apparatus includes a measuring unit for measuring an electrical characteristic of a measurement object by applying an electrical signal, and a discharge detection unit connected to the measuring unit, the discharge detection unit obtaining an electrical signal value that is the value of the electrical signal applied to the measurement object, wherein if the electrical signal value is smaller than a predetermined reference value, the discharge detection unit issues a discharge alarm to the outside when a difference value between the electrical signal value and the reference value becomes larger than a predetermined first comparison value after the difference value becomes smaller than the first comparison value, and wherein the reference value is set equal to or larger than the maximum of the electrical signal value when no electric discharge occurs. | 12-17-2015 |
20150377947 | Current Monitor for Indicating Condition of Attached Electrical Apparatus - A current monitor is described that indicates a condition of attached electrical equipment. The current monitor can determine a predetermined range in which current being withdrawn by the attached electrical apparatus lies. Based on the determined range, corresponding display electronic elements, such as light emitting diodes (LEDs), can be activated. Activated LEDs of a particular color can indicate corresponding conditions of the electrical equipment. The condition of the electrical equipment along with other parameters, such as associated time ranges and other values, can be transmitted via a wired or wireless connection to a software system implemented on a wireless device such that a continuous monitoring and an analysis can be performed remotely. Related apparatus, systems, techniques and articles are also described. | 12-31-2015 |
20160011256 | CONTROLLING SIGNAL PATH INDUCTANCE IN AUTOMATIC TEST EQUIPMENT | 01-14-2016 |
20160018452 | CANCELLATION OF SECONDARY REVERSE REFLECTIONS IN A VERY-FAST TRANSMISSION LINE PULSE SYSTEM - An approach for cancelling reverse reflections in very-fast transmission line pulse (VFTLP) testing of an electrostatic discharge (ESD) device in a semiconductor is provided. A method includes generating an incident pulse in a VFTLP system for applying to a device under test (DUT). The method also includes generating a delayed replica of the incident pulse. The method also includes cancelling a portion of a reverse reflection of the incident pulse by combining the delayed replica with the reverse reflection at a power divider. | 01-21-2016 |
20160033577 | SAFETY CIRCUIT MONITORING USING ALTERNATING VOLTAGE - A monitoring system for people-transporting systems, which systems are in the form of an elevator, escalator or moving walkway, includes at least one interrogation device and at least one safety switch that is connected to the interrogation device via an electrical safety circuit and is used for monitoring an equipment of the people-transporting device. A current direction-dependent unit is arranged in the electrical safety circuit. Furthermore, the interrogation device applies a test voltage with an alternating polarity to the electrical safety circuit. Furthermore, a people-transporting system having such a monitoring system is provided. | 02-04-2016 |
20160054386 | Modular Test Environment for a Plurality of Test Objects - The present invention relates to an arrangement for providing a testing environment for the testing of test objects. The testing environment includes a first test object receiving apparatus and a second test object receiving apparatus, each of which are configured to receive a test object. The testing environment also includes a connection interface configured to connect the first test object receiving apparatus and the second test object receiving apparatus to the testing environment. In one embodiment, the first test object receiving apparatus has a first external connection interface, and the second test object receiving apparatus has a second external connection interface, wherein said first and second external connection interfaces are configured to be selectively coupled with the connection interface of the testing environment. | 02-25-2016 |
20160061926 | Multi-Stage Equalization - An example apparatus for interfacing between automatic test equipment (ATE) and a device under test (DUT) includes: multiple stages arranged in sequence between the ATE and the DUT, where each of the multiple stages includes a driver, at least two of the multiple stages each includes a filter, each filter is arranged between two drivers, and each filter is configured to reduce jitter produced by a preceding driver in a signal transmitted between the ATE and the DUT. | 03-03-2016 |
20160069944 | HIGH-POWERED HIGH-VOLTAGE TEST DEVICE - A high-powered, high-voltage test device is provided comprising means for generating a test voltage, wherein the test voltage is an alternating voltage having an amplitude of at least 100 kV at a power of greater than 1 kW. Said means for generating the test voltage have at least two voltage amplifier branches, of which a first voltage amplifier branch contributes to generating the positive voltage half-cycles of the test voltage and a second voltage amplifier branch contributes to generating the negative voltage half-cycles of the test voltage. The high-voltage test device furthermore has a measurement circuit for measuring the test voltage to be applied to a measurement object and the test current consequently caused in the measurement object and is characterized in that each voltage amplifier branch is installed in a separate assembly having integrated active air cooling. | 03-10-2016 |
20160070631 | Multiuser-Capable Test Environment for a Plurality of Test Objects - The present invention relates to an arrangement for providing a test environment for testing test objects. The arrangement includes a first test case implementation unit and a second test case implementation unit, as well as a first test object and a second test object. In one embodiment, the test environment is configured such that at least the first test case implementation unit is coupled to at least one of the first test object and the second test object for implementing a test case. | 03-10-2016 |
20160084899 | Diagnostic circuit and method for the operation of a diagnostic circuit - A diagnostic circuit detects an interruption in a connection between a circuit arrangement having at least one first controllable switching element, which forms a load path between a first and a second load terminal, and a load connectable thereto. The load is connectable by the switching element to a supply voltage source with a first terminal for a high supply potential and a second terminal for a lower supply potential. At least one further controllable switching element forms a load path between a first and a second load terminal, the load path of which is connected in parallel to the load path of the first switching element. A control unit controls the control inputs of the first and of the further switching element, whereby the control unit is configured for the control of the first and of the further switching element in accordance with a time-adjustable operating sequence. | 03-24-2016 |
20160086527 | TESTING APPARATUS FOR TESTING DISPLAY APPARATUS AND METHOD OF TESTING THE SAME - A testing apparatus for testing a display apparatus includes a base substrate, a plurality of fixing tools on the base substrate to affix the display apparatus to the base substrate, the plurality of fixing tools being movable in a z-axis direction independently of each other, the z-axis direction extending along a normal direction to the base substrate, and a controller that controls the fixing tools to bend the display apparatus in two or more test patterns different from each other. | 03-24-2016 |
20160097804 | TRANSMISSION LINE PULSE AND VERY FAST TRANSMISSION LINE PULSE REFLECTION CONTROL - An approach for transmission line pulse and very fast transmission line pulse reflection control is provided. The approach includes using a power splitter to split an incident pulse into two identical pulses with one going to a device under test (DUT) through a delivery cable and the other going down an open ended delay cable. The structure of the power splitter, along with having the delivery cable and the open ended delay cable with the same signal propagation time and pulse transmission characteristics enable the canceling of pulse reflections from the DUT. | 04-07-2016 |
20160097812 | SEMICONDUCTOR PACKAGE - A semiconductor package may include a probe circuit unit configured to be driven by buffering a signal received from a probe pad during probe testing, a bump circuit unit configured to buffer a signal received from a bump pad, and a power-source selection unit configured to change a level of an internal power-supply voltage applied to the probe circuit unit in response to a test-mode signal. | 04-07-2016 |
20160109499 | DEVICE AND METHOD FOR INVESTIGATING A CABLE SYSTEM - A device for investigating a cable system comprising cables and loads. The loads comprise rectifier circuits coupled to storage circuits. The device comprise a charger circuit for producing charging signals for charging the storage circuits such that they have reduced impacts on performances of the investigation signals. The device may further comprise a discharger circuit or a discharging signalling circuit after being charged by the charger circuit. The device further comprises an investigation circuit for producing an investigation signal and a controller circuit for controlling the other circuits and producing the charger signal before the investigation signal. The device may further comprise a reception circuit for receiving responses to the investigation signals and an analysis circuit for analysing the responses in view of the investigation signals and for in response to analysis results defining a problem and/or a location of a problem. | 04-21-2016 |
20160109520 | TEST PATH COMPENSATING CIRCUIT AND TEST PATH COMPENSATING SYSTEM - A test path compensating circuit may include a plurality of electrical paths electrically coupling a plurality of test pads to a test target circuit. The test path compensating circuit may include a control voltage generation circuit configured to generate a plurality of control voltages. The test path compensating circuit may include a plurality of voltage-control delay circuits electrically coupled to the plurality of electrical paths, respectively, and configured to control delay amounts of input test signals received from one or more of the plurality of test pads, based on one or more of the plurality of control voltages, and provide output test signals to the test target circuit. | 04-21-2016 |
20160126731 | PROGRAMMABLE ALTERNATING CURRENT (AC) LOAD HAVING REGENERATIVE AND DISSIPATIVE MODES - A programmable AC load in communication with an equipment under test (EUT) is disclosed. The EUT generates an equipment under test voltage. The programmable alternating current (AC) load includes an active load profiler (ALP), a grid-connecter inverter, and an operational mode selector. The operational mode selector is in communication with an AC side of the grid-connected inverter. The operational mode selector places the programmable AC load in either a regenerative mode where the equipment under test voltage is sent to a main grid or a dissipative mode where the equipment under test voltage is dissipated by heat. | 05-05-2016 |
20160131699 | APPARATUS AND METHOD FOR INTEGRATED CIRCUIT FORENSICS - A test system including an embodiment having a sensor array adapted to test one or more devices under test in learning modes as well as evaluation modes. An exemplary test system can collect a variety of test data as a part of a machine learning system associated with known-good samples. Data collected by the machine learning system can be used to calculate probabilities that devices under test in an evaluation mode meet a condition of interest based on multiple testing and sensor modalities. Learning phases or modes can be switched on before, during, or after evaluation mode sequencing to improve or adjust machine learning system capabilities to determine probabilities associated with different types of conditions of interest. Multiple permutations of probabilities can collectively be used to determine an overall probability of a condition of interest which has a variety of attributes. | 05-12-2016 |
20160131700 | APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR - Provided is an apparatus for testing a semiconductor. The apparatus includes a chuck on which a wafer is disposed, a probe card disposed on the chuck to provide a test signal to the wafer, a sensor disposed in the probe card, a base unit connected to the probe card to transmit the test signal to the probe card, and a pressure device connecting the base unit to the probe card, the pressure device correcting deformation of the probe card. | 05-12-2016 |
20160146879 | METHODS, APPARATUS AND SYSTEM FOR VOLTAGE RAMP TESTING - At least one method and system disclosed herein involves testing of integrated circuits. A device having at least one transistor and at least one dielectric layer is provided. A first voltage is provided during a first time period for performing a stress test upon the device. A second voltage is provided during a second time period for discharging at least a portion of the charge built-up as a result of the first voltage. The second voltage is of an opposite polarity of the first voltage. A sense function is provided during a third time period for determining a result of the stress test. Data relating to a breakdown of the dielectric layer based upon the result of the stress test is acquired, stored and/or transmitted. | 05-26-2016 |
20160153923 | METHOD FOR EXTRACTING TRAP TIME CONSTANT OF GATE DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE | 06-02-2016 |
20160161548 | PROGRAMMABLE TEST STRUCTURE FOR CHARACTERIZATION OF INTEGRATED CIRCUIT FABRICATION PROCESSES - A test structure includes a dedicated addressing circuit that allows large numbers of test devices to be tested simultaneously and the measurement signals read out serially for different test devices. The test structure may be configured for wafer, die or package-level testing. The test structure may be integrated on a common die with the test devices in a single package, provided on separate die in a common package, separately packaged chips or in the form of a collection of standard die configured as the test structure. If on separate die, the test and addressing circuitry is fabricated from a more mature fabrication process than that being characterized for the devices under test. The processes being characterized may be unqualified whereas the test circuitry may be fabricated with different and more mature or qualified processes. | 06-09-2016 |
20160161549 | LIGHT-ON DETECTION DEVICE AND LIGHT-ON DETECTION METHOD - The present disclosure provides a light-on detection device and a light-on detection method. The light-on detection device includes a substrate, and a probe block provided with probes and connected to the substrate. The light-on detection device further includes a flattening element configured to apply a force onto a surface of the display panel so as to change the surface of the display panel from a first shape having a first height difference to a second shape having a second height difference less than the first height difference, thereby to enable the probes to perform the light-on detection on the display panel with the second shape. | 06-09-2016 |
20160161550 | INTEGRATED CIRCUIT DEVICE COMPRISING ENVIRONMENT-HARDENED DIE AND LESS-ENVIRONMENT-HARDENED DIE - An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions. | 06-09-2016 |
20160195580 | TEST METHOD AND SYSTEM THEREOF | 07-07-2016 |
20160377687 | INVERTER TEST APPARATUS - An inverter test apparatus includes a DC power supply, a second inverter which is connected to a DC side of the first inverter, an inductor which is connected between an AC side of the first inverter and an AC side of the second inverter, a first controller which controls an AC voltage of the first inverter to be at a constant amplitude and a constant frequency, a current detector which detects a current that flows through the inductor, a phase command value computation module which computes a phase command value of the second inverter so as to control the current detected by the current detector, and a second controller which controls a phase of the second inverter, based on the phase command value computed. | 12-29-2016 |