Class / Patent application number | Description | Number of patent applications / Date published |
716016000 | PLA, PLD, FPGA, OR MCM | 32 |
20080209385 | Mapping Programmable Logic Devices - Methods and systems improve mapping of LUT based FPGAs. In some embodiments, a topological sort is performed on a network to be mapped, whereby the network is represented as a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of individual nodes using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore improves the number of LUTs and the time consumed in the mapping process. | 08-28-2008 |
20080222594 | Method and apparatus for aligning multiple outputs of an FPGA - Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained. | 09-11-2008 |
20080229271 | DATA ALIGNER IN RECONFIGURABLE COMPUTING ENVIRONMENT - A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits. | 09-18-2008 |
20080229272 | DATA ALIGNER IN RECONFIGURABLE COMPUTING ENVIRONMENT - A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits. | 09-18-2008 |
20080235647 | MODULAR DESIGN METHOD AND APPARATUS - Disclosed is a procedure or design approach for functional modules that may be used in connection with a multiprocessor integrated circuit chip. The approach includes keeping the dimensions of each module substantially the same and having the bus, power, clock and I/O connection configured the same on all modules. Further requirements for ease of use are to generalize the capability of each module as much as possible and to decentralize functions such as testing to be primarily performed within each module. The use of such considerations or rules substantially eases the design of a given type of custom chips, and based upon an initial chip design greatly facilitates the design of further custom chips, similar in application, but subsequent to the successful completion of the initial chip. The standardization modules and replication of the modules on a given chip also reduces physical verification time in initial chip design as well as redesign time of the initial chip when requirements for chip capability are redefined or otherwise changed. Any subsequent or further custom chips can include more or less of specific modules based upon already established parameters. | 09-25-2008 |
20080244500 | System, methods and apparatuses for integrated circuits for nanorobotics - The invention describes apparatuses for nano-scale integrated circuits applied to nanorobotics. Using EDA techniques, the system develops fully functional nano ICs, including ASICs and microprocessors. Three dimensional nano ICs are disclosed for increased efficiency in nanorobotic apparatuses. Nano-scale FPGAs are disclosed. The nano-scale semiconductors have applications to nano-scale and micro-scale robots. | 10-02-2008 |
20080250378 | CIRCUIT EMULATION AND DEBUGGING METHOD - A synthesizer processes a register transfer level (RTL) netlist description of a circuit to produce a non-optimized gate level netlist preserving all signals referenced by the RTL netlist. The gate level netlist is then processed to identify the circuit's memory devices and to determine logical relationships between its internal signals (all signals other than circuit and memory device input and output signals) and its other signals (circuit and memory device input and output signals). The synthesizer then again processes the RTL netlist to produce an optimized gate level netlist that preserves the identified memory devices, but which omits reference to some or all of the internal signals. A circuit verification system then processes the optimized gate level netlist to produce waveform data representing time-varying behavior of the other signals of the circuit. The waveform data is then processed to produce additional waveform data representing behavior of the internal signals referenced by the RTL netlist in accordance with the determined logical relationships between the internal signals and the other signals. | 10-09-2008 |
20080263499 | DATAPIPE INTERPOLATION DEVICE - A system for data processing comprises a host circuit ( | 10-23-2008 |
20080263500 | Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method - An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin-assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. A pin-swap processing unit retrieves pin swap information from a package-designing CAD apparatus, and reflect the pin swap in the symbol library, the FPGA information, a circuit diagram, and a constrained condition. | 10-23-2008 |
20080282214 | RECONFIGURABLE INTEGRATED CIRCUIT - The purpose of the present invention is to realize reduction of power consumption of reconfigurable integrated circuits such as FPGAs by decreasing leakage current in SRAMs. | 11-13-2008 |
20080288909 | Template-Based Domain-Specific Reconfigurable Logic - A method is provided which creates an architecture of a reconfigurable logic core. The architecture can be deployed for various purposes and its implementation is costefficient in terms of area, performance and power. The invention relies on the perception that a template can be used to describe such an architecture. The architecture can then easily be created as an instance of the template. The template is a model which defines logic components, routing components and interface components of a reconfigurable logic core. For example, logic components may be logic elements, processing elements, logic blocks, logic tiles and arrays in a hierarchical order. Routing components may comprise routing channels comprising routing tracks which provide interconnection means between the logic components. Interface components may be input and output ports. The model is configured by a number of parameters; the value of these parameters is in accordance with an application domain. | 11-20-2008 |
20080320433 | Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit- board manufacturing method - An FPGA-design-CAD interface unit retrieves pin assignment information created by an FPGA-designing CAD apparatus. An FPGA-pin-information managing unit manages the pin assignment information as FPGA pin information. A temporary-library creating unit creates a temporary component shape type library by using the FPGA pin information and outputs the temporary component shape type library in a form capable of being read by a package-designing CAD apparatus to a file. | 12-25-2008 |
20090007050 | System for designing re-programmable digital hardware platforms - A digital design system and method are provided for re-programmable hardware platforms, such as field programmable gate arrays (FPGAs) and other re-programmable system designs. The design system and method bridge the gap between what has previously been a development and prototyping platform used during the design phase of an electronic design system (EDS) project, and commercially viable re-programmable product platforms to replace non-programmable platforms, such as discrete processors and ASICs. | 01-01-2009 |
20090044165 | FPGA with hybrid interconnect - An Application-Specific Field Programmable Gate Array (FPGA) device or fabric is described for use in applications requiring fast reconfigurability of devices in the field, enabling multiple personalities for re-using silicon resources (like arrays of large multipliers in DSP applications) from moment-to-moment for implementing different hardware algorithms. In a general purpose FPGA device or fabric, this fast reconfigurability is normally implemented by special reconfiguration support circuitry and/or additional configuration memory. Unfortunately, this flexibility requires a large amount of programmable routing resource and silicon area—limiting the viability in volume production applications. This invention describes how multi-program FPGA functionalities may be migrated to smaller die by constructing implementations with a hybrid FPGA/ASIC interconnect structure. These implementations retain multi-program capability while requiring a much smaller silicon area than a conventional FPGA when customized for a particular set of user applications. | 02-12-2009 |
20090049419 | Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method - An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin-assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. When performing a DRC, as for in an FPGA, a DRC unit checks an attribute of a pin and the like by referring to the FPGA information that is retrieved from the FPGA-designing CAD apparatus and stored in a FPGA-information storing unit by the FPGA-information managing unit. | 02-19-2009 |
20090070727 | Three dimensional integrated circuits and methods of fabrication - Three dimensional integrated circuitry is described with applications to hybrid multiprocessor and reconfigurable computing. Methods of fabrication of multilayer ICs are shown using multilayer TSVs. | 03-12-2009 |
20090070728 | IP cores in reconfigurable three dimensional integrated circuits - The invention describes IP cores applied to 3D FPGAs, CPLDs and reprogrammable SoCs. IP cores are (a) used for continuously evolvable hardware using 3D logic circuits, (b) applied with optimization metaheuristic algorithms, (c) applied by matching combinatorial logic of netlists generated by Boolean algebra to combinatorial geometry of CPLD architecture by reaggregating IP core elements and (d) continuous recalibration of IP cores with evolvable hardware in indeterministic environments for co-evolutionary reprogrammability. | 03-12-2009 |
20090193384 | SHIFT-ENABLED RECONFIGURABLE DEVICE - A coarse-grain reconfigurable array that implements shift operations within its interconnection network is disclosed. The interconnection network of such a coarse-grain reconfigurable array contains partially or fully populated matrices of switches, where each such matrix of switches is obtained by merging a standard diagonal switch matrix with an array shift unit. The disclosed device provides better performance when the standard routing and shift functions are both required. | 07-30-2009 |
20090204935 | Semiconductor device, design method and structure - A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. At least a first conductive line can comprise a semiconductor material formed over and in contact with the first diffusion region and the second diffusion region. A portion of the first conductive line in contact with the first diffusion region is doped to an opposite conductivity type as the first diffusion region. At least a second conductive line comprising a semiconductor material is formed in parallel with the first conductive line and over and in contact with the first diffusion region and the second diffusion region. A portion of the second conductive line can be in contact with the first diffusion region and doped to a same conductivity type as the first diffusion region. A portion of the second conductive line in contact with the second diffusion region can be doped to a same conductivity type as the second diffusion region. | 08-13-2009 |
20090235222 | CREATING A STANDARD CELL CIRCUIT DESIGN FROM A PROGRAMMABLE LOGIC DEVICE CIRCUIT DESIGN - A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist ( | 09-17-2009 |
20090249276 | METHODS AND SYSTEMS FOR FPGA REWIRING AND ROUTING IN EDA DESIGNS - Disclosed are a method and a system for improving FPGA routings of a circuit. The method comprises: identifying candidate alternative wires for a target wire to be replaced in the circuit according to a first preset rule; selecting a first set of alternative wires from the identified candidates according to a second preset rule; filtering the selected first set of candidates so as to reserve a second set of candidates; estimating wire replacing costs of the second set of candidates to select a third set of candidates that can improve FPGA delay performance of the circuit; and replacing the target wire with the selected third set of candidate alternative wires. | 10-01-2009 |
20090288057 | System and Method for Ordering the Selection of Integrated Circuit Chips - A routing engine for use with a mounter having a chip selector and a method of routing a chip selector of a mounter. In one embodiment, the routing engine includes: (1) a memory configured to receive and store an electronic wafer map that contains coordinates and characterizations of chips of a particular wafer and (2) a travel path generator associated with the memory and configured to employ a heuristic analysis routine to generate a non-raster travel path for the chip selector to traverse with respect to the particular wafer that is shorter than a serpentine raster travel path. | 11-19-2009 |
20090293035 | INCREASED EFFECTIVE FLIP-FLOP DENSITY IN A STRUCTURED ASIC - An H-tree is formed in a conducting layer over the base array of a structured ASIC, the H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of the base array and H-tree. The endpoints of the H-tree are formed at or near sequential elements. When the H-tree is used as part of a clock structure, clock skew to the sequential elements is minimized as is the consumption of routing resources for forming the clock structure. When a pulse generator is coupled to the H-tree, individual flip-flops can be emulated with individual latches, thereby increasing the effective flip-flop density. | 11-26-2009 |
20090300571 | METHODS AND SYSTEMS FOR FPGA REWIRING - There are disclosed a method and system for FPGA rewiring of a circuit. The method comprises: mapping the circuit into a first circuit, the first circuit being logically represented with a plurality of Look-Up Tables; rewiring the first circuit to obtain a second circuit, a mapping area of the second circuit being less than that of the first circuit; mapping the second circuit into a third circuit, the third circuit being logically represented with less Look-Up Tables than the first circuit; and routing the third circuit to generate a FPGA architecture file related to the circuit. | 12-03-2009 |
20100017774 | METHOD AND SYSTEM FOR MOUNTING CIRCUIT DESIGN ON RECONFIGURABLE DEVICE - There is provided a system for generating configuration data for implementing a circuit design in a segmented reconfigurable device. A placement and routing design aiding system ( | 01-21-2010 |
20100017775 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided. | 01-21-2010 |
20100031222 | BASE PLATFORMS WITH COMBINED ASIC AND FPGA FEATURES AND PROCESS OF USING THE SAME - A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions. | 02-04-2010 |
20100058274 | FLEXIBLE HARDWARE UPGRADE MECHANISM FOR DATA COMMUNICATIONS EQUIPMENT - Partial reconfiguration of programmable logic devices may be achieved in a hardware-controlled manner without relying upon software. Upon installation of a new memory module, partial reconfiguration may enable alteration of a clock frequency without affecting operation of the software. When a new interface is installed, partial reconfiguration will allow a programmable logic device to adapt to either a serial or parallel interface before executing a standard boot-up sequence for the computer system. | 03-04-2010 |
20100070942 | Automated Metal Pattern Generation for Integrated Circuits - An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the data points in the set uniquely matched to a plurality of fixed metal tabs; and selecting a metal tab from a first set of selectable metal tabs for a first data value, or a second set of selectable metal tabs for a second data value for each of the fixed metal tabs; wherein a first set metal tab and a second set metal tab couples each said fixed metal tab to first and second voltages respectively. | 03-18-2010 |
20100100864 | FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS - A fast, flexible carry scheme for use in clustered field programmable gate array architectures is described. Each cluster has a cluster carry input node, a cluster carry output node, a cluster carry output circuit having an output coupled to the cluster carry output node, a first input coupled to the cluster carry input node, and a second input and a plurality of logic modules each comprising a logic function generator circuit coupled to a carry circuit. The logic modules are coupled in a series carry arrangement between the cluster carry input node and the second input of the cluster carry output circuit such that the least significant bit of an arithmetic logic circuit can be programmably placed in any of the logic modules. | 04-22-2010 |
20100138804 | Methods and Apparatuses for Automated Circuit Design - Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a logic function feeding a carry chain is implemented through extending the carry chain and through using the extended portion of the carry chain. In one aspect of an embodiment, control/non-control loads are separated from each other through replicating the driver elements of the mixed control/non-control loads. In one aspect of an embodiment, a read only memory (ROM) is implemented using a random access memory (RAM). In one embodiment, a register at the input side of the ROM is generated through inserting a register that is clocked at an inverted clock signal or through retiming a register from the output side of the ROM. | 06-03-2010 |
20100218158 | METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRATED CIRCUIT - A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. | 08-26-2010 |