Class / Patent application number | Description | Number of patent applications / Date published |
714811000 | Forbidden combination or improper condition | 9 |
20100023848 | METHOD AND DEVICE FOR INPUTTING DIGITAL VALUES - The invention concerns a device ( | 01-28-2010 |
20100138729 | Pseudorandom binary sequence checker with control circuitry for end-of-test check - Control circuitry is coupled between an error event output and a data input of a pseudorandom binary sequence (PRBS) checker. The control circuitry is configured to switch between a first operating state in which a received PRBS signal is applied to the data input of the PRBS checker and a second operating state in which an error signal is applied to the data input of the PRBS checker, responsive to detection of a designated condition of the PRBS checker. In an illustrative embodiment, the designated condition is an end-of-test condition indicating that the PRBS checker has completed a test involving the received PRBS signal. | 06-03-2010 |
20100169752 | STORAGE CIRCUIT WITH FAULT DETECTION AND METHOD FOR OPERATING THE SAME - Some embodiments show a storage circuit with fault detection. The storage circuit comprises, first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state. Furthermore the storage circuit comprises a data input, a circuitry configured to cause the first fault detection circuit to assume the first stable state and the second fault detection circuit to assume the second stable state to store a data signal applied to the data input and a first output indicative of the state of the first fault detection circuit and a second output indicative of the state of the second fault detection circuit, wherein an invalid combination of the signal states at the first and second outputs indicate a fault. | 07-01-2010 |
20100281350 | Method, Apparatus, and Computer Program Product for Written Mathematical Expression Analysis - Various methods for written mathematical expression analysis are provided. One method may include receiving written input where the written input is representative of a mathematical expression. The method may also include analyzing the written input to identify at least one operator and at least one operand and constructing an expression tree based at least in part on predefined symbol relationships, the at least one operator, and the at least one operand. Similar apparatuses and computer program products are also provided. | 11-04-2010 |
20110264990 | VERIFYING THE ERROR BOUND OF NUMERICAL COMPUTATION IMPLEMENTED IN COMPUTER SYSTEMS - A verification tool receives a finite precision definition for an approximation of an infinite precision numerical function implemented in a processor in the form of a polynomial of bounded functions. The verification tool receives a domain for verifying outputs of segments associated with the infinite precision numerical function. The verification tool splits the domain into at least two segments, wherein each segment is non-overlapping with any other segment and converts, for each segment, a polynomial of bounded functions for the segment to a simplified formula comprising a polynomial, an inequality, and a constant for a selected segment. The verification tool calculates upper bounds of the polynomial for the at least two segments, beginning with the selected segment and reports the segments that violate a bounding condition. | 10-27-2011 |
20130111310 | Enforcing Input Validation Through Aspect Oriented Programming | 05-02-2013 |
20130117642 | DATA RETURNED RESPONSIVE TO EXECUTING A START SUBCHANNEL INSTRUCTION - An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory. | 05-09-2013 |
714812000 | Specified digital signal or pulse count | 1 |
20130124950 | Low Latency Enumeration Endec - Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data. | 05-16-2013 |
714817000 | Noise level | 1 |
20110060975 | SYSTEM FOR DETECTING OPERATING ERRORS IN INTEGRATED CIRCUITS - Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse. | 03-10-2011 |