Entries |
Document | Title | Date |
20080209285 | Method and Circuit for Measuring Operating and Leakage Current of Individual Blocks Within an Array of Test Circuit Blocks - A method and circuits for measuring operating and leakage current of individual blocks within an array of test circuit blocks provides measurement free of error due to leakage currents through non-selected circuit blocks, without requiring an independent test facility for each circuit block. The circuit includes a pair of power supply grids and selection circuits at each test circuit block to select between a test power grid and a “rest” power grid used to supply current to the non-selected circuits. The leakage currents through the non-selected circuits are thus sourced from the rest grid and error that would otherwise be introduced in the test grid current measurement is avoided. The test circuit blocks may be ring oscillators, and the measured current may be the operating and/or leakage current of the ring oscillator. The circuit blocks may also include individual devices for IV (current-voltage) characterization using an additional gate input grid. | 08-28-2008 |
20080209286 | LOGIC CIRCUITRY AND RECORDING MEDIUM - Logic circuitry has a test point to detect a signal about a delay fault propagating on a logic path between an input terminal and an output terminal, the test point being coupled to the logic path, wherein the test point includes a delay component to delay timing to detect the signal about a delay fault propagating on the logic path by predetermined time. | 08-28-2008 |
20080222465 | Checkpointing user design states in a configurable IC - Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values. The configurable IC also includes a debug network communicatively coupled to the UDS circuits. The debug network is for retrieving the user-design state values of several UDS circuits at various stoppages of the operation of the IC without retrieving configuration data that is used to configure the configurable circuits of the IC. The retrieved user-design state values at each stoppage are used as the checkpointed state of the IC while debugging the IC. In some embodiments, the debug network allows the checkpointing of only certain portions of the configurable IC. | 09-11-2008 |
20080222466 | Meeting point thread characterization - An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run. | 09-11-2008 |
20080222467 | METHOD OF CONTROLLING A TEST MODE OF CIRCUIT - A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. The signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector. | 09-11-2008 |
20080235542 | Electronic testing device for memory devices and related methods - Described are an electronic testing device for memory devices and related methods. The testing device, comprises a memory controller managing a transfer of data and a controller buffer disposed within the memory controller. The controller buffer transfers data between the memory controller and a memory module. The memory controller tests the memory module. The testing device is operable to test the memory module independent of an operating rate of the memory module. The memory controller receives operating data of the memory module. | 09-25-2008 |
20080235543 | CONVERSION DEVICE, CONVERSION METHOD, PROGRAM, AND RECORDING MEDIUM - Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device | 09-25-2008 |
20080250279 | Method of Increasing Path Coverage in Transition Test Generation - A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently. | 10-09-2008 |
20080250280 | Sharing routing of a test signal with an alternative power supply to combinatorial logic for low power design - A device shares an existing test signal routing trace with an alternative power supply delivery channel to portions of registers located in combinatorial logic sections. | 10-09-2008 |
20080250281 | METHODS AND APPARATUS FOR MONITORING INTERNAL SIGNALS IN AN INTEGRATED CIRCUIT - Apparatus and methods are provided for debugging an integrated circuit. Local multiplexer circuits are provided near first and second circuit blocks in the integrated circuit. Each multiplexer circuit includes input nodes, a control node, and an output node. A first input node of the first multiplexer circuit is coupled to an internal node of the first circuit block, a first input node of the second multiplexer circuit is coupled to an internal node of the second circuit block, second input nodes of the first and second multiplexer circuits are coupled to logical | 10-09-2008 |
20080250282 | SERIAL I/O USING JTAG TCK AND TMS SIGNALS - The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. | 10-09-2008 |
20080256404 | FAULT LOCATION ESTIMATION SYSTEM, FAULT LOCATION ESTIMATION METHOD, AND FAULT LOCATION ESTIMATION PROGRAM FOR MULTIPLE FAULTS IN LOGIC CIRCUIT - A fault location estimation system comprises single-fault-assumed diagnostic means that assumes a single fault and stores fault candidates, fault types, and detected error-observation nodes at which an error arrives from the fault candidates; error-observation node basis candidate classification means that classifies error propagating fault candidates into groups according to error-observation nodes using the fault candidates and the error-observation nodes and stores the groups as fault candidate groups; inclusion fault candidate group selection means that acquires a relation between each fault candidate group and a fault output, calculates an inclusion relation among the fault candidate groups, and, if path information on one fault candidate group includes path information on another fault candidate group, deletes the inclusion fault candidate group; inter-pattern overlapping means that calculates combinations of fault candidate groups that can reproduce a test result in all test patterns by referencing the fault candidates and the fault candidate classification result and extracts fault candidates that are common to fault candidate groups, calculated in multiple patterns, to create a new fault candidate group; and multiple-fault simulation checking means that selects fault candidates from the combinations of fault candidate groups, one from each fault candidate group, performs multiple-fault simulation, compares the simulation result with the test result, and outputs a combination of fault candidate groups which matches relatively well with the test result and has a relatively high fault possibility. | 10-16-2008 |
20080263418 | System and Method for Adaptive Nonlinear Test Vector Compression - A system comprises a decompressor configured to receive an input test vector and to generate an output vector in response to the input test vector. A decoder couples to the decompressor and comprises a reset pattern detector, a lookup table, and control logic. The reset pattern detector (RPD) is configured to scan the output vector to identify a predetermined reset pattern. The control logic couples to the RPD and the lookup table and is configured to direct operation of the lookup table in a first mode or a second mode based on whether the output vector comprises the predetermined reset pattern, as identified by the RPD. The lookup table is configured to receive the output vector, to operate in the first mode, comprising storing one of a plurality of codeword sets, each codeword set comprising a plurality of pairs of codewords and associated data; and to operate in the second mode, comprising generating test data blocks in response to identified codewords in the output vector. | 10-23-2008 |
20080263419 | REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY - Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains. | 10-23-2008 |
20080301509 | METHOD AND APPARATUS FOR TESTING INTEGRATED CIRCUITS BY EMPLOYING TEST VECTOR PATTERNS THAT SATISFY PASSBAND REQUIREMENTS IMPOSED BY COMMUNICATION CHANNELS - Embodiments of an apparatus and method for high-speed testing of a device under test are described herein, where the device under test is coupled to a tester via a limited passband communication channel. A plurality of test vector patterns is generated having characteristics such that when a given test vector pattern is transmitted electrically at a transmission rate via the communication channel, the test vector pattern has a frequency content that is less than the frequency content of a high frequency test vector pattern if the high frequency test vector pattern were to be transmitted electrically at the transmission rate via the communication channel, and such that the frequency content of each test vector pattern when transmitted electrically at the transmission rate via the communication channel falls within the passband associated with the communication channel. | 12-04-2008 |
20090013224 | INTEGRATED CIRCUIT WITH BLOCKING PIN TO COORDINATE ENTRY INTO TEST MODE - An integrated circuit (IC) including a blocking pin. An IC may include state logic, a test control unit configured to coordinate access by external circuitry to operating state of the state logic during a test mode, and interface pins configured to couple the integrated circuit to the external circuitry. Shared interface pins may provide input signals to the test control unit during the test mode of operation and may perform distinct I/O functions during normal mode operation. A blocking interface pin, when asserted by external circuitry during normal mode operation, may force test signals derived from at least a portion of the shared interface pins by the test control unit into respective quiescent states, such that subsequent to assertion of the blocking pin, the integrated circuit is operable to enter the test mode of operation from the normal mode of operation without resetting operating state of the state logic. | 01-08-2009 |
20090013225 | TEST MODE CONTROL CIRCUIT - Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated. | 01-08-2009 |
20090044063 | Semiconductor memory device and test system of a semiconductor memory device - A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle. | 02-12-2009 |
20090049352 | CONTROL APPARATUS AND METHOD FOR CONTROLLING MEASURING DEVICES TO TEST ELECTRONIC APPARATUSES - An electronic apparatus testing method is provided. The method includes the step of: reading a product ID of the electronic apparatus when the electronic apparatus is connected to a control apparatus; determining the device type ID from the product ID, wherein the product ID comprises basic information of the electronic apparatus, determining the script files of the functions of the electronic apparatus in the testing table according to the device type ID; obtaining the script files from a data storage and running the script files to test functions of the electronic apparatuses, sending a control instruction to the corresponding measuring device of the function to control the measuring device test the function during the process of running the script files; and displaying test results through a display of the control apparatus. | 02-19-2009 |
20090055695 | INTEGRATED CIRCUIT WITH SELF-TEST FEATURE FOR VALIDATING FUNCTIONALITY OF EXTERNAL INTERFACES - This disclosure describes an integrated circuit with self-test features for validating functionality of external interfaces. Example external interfaces include memory interfaces and bus interfaces, such as a peripheral component interconnect (PCI) bus, an advanced high-performance bus (AHB), an advanced extensible interface (AXI) bus, and other external interfaces that operate a high frequency, e.g., 200 MHz or greater. Test logic may be embedded on the integrated circuit and configured to validate functionality of external interfaces while receiving power and non-test signals from external test equipment. Thus, external test equipment may not supply high frequency test signals to the integrated circuit. The external test equipment may, however, independently validate functionality of a pin interface of the integrated circuit. As a result, the integrated circuit may reduce cost and time required to verify functionality and timing of the external interfaces. | 02-26-2009 |
20090070644 | METHOD AND APPARATUS FOR DYNAMICALLY DETERMINING TESTER RECIPES - A method includes retrieving a group test parameter determined based on test results associated with a plurality of integrated circuit devices. A particular integrated circuit device is tested using a test program and the group test parameter. | 03-12-2009 |
20090113260 | TEST SYSTEM - A test system for testing a plurality of devices under test is disclosed. The test system includes a tester and a plurality of processors. The tester is used for providing a plurality of control signals and determining a plurality of test results for the devices under test according to a plurality of measurement results. Each processor coupled to the tester is used for generating a plurality of test signals according to the plurality of control signals. The plurality of devices under test respectively generates the plurality of test results according to the plurality of test signals. | 04-30-2009 |
20090113261 | CONVERSION DEVICE, CONVERSION METHOD, PROGRAM, AND RECORDING MEDIUM - Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test pattern | 04-30-2009 |
20090119555 | Hyperjtag System Including Debug Probe, On-Chip Instrumentation, and Protocol - A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip instrumentation includes an on-chip instrumentation concentrator and an on-chip instrumentation de-concentrator. The probe includes a probe concentrator and a probe de-concentrator. The probe concentrator concentrates signals from the test instruments into a first serial signal stream for transmission over the connector mechanism. The on-chip instrumentation de-concentrator de-concentrates the first serial signal stream into signals to be directed to at least one of the processor cores. The on-chip instrumentation concentrator concentrates signals from the processor cores into a second serial signal stream for transmission over the connector mechanism. The probe de-concentrator de-concentrates the second serial signal stream into signals to be directed to at least one of the testing instruments. Using this system, the testing instruments are able to simultaneously access and control respective processor cores. In one preferred embodiment the plurality of signals are directed to the processor cores using a plurality of loops, each loop having a chain of nodes, each of the processor cores connected to a respective node. | 05-07-2009 |
20090125765 | Apparatus for Certifying Hardware Abstraction Layer in Mobile Terminal and Method Thereof - Provided is an apparatus and method for certifying a hardware abstraction layer in a mobile terminal. The apparatus includes: a communication unit for receiving a predetermined test case from an external host certifying system and transmitting a test result of performing the received test cast to the host certifying system; an event receiver for receiving a test result of performing an event type test case from a hardware abstraction layer; and a controller for controlling the hardware abstraction layer to perform the test case received through the communication unit, and receiving the test result of performing the received test case received from the event receiver or the hardware abstraction layer and transmitting the received test result to the host certifying system. | 05-14-2009 |
20090125766 | METHOD, SYSTEM AND COMPUTER PROGRAM FOR HARDWARE DESIGN DEBUGGING - A plurality of diagnosis methods are provided for enabling hardware debugging. A first diagnosis method enables hardware debugging by means of time abstraction. A second diagnosis method enables hardware debugging by means of abstraction and refinement. A third diagnosis method enables hardware debugging by means of QBF-formulation for replicated functions. A fourth diagnosis method enables hardware debugging by means of a max-sat debugging formulation. A system and computer program for implementing the diagnosis methods is also provide. | 05-14-2009 |
20090132877 | Method for Embedded Integrated End-to-End Testing - A method and system for automated testing of a system such as a billing module in a telecommunication system is disclosed. In a first embodiment, test APIs, scenarios and configuration information are embedded into the module itself in a way such that, when testing is desired, tests may be conducted without any need for a dedicated test environment. Tests can be run from within the module itself, thereby eliminating the risk, expense and time required to use external testing systems and data to test the module. In another embodiment, operational data such as live operational orders are wrapped in test headers and are used as input data for testing purposes within the billing module. In this embodiment, test APIs may be embedded into all modules of an operational support system so that complete system end-to-end testing is possible without the use of dedicated external test equipment and processes. | 05-21-2009 |
20090138769 | Test System Having A Sub-System To Sub-System Bridge - A test system having a sub-system to sub-system bridge may be provided that utilizes the useful attributes of a plurality of circuit testing techniques, while reducing deficiencies associated with certain types of circuit testing. A bridged test system structure is utilized to facilitate circuit testing that is more effective and time efficient. The method analyzes performance data acquired by a first component for one or more circuits, and sends that performance data to a second test component. The second test component provides test signals to the circuits, using the performance date to enhance the use of the test signals, and also provides test response data for the circuits in response to the provided test signals. | 05-28-2009 |
20090172484 | Method for Implementing a Serialization Construct Within an Environment of Parallel Data Flow Graphs - A serialization construct is implemented within an environment of a number of parallel data flow graphs. A quiesce node is appended to every active data flow graph. The quiesce node prevents a token from passing to a next data flow graph within a chain before an execution of the active data flow graph has been finished. A serial data flow graph is implemented to provided for a serial execution while no other data flow graph is active. A serialize node is appended to a starting point of a serial data flow graph. A serialize end node is appended to an endpoint of the serial data flow graph. The serialize node is activated to start a serial operation. The serialize end node is activated after the serial operation has been terminated. | 07-02-2009 |
20090204860 | Data signal handling circuitry and methods with error analysis capabilities - To help identify a noise (interference) source in an electronic device that may be causing data errors in the device, relatively low level data receiver circuitry in the device is provided with one or more error signal output leads. An error signal on such a lead includes an error indication as soon as possible after the associated low level circuitry detects a data error. The timing of such an error indication is compared to the timing of noise from various possible noise sources in the device. The noise source that produced significant noise closest in time prior to the error indication may be identified as the noise source that was probably responsible for the data error that caused the error indication. | 08-13-2009 |
20090249141 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a flipflop holding and outputting input data according to a clock, the flipflop having: an input end to which data is input; an output end from which data is output; a first logic gate connected between the input end and the output end, the first logic gate operating according to the clock; a second logic gate connected between the first logic gate and the output end, the second logic gate operating according to the clock; and a buffer circuit. An input of the buffer circuit is connected to a node between the first logic gate and the input end. An output of the buffer circuit is connected to a node in an output side of the first logic gate. The buffer circuit transitions according to an enable signal from a high impedance state to a state in which a signal can be transmitted. | 10-01-2009 |
20090259897 | Logic circuit protected against transient disturbances - The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit ( | 10-15-2009 |
20090300445 | METHOD AND SYSTEM FOR ALTERNATING BETWEEN PROGRAMS FOR EXECUTION BY CELLS OF AN INTEGRATED CIRCUIT - A method and device for data processing in an integrated circuit having cells, the cells adapted for executing programs. A first program is run. In response to a waiting condition during which no program execution is able to take place, saving data from the cells to a memory. A second program, e.g., a test program, is run after the data is saved. The saved data is then reloaded into the cells after running the second program. | 12-03-2009 |
20090327823 | REMOVEABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY - Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains. | 12-31-2009 |
20100011262 | REDUCED SIGNALING INTERFACE METHOD AND APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. | 01-14-2010 |
20100050029 | Method And Apparatus For Testing Semiconductor Devices With Autonomous Expected Value Generation - Method and apparatus for testing semiconductor devices with autonomous expected value generation is described. Examples of the invention can relate to apparatus for interfacing a tester and a semiconductor device under test (DUT). An apparatus can include output processing logic configured to receive test result signals from the DUT responsive to testing by the tester, the output processing logic voting a logic value of a majority of the test result signals as a correct logic value; and memory configured to store indications of whether each of the test result signals has the correct logic value. | 02-25-2010 |
20100088560 | METHOD AND SYSTEM FOR SELECTING TEST VECTORS IN STATISTICAL VOLUME DIAGNOSIS USING FAILED TEST DATA - A method and system for test vector selection in statistical volume diagnosis using failed test data is disclosed. A computer-implemented method receives failures representing defects detected by an integrated circuit testing apparatus from a plurality of integrated circuits. Each of the plurality of integrated circuits is tested with a set of test vectors generated by the integrated circuit testing apparatus, and each of the plurality of failures is associated with a failed test vector. Using a first ranking scheme, each of the failures is given a rank and the corresponding failed test vector in each of the plurality of integrated circuits is annotated with the rank. The annotated failed test vectors are grouped using a grouping scheme, and each of the groups is given a group rank. A first group of failed test vectors is selected based on the group rank and diagnostics is run on the first group of tailed test vectors. | 04-08-2010 |
20100138706 | TAP sampling at double rate - An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge. | 06-03-2010 |
20100205491 | LOGIC VALUE DETERMINATION METHOD AND LOGIC VALUE DETERMINATION PROGRAM - The provided are logic value determination method and program for identifying unspecified bits and determining their logic values shortly. The method enables to control the total number of logic value differences between corresponding input and output lines of combinational circuit. The method includes the first step for determining, when output has a logic value and input has an unspecified value, that the unspecified bit has the logic value of output, the second step for determining, when output has an unspecified value and input has a logic value, the logic value of the unspecified bit by justification, and the third step for calculating, when input and output both have unspecified values, probabilities of output to have 0 and 1, and determining the logic value of the unspecified bit based on the difference between the probabilities. The third step is repeated until the total number reaches a target value. | 08-12-2010 |
20100218058 | FAULT INJECTION - Systems, methods, and other embodiments associated with programmable application specific integrated circuit (ASIC) fault injection are described. One example ASIC includes a serializer de-serializer (SERDES). The example ASIC may also include logics to process data in the ASIC. At least one of the logics either receives data from the SERDES and/or provides data to the SERDES. The example ASIC may also include an embedded fault injection logic (EFIL) to control injection of a fault to a path (e.g., data, control) associated with at least one of the logics. The example ASIC may also include an embedded set of multiplexers (ESOMs) controlled by the EFIL. The ESOMs are controllable by the EFIL to inject a fault signal to the data path. | 08-26-2010 |
20100251045 | High Speed Clock Control - On-chip high speed clock control techniques for testing circuits with multiple clock systems are disclosed. The techniques allow certain (e.g. compatible) high speed clocks to be activated with predefined waveforms during a capture period of a logic test, based on a clock control signal. The clock control signal may be supplied via a JTAG control port or via a scan chain load port. The clock control signal may also be generated by a BIST controller. The techniques may ensure glitch-free transitions from slow speed clocks during a shift period to fast speed clocks during a capture period. | 09-30-2010 |
20100325498 | MEMORY SYSTEM - A memory system includes a nonvolatile memory, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that performs communication with a host according to an aspect of the preset invention, wherein the control circuit includes a reading unit that outputs a read enable signal to the nonvolatile memory to read data; a delay unit that delays a signal obtained by returning the read enable signal and outputs the signal as a clock, and a latch unit that latches and outputs the data read from the nonvolatile memory by using the clock output from the delay unit. | 12-23-2010 |
20100332927 | GENERIC DEBUG EXTERNAL CONNECTION (GDXC) FOR HIGH INTEGRATION INTEGRATED CIRCUITS - A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools. | 12-30-2010 |
20110022906 | METHOD AND SYSTEM FOR TEST POINT INSERTION - It is desired to suppress an increase of the TAT or a repetition of processing in inserting a test circuit on designing. A test point insertion method includes: extracting a plurality of logic cones from a net list; generating an order for the plurality of logic cones based on a connection relation of logic cells in each of the plurality of logic cones; and setting a test point in each of the plurality of logic cones in turn in accordance with the order. | 01-27-2011 |
20110029828 | FAULT INJECTION DETECTOR IN AN INTEGRATED CIRCUIT - A circuit for detecting a fault injection in an integrated circuit including: at least one logic block for performing a logic function of said integrated circuit; an isolation block coupled to receive a signal to be processed and an isolation enable signal indicating a functional phase and a detection phase of the logic block, the isolation block applying, during the functional phase, the signal to be processed to at least one input of the logic block, and during the detection phase, a constant value to the input of the logic block; and a detection block adapted to monitor, during the detection phase, the state of the output signal of the logic block, and to generate an alert signal in case of any change in the state of the output signal. | 02-03-2011 |
20110041017 | On-Die Logic Analyzer For Semiconductor Die - In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed. | 02-17-2011 |
20110047423 | Integrated Circuit Including a Programmable Logic Analyzer with Enhanced Analyzing and Debugging Capabilities and a Method Therefor - An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile. | 02-24-2011 |
20110060953 | TESTING MOBILE WIRELESS DEVICES DURING DEVICE PRODUCTION - A system and method of testing a wireless communication device during device production comprises designating as a data log buffer when the device is being produced, at least part of random access memory (RAM) of the device that is allocated for virtual machine and/or application usage when the device is operational; and testing the device and storing test log data in the buffer. After testing, the data can be obtained from the buffer and processed using a debugging and log analysis tool. | 03-10-2011 |
20110078522 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A self-test circuit includes a test circuit for processing input data and outputting output data having higher randomness than the input data; a storage unit for holding initial input data to be inputted to the test circuit when a self-test operation is performed on the test circuit; a feedback unit for feeding back, as input data to the test circuit, the output data which is obtained through processing of the input data by the test circuit and which is outputted from the test circuit; a control unit for controlling the number of times that the feedback unit feeds back the output data from the test circuit as input data to the test circuit; and a comparing unit for comparing the output data outputted from the test circuit and an expected value. | 03-31-2011 |
20110087936 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT - An addressable interface selectively enables JTAG TAP domain operations or Trace domain operations within an IC. After being enabled, the TAP receives TMS and TDI input from a single data pin. After being enabled, the Trace domain acquires data from a functioning circuit within the IC in response to a first clock and outputs the acquired data from the IC in response to a second clock. An addressable two pin interface loads and updates instructions and data to a TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. Trace circuitry within an IC can operate autonomously to store and output functional data occurring in the IC. The store and output operations of the trace circuitry are transparent to the functional operation of the IC. An auto-addressing RAM memory stores input data at an input address generated in response to an input clock, and outputs stored data from an output address generated in response to an output clock. | 04-14-2011 |
20110099439 | AUTOMATIC DIVERSE SOFTWARE GENERATION FOR USE IN HIGH INTEGRITY SYSTEMS - Systems, devices and methods of automatic diverse software generation are disclosed. In an embodiment, a method includes providing a base algorithm implementation related to a first hardware profile of a hardware resource, automatically generating a diverse algorithm implementation related to a second hardware profile different from the first hardware profile using the base algorithm implementation and information about the hardware resource, and executing the base algorithm implementation and the diverse algorithm implementation. Embodiments of systems and devices, including microprocessors and compilers, are also disclosed. | 04-28-2011 |
20110107162 | PARALLELIZATION METHOD, SYSTEM AND PROGRAM - A computer-implemented method, system, and article of manufacture for parallelizing a code configured by coupling a functional block having an internal state and a functional block without any internal state. The method includes: creating and storing a graphical representation where functional blocks are chosen as nodes and connections between functional blocks are chosen as links; visiting the nodes on the graphical representation sequentially, detecting inputs from functional blocks without any internal state to functional blocks having an internal state and storing these functional blocks as a set of use blocks, and detecting inputs from functional blocks having an internal state to functional blocks without any internal state and storing these functional blocks as a set of definition blocks; and forming strands of functional blocks based on information on the set of use blocks and information on the set of definition blocks stored in association with the functional blocks. | 05-05-2011 |
20110126063 | METHOD FOR INSERTING TEST POINTS FOR LOGIC CIRCUITS AND LOGIC CIRCUIT TESTING APPARATUS - This invention is intended to insert test points in a logic circuit under test in an effective manner. The logic circuit testing apparatus includes a fault estimation unit that estimates fault likelihoods for each of signal lines in a logic circuit in accordance with wiring conditions obtained from design data for the logic circuit. The logic circuit testing apparatus also includes an insertion unit that inserts test points, based on the fault likelihoods. The logic circuit testing apparatus executes testing the logic circuit in which the test points were inserted by the insertion unit. | 05-26-2011 |
20110138238 | INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS - A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals. | 06-09-2011 |
20110161755 | Methods of Parametric Testing in Digital Circuits - Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality. | 06-30-2011 |
20110185241 | Method and System for Packet Switch Based Logic Replication - A method and system for compiling a representation of a source circuit including one or more source subchannels associated with portions of source logic driven by a plurality of clock domains are described. Each source subchannel may generate packets carrying signal data from one of the portions of the source logic. A representation of a destination circuit may be compiled to include one or more destination subchannels associated with portions of destination logic replicating the source logic. Each destination subchannel may forward the signal data via the packets to one of the portions of the destination logic. A switching logic may be configured to map the source subchannels to the destination subchannels as virtual channels to forward the packets from the source subchannels to the destination subchannels. A single queue may be configured to couple with the switching logic to record packets from the source subchannels into a packet stream for a delay period to distribute to the destination subchannels. The destination logic may emulate the source logic synchronized with the plurality of clock domains delayed by the delay period. | 07-28-2011 |
20110239066 | REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY - Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains. | 09-29-2011 |
20110246843 | ERROR DETECTION IN PRECHARGED LOGIC - An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged. | 10-06-2011 |
20110271159 | TARGET DEVICE PROVIDING DEBUGGING FUNCTION AND TEST SYSTEM COMPRISING THE SAME - A test system for debugging a target device includes a switch unit configured to transfer a test signal to the target device, the target device including a first intellectual property (IP) block supporting a debugging operation at a normal mode and a second IP block supporting a debugging operation at a power saving mode. The switch unit is configured to form a first signal transfer path for transferring the test signal to the first IP block at the normal mode and to form a second signal transfer path for transferring the test signal to the second IP block at the power saving mode. | 11-03-2011 |
20110320893 | G-ODLAT On-die Logic Analyzer Trigger with Parallel Vector Finite State Machine - An apparatus for debugging internal signals of integrated circuits is presented. In one embodiment, the apparatus comprises a number of vector registers associated with states of a state machine. A group of registers, associated with a state of the state machine, comprises a mask register an arm register. A comparator compares debug data with contents of the mask register and the arm register to determine a comparison result to be stored in one or more bit positions of the vector register. The apparatus further comprises a triggering logic unit to determine whether or not to trigger a fire event based on the vector registers. | 12-29-2011 |
20110320894 | Surrogate Circuit For Testing An Interface - A semiconductor die includes interface logic for performing a function on an external device, and a surrogate circuit in communication with the interface logic. The interface logic facilitates testing of the interface logic by attempting to perform the function on the surrogate circuit. The interface logic may be a memory interface, and the surrogate circuit may be a memory circuit that is a smaller and simpler replica of an external memory die. The surrogate circuit allows the interface logic to be tested before the semiconductor die is physically coupled to the external device, for exampled in a three dimensional (3D) integrated circuit (IC). | 12-29-2011 |
20110320895 | Test circuit for testing execution of a handshake protocol and method for testing execution of handshake protocol - The present invention relates to a checker circuit for a handshake protocol. The checker circuit detects common errors that occur when two communication unit on execute the handshake protocol. The checker circuit is characterized by a compact circuit design that is associated with reduced susceptibility to circuit errors and a significantly reduced spatial requirement. The invention also relates to a method for checking the execution of the handshake protocol. | 12-29-2011 |
20120005545 | Computer product, verification support apparatus, and verification support method - A computer-readable, non-transitory medium stores a program that causes a computer to execute detecting in a circuit-under-test, a change in a signal output from each circuit element on a transmission-side, during one clock cycle on a reception-side at an asynchronous location; inputting to each circuit element on the reception-side, a signal for which a change is not detected at a detection time among detection times when a signal change is detected at the detecting and replacing with a random logic value, a signal for which a change has been detected at a detection time among the detection times and inputting the random logic value to each circuit element on the reception-side, in an action triggered by a rising edge of an operation clock on the reception-side after the one clock cycle; and outputting for each circuit element on the reception-side, an operation result obtained based on input at the inputting. | 01-05-2012 |
20120005546 | INTERCONNECTIONS FOR PLURAL AND HIERARCHICAL P1500 TEST WRAPPERS - A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals. | 01-05-2012 |
20120017128 | SYSTEM FOR TREE SEQUENCE TESTING OF A DEVICE AND METHOD FOR TREE SEQUENCE TESTING OF A DEVICE IN A TEST FRAMEWORK ARCHITECTURE - A system comprises a test framework architecture for tree sequence testing of a device, comprising a plurality of hierarchical layers at least comprising an upmost layer and a lowest layer, each layer of the plurality of hierarchical layers comprising at least one of a plurality of test sequences, each test sequence comprising a plurality of test steps, each test step comprising a current layer information; a test action information for carrying out a test action on the device; and a recovery information for carrying out a recovery action on reception of a recovery call from a next lower layer. | 01-19-2012 |
20120084612 | METHOD OF CONTROLLING A TEST MODE OF A CIRCUIT - A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other output vectors, undergo at least one latching. A signal transmitted by the additional output vector as a result of the final latching activates the lockout circuit. The test vector decode circuit also receives a supervoltage signal. Only by turning off the supervoltage signal can all of the output test vectors be reset, including the additional output vector. | 04-05-2012 |
20120117433 | System-On-A-Chip (SOC) Test Interface Security - Apparatus having corresponding methods and computer programs comprise: a processor; a test interface that is in communication with the processor only when the test interface is enabled; a first memory to store firmware for the processor; and a second memory to store boot code for the processor, wherein when the processor is booted, the boot code causes the processor to read a portion of the firmware from a predetermined location in the first memory; wherein the test interface is enabled only when the portion of the firmware has a predetermined value. | 05-10-2012 |
20120124433 | Feedback Scan Isolation and Scan Bypass Architecture - A feedback scan isolation and bypass architecture apparatus and method. The apparatus includes core logic, and input and output multiplexers. The input multiplexer selectively provides a functional input or the core output to the core input based on a test signal. The output multiplexer selectively provides the core output or the input multiplexer output to a functional output based on the test signal. When the test signal indicates core feedback testing, the output multiplexer outputs the core output and the input multiplexer feeds back the core output to the core input. When the test signal indicates bypass testing, the input multiplexer outputs the functional input and the output multiplexer outputs the functional input bypassing the core logic. Logic can block the feedback or bypass signals when there are timing issues. Logic can modify the number of feedback or bypass signals when the number of functional inputs and outputs are different. | 05-17-2012 |
20120131400 | SYSTEM AND METHOD FOR CORRECTING PROGRAMMING FAILURES IN A PROGRAMMABLE FUSE ARRAY - A system for correcting programming failures in an M-bit primary array of programmable fuses. The address of the failed fuse is stored in a secondary fuse array. Correction logic coupled to the primary and secondary arrays propagates the programming states of the good fuses, and corrects the programming state of the failed fuse, if any. The correction logic preferably comprises a decoder coupled to the secondary array which produces a one-hot M-bit word representing the failed fuse, and combinatorial logic arranged to receive the programming states of the primary array fuses and the one-hot M-bit word at respective inputs and to produce the correction logic output. Multiple failures can be accommodated using multiple secondary arrays, each storing the address of a respective failed fuse, or a tertiary array which stores the address of a failed fuse in either the primary or secondary arrays. | 05-24-2012 |
20120131401 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS - A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 05-24-2012 |
20120159272 | METHODS OF INCREASING FIDELITY OF QUANTUM OPERATIONS - Systems and methods are provided for improving fidelity of a quantum operation on a quantum bit of interest. A controlled quantum gate operation, controlled by the quantum bit of interest, id performed on an ancillary quantum bit. An energy state of the ancillary quantum bit is measured to facilitate the improvement of the fidelity of the quantum operation. | 06-21-2012 |
20120166898 | SINGLE LEVEL OF METAL TEST STRUCTURE FOR DIFFERENTIAL TIMING AND VARIABILITY MEASUREMENTS OF INTEGRATED CIRCUITS - A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (Ml) in the integrated circuit device. | 06-28-2012 |
20120272109 | VOTER TESTER FOR REDUNDANT SYSTEMS - A tester is configured to access and test each redundant channel of a voter. The tester is disposed between the voter and a multitude of redundant circuits supplying redundant channel signals to the voter. The tester includes a number of input ports receiving the redundant channel signals as well as the test signals. In response to a number of logic combinations of the test signals, the voter generates output signals each corresponding to one of the redundant channel signals. In response to other logic combinations of the test signals, the voter generates a voted output signal. The voter is optionally a majority voter. | 10-25-2012 |
20130111284 | ADAPTIVE, WIRELESS AUTOMATIC IDENTIFICATION SYSTEM PILOT PORT INTERFACE | 05-02-2013 |
20130124933 | ASICS HAVING PROGRAMMABLE BYPASS OF DESIGN FAULTS - A relatively small amount of programmable logic may be included in a mostly ASIC device such that the programmable logic can be used as a substitute for a fault-infected ASIC block. This substitution may occur permanently or temporarily. When an ASIC block is temporarily substituted, faulty outputs of the ASIC block are disabled just at the time they would otherwise propagate an error. The operations of the temporarily deactivated ASIC block(s) may be substituted for by appropriately programmed programmable logic. Thus, a fault-infected ASIC block that operates improperly 1% of the time can continue to be gainfully used for the 99% of the time when its operations are fault free. This substitution can be activated in various stages of the ASIC block's life including after: initial design; pilot production; and mass production. This provides for cost saving and faster time-to-market, repair, and maintenance even years after installation and use. | 05-16-2013 |
20130166974 | METHODS AND SYSTEMS FOR LOGIC DEVICE DEFECT TOLERANT REDUNDANCY - Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the logic devices is defective based upon its respective defect indicator. The scheduler intentionally omits sending workloads to the disabled logic units, and thus enables the device to be functional albeit at a lower performance or in a differently performing product. | 06-27-2013 |
20130179741 | MAPPING CIRCUIT TEST LOGIC BY ANALYZING REGISTER TRANSFER LEVEL CIRCUIT MODELS - Methods and systems for mapping and programming the debug logic of a circuit are provided. The system acquires a Register Transfer Level (RTL) representation of a circuit, wherein the circuit implements test logic that is externally programmable for providing one or more output signals corresponding to internal operational signals. The system analyzes the RTL representation to identify test multiplexers (MUXs) having registers for implementing the test logic, and correlates test register values for the test MUXs with outputs corresponding to the internal operational signals, based upon the RTL representation. The system further enables a user to select a desired internal operational signal for acquisition. Additionally, the system programs the test registers of the test MUXs of the circuit based on the correlated test register values to acquire the selected internal operational signal and to apply the acquired signal as one or more output signals. | 07-11-2013 |
20130318408 | Processor Device with Instruction Trace Capabilities - A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module and an external interface, wherein the trace module generates a trace stream including information about executed instructions, wherein the trace stream is output through the external interface, and wherein the trace module is further operable to detect a trigger signal and upon detection to insert a trace packet into the generated trace stream. | 11-28-2013 |
20130326297 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a control signal generation unit configured to generate a control signal in response to a set signal, a test signal and a test reset signal; a first test selection unit configured to generate a first test mode signal in response to a first select signal and the control signal; a second test selection unit configured to generate a second test mode signal in response to a second select signal and the control signal; and a test reset signal generation unit configured to output the second test mode signal as the test reset signal. | 12-05-2013 |
20130346814 | JTAG-BASED PROGRAMMING AND DEBUG - A method of sending programming and debug commands, comprises loading control instructions on a processor from an attached tangible, non-transitory computer-readable medium, copying the contents of a program image file by the processor from the computer-readable medium across a bus to a programmable device on the same card as the processor, signaling the programmable device to send an instruction to a configurable logic device (CLD) on the same card as the processor via a debug channel. | 12-26-2013 |
20140013171 | INTEGRATED DEFECT DETECTION AND LOCATION SYSTEMS AND METHODS IN SEMICONDUCTOR CHIP DEVICES - Embodiments relate to systems and methods for defect detection and localization in semiconductor chips. In an embodiment, a plurality of registers is arranged in a semiconductor chip. The particular number of registers can vary according to a desired level of localization, and the plurality of registers are geometrically distributed such that defect detection and localization over the entire chip area or a desired chip area, such as a central active region, is achieved in embodiments. In operation, a defect detection and localization routine can be run in parallel with other normal chip functions during a power-up or other phase. In embodiments, the registers can be multi-functional in that they can be used for other operational functions of the chip when not used for defect detection and localization, and vice-versa. Embodiments thereby provide fast, localized defect detection. | 01-09-2014 |
20140013172 | DEBUG ARCHITECTURE - Roughly described, a method of controlling transportation of debug data on an integrated circuit chip, the integrated circuit chip comprising a shared hub and a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, wherein between each respective debug unit and the shared hub there is an interface configured to transport data messages over each of a plurality of flows, the flows being assigned priorities, the method comprising: transporting control data for controlling the state of a debug unit on a priority flow having a first priority; and transporting debug data output by a debug unit as a result of debugging the peripheral circuit connected to that debug unit on a flow having a second priority, wherein the first priority is higher than the second priority. | 01-09-2014 |
20140019818 | SYSTEM FOR TESTING ERROR DETECTION CIRCUITS - A system for testing an error detection circuit includes a fault injection unit for operating the error detection circuit in a fault injection mode. A fault is inserted in either of a primary or a redundant processor. Output signals generated by the primary and redundant processors are compared and checked for a mismatch and the error detection circuit outputs a test signal based on the comparison result. | 01-16-2014 |
20140068361 | OFFLINE AT START UP OF A POWERED ON DEVICE - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence. | 03-06-2014 |
20140075253 | METHOD FOR VERIFICATION OF RECONFIGURABLE PROCESSOR - A method for verifying an operation of a reconfigurable processor is provided. The method includes generating an random test program using a test description and an architecture description, executing the generated random test program in a reconfigurable processor and in a simulator, and then comparing type of output values in the execution result. | 03-13-2014 |
20140089748 | HOT-PLUGGING DEBUGGER ARCHITECTURES - Systems and techniques for hot-plugging debugger capabilities are described. A described integrated circuit device includes a processor, a first pad interface, a detector configured to detect a clock signal via the first pad interface, one or more second pad interfaces, two or more components including a debug system that is communicatively coupled with the processor, a multiplexer communicatively coupled with the one or more second pad interfaces and the two or more components, and configured to selectively interconnect the one or more second pad interfaces with a selected component of the two or more components. The multiplexer can be configured to cause the debug system to be the selected component when the clock signal is detected via the first pad interface. | 03-27-2014 |
20140136911 | REMOTE MONITORING SYSTEMS AND RELATED METHODS AND RECORDING MEDIUMS USING THE SAME - Remote monitoring systems for remotely monitoring execution status of a PLC (Programmable Logic controller) program of a machine include a storage module, a parameter retrieval module and a monitoring module. The storage module stores ladder diagram information corresponding to a PLC source program, wherein the ladder diagram information includes PLC signal address relation information, a plurality of logic switches and a responsive collect command of each logic switch of a ladder diagram. The PLC signal address relation information indicates the relations of the logic switches on the ladder diagram. The parameter retrieval module respectively retrieves parameter data corresponding to the logic switches using the responsive collect commands. The monitoring module generates a status of ladder diagram according to the logic switches, the parameter data and the PLC signal address relation information to display the parameter data corresponding to each logic switch when the machine is executing the PLC source program. | 05-15-2014 |
20140143620 | SEMICONDUCTOR APPARATUS AND TEST METHOD THEREOF - A semiconductor apparatus includes a data output unit and a test output unit. The data output unit outputs a plurality of data, through a plurality of data lines, to a plurality of input/output pads. The test output unit receives one of the plurality of data and a plurality of output data, which is output to the plurality of input/output pads, and outputs the received data to a probe pad in a probe test mode. | 05-22-2014 |
20140149811 | AT-SPEED INTEGRATED CIRCUIT TESTING USING THROUGH SILICON IN-CIRCUIT LOGIC ANALYSIS - A method, system, and computer program product for integrated circuit wafer and die testing. The method commences by selecting areas of interest accessible from a backside of an integrated circuit where the areas of interest correspond to electronic devices (e.g., gates or transistors or vias or pads). Then, using a small-beam light source such as a laser, illuminating the areas of interest and collecting the reflected signal returned from illuminated areas of interest. A processor analyses the reflected signal to determine logic states and timing information of the electronic devices and compares the determined logic states and timing information to a pre-determined logic pattern to identify one or more errors as observed from the actual electronic devices. Specific points within an area of interest are determined from CAD layout data, and the pre-determined logic patterns can be retrieved from CAD simulation data. | 05-29-2014 |
20140157069 | SEMICONDUCTOR INSPECTION APPARATUS AND SEMICONDUCTOR INSPECTION METHOD - A semiconductor inspection apparatus has a test-program execution part, a signal-condition detection part, a test-time calculation part to calculate an optimum test time having a duration from a period of the unstable region to a certain period at a leading portion of the stable region subsequent to the unstable region based on the unstable and stable regions detected by the signal-condition detection part, a test-program modification part to reflect the optimum test time in the test program, and a signal waveform importing part to import a signal at the signal output pin of the device to be tested based on a test time written in the test program in which the optimum test time is reflected. The test-program execution part executes the test program again after the optimum test time is reflected in the test program by the test-program modification part. | 06-05-2014 |
20140173370 | DEBUG SYSTEM, APPARATUS AND METHOD THEREOF FOR PROVIDING GRAPHICAL PIN INTERFACE - A debug apparatus for debugging a chip under test with a plurality of pins is provided. The debug apparatus includes a processor for controlling the chip under test via a bridge device. The processor provides graphical data to indicate pin states of the chip under test when the chip under test is controlled by the processor. | 06-19-2014 |
20140195868 | OPERATION MANAGEMENT DEVICE, OPERATION MANAGEMENT METHOD - An operation management to grasp a metric in which a continuous abnormality has occurred in a system, easily, is provided. An operation management apparatus | 07-10-2014 |
20140250341 | CIRCUITS, APPARATUSES, AND METHODS FOR ADDRESS SCRAMBLING - Circuits, apparatuses, and methods are disclosed for address scrambling in integrated circuits. One example apparatus includes a plurality of data regions, each of the plurality of data regions configured to provide a respective portion of data responsive to a physical address provided by a respective decode circuit. The plurality of data regions are configured to provide their respective portions of data responsive to a common logical address. The common logical address is scrambled such that a plurality of different physical addresses are provided to the plurality of data regions. | 09-04-2014 |
20140298122 | DUAL MASTER JTAG METHOD, CIRCUIT, AND SYSTEM - A dual-master controller includes a plurality of JTAG data registers including a controller-mode register that stores information indicating a standard JTAG or a processor-controlled mode of operation. A JTAG TAP controller receives control signals over a standard test access port and a processor controller receives processor control signals over an external processor bus. A selection multiplexer outputs either signals on the standard JTAG access port or the external processor bus responsive to a JTAG mode selection signal. A logic circuit activates the JTAG mode selection signal responsive to the force JTAG signal being active or information in the controller-mode register indicating the standard JTAG mode, and deactivates the JTAG mode selection signal responsive to the force JTAG signal being deactivated or the information in the controller-mode register indicating the processor-controller mode. An instruction decoder and multiplexer circuit applies control signals from the selection multiplexer to control the JTAG data registers. | 10-02-2014 |
20140337677 | Merging Result from a Parser in a Network Processor with Result from an External Coprocessor - A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue. | 11-13-2014 |
20140351664 | TESTING AN INTEGRATED CIRCUIT - Testing an integrated circuit in a test environment that includes a virtual test engine and a test system with an integrated circuit tester. The integrated circuit is connected to the virtual test engine via the integrated circuit tester, and the integrated circuit tester is connected to the integrated circuit via an interface. The virtual test engine communicates with the integrated circuit tester via a command interface to perform functional test during functional test mode and to perform non-functional test during non-functional test mode | 11-27-2014 |
20140359384 | COMMUNICATION DEVICE, TEST SYSTEM AND TEST METHOD THEREOF - A communication device is provided, which includes: a baseband chip; a target test chip integrated into the baseband chip; an upper-layer processing unit corresponding to the target test chip; and at least one data transport interface and at least one data processing unit corresponding to the at least one data transport interface. The communication device further includes: a first switch, adapted to connect the target test chip with the at least one data transport interface or the upper-layer processing unit; a second switch, adapted to connect the at least one data transport interface with its corresponding data processing unit or the target test chip; and a test control unit, configured to control the first switch and the second switch to connect the data transport interface with the target test chip, so as to enable the communication device to test the target test chip. | 12-04-2014 |
20140372817 | AUTOMATED CIRCUIT TRIPLICATION METHOD AND SYSTEM - In one general aspect, a non-transitory computer-readable storage medium can be configured to store instructions that when executed cause a processor to perform a process. The process can include defining a plurality of subsets from a representation of a circuit, and rank-ordering each subset from the plurality of subsets. The process can also include selecting at least one of the subsets for triplication based on the rank-ordering and a triplication condition. | 12-18-2014 |
20150019927 | TEST SYSTEM AND DEVICE - An aspect of the present invention is to provide a test system for detecting whether a continuity fault condition, e.g., a short or open condition, exists in the path between a tester and chips on a wafer during a wafer level burn-in testing. According to one embodiment of the present invention, the test system comprises a probe card and n chips. The probe card comprises m first signal contacts for receiving m test signals from the tester, n second signal contacts for providing n test results to the tester, and a contact array. The probe card is in contact with the chips on the wafer through a plurality of needles. In this manner, the test system can detect whether the continuity fault condition exists in the path between the tester and the chips on the wafer during the wafer level burn-in testing. | 01-15-2015 |
20150067422 | FUSION OF MULTIPLE MODALITIES FOR DETERMINING A UNIQUE MICROELECTRONIC DEVICE SIGNATURE - An example of the invention includes a process and apparatus combining test modalities that collates data, processes it into a standard format, evaluates trends and interrogates via an expert system can increase efficiency and yield greater confidence in testing of parts in a variety of supply chain segments. An exemplary process and test system can collect a variety of test data as pre-processed raw data from a plurality of modalities as an evaluation database. The evaluation database post-processes said raw data via data analysis output to an expert system and decision engine as exemplary rule sets. The decision engine generating a probability that a microelectronic device is unauthorized, does not meet specification(s), is defective or counterfeit. | 03-05-2015 |
20150082107 | STATE MACHINE BASED FUNCTIONAL STRESS TESTS - According to one general aspect, a method of testing an integrated circuit may include executing, on a system control processor of the integrated circuit, a Silicon Test Environment (STE). The STE may be configured to facilitate an interaction of a functional test program with a processor without aid of an operating system. The method may include executing, on a processor of the integrated circuit, one or more instances of the STE. The method may include establishing a plurality of functional test programs by instructing each of the one or more instances of the STE to each perform a respective functional test program targeting a respective hardware component of the integrated circuit. The method may include collecting data produced by the execution of the functional test programs. | 03-19-2015 |
20150100839 | GENERALIZED MODULAR REDUNDANCY FAULT TOLERANCE METHOD FOR COMBINATIONAL CIRCUITS - The generalized modular redundancy fault tolerance method for combinational circuits utilizes redundancy techniques to improve soft error reliability and is based on probability of occurrence for combinations at the outputs of circuits. The generalized modular redundancy method enhances the reliability of combinational circuits. Types of redundant modules, complexity of voters and single versus multiple outputs protection are explored. | 04-09-2015 |
20150149842 | TEST DEVICE AND METHOD USING A SEPARATE CONTROL MODULE FOR TEST - A test device and method using a separate control module for test are disclosed, where a main console is replaced with a control module of the test device, the control module may generate a control command after receiving the a command transmitted from the main console, and transmit the control command to at least one PLD corresponding thereto, the PLD may control the GIPO comprised thereby to test the unit under test according to the received control command, whereby reducing the test time and achieving in the effect where the main console may do the other work concurrently when engaging in the test for the unit under test. | 05-28-2015 |
20150301108 | SCHEDULING OF SCENARIO MODELS FOR EXECUTION WITHIN DIFFERENT COMPUTER THREADS AND SCHEDULING OF MEMORY REGIONS FOR USE WITH THE SCENARIO MODELS - A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output. | 10-22-2015 |
20150316609 | DEBUGGING SYSTEM AND METHOD - A debugging system for debugging an automated test process used on an automated test platform. The debugging system includes a debugging coupler configured to be releasably electrically coupleable to a test head of the automated test platform. A debugging subsystem is electrically coupled to the debugging coupler and includes a signal generator configured to apply one or more signals to one or more conductive paths within the debugging coupler. | 11-05-2015 |
20150316610 | DEBUGGING SYSTEM AND METHOD - A method, computer program product, and computing system for electrically coupling a monitoring subsystem to a first group of conductive paths within a debugging coupler that is configured to be releasably electrically coupleable to a test head of an automated test platform. One or more signals present on the first group of conductive paths are monitored while executing at least a portion of an automated test process on the automated test platform. The monitoring subsystem is electrically coupled to a second group of conductive paths within the debugging coupler. One or more signals present on the second group of conductive paths are monitored while executing the at least a portion of the automated test process on the automated test platform. | 11-05-2015 |
20150316611 | DEBUGGING SYSTEM AND METHOD - A method, computer program product, and computing system for defining a first group of transient values for a first group of conductive paths within a debugging coupler that is configured to be releasably electrically coupleable to a test head of an automated test platform. A monitoring subsystem is electrically coupled to the first group of conductive paths. A first group of signals present on the first group of conductive paths is monitored while executing at least a portion of an automated test process on the automated test platform to determine if any of the first group of signals exceeds any of the first group of transient values. | 11-05-2015 |
20150355275 | LOGIC ANALYZER - A logic analyzer | 12-10-2015 |
20150377961 | SYSTEM AND METHOD FOR TESTING A LOGIC-BASED PROCESSING DEVICE - A method of operating a test device for a logic-based processing device includes the steps of providing an original set of test instructions, generating one or more Quick Error Detection (QED) test programs, and causing the one or more QED test programs to be executed on the logic-based processing device. Each one of the QED test programs includes the original test program with additional instructions inserted at strategic locations within the original set, wherein the additional instructions and the strategic locations vary between each of the QED test programs. | 12-31-2015 |
20150377965 | DEBUG ARCHITECTURE - Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit. | 12-31-2015 |
20220137130 | SELF DIAGNOSTIC APPARATUS FOR ELECTRONIC DEVICE - The present invention relates to a self diagnostic apparatus for an electronic device, which includes a vector memory configured to store a test function code for testing a device under test (DUT) equipped with a plurality of cores which perform arithmetic operations, a function test expected value corresponding to a function test according to the test function code, a design for test (DFT) test code, a DFT test expected value corresponding to a DFT test according to the DFT test code, and a non-test function code for a general arithmetic operation or an operation of the DUT; a test data storage configured to store test data including a DFT test code result value which is a result of the DFT test according to the DFT test code, a test function code result value which is a result of the function test according to the test function code, and a non-test function code result value which is a result of the function test according to the non-test function code; and a safety region test controller configured to select one among the test function code, the DFT test code, and the non-test function code to select a test mode, control an environmental variable of a test signal applied to the DUT in response to the selected test mode and test the DUT, compare the function test expected value stored in the vector memory with the test function code result value stored in the test data storage, and compare the DFT test expected value stored in the vector memory with the DFT test code result value stored in the test data storage to output comparison result information. | 05-05-2022 |