Entries |
Document | Title | Date |
20080209282 | Method of managing a flash memory and the flash memory - One embodiment of the method includes determining a type of cells in a block of the flash memory if an error is detected in at least a portion of the block, and selectively changing one of a cell type indicator and a bad block indicator associated with the block based on the determined type of cells in the block. The cell type indicator indicates a type of the cells in the associated block, and the bad block indicator indicates whether the associated block is a usable block. | 08-28-2008 |
20080215930 | FLASH MEMORY WITH MULTI-BIT READ - A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory cell that uses more than 2 | 09-04-2008 |
20080244335 | Protecting memory operations involving zero byte allocations - Applications are protected from being exposed to exploits and instabilities due to memory operations involving zero byte allocations. Memory operations involving a zero byte allocation are handled by a zero byte memory manager. When an application requests a zero byte allocation, a pointer to a protected part of memory is returned such that when the application attempts to read and/or write to the location the program flow is interrupted. | 10-02-2008 |
20090019321 | ERROR CORRECTION FOR MEMORY - Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing level of error correction is provided within one page of a row of multi-level cells relative to other pages stored within the same row of multi-level cells. | 01-15-2009 |
20090037783 | PROTECTING DATA STORAGE STRUCTURES FROM INTERMITTENT ERRORS - Embodiments of apparatuses and methods for protecting data storage structures from intermittent errors are disclosed. In one embodiment, an apparatus includes a plurality of data storage locations, execution logic, error detection logic, and control logic. The execution logic is to execute an instruction to generate a data value to store in one of the data storage locations. The error detection logic is to detect an error in the data value stored in the data storage location. The control logic is to respond to the detection of the error by causing the execution logic to re-execute the instruction to regenerate the data value to store in the data storage location, causing the error detection logic to check the data value read from the data storage location, and deactivating the data storage location if another error is detected. | 02-05-2009 |
20090077429 | Memory system and wear-leveling method thereof - Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly. | 03-19-2009 |
20090089628 | FILE SYSTEM ERROR DETECTION AND RECOVERY FRAMEWORK - Methods, systems and machine readable media for file system error detection and protection are described. In one aspect, an embodiment of a method includes collecting first data identifying at least one error in performing at least one of reading or writing data to a storage device and determining, through an association between the first data and file identifiers, a set of files which are effected by the at least one error. The collecting may be performed automatically as a background process. In another aspect, an embodiment of a method includes detecting at least one error in file system metadata for a storage device, the detecting being performed automatically as a background process, and storing state information automatically in response to the detecting; the state information indicates that upon next mounting of the storage device, the data processing system will automatically cause the running of a file system check of the file system metadata. | 04-02-2009 |
20090125759 | STORAGE DEVICE WITH SELF-CONDITION INSPECTION AND INSPECTION METHOD THEREOF - A storage device with self-status detection and an inspection method thereof are provided. The storage device includes a plurality of storage areas (i.e., block tables), a plurality of memory blocks, and a status detection unit. The storage areas respectively have a corresponding weight value, and the addresses of memory blocks which have the same number of error correct codes (ECCs) are recorded in the same storage area. The status detection unit obtains a status of the storage device according to the number of addresses of the memory blocks recorded in a storage area and the corresponding weight value of the storage area. | 05-14-2009 |
20090132868 | MESSAGE STATE MAINTENANCE AT A MESSAGE LOG - The present invention extends to methods, systems, and computer program products for maintaining message state at a message log. Messages are accumulated at a message log in accordance with a message retention policy. Any of a variety of message capture assurances can be used when capturing a message from a message producer within a message log. A message becomes visible to message consumers after the outcome of writing the message is known (either failure or success). Messages are requested using (e.g., monotonically increasing) sequence numbers. Messages are also dropped from the message log in accordance with the message retention policy. | 05-21-2009 |
20090172478 | Information Processing Apparatus, Backup Device and Information Processing Method - According to an aspect of the present invention, there is provided an information processing apparatus including: a connector to which a backup device is connected; a data storing unit that stores an objective data; and a processor that is configured: to write the objective data to the backup device as a backup data; to record a change log that specifies an updated part of the objective data; to detect a difference part between the objective data and the backup data when the backup device is connected to the connector; to determine whether the difference part matches the updated part specified by the change log; and if the difference part does not match the updated part, to identify a mismatching part between the difference part and the updated part as an abnormal data. | 07-02-2009 |
20090199048 | SYSTEM AND METHOD FOR DETECTION AND PREVENTION OF FLASH CORRUPTION - A non-volatile memory device comprises an application code sector of sufficient size to store a first copy of an application code and a second copy of the application code; and a boot sector having a boot loader code embodied therein. The boot loader code is configured to cause a processor to check the integrity of both the first and second copies of the application code; if the first copy is corrupted, overwrite the first copy of the application code with the second copy; and if the second copy is corrupted, overwrite the second copy of the application code with the first copy. | 08-06-2009 |
20090287967 | Resilient Data Storage in the Presence of Replication Faults and Rolling Disasters - A method for data protection includes, in a first operational mode, sending data items for storage in a primary storage device and in a secondary storage device, while temporarily caching the data items in a disaster-proof storage unit and subsequently deleting the data items from the disaster-proof storage unit, wherein each data item is deleted from the disaster-proof storage unit upon successful storage of the data item in the secondary storage device. | 11-19-2009 |
20090307537 | Flash storage device with data correction function - A flash controller performs a data correction function while executing a copy back procedure for a flash memory, and the flash memory includes at least one memory unit and a page buffer. The flash controller contains: a transmission buffer, an error correction unit, a correction information register, and a microprocessor. The microprocessor reads out a data from, the page buffer and stores the data into the transmission buffer after producing a read instruction of page copy to the flash memory. The microprocessor controls the error correction unit to check and correct the data in the transmission buffer and calculate a check result. The microprocessor produces a different program command to record the corrected data into the memory unit according to the data error quantity of the check result. Thereby, the present invention can achieve the purpose of improving the flash controller in reliability and access efficiency. | 12-10-2009 |
20090307538 | Managing Paging I/O Errors During Hypervisor Page Fault Processing - In response to a hypervisor page fault for memory that is not resident in a shared memory pool, an I/O paging request is sent to an external storage paging space. In response to a paging service partition encountering an I/O paging error, a paging failure indication is sent to the hypervisor. A simulated machine check interrupt instruction is sent from the hypervisor to the shared memory partition and a machine check handler obtains control. The machine check handler performs data analysis utilizing an error log in an attempt to isolate the I/O paging error to a process or a set of processes in the shared memory partition. The process or set of processes associated with the I/O paging error, or the shared memory partition itself, may be terminated. Finally, the shared memory partition may clear or initialize the page associated with the I/O paging error. | 12-10-2009 |
20100088556 | FAULT MANAGEMENT SYSTEM IN MULTISTAGE COPY CONFIGURATION - A data storing system including: a first, second and third storage systems providing first, second and third logical volumes; wherein the first logical volume and the second logical volume forms a first replication pair which indicates the first logical volume is a replication source and the second logical volume is a replication destination, and the second logical volume and the third logical volume forms a second copy pair which indicates the second logical volume is the replication source and the third logical volume is the replication destination. The replication pairs may adopt differing possible pair statuses, which may affect consistency between such pairs. | 04-08-2010 |
20100125763 | VOLUME AND FAILURE MANAGEMENT METHOD ON A NETWORK HAVING A STORAGE DEVICE - Provided is an environment that storage device configuration management can be efficiently done in a data center having a virtualization device. A SAN manager acquires configuration information from a device constituting a SAN and prepares a correspondence relationship between a host computer and a virtual volume in the SAN, and a corresponding relationship between the host computer and a real volume, depending upon the acquired information. Based on the corresponding relationship, the SAN manager outputs a correspondence relationship of between virtual and real volumes. Meanwhile, by interpreting a failure-notification message received from the devices of the SAN, detected and outputted is an influence upon an access to a real or virtual volume as to the failure. Furthermore, when a plurality of failure notifications are received from the devices connected to the SAN, a plurality of failure notifications are associatively outputted depending upon a correspondence relationship between real and virtual volumes. | 05-20-2010 |
20100131805 | STORAGE CONTROLLER AND METHOD FOR CONTROLLING THE SAME - A storage controller of the present invention detects error with relative ease when reading out data from a storage apparatus. An address data appending device appends address data to each of logical blocks with respect to the data received from a host. A device communication control device determines a divisional position in every data with a size of a predetermined number of blocks, counterchanges the data in anterior and posterior parts around the divisional position, and stores the data in the storage apparatus. When reading the data from the storage apparatus, an address data checking device determines whether or not the value of the address data appended to the block read out and an expected value of the address data calculated based on the divisional position match with each other. If the both values match with each other, the data is sent to the cache memory. If the both values fail to match each other, an error is detected. | 05-27-2010 |
20100131806 | APPARATUS FOR CODING AT A PLURALITY OF RATES IN MULTI-LEVEL FLASH MEMORY SYSTEMS, AND METHODS USEFUL IN CONJUNCTION THEREWITH - A method and system for writing in flash memory, the system operative for, and the method comprising, writing data onto a plurality of logical pages characterized by a plurality of different probabilities of error respectively, the writing including encoding data intended for each of the plurality of physical pages using a redundancy code with a different code rate for each individual physical page, the code rate corresponding to the probability of error in the individual logical page. | 05-27-2010 |
20100138702 | INFORMATION PROCESSING APPARATUS AND SIGN OF FAILURE DETERMINATION METHOD - According to one embodiment, an information processing apparatus includes a disk drive, a monitoring processing module, and a log accumulation module. The monitoring processing module configured to monitor a command which is issued to the disk drive by a disk driver program in response to a disk access request from an operating system, and a response to the command from the disk drive, and to output command identification information indicating a type of the command and response identification information indicating success or failure of processing corresponding to the command executed by the disk drive. The log accumulation module configured to accumulate the command identification information and response identification information output from the monitoring processing module as log information of the disk drive. | 06-03-2010 |
20100146348 | EFFICIENT METHOD AND APPARATUS FOR KEEPING TRACK OF IN FLIGHT DATA IN A DUAL NODE STORAGE CONTROLLER - A storage unit adapted for use in a processing system includes a controller including at least two compute nodes, each of the compute nodes including a read/write cache and a persistent cache; and machine executable instructions stored within machine readable media, the instructions including instructions for tracking in-flight data in the persistent cache and composing a list of the in-flight data segments after a failure of the controller. A processing system and a method are also provided. | 06-10-2010 |
20100174951 | SEMICONDUCTOR MEMORY DEVICE, HOST DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A host device | 07-08-2010 |
20100185904 | System and Method for Fast Cache-Hit Detection - A system and method for fast detection of cache memory hits in memory systems with error correction/detection capability is provided. A circuit for determining an in-cache status of a memory address comprises an error detect unit coupled to a cache memory, a comparison unit coupled to the cache memory, a results unit coupled to the comparison unit, and a selection unit coupled to the results unit and to the error detect unit. The error detect unit computes an indicator of errors present in data stored in the cache memory, wherein the data is related to the memory address. The comparison unit compares the data with a portion of the memory address, the results unit computes a set of possible in-cache statuses based on the comparison, and the selection unit selects the in-cache status from the set of possible in-cache statuses based on the indicator. | 07-22-2010 |
20100199131 | STORAGE SYSTEM AND A CONTROL METHOD FOR A STORAGE SYSTEM - A storage system includes a storage device for storing data, a pair of adapters connected with the storage device, each of the adapters transmitting and receiving the data to and from the storage device respectively. The storage system includes a controller, connected with the adapters, for collecting performance information indicating performance of each of the adapters, comparing the collected performance information of the adapters with each other, and detecting a suspected adapter that is suspected of having a performance failure on the basis of a result of the comparison. | 08-05-2010 |
20100293418 | MEMORY DEVICE, DATA TRANSFER CONTROL DEVICE, DATA TRANSFER METHOD, AND COMPUTER PROGRAM PRODUCT - According to one embodiment, a memory device includes: a driving module configured to store therein data on a sector-by-sector basis; a first verifying module configured to verify, during a reading operation, sector data from the driving module; a partitioning module configured to partition the sector data into sets of subsector data, a size of each set of subsector data being smaller than a size of the sector data; an appending module configured to append an error detecting code to each set of subsector data; a second verifying module configured to store, in a predetermined memory, the sets of subsector data retrieved from a buffer, and to verify the sets of subsector data using respective error detecting codes; and a sending module configured to send, from the memory, the verified sets of subsector data to the host with a transfer size. | 11-18-2010 |
20100299565 | CONTROLLING APPARATUS AND CONTROLLING METHOD - A controlling apparatus for controlling a disk array unit includes a cache memory for caching data of the disk array unit; a nonvolatile memory for storing the data in the cache memory; and a control unit for detecting a defective location in the nonvolatile memory where the data is stored defectively and updating information indicating the defection location, for generating an error detection code of the updated information, for writing the generated information and the associated error detection code into an area of the nonvolatile memory different from any area where any information indicating any defective location previously detected and stored into the nonvolatile memory, and for controlling writing the data in the cache memory into a location of the nonvolatile memory designated by any selected one of the information stored in the nonvolatile memory. | 11-25-2010 |
20110066899 | NONVOLATILE MEMORY SYSTEM AND RELATED METHOD OF PERFORMING ERASE REFRESH OPERATION - A memory system comprises a flash memory and a memory controller. The flash memory comprises a plurality of memory blocks. The memory controller performs a read retry operation on a memory block containing an uncorrectable read error until an accurate data value is read from the memory block. The memory controller then controls the flash memory to perform an erase refresh operation on the memory block. | 03-17-2011 |
20110072320 | CACHE SYSTEM AND CONTROL METHOD THEREOF, AND MULTIPROCESSOR SYSTEM - According to the embodiments, a cache system includes a cache-data storing unit and a failure detecting unit. The failure detecting unit detects failure in units of cache line by determining whether instruction data prefetched from a lower layer memory matches cache data read out from the cache-data storing unit. A cache line in which failure is detected is invalidated. | 03-24-2011 |
20110087930 | SELF-CLEANING MECHANISM FOR ERROR RECOVERY - A system manages a buffer having a group of entries. The system receives information relating to a read request for a memory. The system determines whether an entry in the buffer contains valid information. If the entry is determined to contain valid information, the system transmits the information in the entry in an error message. The system may then store the received information in the entry. In another implementation, the system stores data in one of the entries of the buffer, removes an address corresponding to the one entry from an address list, and starts a timer associated with the one entry. The system also determines whether the timer has exceeded a predetermined value, transferring the data from the one entry when the timer has exceeded the predetermined value, and adds the address back to the address list. | 04-14-2011 |
20110099435 | NAND FLASH MEMORY AND METHOD FOR MANAGING DATA THEREOF - A NAND flash memory and method for managing data reads a header from each storage area, and identifies each storage area. Data of the primary storage area is updated if the primary storage area exists, and an operating system in the NAND flash memory is initiated according to the updated data in the primary storage area, or in the secondary storage area if the primary storage area does not exist but a secondary storage area does. | 04-28-2011 |
20110107158 | RADIATION-HARDENED PROCESSING SYSTEM - A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data. | 05-05-2011 |
20110119535 | PROCESSOR AND METHOD OF CONTROL OF PROCESSOR - A processor including: a first storage unit that stores data; an error detection unit that detects an occurrence of error in data read out from the first storage unit; a second storage unit that stores data read out from the first storage unit based on a load request; a rerun request generation unit that generates a rerun request of a load request to the first storage unit in the same cycle as the cycle in which error of data is detected when the error detection unit detects the occurrence of error in data read out from the first storage unit by the load request; and an instruction execution unit that retransmits the load request to the first storage unit when data in which error is detected and a rerun request are given. | 05-19-2011 |
20110154133 | TECHNIQUES FOR ENHANCING FIRMWARE-ASSISTED SYSTEM DUMP IN A VIRTUALIZED COMPUTER SYSTEM EMPLOYING ACTIVE MEMORY SHARING - A technique for performing a system dump in a data processing system that implements active memory sharing includes assigning, via a hypervisor, a logical partition to a portion of a shared memory. One or more virtual block storage devices are also assigned by the hypervisor to the logical partition to facilitate active memory sharing of the shared memory. When a hypervisor-aided firmware-assisted system dump is indicated and a failure of the logical partition is detected, firmware initiates a system dump of information from the assigned portion of the shared memory to the one or more virtual block storage devices. An operating system of the logical partition is rebooted when enough of the assigned portion of the shared memory is freed to facilitate a reboot of the operating system and the hypervisor-aided firmware-assisted system dump is indicated. | 06-23-2011 |
20110154134 | INFORMATION STORAGE DEVICE - During initial access in which a control unit | 06-23-2011 |
20110179317 | VOLUME AND FAILURE MANAGEMENT METHOD ON A NETWORK HAVING A STORAGE DEVICE - A SAN manager acquires configuration information from devices constituting a SAN and produces a corresponding relationship between a host computer and a virtual volume (virtual volume mapping) and a corresponding relationship between the host computer and a real volume (real volume mapping). Based on those pieces of mapping information, the SAN manager outputs a corresponding relationship between virtual and real volumes. Meanwhile, the failure notification messages received from the in-SAN devices are construed to detect and output an influence of the failure upon the access to a real or virtual volume. Furthermore, when receiving a plurality of failure notifications from the devices connected to the SAN, the plurality of failure notifications are outputted with an association based on the corresponding relationship between real and virtual volumes. | 07-21-2011 |
20110191639 | STORAGE SYSTEM AND CONTROL METHOD - Provided are a storage system and its control method having superb functionality of being able to notify an administrator of the extent of impact of a pool fault in an easy and prompt manner. The foregoing storage system and its control method manage a storage area provided by a storage medium by dividing it into multiple pools, provide a virtual logical device to a host system, dynamically allocate a storage area to the logical device according to a data write request from the host system for writing data into the logical device, move data that was written into the logical device to another pool according to the access status from host system to such data, identify, when a fault occurs in any one of the pools, an extent of impact of the fault based on the correspondence relationship of the logical device and the pool, and notify the identified extent of impact of the fault to an administrator. | 08-04-2011 |
20110191640 | SEMICONDUCTOR MEMORY DEVICE - A memory device and a method of controlling the memory device are provided, comprising: generating commands at a memory controller; counting a number of commands in response to a clock signal; storing the commands and the count numbers corresponding to the commands; transmitting to a memory device the commands, the count number of the commands, and data; receiving at the memory device the commands, the count number of the commands, and data sent from the memory controller; counting at the memory device the number of commands received in response to the clock signal; storing at the memory device the count number of commands received; and transmitting the count number of the commands received to the memory controller, wherein said transmitting the count number of the command to the memory controller is performed upon indication of an error condition. | 08-04-2011 |
20110191641 | RAID DEVICE, ABNORMAL DEVICE DETECTING APPARATUS, AND ABNORMAL DEVICE DETECTING METHOD - A RAID device has a plurality of HDDs for a RAID configuration and controls the RAID configuration. The RAID device has a host that performs various data processes on the HDDs and a control unit that controls communication with the HDDs. With this configuration, if an initialization process for assigning physical addresses unique to the HDDs is performed, the RAID device receives initialization frames from the HDDs. Then, the RAID device detects abnormality of the HDDs in accordance with information contained in the received initialization frames. | 08-04-2011 |
20110197100 | NON-VOLATILE REDUNDANT VERIFIABLE INDICATION OF DATA STORAGE STATUS - A non-volatile redundant verifiable indication of data storage status is provided with respect to data storage operations conducted with respect to removable data storage media, and store the indication with an auxiliary non-volatile memory of the data storage media, such that the indication stays with the media. At least one state value indicating the status of the data storage operation is written to one page of the auxiliary non-volatile memory, and a redundancy check is provided with respect to at least the written state value of the one page of the auxiliary non-volatile memory; and the same state value is written to a second page of the auxiliary non-volatile memory, and a redundancy check is provided with respect to at least the written state value of the second page of the auxiliary non-volatile memory. The redundancy checks indicate the validity of the state values. | 08-11-2011 |
20110219272 | Data Transmission System and Method Thereof - A data transmission system is provided. The data transmission system includes a first control circuit coupled to a first device, a translation circuit coupled to the first control circuit and a second control circuit coupled to the translation circuit. The first control circuit decodes a first format data packet sent by the first device. The translation circuit receives the decoded first format data packet and translates the decoded first format data packet into a second format data packet. The second control circuit transmits the second format data packet to a host. A data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device. | 09-08-2011 |
20110225465 | Managing Memory Refreshes - Systems and methods to manage memory refreshes at a memory controller are disclosed. A method includes determining, at a memory controller device, that a number of transmission errors between a memory controller port and a memory redrive device exceeds an error threshold. The method may include initiating a first link retraining process between the memory controller port and the memory redrive device. The method may further include placing one or more dynamic random access memory modules associated with the memory redrive device in a self-refresh mode. The method may also include removing the one or more dynamic random access memory modules from the self-refresh mode after the link retraining process has completed. The method may further include enabling overlapping refreshes of the one or more dynamic random access memory modules. | 09-15-2011 |
20110225466 | DISPERSED STORAGE UNIT SELECTION - A dispersed storage device for use within a dispersed storage network operates to select a set of dispersed storage units for storage of a data object by slicing an encoded data segment of a data object into error coded data slices, determining slice metadata for the error coded data slices, determining memory characteristics of dispersed storage units capable of storing the error coded data slices and selecting the set of dispersed storage units for storing the error coded data slices based on the slice metadata and the memory characteristics. | 09-15-2011 |
20110231713 | FLASH MEMORY MODULE - Logical/physical conversion information is configured from first conversion information and second conversion information. A controller of a flash memory module restores the first conversion information at boot up time, enables an access command to be received from a host after having restored the first conversion information, and restores the second conversion information after an access command is able to be received. | 09-22-2011 |
20110231714 | CONTENTS DATA RECORDING APPARATUS AND CONTENTS DATA RECORDING METHOD - According to one embodiment, a contents data recording apparatus includes a storage module and a data delete module. The storage module stores encoded first-system and second-system contents data. The data delete module deletes either the first-system contents data or second-system contents data from the storage module based on a predetermined condition after the first-system and second-system contents data has been stored in the storage module. | 09-22-2011 |
20110252282 | PRAGMATIC MAPPING SPECIFICATION, COMPILATION AND VALIDATION - Facilitating translation of data between object oriented programs and database storage tables. A method includes receiving user input from a user. The user input includes a plurality of parts. Each part includes a specification of a source (such as a type source), optionally a filter, and a projection. Each projection assigns values to table columns. Based on the plurality of parts received, the method includes generating one or more views. The one or more views describe relationships between model extents and database tables. | 10-13-2011 |
20110289366 | MEMORY UTILIZATION BALANCING IN A DISPERSED STORAGE NETWORK - A method begins by a processing module identifying a memory loading mismatch between a first memory device and a second memory device of a dispersed storage unit, wherein the first memory device is assigned a first range of slice names and the second memory device is assigned a second range of slice names. The method continues with the processing module determining an estimated impact to reduce the memory loading mismatch and when the estimated impact compares favorably to an impact threshold, modifying the first and second ranges of slices names to produce a first modified range of slice names for the first memory device and a second modified range of slice names for the second memory device based on the memory loading mismatch and transferring one or more encoded data slices between the first and second memory devices in accordance with the first and second modified ranges of slice names. | 11-24-2011 |
20110296255 | INPUT/OUTPUT DEVICE INCLUDING A MECHANISM FOR ERROR HANDLING IN MULTIPLE PROCESSOR AND MULTI-FUNCTION SYSTEMS - An I/O device includes a host interface that may be configured to receive and process a plurality of transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may be configured to determine whether each transaction packet has an error and to store information corresponding to any detected errors within a storage. More particularly, the error handling unit may perform the error detection and capture of the error information as the transaction packets are received, or in real time, while the error handling unit may include firmware that may subsequently process the information corresponding to the detected errors. | 12-01-2011 |
20110296256 | INPUT/OUTPUT DEVICE INCLUDING A MECHANISM FOR ACCELERATED ERROR HANDLING IN MULTIPLE PROCESSOR AND MULTI-FUNCTION SYSTEMS - An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations. | 12-01-2011 |
20110302459 | SYSTEM AND METHOD FOR TESTING HARD DISK PORTS - A method tests hard disk ports located on a motherboard of a computing device. Each of the hard disk ports connects to a respective serial port of a test fixture. The test fixture includes a group of serial ports, a multiplexer and a storage device. Each of the hard disk ports is selected to be tested during the process of hard disk ports test. A data transmission path is formed by building a connection between the storage device and a channel of the multiplexer corresponding to the hard disk port. Data are written to the storage device and read from the storage device through the data transmission path. The hard disk port is working normal if the written data are identical to the read data. The hard disk port is not working normally if the written data are not identical to the read data. | 12-08-2011 |
20110307745 | UPDATING CLASS ASSIGNMENTS FOR DATA SETS DURING A RECALL OPERATION - Provided are a computer program product, system and method for updating class assignments for data sets during a recall operation in a storage environment having a plurality of storage devices. Information on a data set is processed to determine at least one current attribute of the data set. A determination is made as to whether the determined at least one current attribute satisfies a criteria. Indication is made in a catalog to change a class associated with the data set in response to determining that the at least one current attribute satisfies the criteria, wherein the class is used to determine how to manage the data set. The data set is migrated from a first storage to a second storage. A recall operation is initiated to recall the data set from the second storage. In response to the recall operation and determining that the catalog indicates to change the class associated with the data set, the catalog is processed to determine whether to change the class for the data set from a first class to a second class and a management operation is performed on the data set to conform the data set to the second class when recalling the data set. | 12-15-2011 |
20120036400 | DATA PROCSSING SYSTEM WITH PERIPHERAL CONFIGURATION INFORMATION ERROR DETECTION - In a data processing system including a first master operably coupled to a peripheral bus interface and a plurality of peripherals operably coupled to the peripheral bus interface, wherein the first master communicates with each of the plurality of peripherals via the peripheral bus interface, a method includes initiating a write, by the first master, of configuration information to a first peripheral of the plurality of peripherals. In response to initiating the write, the configuration information is provided via the peripheral bus interface for storage into the first peripheral, wherein a first error syndrome of the configuration information is generated by the peripheral bus interface. The provided configuration information is stored in the first peripheral, and the first error syndrome is stored in storage circuitry of the peripheral bus interface. The first error syndrome can be used to check the integrity of configuration information during subsequent error checking. | 02-09-2012 |
20120084610 | METHOD AND DEVICE FOR READING AND WRITING A MEMORY CARD - The present invention discloses a method and device for reading a memory card comprising a primary partition and at least one backup partition. The method comprises the following steps that: after writing a first file into the primary partition of the memory card, a read/write device writes the first file into the at least one back partition; and when reading a second file from the memory card, the read/write device reads the second file from the at least one backup partition or from the primary partition if an error occurs in the reading of the second file from the backup partition. The method and device provided herein address the problems existing in the prior art that an embedded system is unstable because of the low error tolerance of a memory card. | 04-05-2012 |
20120110396 | Error handling mechanism for a tag memory within coherency control circuitry - A data processing system | 05-03-2012 |
20120110397 | DATA TRANSMISSION SYSTEM, STORAGE MEDIUM AND DATA TRANSMISSION PROGRAM - A system has a processor configured to be capable of read and write to a main memory, a storage configured to transmit stored data per block on an I/O bus, and a protocol processing apparatus connected to the I/O bus and configured to perform a communication protocol process on behalf of the processor. The processor includes a specifying part configured to specify data per block to be transmitted from the storage, and an indicating part configured to indicate data transfer from the storage to the protocol processing apparatus by specifying address information of the protocol processing apparatus. The protocol processing apparatus includes a receiving part configured to directly receive data transferred per block from the storage to the I/O bus, without relaying the main memory, and a network processing part configured to transmit the data received per block by the receiving part over a network per packet. | 05-03-2012 |
20120117428 | CACHE MEMORY SYSTEM - A cache memory is operated in a write through system, and an operation to be performed when a cache mishit occurs is performed when corresponding data is not stored in the cache memory, or only when an error occurs although there is the data. Then, a bit indicating that a soft error has occurred before is set in the cache memory, and when the bit indicates “1” and if an error has occurred again, it is determined that a hardware error has occurred, and an interrupt is generated in the CPU. The bit is to be reset at time intervals sufficiently shorter than the frequency at which it is considered that a soft error occurs. | 05-10-2012 |
20120144249 | Program Disturb Error Logging and Correction for Flash Memory - Program disturb error logging and correction for a flash memory including a computer implemented method for storing data. The method includes receiving a write request that includes data and a write address of a target page in a memory. A previously programmed page at a specified offset from the target page is read from the memory. Contents of the previously programmed page are compared to an expected value of the previously programmed page. Error data is stored in an error log in response to contents of the previously programmed page being different than the expected value of the previously programmed page, the error data describing an error in the previously programmed page and the error data used by a next read operation to the previously programmed page to correct the error in the previously programmed page. The received data is written to the target page in the memory. | 06-07-2012 |
20120166891 | TWO-LEVEL SYSTEM MAIN MEMORY - Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. | 06-28-2012 |
20120166892 | ORPHAN OBJECT TRACKING FOR OBJECTS HAVING ACQUIRE-RELEASE SEMANTICS - A method for object tracking of resource objects with acquire and release semantics can include instrumenting both an acquisition method and a release method of a resource object to write a reference to the resource object to an open object set upon acquiring the resource object, and to remove the reference to the resource object in the open object set upon releasing the resource object. The method also can include determining whether the resource object both has been flagged for garbage collection in the virtual machine and also remains referenced in the open object set. Finally, the method can include generating an error record in the virtual machine responsive to determining the resource object to have been both flagged for garbage collection in the virtual machine and also remaining referenced in the open object set. | 06-28-2012 |
20120185738 | DETERMINING LOCATION OF ERROR DETECTION DATA - Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of memory cells includes determining a location of where to store error detection data for data to be stored across a plurality of memory units, including the memory unit having the bad group, based at least partially on a location of the bad group and storing the error detection data in the determined location. | 07-19-2012 |
20120192018 | APPARATUS AND METHOD FOR DETECTING OVER-PROGRAMMING CONDITION IN MULTISTATE MEMORY DEVICE - A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the system powers up. The controller is adapted to implement the program to provide instructions used to program and erase nonvolatile memory cells. A method embodiment comprises loading a program into memory upon powering up a memory system, and implementing the program using a controller, including programming and erasing multi-bit nonvolatile memory cells. | 07-26-2012 |
20120198289 | SYSTEM AND METHOD FOR WRITE PROTECTING PORTIONS OF MAGNETIC TAPE STORAGE MEDIA - Systems and methods for writing data on a magnetic tape having a plurality of partitions and accessed by a tape drive having an associated tape drive processor in communication with a host computer having an associated host processor include storing a read-only partition identifier associated with each of the plurality of partitions, comparing a requested write partition identifier with the stored read-only partition identifiers, and writing data to the requested write partition only if the associated read-only identifier indicates that the requested write partition is not a read-only partition. | 08-02-2012 |
20120266031 | Controlling Method and Controller for Memory - A memory controller including a detection module and a protection module is provided. The memory controller is applicable to a memory having a command transmission port and a data transmission port. The detection module detects whether an error condition occurs in an electronic device associated with the memory. When the error condition is detected, the protection module sends an interrupt command to the memory via the command transmission port to stop an operation associated with the data transmission port. | 10-18-2012 |
20120284572 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM AND SEARCH METHOD - An information processing device includes a memory unit that stores registration data of a search target and error information indicating an error of the registration data in association with each other. The information processing device includes a search unit that searches for registration data from the registration data stored by memory unit, the registration data searched by the search unit being registration data for which a value obtained by subtracting a value of the error information from a value of distance between query data related to a search request and the registration data is within the predetermined neighborhood range. | 11-08-2012 |
20120297256 | Large Ram Cache - Systems and method for configuring a page-based memory device without pre-existing dedicated metadata. The method includes reading metadata from a metadata portion of a page of the memory device, and determining a characteristic of the page based on the metadata. The memory device may be configured as a cache. The metadata may include address tags, such that determining the characteristic may include determining if desired information is present in the page, and reading the desired information if it is determined to be present in the page. The metadata may also include error-correcting code (ECC), such that determining the characteristic may include detecting errors present in data stored in the page. The metadata may further include directory information, memory coherency information, or dirty/valid/lock information. | 11-22-2012 |
20120304025 | DUAL HARD DISK DRIVE SYSTEM AND METHOD FOR DROPPED WRITE DETECTION AND RECOVERY - A system is provided. The system detects a dropped write from a hard disk drive (HDD). The system includes two or more HDDs, each being configured to define a data block spread across the two or more HDDs. The data block is configured to regenerate a checksum across the full data block during a read operation to detect the dropped write. | 11-29-2012 |
20120331356 | DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 12-27-2012 |
20130013966 | ELECTRONIC APPARATUS, CONTROL METHOD AND COMPUTER-READABLE STORAGE MEDIUM - An electronic apparatus includes an error detection times acquiring module and a waiting module. The error detection times acquiring module acquires the number of reading error detection times of a program according to a power-ON instruction instructing a power-ON operation, the number of error detection times being stored in a storage module. The waiting module waits for a reception of data capable of recognizing a communication counterpart device when the number of error detection times is more than a predetermined value by comparing the acquired number of error detection times with the predetermined value. | 01-10-2013 |
20130031427 | Performing Process for Removal Medium - In a controller of a tape drive, when an error recovery section cannot recover an error detected by an error detecting section, an error-report generation section generates an error report, an error-information acquisition section acquires error information of the tape drive and a cartridge loaded in the tape drive, an error-information exchange section acquires pieces of error information of other tape drives and cartridges loaded in these other tape drives, an error-factor judging section judges whether the error is attributable to the tape drive or the cartridge based on these pieces of error information, an error-report update section updates the error report in accordance with the result of this judgment, and an error-report output section outputs the error report thus updated to a host. | 01-31-2013 |
20130036332 | MAXIMIZING ENCODINGS OF VERSION CONTROL BITS FOR MEMORY CORRUPTION DETECTION - Systems and methods for maximizing a number of available states for a version number used for memory corruption detection. A physical memory may be a DRAM comprising a plurality of regions. Version numbers associated with data structures allocated in the physical memory may be generated so that version numbers of adjacent data structures in a virtual address space are different. A reserved set and an available set of version numbers are associated with each one of the plurality of regions. A version number in a reserved set of a given region may be in an available set of another region. The processor detects no memory corruption error in response to at least determining a version number stored in a memory location in a first region identified by a memory access operation is also in a reserved set associated with the first region. | 02-07-2013 |
20130042156 | UTILIZING MULTIPLE STORAGE DEVICES TO REDUCE WRITE LATENCY FOR DATABASE LOGGING - Methods, computer-readable media, and computer systems are provided for initiating storage of data on multiple storage devices and confirming storage of the data after the data has been stored on one but not necessarily all of the devices. A storage server receives, from a client, a request to store data. In response to the request, the storage server initiates, in parallel, storage of the data on multiple storage systems. The storage server detects that the data has been stored on any one of the storage systems, such as an auxiliary system, and, in response, indicates, to the client, that the data has been stored. The storage server may flush or discard data on the auxiliary storage system upon detecting that the data has been successfully stored on a target storage system, where the data persists. | 02-14-2013 |
20130047043 | MERGING MULTIPLE CONTEXTS TO MANAGE CONSISTENCY SNAPSHOT ERRORS - A method including creating a commit-in-progress context from a copy of a data object in a redirect-on-write file system; and begin storing the commit-in-progress context in a persistent storage device. The method further includes, while storing the commit-in-progress context in the persistent storage device: receiving a notification of a pending modification to the first data object, creating an update-in-progress context from a copy of the commit-in-progress context, and begin applying the modification to the update-in-progress context. The method further includes detecting that a connectivity error has occurred between the commit-in-progress context and the storage device, and in response, identifying whether the commit-in-progress context is successfully stored in the storage device. In response to identifying that the commit-in-progress context is not successfully stored: aborting the storing of the commit-in-progress context, assigning a new commit-in-progress context, and begin storing the new commit-in-progress context. | 02-21-2013 |
20130067289 | EFFICIENT NON-VOLATILE READ CACHE FOR STORAGE SYSTEM - A method includes, in a storage device that includes a non-volatile memory having a physical storage space, receiving data items associated with respective logical addresses assigned in a logical address space that is larger than the physical storage space. The logical addresses of the data items are translated into respective physical storage locations in the non-volatile memory. The data items are stored in the respective physical storage locations. | 03-14-2013 |
20130080844 | Systems and Methods for Efficient Data Shuffling in a Data Processing System - Various embodiments of the present invention provide systems and methods for data processing. For example, a method for data processing is disclosed that includes: receiving a data input having at least a first local chunk and a second local chunk, the data input also being defined as having at least a first global chunk and a second global chunk; rearranging an order of the first local chunk and the second local chunk to yield a locally interleaved data set; storing the locally interleaved data set to a first memory, such that the first global chunk is stored to a first memory space, and the second global chunk is stored to a second memory space; accessing the locally interleaved data set from the first memory; and storing the locally interleaved data set to a second memory. The first global chunk is stored to a third memory space defined at least in part based on the first memory space, and the second global chunk is stored to a fourth memory space defined at least in part based on the second memory space. | 03-28-2013 |
20130117613 | Statistical Read Comparison Signal Generation for Memory Systems - Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information for decoding encoded data read from a storage medium. More specifically, some implementations utilize a collection of characterization vectors that include soft information values for bit-tuples that may be read from the storage medium for various combinations of the storage medium characterization parameter values. Some implementations are enabled to determine and utilize read comparison signal values associated with one or more storage medium characterization parameter values. And some implementations are enabled to determine and utilize shifted read comparison signal values associated with one or more storage medium characterization parameter values and an identified error condition. | 05-09-2013 |
20130132783 | REPRESENTATION AND MANIPULATION OF ERRORS IN NUMERIC ARRAYS - In an embodiment, a computer system accesses various different data entries in dense data array, where at least one of those data entries in the dense data array is invalid. The computer system creates an associated sparse data array that includes multiple data entries with zero values as well as data entries with non-zero values. The non-zero data entries are configured to store location information and data values for each of the invalid data entries in the dense array. The zero-value data entries are inferred from the location information of the non-zero data entries. The computer system stores the location information and data values of the non-zero data entries in the sparse data array. Those data values stored in the sparse array are proportional to the number of invalid values in the dense array. | 05-23-2013 |
20130139007 | NONVOLATILE CACHE MEMORY, PROCESSING METHOD OF NONVOLATILE CACHE MEMORY, AND COMPUTER SYSTEM - Disclosed is a nonvolatile cache memory including a nonvolatile memory part and a cache controller. The nonvolatile memory part is configured to store cache data. The cache controller is configured to control reading and writing of the cache data with respect to the nonvolatile memory part. Further, the cache controller is configured to perform, as a preparation for an interruption of power supply, standby preparation processing to generate standby state data and store the generated standby state data in the nonvolatile memory part. Further, the cache controller is configured to perform, at resumption of the power supply, restoration processing of the cache data stored in the nonvolatile memory part using the standby state data. | 05-30-2013 |
20130145223 | STORAGE SUBSYSTEM AND METHOD FOR CONTROLLING THE SAME - In storage subsystems, due to the significant increase in HDD capacity, the time for executing online verification is elongated, affecting accesses from the host computer. By comprehending the status of accesses to the HDD, the sections where error has occurred and the status of restoration thereof, it becomes possible to detect defective or error sections efficiently at an early stage, according to which the reliability and access performance of the storage subsystem can be improved. The present storage subsystem executes one or more of the following processes: (M1) intensive verification of a circumference of an error LBA, (M2) an area-based prioritized verification, and (M3) continuous verification performed for a long period of time to (V1) an area in which error has occurred via IO access, (V2) a highly accessed area, and (V3) during a period of time when IO access is low. | 06-06-2013 |
20130151909 | SYSTEM CONTROL DEVICE, LOG CONTROL METHOD, AND INFORMATION PROCESSING DEVICE - When an error has occurred in one of a plurality of partitions and when an unused area is present in a log area, an information processing device allocates the unused area to the log area of the partition in which the error has occurred and stores a log of the error that has occurred. When an error has occurred in one of the plurality of partitions, when an unused area is not present in a log area, and when a registration count registered in a log area associated with the partition in which the error has occurred exceeds an upper limit, the information processing device allocates, to the log area of the partition in which the error has occurred, the oldest entry in a log area that stores therein error logs the number of which is equal to or greater than an upper limit count that is previously set and stores the log of the error that has occurred. | 06-13-2013 |
20130179738 | BACKGROUND MEMORY VALIDATION FOR GAMING DEVICES - Various embodiments are directed to a gaming device including a background memory validation system. The background memory validation system includes a background kernel thread that validates read-only pages on the gaming device. Additionally, the background kernel thread also minimizes potential timing problems because this process only validates page content in memory that is fully-loaded and functional. | 07-11-2013 |
20130246865 | IDENTIFYING A STORAGE ERROR OF A DATA SLICE - A method begins by a processing module obtaining common storage name information regarding data that is stored in storage units of a distributed storage network (DSN) as a set of data slices. Each data slice of the set of data slices has a unique storage name, where each of the unique storage names for the set of data slices has common naming information regarding the data. The method continues where the processing module interprets the common storage name information to determine whether a difference exists between the common naming information of a data slice of the set of data slices and the common naming information of other data slices of the set of data slices. When the difference exists, the method continues where the processing module indicates a potential storage error of the data slice and implements a storage error process regarding the potential storage error of the data slice. | 09-19-2013 |
20130254597 | SENDING FAILURE INFORMATION FROM A SOLID STATE DRIVE (SSD) TO A HOST DEVICE - A system, method, and computer program product are provided for sending failure information from a solid state drive (SSD) to a host device. In operation, an error is detected during an operation associated with a solid state drive. Additionally, a command is received for failure information from a host device. Further, the failure information is sent from the solid state drive to the host device, the failure information including failure information associated with the solid state drive. | 09-26-2013 |
20130275817 | REGISTER PROTECTED AGAINST FAULT ATTACKS - A circuit and method of detecting a fault attack in a circuit includes a plurality of registers each identified by an address. The method includes storing in a memory the address present on an address bus during a write operation to one of said registers. In response to a first alert signal indicating that the data stored by a first of said registers has been modified, comparing the address identifying said first register with said stored address. | 10-17-2013 |
20130275818 | STORAGE CONTROLLING APPARATUS, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM AND PROCESSING METHOD - Disclosed herein is a storage controlling apparatus, including: a status acquisition section configured to acquire status including a number of times of execution of verification after writing into a memory from the memory; a history information retention section configured to retain a history of the status as history information in an associated relationship with each of predetermined regions of the memory; and a region selection section configured to select a region which satisfies a condition in accordance with the history information when a new region is to be used in the memory. | 10-17-2013 |
20130283107 | Systems and Methods for Calibration Coasting in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for coasting one or more calibration loops based upon identification of a probability of data inaccuracies. | 10-24-2013 |
20130290793 | MANAGING UNRELIABLE MEMORY IN DATA STORAGE SYSTEMS - A data storage system configured to manage unreliable memory units is disclosed. In one embodiment, the data storage system maintains an unreliable memory unit list designating memory units in a non-volatile memory array as reliable or unreliable. The unreliable memory unit list facilitates management of unreliable memory at a granularity level finer than the granularity of a block of memory. The data storage system can add entries to the unreliable memory unit list as unreliable memory units are discovered. Further, the data storage system can continue to perform memory access operations directed to reliable memory units in blocks containing other memory units determined to be unreliable. As a result, the operational life of the data storage system is extended. | 10-31-2013 |
20130326289 | METHOD AND SYSTEM FOR DETECTION OF LATENT FAULTS IN MICROCONTROLLERS - Embodiments relate to systems and methods for detecting register corruption within CPUs operating on the same input data enabling non-invasive read access to and comparison of contents of at least one set of according ones of registers of different CPUs to detect corrupted registers in form of according registers with inconsistent contents. | 12-05-2013 |
20130339808 | BITLINE DELETION - Embodiments relate to a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line and recording a second address of the second error. Embodiments also include comparing the first and second bitline address, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching the first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to a third bitline address and deleting a location corresponding to the third cache line from available cache locations based on the activated bitline delete mode and the third bitline address matching the second bitline address. | 12-19-2013 |
20130339809 | BITLINE DELETION - Embodiments relate to a computer system for bitline deletion, the system including a cache controller and cache. The system is configured to perform a method including detecting a first error when reading a first cache line, recording a first address of the first error, detecting a second error when reading a second cache line, recording a second address of the second error, comparing first and second bitline addresses, comparing the first and second wordline address, activating a bitline delete mode based on matching first and second bitline addresses and not matching first and second wordline addresses, detecting a third error when reading a third cache line, recording a third bitline address of the third error, comparing the second bitline address to the third bitline address and deleting a location corresponding to the third cache line based on the activated bitline delete mode and matching third and second bitline addresses. | 12-19-2013 |
20130346810 | USE OF APPLICATION-LEVEL CONTEXT INFORMATION TO DETECT CORRUPTED DATA IN A STORAGE SYSTEM - A storage system, such as a file server, receives a request to perform a write operation that affects a data block. In response, the storage system writes to a storage device the data block together with context information which uniquely identifies the write operation with respect to the data block. When the data block is subsequently read from the storage device together with the context information, the context information that was read with the data block is used to determine whether a previous write of the data block was lost. | 12-26-2013 |
20140006880 | APPARATUS AND CONTROL METHOD | 01-02-2014 |
20140040676 | DIRECTORY ERROR CORRECTION IN MULTI-CORE PROCESSOR ARCHITECTURES - Technologies are generally described that relate to processing cache coherence information and processing a request for a data block. In some examples, methods for processing cache coherence information are described that may include storing in a directory a tag identifier effective to identify a data block. The methods may further include storing a state identifier in association with the tag identifier. The state identifier may be effective to identify a coherence state of the data block. The methods may further include storing sharer information in association with the tag identifier. The sharer information may be effective to indicate one or more caches storing the data block. The methods may include storing, by the controller in the directory, replication information in association with the sharer information. The replication information may be effective to indicate a type of replication of the sharer information in the directory, and effective to indicate replicated segments. | 02-06-2014 |
20140040677 | STORAGE DEVICE, CONTROL DEVICE AND DATA PROTECTION METHOD - A storage device includes one or more storages and one or more control devices to control writing data to and reading data from one of the storages. Each of the control devices includes a memory, a memory controller, and a processor. The memory controller controls writing data to and reading data from the memory. The processor determines whether the memory and the memory controller have error correcting functions respectively. The processor determines, when at least one of the memory and the memory controller does not have an error correcting function, whether an error is detected in first data expanded in a first memory region of the memory. The first data includes an error detecting code. The processor saves, when no error in the first data has been detected, the first data into a second memory region of the memory. The second memory region is different from the first memory region. | 02-06-2014 |
20140040678 | STORAGE DEVICE AND METHOD FOR MANAGING STORAGE DEVICE - A storage device includes a plurality of control devices to control writing data into one or more storages. Each of the plurality of control devices includes an interface unit and a processor. The interface unit transmits and receives data. The processor acquires first checking information added to first data to be written into a first storage. The processor acquires second checking information calculated based on the first data. The processor compares the first checking information and the second checking information. The processor reports an error by way of the interface unit when a result of the comparison indicates inconsistency between the first checking information and the second checking information. | 02-06-2014 |
20140040679 | RELAY DEVICE AND RECOVERY METHOD - A relay device for dividing a storage device into a plurality of unit areas, assigning an unused unit area from among the plurality of unit areas to received channel-specified data, and performing at least one of adjustment of a transmission timing of the data and conversion of the data by using the assigned unit area, is disclosed. The relay device includes an error detector configured to detect an error where the unit area from which the data is to be read is not specified; and an error control configured to recognize a channel of data stored in the unit area that is not specified due to the error detected by the error detector as a target channel, and to invalidate an assignment of the unit area to the recognized target channel. | 02-06-2014 |
20140040680 | MEMORY CONTROL DEVICE AND CONTROL METHOD - A memory controller receives a read request and also issues a patrol request at a predetermined time interval so as to determine whether any error occurs in data stored in a DIMM. Furthermore, the memory controller generates a patrol address that is the subject of the subsequently issued patrol request. When the memory controller receives a read request, the memory controller compares the patrol address with the read address that is the subject of the received read request. When the read address matches the patrol address, the memory controller cancels the issuance of the subsequent patrol request. | 02-06-2014 |
20140059396 | MEMORY SYSTEM HAVING NAND-TYPE FLASH MEMORY AND MEMORY CONTROLLER USED IN THE SYSTEM - According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. A comparison module of the memory controller compares a first threshold voltage distribution of a first memory area with a second threshold voltage distribution of the first memory area acquired earlier than the first threshold voltage distribution, if an error is detected in data read from the first memory area. An error factor determination module of the memory controller determines a cause of the error based on the comparison result, and inhibits a data move operation of moving data of the first memory area to the second memory area based on the determination result. | 02-27-2014 |
20140089745 | ELECTRONIC DATA PROCESSING SYSTEM PERFORMING READ-AHEAD OPERATION WITH VARIABLE SIZED DATA, AND RELATED METHOD OF OPERATION - A method of reading data in an electronic system comprises detecting whether a trigger signal in the electronic system is enabled, the trigger signal being selectively enabled according to at least one operating condition of the electronic system, as a consequence of detecting that the trigger signal is enabled, changing a size of read-ahead data based on the enabled trigger signal, and performing a read operation based on a read command and the changed size of the read-ahead data. | 03-27-2014 |
20140101497 | EVENT NOTIFICATION SYSTEM, EVENT INFORMATION AGGREGATION SERVER, AND EVENT NOTIFICATION METHOD - Events which have occurred in storage systems can be managed easily regardless of complexity of a storage configuration. | 04-10-2014 |
20140108875 | Systems and Methods for Indirect Information Assisted Media Defect Scan - Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for media defect detection. | 04-17-2014 |
20140223242 | Motivating Lazy RCU Callbacks Under Out-Of-Memory Conditions - A technique for motivating lazy RCU callbacks under out-of-memory conditions. In response to detecting an actual or potential OOM condition, non-lazy callback processing is performed for all processors whose RCU callback lists are non-empty due to at least one callback permitting lazy callback processing being present. | 08-07-2014 |
20140223243 | Secure redundant storage device and secure read/write method on such a device - Redundant storage devices in particular suitable for so-called SSD electronic disks. A data storage system is proposed based on a plurality of redundant physical storage disks in which the read/write commands intended to be sent to the redundant disks are subjected to a transfer function before being sent to at least one of the disks so that the actual commands sent to at least two disks are different. The values returned by the disks that received the commands that had undergone the transfer function are subjected to the inverse transfer function. Thus, a design error in the control module of the disks will be detected, since the control modules of the disks will not be called identically. | 08-07-2014 |
20140245084 | METHODS AND SYSTEMS FOR MONITORING WRITE OPERATIONS OF NON-VOLATILE MEMORY - Systems and methods are disclosed for monitoring the time it takes to perform a write operation, and based on the time it takes, a determination is made whether to retire a block that is a recipient of the write operation. The time duration of the write operation for a page or a combination of pages may indicate whether any block or blocks containing the page or combination of pages is experiencing a physical failure. That is, if the time duration of the write operation for a particular page exceeds time threshold, this may indicate that this page requires a larger number of program cycles than other pages. The longer programming cycle can be an indication of cell leakage or a failing block. | 08-28-2014 |
20140281750 | DETECTING EFFECT OF CORRUPTING EVENT ON PRELOADED DATA IN NON-VOLATILE MEMORY - A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event. | 09-18-2014 |
20140281751 | EARLY DATA DELIVERY PRIOR TO ERROR DETECTION COMPLETION - Embodiments relate to early data delivery prior to error detection completion in a memory system. One aspect is a system that includes a cache subsystem interface with a correction pipeline in a system domain. The system includes a memory control unit interface in a memory controller nest domain and a buffer control block providing an asynchronous boundary layer between the system domain and the memory controller nest domain. A controller is configured to receive a frame of a multi-frame data block and write the frame to the buffer control block. The frame is read by the cache subsystem interface prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to the correction pipeline in the system domain. | 09-18-2014 |
20140298116 | METHOD AND APPARATUS FOR AN IMPROVED FILE REPOSITORY - A method and apparatus for of storing data comprising monitoring a plurality f storage units within a mass storage area and detecting when a storage unit within the mass storage area is overloaded, The method further comprising randomly distributing the data on the overloaded storage unit to the other storage units within the mass storage area. | 10-02-2014 |
20140337675 | COMPUTER SYSTEM AND ITS EVENT NOTIFICATION METHOD - If a failure occurs in physical resources constituting a virtual volume, a management server device is notified of information required by a user. A computer system includes a server device for managing a plurality of virtual volumes, a storage apparatus having a storage unit equipped with a plurality of storage devices, and a controller for controlling data input to, or output from, the storage unit, a management server device which is an access target of a user terminal, and an event management device for managing an event(s) generated by the server device or the storage apparatus, wherein when the event management device receives the event, it judges the content of the event and identifies a virtual volume to be affected by the event; and if a service level that should be satisfied by the identified virtual volume is defined for the identified virtual volume, the event management device identifies, based on the content of the received event, whether an incident in violation of the service level has occurred or not, and then notifies the management server device of the identified content as an event based on an event filter. | 11-13-2014 |
20150019918 | Method and Apparatus for Reducing Read Latency - A method and an apparatus for reducing a read latency are provided. The method includes: when one or more flash chips corresponding to a read command are in a busy state, setting data read from the one or more flash chips in a busy state to wrong data; obtaining, according to the wrong data and data read from other flash chips, reconstructed correct data, and reporting the correct data. By using the present invention, data read from a flash chip is set to wrong data, and reconstructed correct data is obtained according to the wrong data and data read from other flash chips. In this way, when the flash chip is in a busy state, it can be avoided that a read operation is blocked by an erase operation or a write operation, thereby effectively reducing latency and improving a performance of a storage system. | 01-15-2015 |
20150046759 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A micro controller with fault detection function is provided, in which duplex processing by a program is realized without complicating the program. Peripheral circuits are provided with registers and execute processing based on a command. A central processing unit executes twice processing by the same program that accesses the register. A duplex access control circuit is configured with a peripheral bus access unit, a buffer, and a comparator unit. The peripheral bus access unit controls the access to the register by the central processing unit in the first program execution. The buffer stores the access information to the register in the first program execution. The comparator unit compares the access information in the second program execution with the access information stored in the access information storage unit. In the case of disagreement, an error signal is outputted to the central processing unit. | 02-12-2015 |
20150074470 | NON-VOLATILE MEMORY ASSEMBLIES - A non-volatile memory assembly, for use in a programmable device within a power transmission network, comprises a non-volatile reprogrammable primary memory portion and a secondary memory portion. The non-volatile memory assembly also includes a controller that is configured to direct a programmable device to access data from the secondary memory portion; refresh the data in the primary memory portion with data from the secondary memory portion; and direct the programmable device to access data from the primary memory portion. | 03-12-2015 |
20150089306 | FAST PATH USERSPACE RDMA RESOURCE ERROR DETECTION - Mechanisms are provided for providing an early warning of an error state of a remote direct memory access (RDMA) resource to a userspace application. The mechanisms detect, using kernelspace logic, an error event having occurred, and perform a write operation to write an error state value to a userspace shared memory state data structure indicating the RDMA resource to be in an error state. The mechanisms detect, using userspace logic, the RDMA resource being in an error state by reading the error state value from the userspace shared memory state data structure in response to a userspace application attempting to perform a RDMA operation using the RDMA resource. In addition, the mechanisms initiate, by the userspace application, an operation to tear down the RDMA resource in response to detecting the RDMA resource being in the error state. | 03-26-2015 |
20150095722 | PATTERN ORIENTED DATA COLLECTION AND ANALYSIS - A process for determining a problematic condition while running software includes: loading a first pattern data set having a symptom code module, a problematic condition determination module, and a set of responsive action module(s), generating a runtime symptom code in response to a first problematic condition being caused by the running of the software on the computer, determining that the runtime symptom code matches a symptom code corresponding to the first pattern data set, determining that the first problematic condition caused the generation of the runtime symptom code, and taking a responsive action from a set of responsive action(s) that corresponds to the first problematic condition. | 04-02-2015 |
20150095723 | DETECTION SYSTEM FOR DETECTING FAIL BLOCK USING LOGIC BLOCK ADDRESS AND DATA BUFFER ADDRESS IN A STORAGE TESTER - Disclosed is a detection system for detecting fail block using logic block address and data buffer address in a storage tester, which is capable of comparing data read from SSD test without expected data buffer. The system comprises a device driver for controlling HBA; a request processor for reading the request to Root Complex and transmitting the result to a data engine; and the data engine for generating data to be transmitted to SSD and comparing the read data. | 04-02-2015 |
20150355960 | MAINTAINING DATA STORAGE IN ACCORDANCE WITH AN ACCESS METRIC - When an access metric regarding an encoded data object exceeds an access threshold, a method begins by a processing module of a dispersed storage network (DSN) retrieving encoded data slices of a first plurality of sets of encoded data slices and recovering the data object utilizing first dispersed storage error encoding parameters. The method continues with the processing module re-encoding the recovered data object using second dispersed storage error encoding parameters to produce a re-encoded data object, where the re-encoded data object includes a second plurality of sets of encoded data slices. The method continues with the processing module outputting the second plurality of sets of encoded data slices to storage units of the DSN for storage therein and sending a message to retrieving devices of the DSN, where the message indicates use of the second plurality of sets of encoded data slices for the data object. | 12-10-2015 |
20160034331 | MEMORY SYSTEM AND DATA PROTECTION METHOD THEREOF - A memory system includes an abnormality detecting block including a plurality of abnormality detectors to detect whether an abnormal condition has occurred during a normal operation due to an external attack. An abnormality processing block is configured to process the abnormal condition in hardware, and a central processing unit is configured to execute a first process to detect whether the abnormal condition has occurred during the normal operation and to execute a second process to process the abnormal condition in software. A monitoring unit is configured to monitor an operation of the second process and to determine whether an error has occurred in the second process based on a monitoring result. | 02-04-2016 |
20160110241 | APPARATUS, SYSTEM AND METHOD FOR PROTECTING DATA - An apparatus and corresponding method for protecting stored data. The apparatus includes a first encoder, a memory, a second encoder and a comparator. The first encoder is configured to generate first redundancy bits using a protection method to protect input data bits, whereas the input data bits are assigned to at least one of a plurality of classes. The memory is configured to store selectively inverted input data bits and/or selectively inverted first redundancy bits, whereas the selective inversion is based on the assigned at least one of the plurality of classes. The second encoder is configured to generate second redundancy bits using the protection method by encoding the selectively inverted input data bits. The comparator is configured to generate an alarm signal if the second redundancy bits are different from the first redundancy bits. | 04-21-2016 |
20160110248 | STORAGE ARRAY MANAGEMENT EMPLOYING A MERGED BACKGROUND MANAGEMENT PROCESS - In at least one embodiment, a controller of a non-volatile memory array iteratively performs a merged background management process independently of any host system's demand requests targeting the memory array. During an iteration of the merged background management process, the controller performs a read sweep by reading data from each of a plurality of page groups within the memory array and recording page group error statistics regarding errors detected by the reading for each page group, where each page group is formed of a respective set of one or more physical pages of storage in the memory array. During the iteration of the merged background management process, the controller employs the page group error statistics recorded during the read sweep in another background management function. | 04-21-2016 |
20160132379 | Storage Device Calibration Methods and Controlling Device Using the Same - A calibration method includes transmitting first data comprising a calibration data and a first checksum to the storage device according to each of a plurality of training parameter sets; recording a plurality of error indicators respectively which are corresponding to the plurality of training parameter sets and from the storage device; and identifying one of the plurality of training parameter sets as a predetermined parameter set according to the plurality of error indicators respectively corresponding to the plurality of training parameter sets; wherein each error indicator indicates whether transmitting the first data according to the corresponded training parameter set is successful. | 05-12-2016 |
20160170819 | METHOD AND APPARATUS FOR FAILURE DETECTION IN STORAGE SYSTEM | 06-16-2016 |