Entries |
Document | Title | Date |
20080222445 | BIAS AND RANDOM DELAY CANCELLATION - A system and method for digital communication wherein a host provides a host clock and a clockless device transmits to the host a bit stream synchronized according to the clock at a data rate that is an integer multiple of the clock rate. A training mechanism using training data detects time skew between host clock and bit stream, and a digital skew compensation mechanism compensates, substantially in real time, for the skew and for variations in the skew that may occur with the passage of time, in accordance with a vote among at least three samples of a bit of the bit stream, subsequent sampling being retarded or advanced if, respectively, an early or late sample is in disagreement with the vote. Preferably, the compensation value is selected from at least four possible compensation values, and can be stored in a memory to hasten subsequent restarts of the system. | 09-11-2008 |
20080244303 | NIBBLE DE-SKEW METHOD, APPARATUS, AND SYSTEM - De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits. | 10-02-2008 |
20080294927 | Method and System for Clock Skew Reduction in Clock Trees - A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value. | 11-27-2008 |
20090019304 | METHOD AND APPARATUS FOR HARDWARE TIMING OPTIMIZER - A method for optimizing signal operating parameters for a signal sent over a data transmission channel through a programmable logic device (PLD) is provided. A transmit test pattern is generated and is associated with a set of signal operating parameters for the transmission and receiving of the test pattern over a data transmission channel. The data transmission channel loops from a transmit port to a receive port of the PLD. A determination of whether the received test pattern matches the transmit test pattern is performed. The match results and the set of signal operating parameters are recorded. At least one of the signal operating parameters of the set of signal operating parameters is modified through a processor of the PLD. Another transmit pattern is transmitted and received according to the modified set of signal operating parameters and the results are recorded. Methods for optimizing data transfer into a PLD and corresponding apparatuses are included. | 01-15-2009 |
20090063889 | ALIGNING DATA ON PARALLEL TRANSMISSION LINES - The lane skew alignment device of the present invention facilitates the use of the SFI-5 standard interface in an FPGA without the need to rely on feedback signals from a remote device. The delay between lanes is determined using a D-Flip Flop or other type of phase comparator. To minimize the components needed to physically implement the solution a cross-point switch is used to select one of the parallel lanes at a time to be compared to a reference lane, over which the same test signal is transmitted. | 03-05-2009 |
20090138747 | Phase Adjustment Apparatus and Method for a Memory Device Signaling System - Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system. | 05-28-2009 |
20090138748 | APPARATUS AND METHOD FOR MICRO PERFORMANCE TUNING OF A CLOCKED DIGITAL SYSTEM - An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, the clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period. The apparatus further including at least one voltage drop sensor coupled to the core, the sensor being configured to generate an output signal for detecting a voltage drop in the core and to determine whether or not the output signal is detected within the clock period and, if the output signal is not detected, the sensor dynamically adjusts the clock period of the clock signal provided to the core to allow more time to complete state transitions, such that, dynamically adjusting the clock period effectively changes an effective core clock frequency. | 05-28-2009 |
20090138749 | Hypertransport/SPI-4 Interface Supporting Configurable Deskewing - A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a plurality of data line deskew/sampling blocks, a data group deskew module, and an enablement control module. The plurality of data line deskew/sampling blocks deskew and sample incoming data on respective data lines based upon a clock signal to produce deskewed data. The data group deskew module receives deskewed data from each of the plurality of data line deskew/sampling blocks and removes inter-data line skew from the deskewed data to produce received data. The plurality of data line deskew/sampling blocks and the data group deskew module can be configured in a first mode when supporting an aspect of the HyperTransport Standard and configured in a second mode when supporting the at least one other interface standard. In the alternative, a plurality of data line deskew/sampling blocks and the data group deskew module may be set based upon a training sequence received from a link partner. | 05-28-2009 |
20090150708 | Apparatus and method for receiving parallel SFI-5 data interfaced with very high-speed deserializer - The development of transmission technologies have resulted in a several tens Gbps optical transmission system. In the present invention, a low-speed FPGA receives a plurality of several Gbps signals according to a very high-speed parallel converting unit and the SFI-5, divides each of the plurality of several Gbps signals into a plurality of several hundreds (Mbps) parallel signals, and processes the plurality of several hundreds (Mbps) parallel signals in order to constitute an SFI-5 receiving end. | 06-11-2009 |
20090158078 | Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof - The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a digital system is provided that includes a first digital circuit that operates at a first rate determined by a first clock signal and a second digital circuit that operates at a second rate determined by a second clock signal. The first digital circuit is coupled to the second digital circuit by a bus that is used for communications between the first digital circuit and the second digital circuit. A clock ratio controller is used to adjust the frequency of the first clock signal and/or the second clock signal in response to a power management signal without causing a loss of synchronization between the first digital circuit and the second digital circuit. | 06-18-2009 |
20090187784 | FAIR AND DYNAMIC CENTRAL PROCESSING UNIT SCHEDULING - Embodiments that facilitate the fair and dynamic distribution of central processing unit (CPU) time are disclosed. In accordance with one embodiment, a method includes organizing one or more processes into one or more groups. The method further includes allocating a CPU time interval for each group. The allocation of a CPU time interval for each group is accomplished by equally distributing a CPU cycle based on the number of groups. The method also includes adjusting the allocated CPU time intervals based on a change in the quantity of the one or more groups. | 07-23-2009 |
20090240973 | System and method for effectively performing a clock adjustment procedure - A system and method for effectively performing a clock adjustment procedure includes a multi-core processor that has a plurality of processor cores that each operate with reference to a target clock signal for performing various processing tasks. The processor cores include functional processor cores and one or more non-functional processor cores. A clock manager performs the clock adjustment procedure under control of a master processor core by selecting and applying a target clock frequency for the target clock signal. The target clock frequency is selected to allow the functional processor cores to compensate for the non-functional processor cores by collectively performing all of the required processing tasks. | 09-24-2009 |
20090265574 | Systemic Frequency Adjusting Method for Storage Device - A method of adjusting systemic frequency in a storage device, wherein a command is provided by a computer system to count the number of the clock pulses in a set time period of the computer system and the storage device; the value of correction of the systemic frequency of the storage device is obtained by calculation of the computer system, then the value of correction is stored in a storing medium; and the systemic frequency of the storage device is adjusted by the system operating clock frequency adjusting unit according to the value of correction of the systemic frequency, so that the systemic frequency of the storage device can be controlled within a predetermined range that meets the requirement for a device with higher system performance specification, and thereby the cost of production can be reduced. | 10-22-2009 |
20090271652 | METHODS AND COMPUTER PROGRAM PRODUCTS FOR DETERMINING SIMULTANEOUS SWITCHING INDUCED DATA OUTPUT TIMING SKEW - A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a normal operational frequency used to write non-predetermined data to the memory device. The memory device is read to output the predetermined data pattern therefrom at a second operational frequency that is greater than the first operational frequency and about equal to a normal operational frequency used to read non-predetermined data from the memory device. Timing skew is determined between outputs from the memory device based on the actual time when the predetermined data is provided from the memory device. | 10-29-2009 |
20090319819 | Clock Synchronization Using Correlation Events - Two clocks may be synchronized by calculating skew and offset values that may be determined from several correlation events. A correlation event may be the passing of messages in both directions between the two devices. The skew and offset values may be used to determine the time of non-correlated events. The clock synchronization may be performed on a real time basis or may be performed on a post processing basis. One method for calculating the skew and offset may use inequalities within a solution space to refine a solution set with multiple sets of correlation events. | 12-24-2009 |
20100017641 | Communication system communication device and method for determining duty ratio of PWM control - A communication system includes: a master; a plurality of slaves; and a bus for coupling among the master and the plurality of slaves in order to communicate asynchronously among the master and the plurality of slaves. The master supplies electricity to the bus in a power supply period. The master or the slave drives the bus for transmitting a one-bit data through the bus in a data transmission period. The power supply period and the data transmission period are successively performed so that data communication provided by a plurality of one-bit periods is performed among the master and the plurality of slaves. The master finely changes a communication frequency in the data communication. The master changes a drive level of the bus within a predetermined acceptable range in the data communication. | 01-21-2010 |
20100023795 | METHOD FOR HANDLING DATA - A method for handling data in which a serial data flow, with which a plurality of data is transmitted simultaneously per line, is transmitted using a serial protocol, which is formed from data blocks and synchronization blocks. | 01-28-2010 |
20100042865 | Physical Coding Sublayer for a Multi-Pair Gigabit Transceiver - A physical coding sublayer (PCS) transmitter circuit generates a plurality of encoded symbols according to a transmission standard. A symbol skewer skews the plurality of encoded symbols within a symbol clock time. A physical coding sublayer (PCS) receiver core circuit decodes a plurality of symbols based on encoding parameters. The symbols are transmitted using the encoding parameters according to a transmission standard. The received symbols are skewed within a symbol clock time by respective skew intervals A PCS receiver encoder generator generates the encoding parameters. | 02-18-2010 |
20100058104 | SEMICONDUCTOR DEVICE AND DATA TRANSMISSION SYSTEM - To provide a semiconductor device including a data input circuit and a data output circuit connected to a plurality of data input/output terminals, where at least one of the data input circuit and the data output circuit fetches data in response to multi-phase clock signals having different phases to be timing signals for fetching data, and adjusts a valid range for fetching data to be substantially uniform for each of the multi-phase clock signals. According to the present invention, the window width of data can be made uniform by individually adjusting the multi-phase clock signals that are input or output timing signals, and thus characteristics of the semiconductor device can be improved. | 03-04-2010 |
20100083025 | Clock Device and Computer-Readable Record Medium Storing Program for Implementing the Same - A clock device comprises a time information acquisition unit which acquires time information representing present time from an external device at preset time intervals, a time correction unit which corrects time of an internal clock based on the time information, an error calculation unit which calculates an error of the time of the internal clock based on the present time represented by the time information, and a setting change unit which changes the set value of the time interval based on the error. The setting change unit updates the set value to m times the set value when the error is smaller than a first threshold value, while updating the set value to n times the set value when the error is larger than a second threshold value larger than the first threshold value (m, n: positive values satisfying m>1, n<1 and m·n≠1). | 04-01-2010 |
20100106997 | METHOD AND APPARATUS FOR GENERATING EXPECT DATA FROM A CAPTURED BIT PATTERN, AND MEMORY DEVICE USING SAME - Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group. A second group of applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and may be utilized in a variety of integrated circuits, such as an SLDRAMs. | 04-29-2010 |
20100122106 | SERIAL BUS CLOCK FREQUENCY CALIBRATION SYSTEM AND METHOD THEREOF - A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost. | 05-13-2010 |
20100146321 | SINGLE-CLOCK, STROBELESS SIGNALING SYSTEM - A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path. | 06-10-2010 |
20100169699 | MEMORY DEVICE, HOST DEVICE, AND SAMPLING CLOCK ADJUSTING METHOD - A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently. | 07-01-2010 |
20100275053 | CLOCK SKEW MEASUREMENT FOR MULTIPROCESSOR SYSTEMS - Systems and methods (“utility”) for providing more accurate clock skew measurements between multiple CPUs in a multiprocessor computer system by utilizing the cache control or management protocols of the CPUs in the multiprocessor system. The utility may utilize a time stamp counter (TSC) register of the CPUs in the multiprocessor computer system to detect the clock skew between the various CPUs in the system. Further, the delay between measurements of the TSC registers of the CPUs may be minimized by utilizing the features of the hardware cache control or management protocols of the computer system, thereby providing more accurate clock skew measurements. | 10-28-2010 |
20100281290 | CLOCK GENERATING CIRCUIT OF COMPUTER - A clock signal generating circuit of a computer includes a first phase locked loop (PLL) circuit and a second PLL circuit. The computer includes a central processing unit (CPU) and a data bus. The first PLL provides a CPU clock signal to the CPU. A frequency of the CPU clock signal is the same as a working frequency of the CPU. The second PLL circuit provides a bus clock signal to the data bus. A frequency of bus clock signal is the same as a working frequency of the data bus. The data bus is to communicate with a graphic chip. The CPU clock signal is to control a working speed of the CPU. The bus clock signal is to control a working speed of the data bus. | 11-04-2010 |
20100281291 | METHOD FOR ADJUSTING COMPUTER SYSTEM AND MEMORY - The invention provides an adjusting method of a system for changing a working frequency in an operation system for a computer system. The adjusting method includes establishing a look-up table, and detecting a newest value of the working frequency. An adjustment value can be obtained from the look-up table according to the newest value of the working frequency. In addition, a phase difference of a control signal of a memory is adjusted in the computer system according to the adjustment value and the working frequency is executed stably in optimum status according to the present invention. | 11-04-2010 |
20100306569 | DATA FLOW CONTROL IN MULTIPLE INDEPENDENT PORT - A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a device address (DA) or ID number for designating a device that executes a command. Data contained in the command sent by the memory controller is captured by an individual link control circuit, in response to internally generated clock with appropriate latencies. The captured data is written into a corresponding memory bank. The data stored in one of a plurality of memory banks of one memory device is read in accordance with the addresses issued by the memory controller. The read data is propagated from the memory device through the series-connected memory devices to the memory controller. | 12-02-2010 |
20110016346 | SERIAL BUS CLOCK FREQUENCY CALIBRATION SYSTEM AND METHOD THEREOF - A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to share the same oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution, greatly reduce system complexity and save element cost. | 01-20-2011 |
20110047403 | IMAGE FORMING APPARATUS - This invention provides an image forming apparatus that suppresses a control error between CPUs when the CPUs operate in cooperation with each other in distributed control by the CPUs. To accomplish this, the image forming apparatus utilizes a distributed control system. Respective CPUs measure time interval concerning image formation processing using their built-in clock oscillators, and perform operations in cooperation with each other. Correction coefficients are calculated based on the time interval measured by the respective CPUs to correct a measurement error generated by the operation an error of the respective clock oscillators. Clock count values each indicating a timing to drive a load is corrected based on the correction coefficients. | 02-24-2011 |
20110099410 | CLOCK DATA RECOVERY AND SYNCHRONIZATION IN INTERCONNECTED DEVICES - For synchronizing a master device and a slave device connected by a data transfer link, the master device measures a phase offset in a signal received from the slave device with respect to the master's clock signal. The master determines a control symbol based on the phase offset. The master encodes the control symbol in a transmit signal for the slave. The slave decodes the control symbol from the signal received from the master. The slave uses the control symbol to adjust the phase shift to compensate for the phase offset of a signal to be transmitted to the master device. When the phase compensated signal is received at the master, its phase offset is smaller than the original phase offset. This procedure can be performed iteratively until the phase offset is within a desired tolerance. | 04-28-2011 |
20110119521 | REPRODUCIBILITY IN A MULTIPROCESSOR SYSTEM - Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state. | 05-19-2011 |
20110138216 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 06-09-2011 |
20110145623 | SYSTEM ON A CHIP WITH CLOCK CIRCUITS - An embodiment of a system on a chip includes a reference clock circuit configured to produce a reference clock signal, a first clock circuit configured to produce a first clock signal, and adjustment circuitry. The adjustment circuitry is configured to make a determination of whether a characteristic of the reference clock signal compares unfavorably with a characteristic of the first clock signal, and when the characteristic of the reference clock signal compares unfavorably with the characteristic of the first clock signal, to adjust a parameter of the first clock circuit that results in tuning the first clock signal. | 06-16-2011 |
20110185218 | Adjustment of Write Timing Based on a Training Signal - A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference. | 07-28-2011 |
20110197088 | METHOD AND SYSTEM TO PROVIDE A COMPLIANCE CLOCK SERVICE SUITABLE FOR CLOUD DEPLOYMENT - A method and system for providing an improved compliance clock service are described. An example method comprises establishing a system compliance clock (SCC) for a storage system that provides a compliant storage service, and establishing, for a volume in the storage system, a volume compliance clock (VCC). A current value of the SCC may be periodically updated based on hardware ticks monitored at the associated storage node. The volume compliance clock is to update its value based on a current value of the SCC. | 08-11-2011 |
20110225443 | IMAGE FORMING APPARATUS AND CONTROL APPARATUS - The present image forming apparatus includes a first control unit and a second control unit driven by built-in clock oscillators to realize the distributed control. The first control unit generates, using a first timer driven by the built-in clock oscillator of the first control unit, a pulse signal corresponding to a predetermined clock rate and outputs the pulse signal to the second control unit. The second control unit measures, using a second timer driven by the built-in clock oscillator of the second control unit, a pulse width of the pulse signal outputted from the first control unit, and calculates a correction coefficient using reference pulse width corresponding to the predetermined clock rate and the measured pulse width. The processing unit processes using the calculated correction coefficient. | 09-15-2011 |
20110239034 | TRANSMISSION APPARATUS AND CONTROL METHOD - There is provided a transmission apparatus including: a clock generator; a first circuit including first data processors to process input data based on a first input clock, the first data processors electrically connected in series each transmitting data processed thereby and the first input clock to the next first data processor, the first input clock of the beginning first data processor being one of the clocks generated by the clock generator; a second circuit including: second data processors same as the first data processors; and phase adjusters each to adjust a phase of the second input clock and transmitting the second input clock adjusted thereby to the next second data processor; phase comparators each to compare phases of the first input clock and the second input clock; and a delay controller to control the phase adjusters, based on comparison results of the phase comparators. | 09-29-2011 |
20110239035 | METHOD AND APPARATUS FOR GENERATING A CLOCK SIGNAL AND FOR CONTROLLING A CLOCK FREQUENCY USING THE SAME - A method and a device for generating a clock signal determine a number of pulses to be discarded from each predetermined cycle of a reference clock signal in order to obtain, on average, a target frequency. A masking pattern is created for discarding the number of pulses to be discarded from each predetermined cycle of the reference clock signal. The clock signal, which includes the target frequency, is generated by discarding the number of pulses from the reference clock signal using the masking pattern. | 09-29-2011 |
20110289340 | DYNAMIC SYSTEM CLOCK RATE - In a first embodiment of the present invention, a method for dynamically adjusting a system clock of a plurality of system clock-controlled components in a system is provided, the method comprising: detecting the receipt of a command at a non-system clock-controlled component of the system; and adjusting the system clock to a fast speed based on the detecting. This embodiment may also include: determining that the command has been completed; determining that there are no outstanding commands in the plurality of system clock-controlled components; and adjusting the system clock to a slow speed based on the determination that there are no outstanding commands in the plurality of system clock-controlled components. | 11-24-2011 |
20110296227 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 12-01-2011 |
20120005518 | Host Controller, Semiconductor Device, Information Processing Apparatus, and Sampling Method - According to one embodiment, there is provided a host controller. The host controller includes a plurality of data input sections and a controller. The plurality of data input sections is configured to repeat an operation of acquiring a plurality of values by sampling a content of read data and additional information accompanying the content with a plurality of clocks of different phases. The controller is configured to adjust phases of the clocks based on the plurality of values acquired by the data input sections. | 01-05-2012 |
20120030500 | Hysteresis Management in SOI Data Processing Circuits - Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry is used to reduce the effects of hysteresis. The embodiment disclosed herein provides significant reduction in the effects of hysteresis and, therefore, a significant reduction in the amount of guard band needed to compensate for hysteresis effects in SOI processes and thereby improving the performance/power characteristics of the circuit. | 02-02-2012 |
20120089857 | METHOD FOR COMPENSATING FOR VARIATIONS IN DATA TIMING - A method for compensating for variations in timing of data sent to a processor on data bit lines relative to a strobe clock sent to the processor on a strobe clock line that can be used in a dual data rate (DDR) memory identifies discrete minimum and maximum time offset values for test data in selected data bit patterns for the data bit lines. The discrete minimum time offset value is the minimum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock and the discrete maximum time offset value is a maximum timing adjustment required to allow the processor to receive the data in a steady-state condition during a data valid window of the strobe clock. The discrete minimum and maximum time offset values identify a valid range when the data bit lines supply data in a steady-state condition for latching into the processor by the strobe clock. | 04-12-2012 |
20120117414 | PREAMBLE ACQUISITION WITHOUT SECOND ORDER TIMING LOOPS - A clock is adjusted by obtaining a first plurality of samples and a second plurality of samples associated with a preamble portion of a data packet. The first plurality of samples and the second plurality of samples are sampled using a clock. A first intermediate value is determined based at least in part on the first plurality of samples and a second intermediate value is determined based at least in part on the second plurality of samples. An ending value associated with an end of the preamble portion is determined based at least in part on the first intermediate value and the second intermediate value. The clock is adjusted based at least in part on the ending value without use of a second order timing loop. | 05-10-2012 |
20120117415 | PROVIDING FAULT-TOLERANT SPREAD SPECTRUM CLOCK SIGNALS IN A SYSTEM - To provide fault-tolerant, spread spectrum clock signals, a plurality of processing modules having respective spread spectrum control circuits are provided. Clock signals of redundant clock sources are provided to the plurality of processing modules. Failover control logic selects a corresponding one of the clock signals from the redundant clock sources for use in each of the processing modules. Frequency spreading is applied to the corresponding selected clock signal in each of at least some of the plurality of processing module. | 05-10-2012 |
20120124409 | SEMICONDUCTOR DEVICE HAVING DLL CIRCUIT - A semiconductor device with a clock control circuit that outputs an internal clock signal configured by delaying external clock signals based on at least a feedback clock signal; a plurality of output buffers that output data in synchronization with the internal clock signal; an output replica that is a replica of the output buffers and that generates the feedback clock signal in synchronization with the internal clock signal and supplies the feedback clock signal to the clock control circuit; and a clock tree that receives the internal clock signal from the clock control circuit and transmits the internal clock signal to the plurality of output buffers and the output replica such that signal line are substantially equal to one another. | 05-17-2012 |
20120166863 | Methods And Apparatus For Synchronizing Communication With A Memory Controller - A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. | 06-28-2012 |
20120173917 | PERFORMING A PERFORM TIMING FACILITY FUNCTION INSTRUCTION FOR SYNCHRONIZING TOD CLOCKS - A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes receiving, at a processing unit, a request to change a clock steering rate used to control a TOD-clock offset value for the processing unit, the TOD-clock offset defined as a function of a start time (s), a base offset (b), and a steering rate (r). The unit schedules a next episode start time with which to update the TOD-clock offset value. After updating TOD-clock offset value (d) at the scheduled time, TOD-clock offset value is added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator. | 07-05-2012 |
20120185722 | MASTER SLAVE INTERFACE - Implementations related to systems, devices, and methods that make use of a master slave arrangement are described. In one implementation, a method of reducing overall power consumption in a master-slave system includes generating a clock signal in a master device having a first power consumption rate, transmitting the clock signal from the master device to a slave device having a second power consumption rate, the first power consumption rate is lower than the second power consumption rate, sampling data receive by the slave device, the data being provided by the master device, generating phase error information of the clock signal in the slave device, transmitting the phase error information from the slave device to the master device, and adjusting the clock signal in response to the phase error information. | 07-19-2012 |
20120216066 | AUTOMATIC REFERENCE FREQUENCY COMPENSATION - In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method comprising: beginning a link negotiation stage between the device and the host using the device reference clock; during the link negotiation stage, sampling data received from the host to determine a frequency offset of the host reference clock; applying the frequency offset to the device reference clock to create a corrected device reference clock; and completing the link negotiation stage using the corrected device reference clock. This completing may include either continuing the original link negotiation stage or restarting it. | 08-23-2012 |
20120233490 | Openstack synchronization and ordering - Several different embodiments of a massively scalable object storage system are described. The object storage system is particularly useful for storage in a cloud computing installation whereby shared servers provide resources, software, and data to computers and other devices on demand. In several embodiments, the object storage system includes a ring implementation used to associate object storage commands with particular physical servers such that certain guarantees of consistency, availability, and performance can be met. In other embodiments, the object storage system includes a synchronization protocol used to order operations across a distributed system. In a third set of embodiments, the object storage system includes a metadata management system. In a fourth set of embodiments, the object storage system uses a structured information synchronization system. Features from each set of embodiments can be used to improve the performance and scalability of a cloud computing object storage system. | 09-13-2012 |
20120266010 | CONVERSION OF TIMESTAMPS BETWEEN MULTIPLE ENTITIES WITHIN A COMPUTING SYSTEM - Method, apparatus and system are described for converting received timestamps to a time-recording standard recognized by the receiving computing system. Embodiments of the invention generally include receiving data from an external device that includes a timestamp. If the received data is the first communication from the external device, creating a time base used for converting subsequently received timestamps to a recognized standard. Moreover, the system updates the time base if a counter failure at the external device is detected. When the external device transmits subsequent data, the time base is added to the subsequently received timestamps to convert the subsequent timestamps to a time-recording standard recognized by the computing system. | 10-18-2012 |
20120303996 | APPARATUS FOR SYNCHRONIZING A DATA HANDOVER BETWEEN A FIRST CLOCK DOMAIN AND A SECOND CLOCK DOMAIN - Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a synchronization pulse generator, a phase information provider and a feedback path. The calculator is clocked with a clock of the first clock domain and configured to provide synchronization pulse cycle duration information describing a temporal position of a synchronization pulse at a clock of the second clock domain. The synchronization pulse generator is clocked with the clock of the second clock domain and configured to generate the synchronization pulse such that the synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information. The phase information provider is clocked with the clock of the second clock domain and configured to provide a phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain. The feedback path is configured for feeding back the phase information to the calculator. In addition, the calculator is configured to adjust the synchronization pulse cycle duration information based on the phase information. | 11-29-2012 |
20120311372 | MEMORY ACCESS CIRCUIT AND MEMORY ACCESS SYSTEM - According to one embodiment, a memory access circuit includes a PLL, a phy-clock tree, first, second, and master DLLs, and first and second PDs. The PLL generates a PLL output locked to a reference frequency. The phy-clock tree delays the PLL output and generates a reference clock signal. The first DLL corrects a clock skew between reference and system clock signals, and generates a source of the system clock signal. The second DLL corrects a clock skew between reference clock and phy-clock signals, and generates a source of the phy-clock signal. The first and second PDs detect a phase difference, and generate first and second detection signals. The master DLL counts the reference clock signal and generates a delay correction signal. The first and second DLLs determine a correction direction and a correction amount based on first and second detection and delay correction signals, respectively. | 12-06-2012 |
20130055006 | CLOSED-LOOP MULTIPHASE SLEW RATE CONTROLLER - A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules. | 02-28-2013 |
20130055007 | ESTIMATING CLOCK SKEW - The present invention relates to a method and an apparatus for estimating a clock skew. The method comprises: obtaining a basic clock skew of each clock tree in the circuit; judging whether two units are in a same clock domain; if they are in different clock domains, estimating the clock skew between units to be a larger one of basic clock skews of the clock trees corresponding to these two unit; if these two units are in the same clock domain, further judging whether they are in a same hierarchical logic block; if they are in different hierarchical logic blocks, estimating the clock skew between units to be the basic clock skew of the clock tree of these two units plus additional clock skew caused by different hierarchical logic blocks. The apparatus is corresponding to the method. With the method and apparatus, the clock skew in the circuit can be estimated more accurately, which improves the efficiency of circuit design. | 02-28-2013 |
20130117598 | GLITCHLESS PROGRAMMABLE CLOCK SHAPER - In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a falling edge of the clock input signal independent of adjustment of the rising edge. | 05-09-2013 |
20130117599 | SEMICONDUCTOR DEVICE OPERATING ACCORDING TO LATENCY VALUE - Disclosed herein is a device that includes a first register temporarily storing first information indicative of a reference latency, a second register temporarily storing second information indicative of an offset latency, a third register temporarily storing third information indicative of one of first and second operation modes, and a logic circuit configured to produce latency information in response to the first information when the third information is indicative of the first operation mode and to both of the first information and the second information when the third information is indicative of the second operation mode. | 05-09-2013 |
20130145201 | AUTOMATIC INTERNAL TRIMMING CALIBRATION METHOD TO COMPENSATE PROCESS VARIATION - A method is described for performing an automatic internal trimming operation that can compensate process variation and supply voltage variation in an integrated circuit. A reference signal is applied when the integrated circuit is in an automatic internal trimming mode, and integrated circuit timing is trimmed into a predetermined target range after applying predefined reference cycles. | 06-06-2013 |
20130173949 | HS-CAN BUS CLOCK RECOVERY USING A TRACKING OSCILLATOR CIRCUIT - A method for recovering a clock frequency of a CAN bus, the method including: receiving a data signal, wherein the data signal includes at least one state transition; detecting the state transition; and adjusting a frequency of a clocking signal generated by an oscillator circuit, wherein the frequency is adjusted when the state transition is detected and adjusting the frequency is for recovering the clock frequency of the CAN bus. | 07-04-2013 |
20130173950 | METHOD AND APPARATUS FOR COMMUNICATING TIME INFORMATION BETWEEN TIME AWARE DEVICES - According to one embodiment, an apparatus includes a first processing unit operating according to a first clock, a second processing unit operating according to a second clock running separately from the first clock, and a synchronization controller coupled to the first communication unit and the second communication unit. The synchronization controller is configured to (i) cause the first communication unit to generate a first indication of time at which the first processing unit transmits a signal to the second processing unit, according to the first clock, (ii) cause the second processing unit to generate a second indication of time at which the second processing unit receives the signal, according to the second clock, and (iii) determine an offset between the first clock and the second clock based on the first indication of time and the second indication of time. | 07-04-2013 |
20130185585 | USB BASED SYNCHRONIZATION AND TIMING SYSTEM - A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure (such as a clock carrier signal) containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; and circuitry for receiving the decoded carrier signal, for generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and for passing the software interrupt to the USB microcontroller; wherein the USB microcontroller is configured to respond to the software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal. | 07-18-2013 |
20130191679 | DUAL MODE CLOCK/DATA RECOVERY CIRCUIT - A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst. | 07-25-2013 |
20130212421 | USING PULSES TO CONTROL WORK INGRESS - Clock pulses of a variable speed clock are adjusted relative to system utilization. A load monitor periodically collects sensor measurements of resources and based on the sensor measurements, the load monitor adjusts the clock speed up or down. | 08-15-2013 |
20130219208 | METHOD OF CORRECTING A DUTY RATIO OF A DATA STROBE SIGNAL - A method of correcting a duty ratio of a data strobe signal is provided. By the method, a duty ratio of a data strobe signal output from a semiconductor memory device is detected and a duty ratio of a clock signal input to the semiconductor memory device is adjusted based on the duty ratio of the data strobe signal. | 08-22-2013 |
20130227330 | ANALYSING TIMING PATHS FOR CIRCUITS FORMED OF STANDARD CELLS - A method of performing and correcting a timing analysis performed by a data processing apparatus on a circuit formed of a plurality of cells to account for the reverse Miller effect. The timing analysis steps includes identifying cells on and in parallel with a signal path that are driven by a same signal and determining an output transition time and a delay using the characterisation data for the cell. The correcting steps includes providing further characterisation data for some of the cells; correcting the output transition time for some of the cells by increasing the output transition time by an amount dependent upon the Miller capacitance for the cell and using the correction to the output transition time to correct an input transition time for a next cell; and calculating a time taken for a data signal to travel along the signal path from the delay times. | 08-29-2013 |
20130232373 | METHOD FOR PERFORMING REAL TIME CLOCK CALIBRATION THROUGH FRAME NUMBER CALCULATION, AND ASSOCIATED APPARATUS - A method and apparatus for performing real time clock (RTC) calibration through frame number calculation are provided, where the method is applied to an electronic device. The method includes the steps of: before power failure of the electronic device occurs, obtaining an original time value from an RTC of the electronic device and storing the original time value and a frame number of a first frame into a storage unit; and after the electronic device is powered on since elimination of the power failure, obtaining a frame number of a second frame and performing at least one calculation operation according to the frame number of the second frame, the frame number of the first frame, and the original time value to determine a calibrated time value of the RTC, and updating the RTC with at least one of the calibrated time value and a derivative of the calibrated time value. | 09-05-2013 |
20130246835 | SLEEP CLOCK SLEW COMPENSATION - A method for compensating for sleep clock slew is disclosed. The method may conserve battery power. The method includes operating in a discontinuous receive mode. A measured sleep clock slew is determined. Discontinuous receive mode parameters are adjusted based on the measured sleep clock slew. Discontinuous receive mode wake-up procedures are performed. The discontinuous receive mode parameters may include a sleep time and a search time. Other aspects, embodiments, and features are also claimed and described. | 09-19-2013 |
20130254585 | CLOCK GENERATION FOR TIMING COMMUNICATIONS WITH RANKS OF MEMORY DEVICES - A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device. | 09-26-2013 |
20130283085 | BLOCK ALIGNER-BASED DEAD CYCLE DESKEW METHOD AND APPARATUS - A method and apparatus to deskew dead cycles is described using a block aligner. In one example a method includes receiving a sequence of bytes into a first buffer from each lane of a multiple lane peripheral device bus and receiving the sequence of bytes into a second buffer delayed one clock cycle from the first buffer. The method further includes providing the sequence of bytes from the first buffer to an output buffer, counting clock cycles of data as the data is received into the first and second buffers, upon reaching a predetermined count, inserting a dead cycle into the output buffer, and after inserting the dead cycle providing the sequence of bytes from the second buffer instead of the first buffer to the output buffer. | 10-24-2013 |
20130290768 | ARITHMETIC PROCESSING DEVICE, METHOD FOR CONTROLLING ARITHMETIC PROCESSING DEVICE, AND SYSTEM - An arithmetic processing device includes: a communicating unit that communicates with another arithmetic processing device; a clock controller that requests a change in the frequency of a clock signal; a sequence controller that instructs the other arithmetic processing device to change the amount of data to be transmitted by the other arithmetic processing device to the arithmetic processing device per unit time when the sequence controller is requested by the clock controller to change the frequency of the clock signal; and a control circuit that changes the amount of data to be transmitted by the communicating unit to the other arithmetic processing device per unit time when the other arithmetic processing device instructs the arithmetic processing device to change the amount of data to be transmitted by the arithmetic processing device to the other arithmetic processing device per unit time. | 10-31-2013 |
20130305079 | Memory Component that Samples Command/Address Signals in Response to Both Edges of a Clock Signal - A memory component has a signaling interface, data input/output (I/O) circuitry and command/address (CA) circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component. | 11-14-2013 |
20130326258 | Predicting Timing Violations - For predicting timing violations, a prediction module predicts a timing violation for a first instruction in a semiconductor device in response to use by the first instruction of a specified sensitized path. The prediction module further mitigates the predicted timing violation. | 12-05-2013 |
20130326259 | SYSTEM AND METHOD FOR MULTIPLE BACKPLANE TIME SYNCHRONIZATION - A system and method for synchronizing multiple backplanes within an information handling system are disclosed. An information handling system includes a first controller that may be operable to generate a time command at a predetermined time interval. A backplane including a second controller is communicatively coupled to the first controller. The second controller may be operable to receive the time command from the first controller and calculate a skew for the time command based at least on a location of the backplane. The second controller may further be operable to adjust a time domain of the backplane based on the calculated skew for the time command to synchronize the backplane. | 12-05-2013 |
20140068315 | METHOD AND SYSTEM FOR CLOCK OFFSET AND SKEW ESTIMATION - This invention relates to methods and devices for clock offset and skew estimation. The invention has particular application in the alignment of slave clocks to a master clock. In embodiments of the invention, the slave clock employs an independent free running clock and a recursive estimation technique to estimate the clock offset and clock skew between the slave and master clocks. The slave can then use the offset and skew to correct the free running clock to reflect an accurate image of the master clock. | 03-06-2014 |
20140082404 | EMBEDDED MULTIMEDIA CARD (eMMC), eMMC SYSTEM, AND METHODS OF OPERATION - An embedded multimedia card (eMMC) communicating with a host includes; a latch circuit that receives and latches a data signal according to either a first edge or a second edge of a clock to thereby generate a latched data signal, and a start bit detector that detects in the latched data signal a start bit and provides a valid data signal from a portion of the latched data signal following the start bit. | 03-20-2014 |
20140122916 | REDUCING THE OVERHEAD ASSOCIATED WITH FREQUENCY CHANGES IN PROCESSORS - In many cases, processors may change frequency sufficiently often to result in significant performance and power consumption losses. These performance and power consumption losses may be mitigated by changing the frequency using a squashing technique rather than using a phase locked loop technique. The squashing technique involves simply eliminated clock pulses to reduce the frequency. This can be done more quickly, resulting in less overhead in some cases. | 05-01-2014 |
20140129869 | Adjustable Byte Lane Offset For Memory Module to Reduce Skew - Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors. | 05-08-2014 |
20140143585 | METHOD AND APPARATUS TO ELIMINATE FREQUENCY HOLES IN A MEMORY I/O SYSTEM - Various methods and apparatus for managing signals between a processor and a memory device are disclosed. In one aspect, a method of managing signals between a processor and a memory device wherein the processor and the memory device are operatively coupled by a data signal path and a clock signal path is provided. The method includes setting the skew between the data signal path and the clock signal path away from a spectral peak of a phase jitter transfer function. | 05-22-2014 |
20140149780 | SPECULATIVE PERIODIC SYNCHRONIZER - A method and a system are provided for speculative periodic synchronization. A phase value representing a measured phase of the second clock signal relative to the first clock signal measured at least one cycle earlier is received. A period value representing a period of the second clock signal relative to the first clock signal measured at least one cycle earlier is also received. A reduced timing margin is determined based on the phase value and the period value. A speculatively synchronized output signal is generated based on the reduced timing margin. | 05-29-2014 |
20140201561 | CLOCK SKEW ANALYSIS AND OPTIMIZATION - A method for adjusting clock skew in a network is disclosed. A model is fit to a first clock input signal received at a first receiver of the network and to a second clock input signal received at a second receiver of the network to obtain a fitted model. A first response signal is simulated using the fitted model and the first clock input signal and a second response signal is simulated using the fitted model and the second clock input signal. A time difference is determined between the simulated first response signal and the simulated second response signal. A parameter of at least one of the network clock network, the first receiver and the second receiver is altered to adjust the determined time difference. | 07-17-2014 |
20140223221 | APPROACH TO CLOCK FREQUENCY MODULATION OF A FIXED FREQUENCY CLOCK SOURCE - A modulated clock device is provided that includes an update device for updating a phase of the modulated clock device. In one example, the update device includes an update phase multiplexer coupled to an output phase multiplexer of an output clock generator and configured to receive an input clock signal and one or more phases of the input clock signal; an output phase fractional counter coupled to the update phase multiplexer and configured to receive an update clock signal and to generate an output phase; and an update phase device coupled to the output phase fractional counter and to the update phase multiplexer. The output phase fractional counter is further configured to send the output phase to the output phase multiplexer and to the update phase device. The update phase device is configured to generate an update phase and to send the update phase to the update phase multiplexer. | 08-07-2014 |
20140258767 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period. | 09-11-2014 |
20140281660 | INFORMATION PROCESSING DEVICE, TIME ADJUSTING METHOD, AND TIME ADJUSTING PROGRAM - One embodiment provides an information processing device which includes a clock unit, a file access unit and a setting unit. The clock unit is configured to count up an elapsed time from a prescribed reference time if an origin time has not been set, and to count up an elapsed time from the origin time if the origin time has been set. The file access unit is configured to access a file which has time information given by an external device or the information processing device. The file is stored in a storage device. The setting unit is configured to acquire the time information from the file via the file access unit, and to set the acquired time information into the clock unit as the origin time. | 09-18-2014 |
20140325252 | Generating Interface Adjustment Signals in a Device-To-Device Interconnection System - Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits. | 10-30-2014 |
20150019899 | MEMORY SYSTEM WITH IMPROVED BUS TIMING CALIBRATION - A method includes communicating between a memory controller and multiple memory devices over an interface that includes at least a control signal and an information signal. For each memory device, a respective individual skew parameter, which is indicative of a timing misalignment between the control signal and the information signal when communicating with that memory device, is produced. The respective individual skew parameter is stored coupled to each memory device. The timing misalignment is corrected at the memory device using the stored individual timing skew. | 01-15-2015 |
20150046743 | SEMICONDUCTOR DEVICE AND SYSTEM INCLUDING THE SAME - A semiconductor device includes a plurality of data output circuits suitable for outputting data to outside; an address training driver suitable for generating a plurality of address training data and a control signal; a plurality of data lines suitable for transferring the address training data to the data output circuits; and a self-correction circuit suitable for correcting a delay time of the address training data that reaches the data output circuits from the address training driver through the plurality of data lines, and correcting skew of the data that is outputted from the data output circuits. | 02-12-2015 |
20150100815 | Method and Apparatus for Aligning Signals - A method and corresponding apparatus for aligning a data signal with a corresponding clock signal include oversampling the data signal based on the corresponding clock signal and generating corresponding data samples. An indication of skew between the data signal and the corresponding clock signal is detected based on data samples. A variable delay line coupled to the data signal is then adjusted based on the indication of skew detected. According to at least one example implementation, the data signal is oversampled based on the corresponding clock signal and multiple time-shifted versions of the corresponding clock signal. At least one signal of the corresponding clock signal and the multiple time-shifted versions of the corresponding clock signal is employed in sampling the data signal at a potential transition edge of the data signal. | 04-09-2015 |
20150135000 | INFORMATION PROCESSING APPARATUS CAPABLE OF CORRECTING TIME-OF-DAY MANAGEMENT FUNCTION, CONTROL METHOD THEREFOR, AND STORAGE MEDIUM - An information processing apparatus that is capable of correcting a time-of-day management function in the information processing apparatus even in an environment where the time of day cannot be properly measured in the information processing apparatus in a power-saving mode. A first time of day is obtained from an external apparatus on a network. A second time of day is identified based on the number of input CPU clocks per prescribed time period. The number of input CPU clocks per prescribed time period is corrected based on the first time of day and the second time of day. | 05-14-2015 |
20150346760 | DISTRIBUTION DEVICE, DISTRIBUTION SYSTEM, AND DISTRIBUTION METHOD - Provided is distribution device that distributes time information to at least one sensor device, the distribution device including a storage unit that stores a time adjustment amount to be used for adjusting a local time, a calculation unit that calculates a time difference between a reference time and the local time, an adjustment unit that calculates an adjusted local time by adjusting the local time by an amount equal to or less than the time adjustment amount, when the time difference is greater than the time adjustment amount, and a distribution unit that distributes time information of the adjusted local time to the sensor device. | 12-03-2015 |
20150355671 | CLOCK SWALLOWING DEVICE FOR REDUCING VOLTAGE NOISE - Systems and methods for controlling a frequency of a clock signal by selectively swallowing pulses in the clock signal are described herein. In one embodiment, a method for adjusting a frequency of a clock signal comprises receiving the clock signal, and swallowing pulses in the clock signal according to a repeating clock-swallowing pattern, wherein the pattern is defined by a sequence of numbers. | 12-10-2015 |
20160011625 | DIGITAL FILTER WITH A PIPELINE STRUCTURE, AND A CORRESPONDING DEVICE | 01-14-2016 |
20160116936 | DATA INTERFACE AND DATA TRANSMISSION METHOD - A data interface includes a first sampler sampling a first bitset and a second sampler sampling a second bitset. The first bitset includes a first bit which is included in a first image data and a third bit which is included in a second image, and the second bitset includes a second bit which is included in the first image data and is a higher-order bit than the first bit and a fourth bit which is included in the second image data and is a higher-order bit than the third bit. The data interface further includes a clock generator configured to adjust a sampling timing of the first and second bitsets based on a multi-phase clock, and a clock data recovery (CDR) circuit shared by the first sampler, the second sampler and configured to output the multi-phase clock to the clock generator. | 04-28-2016 |
20160139623 | RESISTANCE CORRECTION CIRCUIT, RESISTANCE CORRECTION METHOD, AND SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor. | 05-19-2016 |
20160161977 | DRIFT DETECTION IN TIMING SIGNAL FORWARDED FROM MEMORY CONTROLLER TO MEMORY DEVICE - A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift. | 06-09-2016 |
20160170437 | METHOD AND DEVICES FOR CLOCK SYNCHRONIZATION OVER LINKS WITH ASYMMETRIC TRANSMISSION RATES | 06-16-2016 |
20160170440 | METHOD AND DEVICES FOR TIME TRANSFER USING END-TO-END TRANSPARENT CLOCKS | 06-16-2016 |
20160195894 | DRIFT COMPENSATION FOR A REAL TIME CLOCK CIRCUIT | 07-07-2016 |
20160378132 | LIGHT-WEIGHT ON-CHIP SIGNAL MONITOR WITH INTEGRATED MEMORY MANAGEMENT AND DATA COLLECTION - Embodiments of a device and method to automatically acquire signal quality metrics in a digital communication system are disclosed. The device may include acquisition means to sample the likelihood of a digital communication signal passing through a grid of time and amplitude regions, and storage means by which such likelihood measurements may be accumulated in a computer memory array for analysis. A state machine may execute a method that controls both the acquisition means and the storage means, requiring minimal intervention from supervisory systems. | 12-29-2016 |