Class / Patent application number | Description | Number of patent applications / Date published |
711220000 | Combining two or more values to create address | 8 |
20080301400 | Method and Arrangement for Efficiently Accessing Matrix Elements in a Memory - The invention relates to a method for accessing matrix elements, wherein accesses to two matrix elements that are adjacent in a row or in a column of a matrix and that are each specified by a respective relative address (a | 12-04-2008 |
20090144520 | METHOD AND APPARATUS FOR SELECTING A DATA ITEM - A method of selecting a data item from a memory within a first device, the method comprising the steps of evaluating within the first device a function of an input argument so as to form an output value, using the output value to select a data item from the memory and transmitting the selected data item to a second device. | 06-04-2009 |
20100064114 | STACKED DEVICE IDENTIFICATION ASSIGNMENT - Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die. | 03-11-2010 |
20110314252 | REDUCED HARDWARE MULTIPLIER - The invention is directed to a multiplication apparatus or arrangement comprising: an address unit being adapted to receive address words from an external system, which address words have a first part comprising a first number X and a second part comprising a second number Y; a memory area comprising M×M memory cells arranged to be addressed by said address words, wherein a cell addressed by a particular address word is provided with the product P of the first and second number X and Y; and an output unit arranged to provide products P from the memory area to an external system. The invention is characterized in that the cells in the memory area addressed by address words wherein Y12-22-2011 | |
20110314253 | SYSTEM, DATA STRUCTURE, AND METHOD FOR TRANSPOSING MULTI-DIMENSIONAL DATA TO SWITCH BETWEEN VERTICAL AND HORIZONTAL FILTERS - A system, processor, and method for filtering multi-dimensional data, for example, image data. A processor may receive an instruction to execute a horizontal filter by combining multi-dimensional data values horizontally aligned in a single row of a first data structure. A second data structure may include a plurality of individually addressable internal memory units. A load unit may load the horizontally aligned values in a transposed orientation for storage as vertically aligned values in a single column in the second data structure in the individually addressable memory units. Each transposed value in the single column may be separately stored in a different respective one of the individually addressable memory units. The processor may independently manipulate and combine each transposed value designated for combination by the horizontal filter by individually accessing the separate memory units. | 12-22-2011 |
20120166760 | HIGH SPEED COUNTER DESIGN - Techniques for incrementing counters in an efficient manner. In one set of embodiments, counter logic circuits are provided that can operate at higher frequencies than existing counter logic circuits, while being capable of being implemented in currently available field programmable gate arrays (FPGAs) or fabricated using currently available process technologies. The counter logic circuits of the present invention may be used to increment statistics counters in network devices that support line speeds of 40 Gbps, 100 Gbps, and greater. | 06-28-2012 |
20120233440 | ADDRESS GENERATION IN A DATA PROCESSING APPARATUS - A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided. | 09-13-2012 |
20140032876 | SYSTEM & METHOD FOR STORING A SPARSE MATRIX - A system and method for storing and retrieving a sparse matrix from memory of a computing device while minimizing the amount of data stored and costly jumps in memory. The computing device may be an FPGA having memory and processing elements. The method comprises storing non-zero data elements of the matrix in a data array and storing their corresponding column address values in a column index array. To read this stored data from memory, each preceding value of the column index array may be compared with each current value of the column index array to determine if the data array value corresponding with the current column index array value belongs on the next row of the matrix. The method may include pre-ordering the matrix with zero-pad placeholders or creating a row increment pointer array which typically stores fewer values than the number of rows in the matrix. | 01-30-2014 |