Class / Patent application number | Description | Number of patent applications / Date published |
710307000 | Variable or multiple bus width | 34 |
20080222340 | Bus Interface Controller For Cost-Effective HIgh Performance Graphics System With Two or More Graphics Processing Units - A bus interface controller manages a set of serial data lanes. The bus interface controller supports operating a subset of the serial data lanes as a private bus. | 09-11-2008 |
20080294831 | METHOD FOR LINK BANDWIDTH MANAGEMENT - A method for link bandwidth management between two devices in communication through a bus in a computer system. Whether a change condition of the bus having a link is activated is monitored. Change a bandwidth of the bus from a first bandwidth with a first width and a first speed to a target bandwidth with a second width and the first speed or with the first width and a second speed when the change condition of the bus is activated. The bus will operate at the target bandwidth without disabling the link or powering down the computer system if subsequent failure speed management and unreliable speed management have passed. | 11-27-2008 |
20080307145 | Interconnect and a Method for Designing an Interconnect - A method for designing an interconnect, the method includes determining an amount of input ports, an amount of output ports; characterized by selecting multiple modular components such as to form an interconnect, whereas each modular component is selected from a group of modular components that are verified by parametric verification environment. An interconnect that includes multiple input ports and multiple output ports, characterized by including multiple modular components; whereas each modular component is adapted to support a certain point-to-point protocol; whereas at least one modular component includes a sampling circuit and a bypass circuit, whereas the sampling circuit is selectively bypassed by the bypass circuit. | 12-11-2008 |
20090019207 | DUAL BUS MATRIX ARCHITECTURE FOR MICRO-CONTROLLERS - A dual bus matrix architecture comprising: a first interconnect matrix connected to a plurality of high performance peripherals and having a plurality of master ports and a plurality of slave ports; a second interconnect matrix connected to a plurality of limited bandwidth peripherals and having a plurality of master ports and a plurality of slave ports; and a shared multiport controller connected to one (or more) of the slave ports of the first interconnect matrix and to one (or more) of the master ports of the second interconnect matrix, wherein the shared multiport controller controls accesses to the high performance peripherals and the limited bandwidth peripherals by directing accesses to the high performance peripherals through the first interconnect matrix and accesses to the limited bandwidth peripherals through the second interconnect matrix. | 01-15-2009 |
20090119438 | Data Processing Device Adaptable to Variable External Memory Size and Endianess - A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data. The data processing device (D) also comprises a configuration means (CM) coupled to the embedded processor (EP) and to the external memory interface (EMI) and arranged to deduce from at least one part of 8 bits of this N-bit data word (C), read by the external memory interface at the chosen address of the external memory (EM), the size and the Endian form of storage of the external memory, and to set the width of the external memory interface (EMI) according to the deduced external memory size and the data processing mode of the embedded processor (EP) according to the deduced Endian form of storage. | 05-07-2009 |
20090132748 | MULTIPLE CARRIER SIGNALS ON A LEGACY BUS - A device (e.g., an ultra-wideband device) is added to a system including a legacy wired bus (e.g., a MIL-STD 1553 bus). The legacy bus has a legacy bus signal with a center frequency, and the device has a carrier signal with a frequency that is substantially higher than the center frequency. Adding the device to the system includes coupling the device to the bus, and adding equipment for superimposing the device carrier signal on the legacy bus signal. | 05-21-2009 |
20090198857 | SELECTIVE BROADCASTING OF DATA IN SERIES CONNECTED DEVICES - A method and system for the selective broadcasting of commands to a subset of a plurality of devices connected in series to a memory controller, where each of the plurality of devices has a unique identification number (ID). The memory controller designates the subset of devices to execute the command, excluding the non-selected devices from executing the command. The memory controller encodes the ID numbers of the designated devices into a single coded address, and sends the command along with the coded address in a packet to the series connected devices. Each device receives the packet in a serial bitstream and decodes the coded address using its ID number in order to determine whether it is selected or not. If the device is selected, the command is executed. Otherwise, the packet is forwarded without executing the command. | 08-06-2009 |
20090198858 | Semiconductor memory device and operation method therefor - Disclosed herein is a semiconductor memory device, including: a memory array section wherein a memory array which is accessed with a predetermined data bus width is formed; an interface section configured to carry out interfacing between an external apparatus and the memory array section; and a converter having a conversion function of data and a control signal between the interface section and the memory array section and having conversion functions corresponding to specifications of the memory array; the interface section including a plurality of interface modules individually corresponding to different memory types and selectively adapted for the interfacing process between the external apparatus and the memory array section; the converter having a data width variation function of issuing a command and an address for the memory array based on information of access data of the memory array and outputting the access data after varying or without varying the data width. | 08-06-2009 |
20100017553 | INTERFACE BETWEEN A TWIN-WIRE BUS AND A SINGLE-WIRE BUS - A method and a device for converting a first bus including at least a data wire and a clock wire into a single-wire bus, wherein a data bit of the first bus is converted on half a period of the clock signal for transmission over the second bus, a waiting pattern being placed on the second bus during the other half-period. | 01-21-2010 |
20100064089 | BUS WIDTH NEGOTIATION - There is provided a method and apparatus for bus negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable data storage device. If the first bond pad indicates the host is configured to communicate with a fixed data storage device, then the method additionally includes determining the configuration of a second bond pad. The second bond pad indicates the supported bus width of the fixed data storage device. | 03-11-2010 |
20100153609 | NON-SYSTEM BUS WIDTH DATA TRANSFER EXECUTABLE AT A NON-ALIGNED SYSTEM BUS ADDRESS - Disclosed are a method and apparatus of non-system bus width data transfer executable at a non-aligned system bus address. In one embodiment, a method of a controller is described. The method includes applying a FIFO buffer having a buffer width (e.g., determined using a transfer algorithm) that is wider than that of a system bus width. A system bus that permits transfer of data amounts which are non-integer multiples of a width of the system bus is used. The system bus is designed such that it supports any non-aligned system bus address. Data is transferred between devices coupled to the system bus. | 06-17-2010 |
20100332714 | INTEGRATED CIRCUIT SYSTEM, AND DATA READOUT METHOD - An integrated circuit system includes: a first integrated circuit that is connected with a first data bus having first bus width and requires first time to perform data transmission and reception once; a second integrated circuit that is connected with a second data bus having second bus width larger than the first bus width in bit width and requires second time longer than the first time to perform data transmission and reception once; and a relay circuit that is connected with the first data bus and the second data bus and transmits and receives data to and from the first integrated circuit and the second integrated circuit respectively via the buses. | 12-30-2010 |
20110119425 | DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM - The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module. | 05-19-2011 |
20110258360 | Methods and Systems to Accomplish Variable Width Data Input - Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes. | 10-20-2011 |
20120278521 | EMBEDDED SYSTEM - An embedded system includes an ARM processor and a number of b-bit peripheral processors connected to the ARM processor through a converting chip. The ARM processor includes pins P | 11-01-2012 |
20130019044 | SEMICONDUCTOR DEVICEAANM KAIWA; NakabaAACI TokyoAACO JPAAGP KAIWA; Nakaba Tokyo JPAANM MATSUI; YoshinoriAACI TokyoAACO JPAAGP MATSUI; Yoshinori Tokyo JP - A semiconductor memory device includes a memory cell array section including a plurality of memory cell arrays, a peripheral circuit section, and an internal bus | 01-17-2013 |
20130091315 | HIGH SPEED MEMORY CHIP MODULE AND ELECTRONICS SYSTEM DEVICE WITH A HIGH SPEED MEMORY CHIP MODULE - A high speed memory chip module includes a type of memory cell array group and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ICs), and each of the memory cell array ICs has a data bus and at least one memory cell array, and corresponds to first metal-oxide-semiconductor field-effect transistor (MOSFET) gate length corresponding to a first MOSFET process. The logic unit accesses the type of memory cell array group through a first transmission bus, where bus width of the first transmission bus is wider than bus width of the data bus of each of the memory cell array ICs. Corresponding to a second MOSFET process, the logic unit has a second MOSFET gate length which is shorter than the first MOSFET gate length. | 04-11-2013 |
20130111099 | PROCESSOR WITH PROGRAMMABLE VIRTUAL PORTS | 05-02-2013 |
20130159589 | BUS CONTROL DEVICE AND BUS CONTROL METHOD - A bus control device includes a storing unit that stores therein a threshold related to bus width of a bus that is a transfer path for data, a comparing unit that compares, when the bus width is reduced, the reduced bus width with the threshold stored in the storing unit, and a selecting unit that selects, on the basis of the result of the comparison performed by the comparing unit, an interrupt operation performed on a processor that performs a process related to a reduction of the bus width. | 06-20-2013 |
20130275646 | BUS CIRCUIT AND SEMICONDUCTOR DEVICE - A bus circuit which transfers data of a plurality of bits output from one module to another module, includes: a data bus; a division circuit configured to divide the data into a plurality of pieces of divided data including a plurality of bits in a number equal to or less than half a bit width of the data bus; an inverter circuit configured to generate a plurality of pieces of inverted divided data by inverting each of the plurality of pieces of divided data; an output circuit configured to output each of the plurality of pieces of divided data and each of the pieces of inverted divided data corresponding to each of the pieces of divided data as a data pair; and a coupling circuit configured to extract and couple the plurality of pieces of divided data from the data pair received from the data bus. | 10-17-2013 |
20140006673 | UTILIZATION-AWARE LOW-OVERHEAD LINK-WIDTH MODULATION FOR POWER REDUCTION IN INTERCONNECTS | 01-02-2014 |
20140115221 | Processor-Based System Hybrid Ring Bus Interconnects, and Related Devices, Processor-Based Systems, and Methods - Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements. This provides conservation of power when full bandwidth requirements on the processor-based system hybrid ring bus interconnect are not required. | 04-24-2014 |
20140244887 | DATA PROCESSING APPARATUS AND CONTROL METHOD - A connected access request is generated by connecting access requests that are issued within a period of carrying out connections from when a initially received leading access request is issued. At this time the period of carrying out connections is set so that access to data corresponding to the connected access request is completed within a time from when the leading access request is issued until other access to a memory device is performed. | 08-28-2014 |
20140258581 | Method and Device for Serial Data Transmission Having a Flexible Message Size and a Variable bit Length - A method for serial data transfer in a bus system having at least two bus subscribers that exchange messages via the bus, the transmitted messages having a logical structure according to CAN standard ISO 11898-1, the logical structure encompassing a start-of-frame bit, arbitration field, control field, data field, CRC field, acknowledge field, and end-of-frame sequence, the control field encompassing a data length code having an information item regarding the data field length. When a first marker (EDL) is present, the control field of the messages, divergently from the CAN standard ISO 11898-1, encompasses more than six bits; when the first marker (EDL) is present, the control field of the message is expanded to include at least one further bit (ESI); and the further bit (ESI) or one of the further bits causes an information item regarding the “error passive” state of the bus subscriber to be integrated into transmitted messages. | 09-11-2014 |
20140258582 | SEMICONDUCTOR DEVICE WITH VIAS ON A BRIDGE CONNECTING TWO BUSES - A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses. | 09-11-2014 |
20140289440 | SYSTEMS AND METHODS INVOLVING DATA BUS INVERSION MEMORY CIRCUITRY, CONFIGURATION AND/OR OPERATION - Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, and circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, memory devices herein may store and process the DBI bit on an internal data bus as a regular data bit. | 09-25-2014 |
20150032931 | Synchronous Bus Width Adaptation - A system includes a first processing component, a second processing component, and an adapted bus linking the first and second processing components. The adapted bus may account for a circuit characteristic or on-chip variation in the system. For example, the bus may be adapted to include a wider data width because of an effect of the on-chip variation that limits performance of the bus at a lower data width. The bus may include a widened data width for a portion of the bus. In that regard, the bus may include a bus expander and a bus narrower for adjusting the data width of the bus. | 01-29-2015 |
20150074314 | MEMORY, MEMORY SYSTEM AND MEMORY CONTROL METHOD - A memory includes a buffer which retains data, a band conversion unit converts a band of an internal data bus that is used for data transfer between the band conversion unit and the buffer which retains data into a band wider than that of an external data bus that is used for data transfer between the band conversion unit and a memory controller, and an access control unit controls access to a memory cell using the buffer, during a wait time occurring in the internal data bus due to a difference between the band of the internal data bus and the band of the external data bus. | 03-12-2015 |
20150089112 | SYSTEM AND METHOD FOR CONSERVING MEMORY POWER USING DYNAMIC MEMORY I/O RESIZING - Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus. | 03-26-2015 |
20150293870 | SYSTEMS AND METHODS FOR FREQUENCY CONTROL ON A BUS THROUGH SUPERPOSITION - Systems and methods for frequency control on a bus through superposition are disclosed. In one embodiment, instead of adding pins or increasing the operating frequency of the bus, three signals are placed on lines within the bus using superposition. In this fashion, three bits may be sent over two conductors, effectively obviating the need for an additional pin and effectively increasing the frequency of bit transmission without having to increase the clock speed. | 10-15-2015 |
20150317277 | COMPUTER ARCHITECTURE HAVING SELECTABLE, PARALLEL AND SERIAL COMMUNICATION CHANNELS BETWEEN PROCESSORS AND MEMORY - A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application. | 11-05-2015 |
20160170918 | FAULT TOLERANT LINK WIDTH MAXIMIZATION IN A DATA BUS | 06-16-2016 |
20160196231 | SYSTEM AND METHOD FOR BUS BANDWIDTH MANAGEMENT IN A SYSTEM ON A CHIP | 07-07-2016 |
20160378711 | HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER - A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link. | 12-29-2016 |