Class / Patent application number | Description | Number of patent applications / Date published |
708524000 | Multiple parallel operations | 9 |
20090024684 | Method for Controlling Rounding Modes in Single Instruction Multiple Data (SIMD) Floating-Point Units - A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively. | 01-22-2009 |
20090049113 | Method and Apparatus for Implementing a Multiple Operand Vector Floating Point Summation to Scalar Function - Embodiments of the invention provide methods and apparatus for executing a multiple operand instruction. Executing the multiple operand instruction comprises computing an arithmetic result of a pair of operands in each processing lane of a vector unit. The arithmetic results generated in each processing lane of the vector unit may be transferred to a dot product unit. The dot product unit may compute an arithmetic result using the arithmetic result computed by each processing lane of the vector unit to generate an arithmetic result of more than two operands. | 02-19-2009 |
20090271464 | ARITHMETIC OR LOGICAL OPERATION TREE COMPUTATION - A method of computing at least a first and a second tree of arithmetic or logical operations on a microprocessor comprising at least n parallel processing elements. The method comprises: a) executing (in | 10-29-2009 |
20090292757 | Method and apparatus for zero prediction - A zero prediction method and apparatus for use in a reduced instruction set computer. The zero predictor | 11-26-2009 |
20100325186 | Processing with Compact Arithmetic Processing Element - A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic). | 12-23-2010 |
20120221618 | ENCRYPTION METHOD COMPRISING AN EXPONENTIATION OPERATION - A method and a device protected against hidden channel attacks includes a calculation of the result of the exponentiation of a data m by an exponent d. The method and the device are configured to execute only multiplications of identical large variables, by breaking down any multiplication of different large variables x, y into a combination of multiplications of identical large variables. | 08-30-2012 |
20120331028 | PROCESSOR FOR PERFORMING MULTIPLY-ADD OPERATIONS ON PACKED DATA - A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data. | 12-27-2012 |
20130031153 | Processing with Compact Arithmetic Processing Element - A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic). | 01-31-2013 |
20140095571 | Processing with Compact Arithmetic Processing Element - A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic). | 04-03-2014 |