Class / Patent application number | Description | Number of patent applications / Date published |
708420000 | Convolution | 6 |
20080263118 | System for convolution calculation with multiple computer processors - A process for loading a signal data values and convolution filter coefficient values into a target processor (c | 10-23-2008 |
20090083355 | Convolution integral calculation apparatus - A convolution integrator that can be used favorably to prepare, at high speed, a computer generated hologram that can reproduce a reproduction image formed by reproduction points at various distances and differing in initial phase is provided. A plurality of element processors PE are practically cascade-connected. Each element processor PE includes: a constant generator | 03-26-2009 |
20120036173 | Systems and Methods for Sequence Detection in Data Processing - Various embodiments of the present invention provide systems and methods for sequence detection. As an example, a method for data detection is disclosed that includes: receiving a series of data samples at a detector circuit; multiplying a portion of the series of data samples by a first correlator value corresponding to a first binary transition to yield a first value; multiplying the portion of the series of data samples by a second correlator value corresponding to a second binary transition to yield a second value; adding the first value to a prior state value to yield a first interim value; adding the second value to the prior state value to yield a second interim value; and selecting the larger of the first interim value and the second interim value to yield a surviving interim value. | 02-09-2012 |
20130191431 | EFFICIENT FIR FILTERS - A processor for calculating a convolution of a first input sequence of numbers with a second input sequence of numbers to generate an output sequence is provided. The processor includes multipliers, each multiplying two real numbers to generate an output; multiplexers to direct the numbers in the first and second input sequences or parts of the numbers to the multipliers; and control circuitry to control the multiplexers to direct the first and second input sequences of numbers to the multipliers dependent on whether the numbers are complex or real. An accumulator adds partial products from multiplications performed by the multipliers to calculate the convolution. | 07-25-2013 |
20140317163 | Vector Processor Having Instruction Set With Sliding Window Non-Linear Convolutional Function - A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that performs a non-linear convolution function for a plurality of input delayed signal samples. In response to the software instruction for the non-linear convolution function, the processor generates a weighted sum of two or more of the input delayed signal samples, wherein the weighted sum comprises a plurality of variable coefficients defined as a sum of one or more non-linear functions of a magnitude of the input delayed signal samples; and repeats the generating step for at least one time-shifted version of the input delayed signal samples to compute a plurality of consecutive outputs. The software instruction for the non-linear convolution function is optionally part of an instruction set of the processor. The non-linear convolution function can model a non-linear system with memory, such as a power amplifier model and/or a digital pre-distortion function. | 10-23-2014 |
20160062947 | PERFORMING MULTI-CONVOLUTION OPERATIONS IN A PARALLEL PROCESSING SYSTEM - In one embodiment of the present invention a convolution engine configures a parallel processing pipeline to perform multi-convolution operations. More specifically, the convolution engine configures the parallel processing pipeline to independently generate and process individual image tiles. In operation, for each image tile, the pipeline calculates source locations included in an input image batch. Notably, the source locations reflect the contribution of the image tile to an output tile of an output matrix—the result of the multi-convolution operation. Subsequently, the pipeline copies data from the source locations to the image tile. Similarly, the pipeline copies data from a filter stack to a filter tile. The pipeline then performs matrix multiplication operations between the image tile and the filter tile to generate data included in the corresponding output tile. To optimize both on-chip memory usage and execution time, the pipeline creates each image tile in on-chip memory as-needed. | 03-03-2016 |