# Shifting

## Subclass of:

## 708 - Electrical computers: arithmetic processing and calculating

## 708100000 - ELECTRICAL DIGITAL CALCULATING COMPUTER

## 708200000 - Particular function performed

### Patent class list (only not empty are listed)

#### Deeper subclasses:

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Document | Title | Date |
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20160085510 | METHOD AND APPARATUS FOR PERFORMING RAY-NODE INTERSECTION TEST - A method and apparatus to perform a ray-node intersection test are provided. The method includes receiving an input representing coordinates of a bounding box and an origin coordinate of a ray as fixed-point numbers, obtaining difference values between the input coordinates of the bounding box and the origin coordinate, and obtaining multiplication values between the obtained difference values and a reciprocal number of a direction vector of the ray, where the reciprocal number is a floating-point number. | 03-24-2016 |

20090292750 | METHODS AND APPARATUS FOR AUTOMATIC ACCURACY- SUSTAINING SCALING OF BLOCK-FLOATING-POINT OPERANDS - A computer-implemented method performs an operation on a set of at least one BFP operands to generate a BFP result. The method is designed to reduce the risks of overflow and loss of accuracy attributable to the operation. The method performs an analysis to determine respective shift values for each of the operands and the result. The method calculates result mantissas by shifting the stored bit patterns representing the corresponding operand mantissa values by their respective associated shift values determined in the analysis step, performing the operation on shifted operand mantissas to generate preliminary result mantissa, and shifting the preliminary result mantissas by a number of bits determined in the analysis step. | 11-26-2009 |

20160085511 | ARITHMETIC PROCESSING METHOD AND ARITHMETIC PROCESSOR - An arithmetic processing method is provided using a binary fixed-point arithmetic processing circuit to carry out an operation of multiplicatively dividing a dividend by a divisor. The method comprises shifting the divisor by a specific number of bits when the absolute value of the divisor is within a specific range, and holding the divisor without shifting the divisor when the absolute value of the divisor is out of the specific range, acquiring an initial value of approximation calculation for the divisor that is shifted or held without being shifted, calculating a reciprocal of the divisor by performing asymptotic approximation of the acquired initial value more than once, and calculating a product of the calculated reciprocal and the dividend, and shifting the calculated product by the specific number of bits when the divisor is shifted. | 03-24-2016 |

20130060828 | FLOATING POINT MULTIPLY ACCUMULATOR MULTI-PRECISION MANTISSA ALIGNER - A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. | 03-07-2013 |

20160132294 | ADDER DECODER - The present disclosure relates to an add and decode hardware logic circuit for adding two n bit inputs, A and B. A series of n logic stages are each configured to perform a first operation of propagating a result of a preceding stage on the condition that the sum of A[m] and B[m] is equal to 0, wherein 0<=m | 05-12-2016 |

20120254271 | ARITHMETIC OPERATION CIRCUIT AND METHOD OF CONVERTING BINARY NUMBER - An arithmetic operation circuit includes: an extractor circuit that extracts one or a plurality of bits consecutive from a most significant bit or from a least significant bit of a binary number; a sum register that stores an X-adic sum, where X is an integer more than two; and an update circuit that updates the stored X-adic sum with a value obtained by adding a first X-adic number to be cyclically multiplied by a certain coefficient to the X-adic sum in accordance with the extracted one or plurality of bits. | 10-04-2012 |

20130204915 | RANDOM NUMBER GENERATING METHOD - A random number generating method includes sending a signal source for outputting a data sequence and randomly retrieving a segment of data having an operation length as a seed; converting the seed into a first operation value, determining whether a difference between the first operation value and a second operation value is larger than a threshold value, and determining whether a total number of times the first operation value has been inputted into the operation value processing step is larger than a predetermined value. The first operation value is reset by a reset algorithm; otherwise the sample selection step is re-performed. The operation values are converted into a random number. A total number of bits of the random number is calculated. The operation value setting step is performed or a latest random number having a length equal to the operation length is set as the seed. | 08-08-2013 |

20110264720 | CRYPTOGRAPHIC SYSTEM, METHOD AND MULTIPLIER - In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic. | 10-27-2011 |

20160085507 | METHOD AND APPARATUS FOR CONTROLLING RANGE OF REPRESENTABLE NUMBERS - Provided are a method of controlling a range of representable numbers includes receiving a floating point value represented by an exponent and a mantissa, each represented by a predetermined numbers of bits, determining a bit configuration of the exponent and the mantissa of the floating point value based on a value of a most significant bit of the exponent of the floating point value, and determining a constant required for calculation of the floating point value according to the determined bit configuration of the exponent, and an apparatus for providing such a method. | 03-24-2016 |

20110040816 | Negative two's complement processor for windowing in harmonic analysis - The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors for calculating harmonic analysis using a discrete time-frequency transform. In the negative two's complement processor a n-bit number, A, has a sign bit, a | 02-17-2011 |

20110208794 | COMPUTING HALF INSTRUCTIONS OF FLOATING POINT NUMBERS WITHOUT EARLY ADJUSTMENT OF THE SOURCE OPERANDS - Apparatus and methods are disclosed for a floating point adder having half-adder capability that does not have the overhead of determining half-adder conditions prior to starting the SED, LED, and EXP datapaths. | 08-25-2011 |

20100146023 | SHIFTER WITH ALL-ONE AND ALL-ZERO DETECTION - A shifter that includes a plurality of shift stages positioned within the shifter, and receiving and shifting input data to generate a shifted result, and a detection circuit coupled at an input of a final shift stage of the plurality of shifters, in a final stage within the shifter. The detection circuit receives a partially shifted vector at the input of the final shift stage along with a predetermined shift amount, and performing an all-one or all-zero detection operation using a portion of the partially shifted vector and the predetermined shift amount, in parallel, to a shifting operation performed by the final shift stage to generate the shifted result. | 06-10-2010 |

20140188963 | EFFICIENT CORRECTION OF NORMALIZER SHIFT AMOUNT ERRORS IN FUSED MULTIPLY ADD OPERATIONS - A method for correcting a shift error in a fused multiply add operation. The method comprises adjusting a normalized floating-point number before performing a shift error correction to produce an adjusted normalized floating-point number, and correcting a shift error in the adjusted normalized floating-point number. The correcting the shift error comprises shifting a mantissa of the adjusted normalized floating-point number in one direction. A fused multiply add module comprising a normalizer module, a compensation logic, and a round. The normalizer module is operable to normalize a floating-point number to produce a normalized floating-point number. The floating-point number is normalized based upon an estimated quantity of leading zeros. The compensation logic is operable to manage a correction of a shift error in the normalized floating-point number. The rounder is operable to correct the shift error with a mantissa shift in only one direction. | 07-03-2014 |

20140358979 | GENERATING A FAST 3x MULTIPLAND TERM FOR RADIX-8 BOOTH MULTIPLICATION - A 3× circuit for partial product generation used in a radix-8 multiplier receiving only a single multiplicand input. Rather than providing 2-inputs to the adder (a 2× of multiplicand and the multiplicand itself), the new 3× circuit uses the multiplicand as the only input. Thus, in terms of connections at the multiplier circuit level, only one bus is required to connect to the input of the new 3× circuit. The 3× generation adder circuit further operates at a reduced number of logic levels and speeds up the critical path by taking advantage of the repetition and fixed spatial separation of the bits for the adder inputs. | 12-04-2014 |

20140095563 | Shift Significand of Decimal Floating Point Data - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including a shift significand instruction. | 04-03-2014 |

20120215823 | Apparatus and method for performing floating point addition - An apparatus and method are provided for performing an addition operation on operands A and B in order to produce a result R, the operands A and B and the result R being floating point values each having a significand and an exponent. The apparatus comprises prediction circuitry for generating a shift indication based on a prediction of the number of leading zeros that would be present in an output produced by subjecting the operands A and B to an unlike signed addition. Further, result pre-normalization circuitry performs a shift operation on the significands of both operand A and operand B prior to addition of the significands, this serving to discard a number of most significant bits of the significands of both operands as determined by the shift indication in order to produce modified significands for operands A and B. Operand analysis circuitry detects, with reference to the exponents of operands A and B, the presence of a leading bit cancellation condition, and addition circuitry is configured, in the presence of the leading bit cancellation condition, to perform an addition of the modified significands for operands A and B, in order to produce the significand of the result R. Such an approach provides a particularly simple and efficient apparatus for performing addition operations. | 08-23-2012 |

20100169398 | METHOD AND APPARATUS HAVING A MEASURED VALUE INPUT FOR APPLYING A MEASURED VALUE - The invention pertains to a device such as a sensor, operator device, communication device, or a liquid level metering device, with a measured value input to apply a measured value. The device includes at least a first memory region to provide for an adjustment factor, and a computer, which is designed and/or controlled to multiply a first whole number by a floating-point number to obtain a product of the multiplication, while the first whole number corresponds either to the applied measured value or the provided adjustment factor; and, the floating-point number corresponds to the other measured value or to the adjustment factor. The computer has a second memory region for the storing of the floating-point number in a format of a second whole number, and the computer is designed and/or controlled to carry out a multiplication of the first whole number and the second whole number. | 07-01-2010 |

20100293210 | SOFTWARE IMPLEMENTATION OF MATRIX INVERSION IN A WIRELESS COMMUNICATION SYSTEM - A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers. | 11-18-2010 |

20100211623 | FILTER PROCESSING MODULE AND SEMICONDUCTOR DEVICE - The present invention is directed to improve efficiency of a filter processing on an image. A filter processing module includes a filter circuit and a control circuit. The filter circuit includes: a first register capable of storing data; a first arithmetic logic unit capable of executing a first filter processing on the basis of output data of the first register; a second register capable of storing a result of the arithmetic operation of the first arithmetic logic unit; and a second arithmetic logic unit capable of executing a second filter processing on the basis of output data of the second register. The control circuit adjusts the number of pieces of data which is input per cycle in the first register in accordance with the number of taps in the first filter processing, size of an execution result of the first filter processing, and the number of second arithmetic logic units, thereby promptly completing the first filter processing. | 08-19-2010 |

20160092166 | SINGLE OPERATION ARRAY INDEX COMPUTATION - Embodiments are directed to a processor for adjusting an index, wherein the index identifies a location of an element within an array. The processor includes a shift circuit configured to perform a single operation that adjusts a first parameter of the index to match a parameter of an array address. The single operation further adjusts a second parameter of the index to match a parameter of an array element. | 03-31-2016 |

20110131262 | FLOATING POINT DIVIDER AND INFORMATION PROCESSING APPARATUS USING THE SAME - A floating point divider includes a mantissa repetitive processing unit and an operation execution control unit. The mantissa repetitive processing unit calculates a quotient and a partial remainder by a digit-recurrence process for a mantissa of a dividend of an input operand. The operation execution control unit determines a bit value at a specified position uniquely specified based on a radix of an operation execution process with respect to the partial remainder. The mantissa repetitive processing unit reduces the number of digit-recurrence processes by calculating a quotient and a remainder based on a determining result of the operation execution control unit. The number of bits of the quotient is double of that of a quotient calculated once every the digit-recurrence process. The number of left-shift processes processed on the remainder is double of that of a remainder calculated once every the digit-recurrence process. | 06-02-2011 |

20100306293 | Galois Field Multiplier - A Galois field multiplier is provided, comprising a multiplication circuit for inputting two m bits binary multiplicators and outputting their product, wherein m is an integral power of 2, and the output of said multiplication circuit is consisted of a high bits portion output and a low bits portion output; a memory for storing a Galois field multiplication coefficient array calculated from a selected Galois field primitive polynomial; a first module for performing operation on the output of said multiplication circuit and the Galois field multiplication coefficient array stored in said memory to obtain the product of the two m bits binary multiplicators over Galois field. The Galois field multiplier has small hardware footprint, short response latency and strong universality. | 12-02-2010 |

20100306292 | DSP Engine with Implicit Mixed Sign Operands - A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode. | 12-02-2010 |

20140181164 | SELECTIVELY COMBINABLE SHIFTERS - An apparatus for mathematical manipulation is described allowing the selective combination of shifters to shift binary numbers of various widths. Selective combination allows on-the-fly adjustment of shifters from independent to coordinated shifting operations. Selective combination allows adjustable hardware-based shifting while saving space and resources. Multiple eight-bit shifters can be configured for a variety of operand widths, such as a 32-bit width, a 24-bit width, a 16-bit width, or an eight-bit width. Multiplexers route the appropriate input data to the appropriate shifters. Opcodes configure the shifters for the desired type of shift and a shifted result is generated. | 06-26-2014 |

20100306291 | Barrel shifter - A data processing apparatus is described which comprises processing circuitry responsive to data processing instructions to execute data processing operations and a register file having a set of registers for storing data values for processing by the processing circuitry. The data processing apparatus comprises first shift circuitry which is arranged to receive a data value from the register file and is responsive to a first control signal indicating a first shift amount S | 12-02-2010 |

20100281087 | APPROXIMATE SRT DIVISION METHOD - The invention relates to a program storage device readable by a machine, tangibly embodying a program of instructions executable by a specific semiconductor-based computational device situated in the machine to perform the steps of a partial SRT (PSRT) division of a dividend X by a divisor D to obtain a quotient Q. The steps include: causing a computer to obtain the dividend X and the divisor D; representing the dividend X and the divisor D as a digital representation having a plurality of bits; and performing iteratively a series of steps until a desired accuracy of the quotient Q is achieved. The invention also relates to an article of manufacture including a computer usable medium having computer readable program code embodied therein for causing a partial SRT (PSRT) division of a dividend X by a divisor D to generate a quotient Q. | 11-04-2010 |

20100293212 | BARREL SHIFTER - A barrel shifter receiving N symbols, arranged n | 11-18-2010 |

20100293211 | APPARATUS AND METHOD FOR GENERATING MEAN VALUE - There is provided an apparatus for generating a mean value of N-bit input data in M-bit operations (M and N are integers, and M is greater than N) by dividing a total sum of the input data by number of times the data are input, including a ROM (Read Only Memory) storing therein, as denominators, quotients of dividing 2 | 11-18-2010 |

20100191787 | Sequential Multiplier - A sequential multiplier for multiplying a binary multiplier and a binary multiplicand to produce a final product. A first logic circuit generates a control signal based on the multiplier. A second logic circuit generates a partial product based on the control signal and the multiplicand. A full adder generates a partial sum and a partial carry in each of a sequence of cycles. In the first cycle the partial sum and the partial carry are both initialized to zero. In each said cycle the partial sum, the partial carry, and the partial product are added to generate a new partial sum and a new partial carry. After a last cycle, the partial sum is the final product. | 07-29-2010 |

20100191786 | DIGITAL SIGNAL PROCESSING BLOCK WITH PREADDER STAGE - A digital signal processing block with a preadder stage for an integrated circuit is described. The digital signal processing block includes a preadder stage and a control bus. The control bus is coupled to the preadder stage for dynamically controlling operation of the preadder stage. The preadder stage includes: a first input port of a first multiplexer coupled to the control bus; a second input port of a first logic gate coupled to the control bus; a third input port of a second logic gate coupled to the control bus; and a fourth input port of an adder/subtractor coupled to the control bus. | 07-29-2010 |

20100017448 | Bit selection circuit - A bit selection circuit that arbitrarily selects, from among (2 | 01-21-2010 |

20100235416 | MECHANISM FOR FAST DETECTION OF OVERSHIFT IN A FLOATING POINT UNIT OF A PROCESSING DEVICE - A floating point unit includes a floating point adder to perform a floating point addition operation between first and second floating point numbers each having an exponent and a mantissa. The floating point unit also includes an alignment shifter that may calculate a shift value corresponding to a number of bit positions to shift the second mantissa such that the second exponent value is the same as the first exponent value. The alignment shifter may detect an overshift condition, in which the shift value is greater than or equal to a selected overshift threshold value. The selected overshift threshold value comprises a base 2 number in a range of overshift values including a minimum overshift threshold value and a maximum overshift threshold value, and which has a largest number of a consecutive of bits that are zero beginning at a least significant bit. | 09-16-2010 |

20090248769 | Multiply and accumulate digital filter operations - A multiply and accumulate engine may implement a digital filter. In some embodiments, the number of coefficients that are stored may be equal to only half of the number of filter taps that are implemented. This may be done by doing multiplications operand by operand within two data registers in a first direction and then shifting directions so that the first operand in a first register is multiplied by the last operand in another register. In some embodiments, the multiply and accumulate engine may be implemented as a two cycle engine wherein in the first stage, multiply and accumulate operations are implemented and then stored into a register. In a second stage and a second cycle, the results stored in the register are further accumulated. | 10-01-2009 |

20140304315 | Low Delay Modulated Filter Bank - The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a 64 channel filter bank using a prototype filter length of 640 coefficients and a system delay of 319 samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip. The method offers improvements for various types of digital equalizers, adaptive filters, multiband companders and spectral envelope adjusting filter banks used in high frequency reconstruction (HFR) or parametric stereo systems. | 10-09-2014 |

20130339412 | DATA PROCESSING APPARATUS AND METHOD - Processing circuitry is provided for performing a shift-round-and-accumulate operation. The operation comprises shifting an input value to generate a shifted value using shifting circuitry, adding the shifted value to an accumulate value using adding circuitry, and performing rounding by adding a rounding value to the sum of the shifted value and the accumulated value using the adding circuitry. The same adding circuitry is used to perform both the addition of the shifted value and the accumulated value and the addition of the rounding value in the same processing cycle. | 12-19-2013 |

20140280409 | DATA PROCESSING DEVICE, DATA PROCESSING METHOD, AND COMPUTER PROGRAM - A device for temporarily storing data output from a register or data obtained by processing the output data, a processing method therefor, a program, and the like is provided. A circuit (hereinafter, referred to as a selective memory cell) in which a plurality of switches and a signal storing circuit are connected is provided in a data processing device. The selective memory cell can selectively store necessary data. A result of a frequently performed process is stored in the selective memory cell. A process whose result is stored can be performed by only outputting the stored data instead of performing the whole process; thus, input data does not need to be transferred, which can result in a reduction in processing time. | 09-18-2014 |

20100042665 | Subnormal Number Handling in Floating Point Adder Without Detection of Subnormal Numbers Before Exponent Subtraction - In an embodiment, a floating point unit (FPU) comprises an adder configured to add a first mantissa and a second mantissa and an operand adjust unit coupled to provide at least the first mantissa to the adder. The operand adjust unit is coupled to receive a first operand and a second operand for a floating point add operation, and is configured to: right shift at least one mantissa corresponding to one of the first and second operands responsive to a shift count generated from exponent portions of the first and second operands; to detect whether or not neither, one, or both of the first and second operands are subnormal numbers in parallel with at least a portion of the right shifting; and to left shift by one bit the right shifted mantissa responsive to only one of the first and second operands being a subnormal floating point number. | 02-18-2010 |

20120215824 | ITERATIVE-DIVISION OPERATIONS SUCH AS FOR HEADER COMPRESSION IN PACKET-BASED COMMUNICATIONS - In one embodiment of a header-compression method, a 32-bit timestamp value is divided by a 16- or 8-bit stride value using a plurality of 16/8-bit division operations, each performed using a corresponding hardware instruction issued to an arithmetic logic unit (ALU) of the corresponding communication device, such as an access terminal or a base station of a communication system. When specialized 32/16-bit and/or 32/8-bit division-logic circuitry is not available in the ALU, embodiments of the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices. | 08-23-2012 |

20100146024 | DIGITAL FILTER, ITS SYNTHESIZING DEVICE, SYNTHESIZING PROGRAM AND SYNTHESIZING PROGRAM RECORDING MEDIUM - In an IIR digital filter, for example, a multi-input multiplier/adder circuit is used as a component in place of a plurality of multipliers and a plurality of adders. With this omission of a plurality of multipliers and a plurality of adders, the circuit size can be reduced. Also, since the multi-input multiplier/adder circuit permits pipelining for increasing the processing speed in feedback processing, filter processing can be performed at high speed. | 06-10-2010 |

20110004643 | SHIFT CALCULATOR - A shift calculator including a first shifter includes a right shifter configured to perform a right shift of 0 to 3 bits and a left shifter configured to perform a left shift of 0 to 3 bits, on input data of which a data width is N bits, in accordance with left/right selection signals, based on a shift amount of 3 bits or smaller out of an input shift amount, a rotator configured to perform a right rotate shift of 0 to N−4 bits or a left rotate shift of 0 to N−4 bits, on output data from said first shifter, in accordance with said left/right selection signals, based on a shift amount of 4 bits or greater out of the input shift amount, and a mask unit configured to perform mask processing in 4-bit increments on output data from said rotator based on mask signals. | 01-06-2011 |

20100161696 | RANDOM NUMBER GENERATOR AND PSEUDO-RANDOM NUMBER GENERATOR - A random number generator which includes a bus including a plurality of bus lines configured to send and receive a signal between a circuit and another circuit, a calibration unit configured to dynamically adjust a reception condition of the signal, and a random number generating unit configured to generate a random number based on adjustment information of the calibration unit. | 06-24-2010 |

20100198894 | Digital Signal Processor Having Instruction Set With An Exponential Function Using Reduced Look-Up Table - A digital signal processor is provided having an instruction set with an exponential function that uses a reduced look-up table. The disclosed digital signal processor evaluates an exponential function for an input value, x, by decomposing the input value, x, to an integer part, N, a first fractional part, q | 08-05-2010 |

20100198893 | Digital Signal Processor Having Instruction Set With An Xk Function Using Reduced Look-Up Table - A digital signal processor is provided having an instruction set with an x | 08-05-2010 |

20100131577 | Programmable CORDIC Processor - A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input. | 05-27-2010 |

20110161389 | LARGE MULTIPLIER FOR PROGRAMMABLE LOGIC DEVICE - A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. | 06-30-2011 |

20100174765 | PERFORMING VARIABLE AND/OR BITWISE SHIFT OPERATION FOR A SHIFT INSTRUCTION THAT DOES NOT PROVIDE A VARIABLE OR BITWISE SHIFT OPTION - Some embodiments present a method of performing a variable shift operation. This method can be used by a microprocessor that does not allow variable shift operation for certain operand sizes. The method simulates a shift instruction that shifts an operand by a shift count. The method identifies a first shift command and a second shift command. The method computes a mask value. The mask value depends on whether the shift count is less than half of the operand size or greater than or equal to half of the operand size. The method uses the mask value to cause one of the first shift command and the second shift command to produce no shift. In some embodiments, the method allows for the shift count to be specified in bytes or in bits. | 07-08-2010 |

20100146022 | FLOATING-POINT FUSED ADD-SUBTRACT UNIT - In a particular embodiment, a method is disclosed that includes receiving first and second operands at a floating-point fused add-subtract circuit. The method further includes simultaneously performing add and subtract operations on the first and second operands via the floating-point fused add-subtract circuit to produce a sum result output and a difference result output. The floating-point fused add-subtract circuit includes sign logic, exponent adjustment logic, and shift logic that are shared by an add/round and post-normalize circuit and a subtract/round and post-normalize circuit to produce the sum and difference result outputs. | 06-10-2010 |

20100179976 | SEMICONDUCTOR DEVICE PERFORMING OPERATIONAL PROCESSING - A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data. | 07-15-2010 |

20100153477 | METHOD OF CALCULATING TRANSPORT BLOCK SIZES IN COMMUNICATION SYSTEM - A method of calculating a transport block size in an HSPA receiver of a communication system is provided. After decomposing an exponential function P | 06-17-2010 |

20140181165 | Three-Term Predictive Adder and/or Subtracter - A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2 | 06-26-2014 |

20150058389 | EXTENDED MULTIPLY - Techniques are disclosed relating to performing extended multiplies without a carry flag. In one embodiment, an apparatus includes a multiply unit configured to perform multiplications of operands having a particular width. In this embodiment, the apparatus also includes multiple storage elements configured to store operands for the multiply unit. In this embodiment, each of the storage elements is configured to provide a portion of a stored operand that is less than an entirety of the stored operand in response to a control signal from the apparatus. In one embodiment, the apparatus is configured to perform a multiplication of given first and second operands having a width greater than the particular width by performing a sequence of multiply operations using the multiply unit, using portions of the stored operands and without using a carry flag between any of the sequence of multiply operations. | 02-26-2015 |

20100023568 | Dynamic Range Adjusting Floating Point Execution Unit - A floating point execution unit is capable of selectively repurposing a subset of the significand bits in a floating point value for use as additional exponent bits to dynamically provide an extended range for floating point calculations. A significand field of a floating point operand may be considered to include first and second portions, with the first portion capable of being concatenated with the second portion to represent the significand for a floating point value, or, to provide an extended range, being concatenated with the exponent field of the floating point operand to represent the exponent for a floating point value. | 01-28-2010 |

20100198895 | Digital Signal Processor Having Instruction Set With A Logarithm Function Using Reduced Look-Up Table - A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table. The disclosed digital signal processor evaluates a logarithm function for an input value, x, by decomposing the input value, x, to a first part, N, a second part, q, and a remaining part, r, wherein the first part, N, is identified by a position of a most significant bit of the input value, x, and the second part, q, is comprised of a number of bits following the most significant bit, wherein the number is small relative to a number of bits in the input value, x; obtaining a value | 08-05-2010 |

20140089363 | HIGH SPEED AND LOW POWER CIRCUIT STRUCTURE FOR BARREL SHIFTER - A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. The encoding scheme using a sign magnitude to 2's complement converter allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption. | 03-27-2014 |

20100179975 | METHOD FOR DECOMPOSING BARREL SHIFTER, DECOMPOSED CIRCUIT AND CONTROL METHOD THEREOF - A method for decomposing a barrel shifter decomposes N, the number of digits of input word, into N | 07-15-2010 |

20140074901 | BANDWIDTH EFFICIENT INSTRUCTION-DRIVEN MULTIPLICATION ENGINE - Multiplication engines and multiplication methods are provided for a digital processor. A multiplication engine includes multipliers, each receiving a first operand and a second operand; a local operand register having locations to hold the first operands for respective multipliers; a first operand bus coupled to the local operand register to supply the first operands from a compute register file to the local operand register; a second operand bus coupled to the plurality of multipliers to supply one or more of to the second operands from the compute register file to respective multipliers; and a control unit responsive to a digital processor instruction to supply the first operands from the local operand register to respective multipliers, to supply the second operands from the compute register file to respective multipliers on the second operand bus and to multiply the first operands by the respective second operands in the respective multipliers, wherein one or more of the first operands in the local operand register are reused by the multipliers in two or more multiplication operations. | 03-13-2014 |

20140280410 | Constant Fraction Integer Multiplication - A binary logic circuit is provided for determining a rounded value of | 09-18-2014 |

20120150932 | DIVIDER CIRCUIT AND DIVISION METHOD - A divider circuit includes: a register which is configured of an even number of bits and in which a dividend data is stored. A shift operation section is configured to acquire a data stored in an upper bit portion of the register when the even number of bits of the register is equally divided to the upper bit portion and a lower bit portion, as a quotient data when the dividend data is divided by a maximum of a divisor data which can be expressed by a half of the even number of bits of the register. | 06-14-2012 |

20150347090 | FLOATING POINT MULTIPLY ACCUMULATOR MULTI-PRECISION MANTISSA ALIGNER - A processing device is provided that includes a first, second and third precision operation circuit. The processing device further includes a shared, bit-shifting circuit that is communicatively coupled to the first, second and third precision operation circuits. A method is also provided for multiplying a first and second binary number including adding a first exponent value associated with the first binary number to a second exponent value associated with the second binary number and multiplying a first mantissa value associated with the first binary number to a second mantissa value associated with the second binary number. The method includes performing the exponent adding and mantissa multiplying substantially in parallel. The method further includes performing at least one of adding or subtracting a third binary number to the product. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. | 12-03-2015 |

20100228807 | Digital signal processing circuitry with redundancy and bidirectional data paths - Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). | 09-09-2010 |

20150095388 | Configurable Multiply-Accumulate - Field programmable gate arrays (FPGA) contain, in addition to random logic, also other components, such as processing units, multiply-accumulate (MAC) units, analog circuits, and other elements, configurable with respect of the random logic, to enhance the capabilities of the FPGA. A circuit for a filed configurable MAC unit is provided to allow various configurations of ADD, SUBTRACT, MULTIPLY and SHIFT functions. Optionally, registered input and registered output support a multi-cycle path. A configuration of a constant facilitates the configuration of the circuit to perform infinite impulse response (IIR) and finite impulse response (FIR) functions in hardware. | 04-02-2015 |

20130218938 | FLOATING-POINT ADDER WITH OPERAND SHIFTING BASED ON A PREDICTED EXPONENT DIFFERENCE - Provided are a floating-point adder and methods for implementing a floating-point adder with operand shifting based on a predicted exponent difference when performing an effective subtraction on normal or subnormal numbers. In an aspect, two least significant bits (LSBs) of a first floating-point operand's exponent are compared with two LSBs of a second floating-point operand's exponent to estimate a difference between the two exponents. A first shift of up to one of the first and the second operands is performed, based on the estimated difference. A prospective result is then produced by subtracting the first operand and the second operand. Contemporaneously, one of the first operand's exponent and the second operand's exponent is subtracted from the other of the first operand's exponent and the second operand's exponent to determine if the exponents actually differ by one or less. If the first operand's exponent and the second operand's exponent differ by one or less, the prospective result is provided as the raw difference of the operands. | 08-22-2013 |

20140330878 | FAST COMPUTATION OF PRODUCTS BY DYADIC FRACTIONS WITH SIGN-SYMMETRIC ROUNDING ERRORS - A product of an integer value and an irrational value may be determined by a sign-symmetric algorithm. A process may determine possible algorithms that minimize metrics such as mean asymmetry, mean error, variance of error, and magnitude of error. Given an integer variable x and rational dyadic constants that approximate the irrational fraction, a series of intermediate values may be produced that are sign-symmetric. The intermediate values may include a sequence of addition, subtraction and right shift operations the when summed together approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0s or shifts by 0 bits may be removed. | 11-06-2014 |

20100070547 | INTEGER DIVISION CIRCUIT WITH ALLOWABLE ERROR - An integer division circuit with allowable error is described, what a signal processing apparatus includes a pointer, a first left shifter, a second left shifter, a subtractor, a multiplier, and a right shifter. The pointer searches for a most significant non-zero bit of a divisor and outputs a most significant byte value. The first left shifter performs a shift operation according to the most significant byte value, so as to generate a first exponential coefficient. The second left shifter performs a shift operation according to the most significant byte value, so as to generate a second exponential coefficient. The subtractor calculates a multiplier factor according to the divisor, the first exponential coefficient, and the second exponential coefficient and outputs the multiplier factor to the multiplier. The multiplier multiplies an input value with the multiplier factor and outputs a result to the right shifter. The right shifter outputs a calculation result. | 03-18-2010 |

20110035425 | DISCRETE COSINE AND INVERSE DISCRETE COSINE TRANSFORM CIRCUIT - A discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) circuit includes a microcode memory, a processor, and a butterfly operation circuit. The microcode memory stores multiple microcode groups corresponding to DCT/IDCT operations and each of the microcode groups includes a series of microcodes. The processor obtains one of the microcode groups corresponding to one of the DCT/IDCT operations to be performed and retrieves microcodes in the obtained microcode group in sequence. The butterfly operation circuit performs butterfly operations according to the retrieved microcodes to execute one of the DCT/IDCT operations. | 02-10-2011 |

20110035426 | Bitstream Buffer Manipulation with a SIMD Merge Instruction - Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block. | 02-10-2011 |

20140337396 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A TRANSFORM BETWEEN SPATIAL AND FREQUENCY DOMAINS WHEN PROCESSING VIDEO DATA - A data processing apparatus and method are provided for performing a transform between spatial and frequency domains when processing video data. The data processing apparatus comprises transform circuitry configured to receive N input values and to perform a sequence of operations to generate N output values representing the transform of the N input values between the spatial and frequency domains. In doing this, the transform circuitry employs a base circuitry that is configured to receive M internal input values generated by the transform circuitry, where M is greater than or equal to 4, and to perform a base operation equivalent to matrix multiplication of the M internal input values by a Hankel matrix, which is a square matrix with constant skew diagonals, where each element of the array identifies a coefficient, performance of the base operation generating M internal output values for returning to the transform circuitry. The transform circuitry is arranged during performance of the sequence of operations to generate from the N input values multiple sets of the M internal input values, to provide each set of M internal input values to the base circuitry in order to cause multiple sets of the M internal output values to be produced, and to derive the N output values from the multiple sets of M internal output values. It has been found that such an approach is scalable to accommodate varying sizes of N, results in a significant reduction in the number of multiplications required in order to perform the transform between the spatial and frequency domains of the N input values, and produces a bit exact result. | 11-13-2014 |

20140337395 | SEMICONDUCTOR MEMORY DEVICE AND RANDOM NUMBER GENERATOR - According to one embodiment, semiconductor memory device and a random number generator includes A semiconductor memory device includes: a semiconductor memory | 11-13-2014 |

20160026435 | SIMPLIFIED INVERSIONLESS BERLEKAMP-MASSEY ALGORITHM FOR BINARY BCH CODE AND CIRCUIT IMPLEMENTING THEREFOR - A simplified inversionless Berlekamp-Massey algorithm for binary BCH codes and circuit implementing the method are disclosed. The circuit includes a first register group, a second register group, a control element, an input element and a processing element. By breaking the completeness of math structure of the existing simplified inversionless Berlekamp-Massey algorithm, the amount of registers used can be reduced by two compared with conventional algorithm. Hardware complexity and operation time can be reduced. | 01-28-2016 |

20140006466 | HIGH SPEED AND LOW POWER CIRCUIT STRUCTURE FOR BARREL SHIFTER | 01-02-2014 |

20100191788 | Multiplier with Shifter - A digital system has a memory configured to hold operands and a multiply-shift unit coupled to the memory and configured to receive a first operand and a second operand from the memory in parallel, wherein the first operand includes a concatenated encoded shift amount. The multiply-shift unit includes a multiplier configured to receive the first operand after being separated from the concatenated encoded shift amount and to form a quotient from the two operands. A shifter is coupled to receive the quotient and to shift the quotient by an amount indicated by the encoded shift amount and to thereby form a shifted quotient on an output of the multiply-shift unit. | 07-29-2010 |

20150067010 | FLOATING-POINT ADDER CIRCUITRY - An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point operation. The exact bit extension is dependent on the number of floating-point numbers to be added. The mantissas of all floating-point numbers with an exponent smaller than the biggest exponent are shifted to the right. The number of right shift bits is dependent on the difference between the biggest exponent and the respective floating-point exponent. | 03-05-2015 |

20120016919 | EXTENDED-WIDTH SHIFTER FOR ARITHMETIC LOGIC UNIT - A processor includes a shift device for extending the width of a rotator without increasing propagation delays. An extended-width result is obtained by combining a rotation result with a shift result in accordance with a mask that is selected in response to at least a portion of the value of the degree to which a data word is to be shifted. | 01-19-2012 |

20140082037 | PERFORMING QUOTIENT SELECTION FOR A CARRY-SAVE DIVISION OPERATION - The disclosed embodiments disclose techniques for performing quotient selection in an iterative carry-save division operation that divides a dividend, R, by a divisor, D, to produce an approximation of a quotient, Q=R/D. During a divide operation, a divider approximates Q by iteratively selecting an operation to perform for each iteration of the carry-save division operation and then performing the selected operation. The operation for each iteration is selected based on the current partial sum bits of a partial remainder in carry-save form (rs) and the current partial carry bits of a partial remainder in carry-save form (rc). More specifically, the operation is selected from a set of operations that includes: (1) a 2X* operation; (2) an S1 & 2X* operation; (3) an S2 & 2X* operation; (4) an A1 & 2X* operation; and (5) an A2 & 2X* operation. | 03-20-2014 |

20090248770 | METHODS AND APPARATUS FOR REDUCING OR AVOIDING USE OF NON-SHIFT BASED DIVISIONS IN A COMMUNICATIONS DEVICE - Methods and apparatus which reduce or completely eliminate non-shift based divisions as part of estimating transmitted symbols and/or generating slicing parameters corresponding to two symbol transmission streams in a wireless communication system are described. A linear least squares error estimation filtering module performs symbol estimations and/or slicing parameter generation while avoiding non-shift based division operations. The linear least squares estimation module generates intermediate parameters, and implements equations which facilitate symbol estimation utilizing shift based divisions while avoiding non-shift based divisions. | 10-01-2009 |

20090265405 | Adder for Obtaining Maximum Accumulated Value of Correlation for Mode Detection in Communication System and Adding Method Using the Adder - Disclosed are an adder for obtaining a maximum accumulated value of correlation for mode detection in a communication system, and an adding method using the adder. According to the present disclosure, an adder for obtaining a maximum accumulated value of correlation values used to detect a mode in an orthogonal frequency division multiplexing (OFDM) system, includes one or more adding logic circuits for adding input values constituting the correlation values to stored values and outputting accumulated values, by using one or more memories; and one or more controllers for, if one of the accumulated values stored in the memories is greater than a predetermined value, shifting all of the accumulated values and the input values of the memories in a direction for decreasing the accumulated values and transmitting the shifted accumulated values and the input values to the adding logic circuits. | 10-22-2009 |

20130297664 | NUMBER SQUARING COMPUTER-IMPLEMENTED METHOD AND APPARATUS - Embodiments of the present disclosure describe computer-implemented methods, computer-readable media and computer system associated with big number squaring. A computer-implemented method to square a number x may include storing a t-digit vector representation of x in t b-bit registers of a processor. A 2t-digit intermediate vector may be generated and stored in 2t b-bit registers of the processor, using x stored in said t b-bit registers. A value stored in at least one of the t b-bit or 2t b-bit registers may be shifted to the left by n. n may be an integer at least equal to 1. At some point after the shifting, w, square of the number x, may be represented by the 2t-digit result vector stored in the 2t b-bit registers. Other embodiments may be described and/or claimed. | 11-07-2013 |

20150355884 | FLOATING-POINT CALCULATION APPARATUS, PROGRAM, AND CALCULATION APPARATUS - A floating-point calculation apparatus comprising: a selection part; an addition and subtraction calculation part; an output determination part; and a buffer management part configured to add, when it is determined that a buffer used to store an input value is not prepared, a buffer that corresponds to the input value, wherein when a number of significant digits of the result of performing an addition and subtraction calculation exceeds a number of significant digits of the buffer selected by the selection part, the addition and subtraction calculation part shifts right or shifts left part of the result of performing the addition and subtraction calculation and divides the result of performing the addition and subtraction calculation into values each being storable in one of a plurality of buffers. | 12-10-2015 |

20130007080 | MULTI-MODE COMBINED ROTATOR - A system and method for efficiently rotating data in a processor for multiple operand sizes. A processor comprises a rotator configured to support multiple operand sizes. The rotator receives a rotate amount and an input operand with a size less than a maximum operand size supported by the processor. The rotator generates a mask with a same size as the received input operand. The mask comprises a number of asserted most-significant bits equal to the rotate amount. The remaining bits in the mask are deasserted. For a given rotation result bit position with an associated asserted mask bit, the rotator selects a value in the input operand at a bit position with a distance from the given result bit position equal to the rotate amount plus a difference between the maximum operand size supported by the processor and the input operand size. | 01-03-2013 |

20140337397 | Generating a Signal - A method for generating a signal for a transmission antenna in a magnetic resonance imaging system includes generating a real part and an imaginary part of a baseband signal, generating a real part and an imaginary part of variations in frequency and in phase, and performing a complex multiplication of the baseband signal with the variations in frequency and in phase and a radiofrequency carrier signal for modulation. The method also includes modifying the modulated signal, and may include establishing a characteristic angle for a phase shift of the modified signal, and correcting the modulation based on the established angle in a closed-loop control. | 11-13-2014 |

20110060781 | Systems and Methods for Performing Fixed-Point Fractional Multiplication Operations in a SIMD Processor - Systems and methods for performing multiplication of fixed-point fractional values with the same throughput as addition and subtraction operations, and without loss of accuracy in the result. In one embodiment, a method includes reading data from a pair of source registers that contains multiple single-width multiplicand values. Each multiplicand value in one of the source registers is paired with a corresponding multiplicand value in the other source register. For each pair of multiplicands, a double-width product is generated, then a single-width portion of the product is selected and stored in a target register. The selection of the single-width portion is performed by shifting the double-width products in funnel shifters. The immediate shifting of the double-width products to select the single-width portions allows the operation to achieve the same throughput as addition and subtraction operations. | 03-10-2011 |

20140337398 | INCLUSIVE OR BIT MATRIX TO COMPARE MULTIPLE CORRESPONDING SUBFIELDS - A computer system is operable to identify subfields that differ in two data elements using a bit matrix compare function between a first matrix filled with pattern elements and a reference pattern. | 11-13-2014 |

20130159367 | Implementation of Negation in a Multiplication Operation Without Post-Incrementation - A multiplier circuit for generating a product of at least first and second multiplicands includes encoding circuitry comprising a plurality of encoders. Each of the encoders is operative to receive at least a subset of bits of the first multiplicand and to generate a partial product corresponding to the subset of bits of the first multiplicand. The encoding circuitry is further operative to incorporate a negation of the product as a function of at least a first control signal supplied to the multiplier circuit. The multiplier circuit further includes summation circuitry coupled with the encoding circuitry. The summation circuitry is operative to sum each of the partial products generated by the encoding circuitry to thereby generate the product without performing post-incrementation. | 06-20-2013 |

20130018933 | Data Shifter and Control Method Thereof, Multiplexer, Data Sifter, and Data SorterAANM Asanaka; KazunoriAACI YokohamaAACO JPAAGP Asanaka; Kazunori Yokohama JP - A data shifter ( | 01-17-2013 |

20150134713 | DIVSION OPERATIONS FOR MEMORY - Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first address space comprising a first number of memory cells coupled to a sense line and to a first number of select lines wherein the first address space stores a dividend value. A second address space comprises a second number of memory cells coupled to the sense line and to a second number of select lines wherein the second address space stores a divisor value. A third address space comprises a third number of memory cells coupled to the sense line and to a third number of select lines wherein the third address space stores a remainder value. Sensing circuitry can be configured to receive the dividend value and the divisor value, divide the dividend value by the divisor value, and store a remainder result in the third number of memory cells. | 05-14-2015 |

20160139879 | HIGH PERFORMANCE SHIFTER CIRCUIT - An improved shifter design for high-speed data processors is described. The shifter may include a first stage, in which the input bits are shifted by increments of N bits where N>1, followed by a second stage, in which all bits are shifted by a residual amount. A pre-shift may be removed from an input to the shifter and replaced by a shift adder at the second stage to further increase the speed of the shifter. | 05-19-2016 |

20130124590 | RECONFIGURABLE CYCLIC SHIFTER ARRANGEMENT - In one embodiment, a reconfigurable cyclic shifter arrangement has first and second reconfigurable cyclic shifters connected in series that are each selectively and independently configurable to operate in any one of three different modes at a time. In a first mode, the reconfigurable cyclic shifter is configured as four 4×4 cyclic shifters to cyclically shift four sets of four input values. In a second mode, the reconfigurable cyclic shifter is configured as two 8×8 cyclic shifters to cyclically shift two sets of eight input values. In a third mode, the reconfigurable cyclic shifter is configured as one 16×16 cyclic shifter to cyclically shift one set of 16 input values. Because the first and second reconfigurable cyclic shifters are independently configurable, there are nine different configurations of the reconfigurable cyclic shifter arrangement. | 05-16-2013 |

20150039662 | FFMA OPERATIONS USING A MULTI-STEP APPROACH TO DATA SHIFTING - A fused floating-point multiply-add element includes a multiplier that generates a product, and a shifter that shifts an addend within a narrow range. Interpreting logic analyzes the magnitude of the addend relative to the product and then causes logic arrays to position the shifted addend within the left, center, or right portions of a composite register depending in the magnitude of the addend relative to the product. The interpreting logic also forces other portions of the composite register to zero. When the addend is zero, the interpreting logic forces all portions of the composite register to zero. Final combining logic then adds the contents of the composite register to the product. | 02-05-2015 |

20120102081 | LOW-LATENCY ARC-TANGENT CALCULATION STRUCTURE AND CALCULATION METHOD THEREOF - The present invention provides a low-latency arc-tangent calculation structure and a calculation method thereof. The arc-tangent calculation structure comprises two lookup tables, a subtractor, a sign comparator, a numerical comparator and a shift encoder. The present invention divides the coordinate system into a plurality of sectors for simplifying the lookup tables. The first lookup table is used to perform logarithmic transformation so as to replace a divider with a subtractor. The second lookup table integrates an exponentiation table and an angle table to translate the output of the subtractor into arc-tangent value θ. Then, θ is shifted to a correct angle according to the output of the shift encoder. | 04-26-2012 |

20130151577 | Performing Arithmetic Operations Using Both Large and Small Floating Point Values - Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands. | 06-13-2013 |

20120117135 | METHOD FOR GENERATING A SEQUENCE IN A WIRELESS COMMUNICATION SYSTEM, AND APPARATUS FOR SAME - Disclosed is a method for generating a sequence and an apparatus for the same which can satisfy the number M′ of sequences sufficiently larger than a length N of a sequence required in a wireless communication system. When the generation of a sequence of the wireless communication system is intended, a first sequence is generated from an m | 05-10-2012 |

20120143933 | CARRYLESS MULTIPLICATION UNIT - An apparatus having a carryless preformat unit, a Booth encoder, a compressor, a left shifter, and exclusive-OR logic. The carryless preformat unit receives a multiplier operand and partitions the multiplier operand into parts. The Booth encoder receives the parts and directs selection of first partial products of a multiplicand that do not reflect implicit carry operations. The compressor sums the first partial products via a configuration of carry save adders that generate sum bits and carry bits, where generation of the carry bits is disabled during execution of the carryless multiplication. The left shifter shifts bits of one or more outputs of the compressor. The exclusive-OR logic is coupled to the compressor and the left shifter, and is configured to execute an exclusive-OR function on the outputs to yield a carryless multiplication result. | 06-07-2012 |

20120143934 | MECHANISM FOR CARRYLESS MULTIPLICATION THAT EMPLOYS BOOTH ENCODING - An apparatus having operand registers, an opcode dectector, a carryless preformat unit, a compressor, a left shifter, and exclusive-OR logic. The operand registers receive operands for a carryless multiplication. The opcode dectector receives a carryless multiplication instruction, and asserts a carryless signal. The carryless preformat unit partitions a first operand into a plurality of parts that are such that a Booth encoder is precluded from selection of second partial products of a second operand, where the second partial products reflect implicit carry operations. The compressor sums first partial products of the second operand via carry save adders arranged in a Wallace tree configuration, where generation of carry bits is disabled. The left shifter shifts one or more outputs of the compressor. The exclusive-OR logic executes an exclusive-OR function to yield a carryless multiplication result. | 06-07-2012 |

20150363169 | MULTIPLIER UNIT WITH SPECULATIVE ROUNDING FOR USE WITH DIVISION AND SQUARE-ROOT OPERATIONS - Embodiments of a multiplier unit that may be used for division and square root operations are disclosed. The embodiments may provide a reduced and fixed latency for denormalization and rounding used in the division and square root operations. A storage circuit may be configured to receive first and second source operands. A multiplier circuit may be configured to perform a plurality of multiplication operations dependent upon the first and second source operands. Each result after an initial result of the multiplier may also depend on at least one previous result. Circuitry may be configured to perform a shift operation and a rounding operation on a given result of the plurality of results. An error of the given result may be less than a predetermined threshold value. | 12-17-2015 |

20130151578 | Performing Arithmetic Operations Using Both Large and Small Floating Point Values - Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands. | 06-13-2013 |

20120030267 | Performing Multiplication for a Multi-Channel Notch Rejection Filter - A system for processing sample sequences, that may include an input, a sequence of coupled registers, including an accumulator register, and first circuitry that may be coupled to the accumulator register and to the input. The input may be configured to receive a first number of sample sequences having two or more samples. To process the first number of sample sequences, the first circuitry may be configured to generate a current effective sample corresponding to the sample for each sample in each sample sequence, write the current effective sample to the accumulator register, and shift the contents of each register into a successive register in the sequence of registers. After processing, each register of at least a subset of the sequence of registers may hold a respective final effective sample that may correspond to a different position in a processed sample sequence. | 02-02-2012 |

20150363168 | PIPELINED MULTIPLY-SCAN CIRCUIT - A pipelined multiply-scan circuit that may be used for high-performance computing. The pipelined multiply-scan circuit may comprise dedicated hardware configured to execute one or more sub-calculations associated with a pipelined multiply-scan process utilizing one or more serially-connected left-shift modules, and one or more serially-connected adder. | 12-17-2015 |

20120166504 | Coefficient Boost Multiply Accumulate Unit - In order to reduce the area and power consumption of MAC units, some aspects of the present disclosure relate to MAC units having a feedback path with an arithmetic element disposed thereon. The arithmetic element is often controlled so as to limit the number of bits needed in the data path, thereby limiting power and area required for the MAC unit. | 06-28-2012 |

20120317159 | MODULAR OPERATOR, DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF - A modular operator, a smart card including the same, and a method of operating the same are provided. The modular operator includes: an input unit configured to receive first data, second data, and a modulus; and an accumulator configured to perform an accumulation operation on the first data and a first portion of the second data, to shift the accumulation operation result to the right as much as the number of bits of the first portion, and to perform an accumulation operation on a result of a shifted accumulation operation, a second part, of the second data, which is shifted to the right as much as the number of bits of the first portion, and the modulus. | 12-13-2012 |

20110314073 | METHODS FOR EFFICIENT STATE TRANSITION MATRIX BASED LFSR COMPUTATIONS - A method for efficient state transition matrix based LFSR computations are disclosed. A polynomial associated with a linear feedback shift register is defined. This polynomial is used to generate a single step state transition matrix. The single step state transition matrix is then modified into a more general k-step state transition matrix. The resultant combined matrix is reduced in size and can be multiplied by a state input vector, ultimately producing a plurality of next state-input vectors thereby providing improved efficiency in computing a LFSR. | 12-22-2011 |

20130311529 | ARITHMETIC MODULE, DEVICE AND SYSTEM - An arithmetic module is provided, including a first adder, a first shifter coupled to the first adder, a multiplier coupled to the first shifter for receiving an external coefficient signal, a digit alignment unit coupled to the multiplier, a second adder coupled to the digit alignment unit, and a second shifter coupled to the second adder. The arithmetic module reduces the overall computation time effectively, as compared with a scalar processor, by employing a serial data connection design, and also significantly reduces power consumption of the digital signal processor by requiring fewer input and output ends than those of a multi-issue processor. | 11-21-2013 |

20140365546 | ARITHMETIC OPERATION DEVICE, CONTROL METHOD, AND PROGRAM - Provided is an arithmetic operation device including a plurality of shift registers each constituted by first to (N+1) | 12-11-2014 |

20150100612 | APPARATUS AND METHOD OF PROCESSING NUMERIC CALCULATION - A method and apparatus for processing numeric calculation are provided. The method includes determining a shift bit and an index bit that falls within an index range of a lookup table from among bits representing a divisor scaled up by an offset, obtaining a replacement value corresponding to an index value of the determined index bit by using the lookup table, multiplying a dividend scaled up by the offset by the obtained replacement value, and outputting a value corresponding to a division operation by correcting a scale of a result of the multiplication using a right shift operation. | 04-09-2015 |

20140372494 | GATE DRIVER CIRCUIT - A gate driver circuit includes several shift register stages. One of shifter register stages includes a pull-up unit, a pull-up control unit, and an output unit. The pull-up unit is configured for generating a driving signal according to a first clock signal and an operating signal. The pull-up control unit is configured for generating a next-stage operating signal to a next-stage shift register stage according to the first clock signal, the operating signal and the driving signal. The output unit is configured for receiving the driving signal and generating a first gate driving signal and a second gate driving signal according to a first controlling signal and a second controlling signal, respectively. | 12-18-2014 |

20140372493 | SYSTEM AND METHOD FOR ACCELERATING EVALUATION OF FUNCTIONS - A system and method for accelerating evaluation of functions. In one embodiment, a method includes receiving, by a processor, a value to be processed, and notification of a function to be applied to the value. The value is represented in a floating point format. The value is converted, by the processor, to a fixed point format. Which of Newton-Raphson and polynomial approximation is to be used to apply the function to the value in the fixed point format is determined by the processor. The function is applied to the value in the fixed point format to generate a result in the fixed point format. The result is converted to the floating point format by the processor. | 12-18-2014 |

20160013773 | METHOD AND APPARATUS FOR FAST DIGITAL FILTERING AND SIGNAL PROCESSING | 01-14-2016 |

20140379769 | METHOD AND SYSTEM FOR PERFORMING DIVISION/MULTIPLICATION OPERATIONS IN DIGITAL PROCESSORS, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT - A digital processor, such as, e.g., a divider in a PID controller, performs a mathematical operation such as division (or multiplication) involving operands represented by strings of bit signals and an operator to produce an operation result. The processor is configured by identifying first and second power-of-two approximating values of the operator as the nearest lower and nearest higher power-of-two values to the operator. The operation is performed on the input operands by means of the first and second power-of-two approximating values of the operator by shifting the bit signals in the operands by using the first and second power-of-two approximating values in an alternated sequence to produce: first approximate results by using the first power-of-two approximating value, second approximate results by using the second power-of-two approximating value. The average of the first and second approximate results is representative of the accurate result of the operation. | 12-25-2014 |

20130151576 | APPARATUS AND METHOD FOR ROUNDING A FLOATING-POINT VALUE TO AN INTEGRAL FLOATING-POINT VALUE - Processing circuitry is provided to perform an operation FRINT for rounding a floating-point value to an integral floating-point value. Control circuitry controls the processing circuitry to perform the FRINT operation in response to an FRINT instruction. The processing circuitry includes shifting circuitry for generating a rounding value by shifting a base value, adding circuitry for adding the rounding value to the significand of the floating-point value to generate a sum value, mask generating circuitry for generating a mask for clearing fractional-valued bits of the sum value, and masking circuitry for applying the mask to the sum value to generate the integral floating-point value. | 06-13-2013 |

20120197954 | FLOATING POINT MULTIPLIER CIRCUIT WITH OPTIMIZED ROUNDING CALCULATION - An optimized floating point multiplier rounding circuit that minimizes the increase of the critical timing path of the calculation. The values of the temporary mantissa required to make the rounding decision are calculated simultaneously by the circuit shown in the invention. | 08-02-2012 |

20150378677 | SHIFT AMOUNT CORRECTION FOR MULTIPLY-ADD - Methods and apparatuses for performing a floating point multiply-add operation with alignment correction. A processor receives a first operand, a second operand and a third operand, wherein the first, second and third operands each represent a floating point number comprising a significand value and a biased exponent value. A processor determines a shift amount based, at least in part, on the one or more biased exponent values of the first, second or third operand. A processor determines a shift amount correction based, at least in part, on the one or more biased exponent values of the first, second or third operand being equal to zero. | 12-31-2015 |

20140059097 | MULTIPLYING DEVICE AND MULTIPLYING METHOD - A multiplying device includes: a circuit which left-shifts a mantissa part of a floating-point number being a multiplicand by a shift amount; a circuit which calculates a digit number of the mantissa part of the multiplier by subtracting the count value from the digit number of the fixed precision of the mantissa part; a multiplying circuit which outputs an intermediate product on a digit-by-digit basis of the mantissa part of the multiplier based on the mantissa part of the left-shifted multiplicand and the mantissa part of the multiplier; an adding circuit which adds exponent parts of the multiplicand and the multiplier; and a control circuit which outputs the intermediate product output by the multiplying circuit, as a mantissa part of a floating-point number being a product and outputs the value output by the adding circuit, as an exponent part of the floating-point number being the product. | 02-27-2014 |

20140059096 | DIVIDING DEVICE AND DIVIDING METHOD - A dividing device includes: shifting circuits which left-shift the mantissa parts of the dividend and the divisor by a first and a second count values; a digit number arithmetic circuit which calculates a quotient digit number expected value based on the first count value and the second count value; a dividing circuit which outputs a quotient and a remainder in sequence on a digit-by-digit basis based on the mantissa parts of the dividend and the divisor left-shifted by the shifting circuits; a subtracting circuit which subtracts an exponent part of the floating-point number being the divisor from an exponent part of the floating-point number being the dividend to output a resultant value; and a control circuit which outputs a mantissa part and an exponent part of a floating-point number being a quotient. | 02-27-2014 |

20150149518 | HIGH SPEED AND LOW POWER CIRCUIT STRUCTURE FOR BARREL SHIFTER - A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. This encoding scheme allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for an implementation adapted to shift a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption. | 05-28-2015 |

20120239717 | FUNNEL SHIFTER IMPLEMENTATION - A funnel shifter includes an input, an output, and a multiplexer unit including a number of multiplexer levels. The multiplexer unit may perform one of a plurality of shift operations on an input value and to provide an output value in response to receiving a shift value and a shift operation value. A first multiplexer level may be configured to format and expand the input value into a larger intermediate value. At least a second multiplexer level may be configured to perform a linear shift of the intermediate value without wrapping any bits for creating the output value. At least some of the multiplexer levels may include multiplexer select signals that may be represented as a plurality of N-Nary one of N signals where N is greater than or equal to two, wherein each of the plurality of N-Nary signals being implemented on a set of physical wires. | 09-20-2012 |

20160062946 | FRACTIONAL DELAY ESTIMATION FOR DIGITAL VECTOR PROCESSING USING VECTOR TRANSFORMS - A fractional delay estimation module estimates a delay of a section of a forward processing path between a first point and a second point. The fractional delay estimation component determines an integer component and a fractional component of a first path delay based on a transform of a first vector inserted into the forward processing path at the first point and based on a transform of a first feedback vector received from a feedback path, determines an integer component and a fractional component of a second path delay in the forward processing path based on a third transform of a third vector inserted into the forward processing path at the second point and based on a fourth transform of a second feedback vector received from the feedback path, and further determines the estimated delay of the section based on a difference between the first and second path delays. | 03-03-2016 |

20150378682 | EFFICIENT CONSTANT MULTIPLIER IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES - Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a constant multiplier operation in the design, determining a nearest boundary condition for the constant multiplier operation, and decomposing the constant multiplier operation using the nearest boundary condition to reduce the plurality of PLD components. The reduced plurality of PLD components comprise at least one look up table (LUT) configured to implement an addition or subtraction operation of the decomposed constant multiplier operation. | 12-31-2015 |

20150378681 | APPARATUS AND METHOD FOR EFFICIENT DIVISION PERFORMANCE - A data processing apparatus and method of operating such a data processing apparatus are provided, for responding to a division instruction to perform a division operation to generate a result value by dividing an input numerator specified by the division instruction by an input denominator specified by the division instruction. The input numerator and input denominator are binary values. The apparatus comprises division circuitry configured to generate the result value by carrying out the division operation, power-of-two detection circuitry configured to signal a bypass condition if the input denominator has a value given by ±2 | 12-31-2015 |

20150378678 | SHIFT AMOUNT CORRECTION FOR MULTIPLY-ADD - Methods and apparatuses for performing a floating point multiply-add operation with alignment correction. A processor receives a first operand, a second operand and a third operand, wherein the first, second and third operands each represent a floating point number comprising a significand value and a biased exponent value. A processor determines a shift amount based, at least in part, on the one or more biased exponent values of the first, second or third operand. A processor determines a shift amount correction based, at least in part, on the one or more biased exponent values of the first, second or third operand being equal to zero. | 12-31-2015 |

20140143290 | LOGARITHMIC GAIN ADJUSTER - A circuit for multiplying a digital signal by a variable gain, controlled in dependence on a digital gain control value. The circuit comprises: a multiplier input for receiving the digital signal; a multiplier output for outputting the digital signal multiplied by the gain; a plurality of multiplier stages each arranged to multiply by a respective predetermined multiplication factor; and switching circuitry arranged so as to apply selected ones of the multiplier stages in a multiplication path between the input and output, in dependence on the digital gain control value. The multiplication factors are arranged such that binary steps in the digital gain control value result in logarithmic steps in said gain. | 05-22-2014 |

20140082036 | PERFORMING A DIVISION OPERATION USING A SPLIT DIVISION CIRCUIT - The disclosed embodiments disclose techniques for using a split division circuit that includes a first divider that is optimized for a first range of divisor values and a second divider that is optimized for a second range of divisor values; the first range is distinct from the second range. During operation, the circuit receives a divisor for the division operation. The circuit: determines whether the divisor is in the first range or the second range to determine whether the first divider or the second divider should perform the division operation; performs the division operation in the selected host divider; and then outputs the result that was generated by the selected host divider. | 03-20-2014 |

20140164457 | EXTENSIBLE ITERATIVE MULTIPLIER - An extensible iterative multiplier design is provided. Embodiments provide cascaded 8-bit multipliers for simplifying the performance of multi-byte multiplications. Booth encoding is performed in the lowest order multiplier, with the result of the Booth encoding then provided to higher order multipliers. Additionally, multiply-add operations can be performed by initializing a partial product sum register. Configurable connections between the multipliers facilitate a variety of possible multiplication options, including the possibility of varying the width of the operands. | 06-12-2014 |

20140108477 | VECTOR PROCESSOR HAVING INSTRUCTION SET WITH VECTOR CONVOLUTION FUNCTION FOR FIR FILTERING - A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N | 04-17-2014 |

20140089362 | Modified Fixed-Point Algorithm For Implementing Infrared Sensor Radiation Equation - A system including an integrated circuit chip also includes a microcontroller in the chip and an algorithm for execution by the microcontroller. The algorithm includes addition, subtraction, and multiplication operators (e.g. | 03-27-2014 |

20140025717 | SIMD INTEGER ADDITION INCLUDING MATHEMATICAL OPERATION ON MASKS - Methods, apparatuses, and articles associated with SIMD adding two integers are disclosed. In embodiments, a method may include element-wise SIMD adding corresponding elements of a first SIMD-sized integer (A) and a second SIMD-sized integer (B) to generate a SIMD-sized integer result (R) and a carry bit. A may have an integer size (SizeA), while B may have an integer size (SizeB). The addition, in response to SizeA greater than SizeB, may further include updating R and the carry bit in view of one or more elements of A that do not have corresponding element or elements of B. Further, element-wise SIMD adding may include performing one or more mathematical operations on first one or more masks, with the first one or more masks interpreted as integers, and interpreting one or more integer results of the one or more mathematical operations as second one or more masks. | 01-23-2014 |

20140032622 | Parameterized Digital Divider - A method of performing digital division includes right-shifting a divider to provide a temporary divider, subtracting the temporary divider from a temporary dividend to provide a difference, determining the temporary dividend based on at least one of a dividend and the difference, and left-shifting a quotient based on the difference. A corresponding computer-readable medium and device are provided. A system to perform digital division includes a counter and a division circuit. The counter provides a count, and the division circuit is operatively coupled to the counter. The division circuit divides a dividend by a divider to provide a quotient in response to the counter. At least one of the counter and division circuit is configured to accept at least one of the count, dividend, divider, and quotient with a configurable bit-width. | 01-30-2014 |

20140059098 | DATA SIMILARITY CALCULATION METHOD AND DATA SIMILARITY CALCULATION APPARATUS - There is provided a data similarity calculation method. The method includes: (a) acquiring a first waveform; (b) storing time series data; (c) converting the stored time series data into a waveform on two-dimensional coordinates, wherein the two-dimensional coordinates consists of a time axis and an a value axis representing values of the time series data, and the time axis is orthogonal to the value axis; (d) shifting the converted waveform in both directions of the time axis and the value axis so as to generate a second waveform; (e) calculating a similarity between the first waveform and the second waveform; and (f) extracting a shift amount in the direction of the time axis and a shift amount in the direction of the value axis when the similarity is the highest by repeatedly performing steps (d) and (e). | 02-27-2014 |

20160070539 | OPTIMIZED MULTI-PRECISION DIVISION - In an embodiment, multi-precision numbers A and B are accessed from a storage device (e.g., a memory array), where A is a dividend and B is a divisor. A multi-precision division operation is iteratively performed on the numbers A and B including: performing a multi-precision subtraction operation on A and B during a first iteration of the multi-precision division operation; performing a multi-precision addition operation on A and B during a second iteration of the multi-precision division operation as a result of a determination that a final borrow occurred during the subtraction operation; and performing a multi-precision addition operation on A and B after a final iteration of the multi-precision division operation. | 03-10-2016 |

20120265794 | MONTGOMERY MULTIPLICATION CIRCUIT - A circuit for calculating a sum of products, each product having a q-bit binary operand and a k-bit binary operand, where k is a multiple of q,includes a q-input carry-save adder (CSA); a multiplexer ( | 10-18-2012 |

20110225222 | METHODS AND APPARATUSES FOR CORDIC PROCESSING - A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array. | 09-15-2011 |

20110213818 | SHIFT SIGNIFICAND OF DECIMAL FLOATING POINT DATA - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including a shift significand instruction. | 09-01-2011 |

20110264721 | SIGNAL PROCESSING BLOCK FOR A RECEIVER IN WIRELESS COMMUNICATION - A QRD processor for computing input signals in a receiver for wireless communication relies upon a combination of multi-dimensional Givens Rotations, Householder Reflections and conventional two-dimensional (2D) Givens Rotations, for computing the QRD of matrices. The proposed technique integrates the benefits of multi-dimensional annihilation capability of Householder reflections plus the low-complexity nature of the conventional 2D Givens rotations. Such integration increases throughput and reduces the hardware complexity, by first decreasing the number of rotation operations required and then by enabling their parallel execution. A pipelined architecture is presented ( | 10-27-2011 |

20110153701 | IMPLEMENTATION OF ARBITRARY GALOIS FIELD ARITHMETIC ON A PROGRAMMABLE PROCESSOR - A method for a Galois Field multiply includes executing first and second instructions. The first instruction includes receiving a first input, such as a first variable, receiving a second input, such as a second variable, performing a polynomial multiplication over GF(2 | 06-23-2011 |

20110153700 | Method and apparatus for performing a shift and exclusive or operation in a single instruction - Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value. | 06-23-2011 |

20080222227 | Design Structure for a Booth Decoder - A design structure for a Booth decoder is provided. The Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal output. A third circuit is used to generate an invert control signal output. The first and second circuits receive the three-bit block as an input and generate their respective outputs based on the setting of each of the bits. The third circuit receives only the most significant bit of the three-bit block as its input and generates an invert signal output based on the setting of the most significant bit. In each of these circuits, the number of complex gates and transistors is minimized thereby reducing gate delay and power consumption in generating the control signals for performing a Booth multiplication operation. | 09-11-2008 |

20080222226 | Bandwidth efficient instruction-driven multiplication engine - Multiplication engines and multiplication methods are provided for a digital processor. A multiplication engine includes multipliers, each receiving a first operand and a second operand; a local operand register having locations to hold the first operands for respective multipliers; a first operand bus coupled to the local operand register to supply the first operands from a compute register file to the local operand register; a second operand bus coupled to the plurality of multipliers to supply one or more of the second operands from the compute register file to respective multipliers; and a control unit responsive to a digital processor instruction to supply the first operands from the local operand register to respective multipliers, to supply the second operands from the compute register file to respective multipliers on the second operand bus and to multiply the first operands by the respective second operands in the respective multipliers, wherein one or more of the first operands in the local operand register are reused by the multipliers in two or more multiplication operations. | 09-11-2008 |

20090193065 | Deterministic random number generator for cryptography and digital watermarking - A deterministic random number generator comprising: | 07-30-2009 |

20080243975 | Sensor driving circuit - A sensor driving circuit includes a shift circuit that outputs clock signals the high level period of each of which is limited to a predetermined period in one pulse period and whose high level periods are shifted by one pulse period from each other, to respective capacitance elements each of which changes in the distance of its electrodes to change its capacitance value in accordance with the magnitude of a force or moment. The circuit further includes addition signal outputting sections that output addition signals having their duty ratios corresponding to the capacitance values of the respective capacitance elements; and subtraction signal outputting sections that receive as their inputs the addition signals output from the addition signal outputting sections, and output subtraction signals in which the high and low levels are inverted only during the pulse periods including the high level periods of the respective addition signals. | 10-02-2008 |

20090070394 | CANONICAL SIGNED DIGIT MULTIPLIER - A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected constant value. Each of the multiplexers has a plurality of inputs, and is connected to receive the input data value, the inverse of the input data value, and all zeros on said inputs, and it is controlled such that it outputs either the input data value, the inverse of the input data value, or all zeros, depending on the values of the respective pair of bits of the selected constant value. Variable shift blocks are each connected to receive an input from a respective one of said multiplexers, and are each adapted to shift their received input by a first bit shift value or a second bit shift value, depending on the values of the respective pair of bits of the selected constant value, wherein the first bit shift value and the second bit shift value differ by 1. The multiplier also includes combination circuitry, for receiving the outputs from the plurality of shift blocks, and for combining the outputs from the plurality of shift blocks and applying further bit shifts, to form an output value equal to the result of multiplying the input data value by the selected constant value. | 03-12-2009 |

20080307023 | METHOD AND APPARATUS FOR ADJUSTING REFERENCE FREQUENCY - The invention discloses a method for adjusting a reference frequency. First, a training signal is received based on the reference frequency. Then, a target region of the training signal is divided by an original training sequence so that a quotient polynomial is generated. Afterward, the quotient polynomial is divided by a predetermined polynomial so that a remainder polynomial is generated. Finally, the reference frequency is adjusted based on the remainder polynomial. | 12-11-2008 |

20090177724 | Processor and Method of Determining a Normalization Count - In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand. | 07-09-2009 |

20090138534 | Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor - Microprocessor shifter circuits utilizing butterfly and inverse butterfly circuits, and control circuits therefor, are provided. The same shifter circuits can also perform complex bit manipulations at high speeds, including butterfly and inverse butterfly operations, parallel extract and deposit operations, group operations, mix operations, permutation operations, as well as instructions executed by existing microprocessors, including shift right, shift left, rotate, extract, deposit and multimedia mix operations. The shifter circuits can be provided in various combinations to provide microprocessor functional units which perform a plurality of bit manipulation operations. | 05-28-2009 |

20090172053 | ARITHMETIC APPARATUS FOR MULTI-FUNCTION UNIT AND METHOD - An arithmetic apparatus for a multi-function unit and a method integrates all operations which are necessary to the GPU (graphics processing unit) with one operational device to decrease the area and power of the hardware and to control all operations except a matrix-vector multiplication to achieve a single-cycle throughput and to control a matrix-vector multiplication to achieve a 2-cycle throughput. Thus, the whole power consumption and the size and the efficiency of 3 dimensional graphics systems for the embedded systems such as the cell phone or Personal Digital Assistant can be improved as the GPU can be small-sized and advanced. | 07-02-2009 |

20080270500 | COMPOSITION OF DECIMAL FLOATING POINT DATA, AND METHODS THEREFOR - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. | 10-30-2008 |

20080256150 | Three-path fused multiply-adder circuit - A three-path floating-point fused multiply-adder is disclosed. The fused multiply-adder is for the single instruction execution of (A×B)+C. The three-path fused multiply-adder is based on a dual-path adder and reduces latency significantly by operating on case data in parallel and by reducing component bit size. The fused multiply-adder is a common serial fused multiply-adder that reuses floating-point adder (FPA) and floating-point multiplier (FPM) hardware, allowing single adds, single multiplies, and fused multiply-adds to execute at maximum speed. | 10-16-2008 |

20080208940 | RECONFIGURABLE CIRCUIT - A reconfigurable circuit including a multiplier for multiplying a value, an accumulator for cumulatively adding said multiplied value and a round-off processing unit for rounding off said cumulatively added value; wherein said multiplier, said accumulator and said round-off processing unit are disposed within a single processing element and said accumulator provides an output at a timing according to a control signal. | 08-28-2008 |

20080243974 | ELECTRONIC DATA SHIFT DEVICE, IN PARTICULAR FOR CODING/DECODING WITH AN LDPC CODE - The electronic shift device includes N inputs and N outputs, a configurable barrel shifter connected between the N inputs and the N outputs. A second shifter is arranged and connected between some of the outputs of the barrel shifter and some of the N outputs according to different predetermined organizations of data that can be received simultaneously on at least some of the N inputs. The second shifter is configurable so that, for a relevant organization and regardless of the desired shift value compatible with the organization, the corresponding input data are delivered to predetermined outputs. A first controller is able to configure the barrel shifter according to the desired shift value and a second controller is able to configure the second shifter according to the organization of the data that can actually be received and according to the desired shift value. | 10-02-2008 |