Entries |
Document | Title | Date |
20080280447 | SPIN ON GLASS (SOG) ETCH IMPROVEMENT METHOD - A system and method of preventing pattern lifting during a trench etch/clean process is disclosed. A first layer comprising a first dip is formed over a first via pattern. A trench resist layer is formed. The trench resist layer is patterned with a trench reticle to produce a second via pattern in the trench resist layer over the first via pattern. A photo resist over the first via pattern is opened during a trench processing. Thus, an additional pattern added on a trench pattern reticle is used to open, i.e., remove resist over, a huge via feature area causing under layer dip. | 11-13-2008 |
20080280448 | METHOD FOR MANUFACTURING GATE OXIDE LAYER WITH DIFFERENT THICKNESSES - A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region. | 11-13-2008 |
20080286973 | METHOD FOR FORMING SEMICONDUCTOR FINE-PITCH PATTERN - A method for forming a fine-pitch pattern on a semiconductor substrate is provided. The method includes patterning the semiconductor substrate to form a plurality of fine lines, forming a thermal oxide layer on the fine lines, polishing the thermal oxide layer to expose a top surface of the fine lines; etching the fine lines using the thermal oxide layer as a mask to expose first portions of the semiconductor substrate, etching a central bottom portion of the thermal oxide layer to expose second portions of the semiconductor substrate, and etching the semiconductor substrate using the etched thermal oxide layer as a mask. | 11-20-2008 |
20080286974 | Etching solution for multiple layer of copper and molybdenum and etching method using the same - An etching solution for a multiple layer of copper and molybdenum includes: about 5% to about 30% by weight of a hydrogen peroxide; about 0.5% to about 5% by weight of an organic acid; about 0.2% to about 5% by weight of a phosphate; about 0.2% to about 5% by weight of a first additive having nitrogen; about 0.2% to about 5% by weight of a second additive having nitrogen; about 0.01% to about 1.0% by weight of a fluoric compound; and de-ionized water making a total amount of the etching solution 100% by weight. | 11-20-2008 |
20080305639 | DUAL DAMASCENE PROCESS - A method and system for forming dual damascene structures in a semiconductor package. In one embodiment, the method includes forming an intermediate dielectric layer on a bottom stop layer; forming an ashing removable dielectric layer on the intermediate dielectric layer; forming a patterned photoresist layer above the ashing removable dielectric layer in the semiconductor structure; and defining an in-situ hard mask in the ashing removable dielectric layer having an opening with a profile selected from the group consisting of a via, a trench, or a combination thereof. The profile of the in-situ mask preferably is capable of being transferred to the intermediate dielectric layer by etching. | 12-11-2008 |
20080305640 | METHOD FOR PREPARING TRENCH POWER TRANSISTORS - A method for preparing a trench power transistor comprises the steps of forming a mask layer having a plurality of openings on a semiconductor substrate, removing a portion of the semiconductor substrate under the openings to form a plurality of trenches in the semiconductor substrate in an array manner, coating a photoresist layer covering the surface of the mask layer, patterning the photoresist layer, and removing a portion of the mask layer not covered by the photoresist layer to form a mask block exposing a portion of the semiconductor substrate in the array region. | 12-11-2008 |
20090004868 | Amorphous silicon oxidation patterning - In one embodiment, a method comprises forming a sacrificial amorphous silicon layer on a semiconductor substrate, forming a hardmask on the amorphous silicon layer, etching one or more lines in the sacrificial amorphous silicon layer, growing oxide structures on the amorphous silicon layer, and forming a trench in the semiconductor substrate between the oxide structures. | 01-01-2009 |
20090017630 | Methods For Forming Contacts For Dual Stress Liner CMOS Semiconductor Devices - Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL. | 01-15-2009 |
20090075483 | ULTRA LIGHTWEIGHT PHOTOVOLTAIC DEVICE AND METHOD FOR ITS MANUFACTURE - An ultra lightweight semiconductor device such as a photovoltaic device is fabricated on a non-etchable barrier layer which is disposed upon an etchable substrate. The device is contacted with an appropriate etchant for a period of time sufficient to remove at least a portion of the thickness of the substrate. The barrier layer prevents damage to the photovoltaic material during the etching process. Photovoltaic devices fabricated by this method have specific power levels in excess of 300 w/kg. | 03-19-2009 |
20090104779 | Method of producing phase change memory device - An area where a lower electrode is in contact with a variable resistance material needs to be reduced to lower the power consumption of a variable resistance memory device. The present invention is to provide a method of producing a variable resistance memory element whereby the lower electrode can be formed smaller. Combining an anisotropic etching process with an isotropic etching process enables the lower electrode to be formed smaller. | 04-23-2009 |
20090124085 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAS A LENGTHENED CHANNEL LENGTH - The present invention discloses a method for forming a semiconductor device. The method includes providing a substrate; forming at least one first opening in the substrate to a predetermined depth and exposing a sidewall of the substrate in the first opening; forming a spacer on the sidewall and exposing a portion of the substrate in the bottom of the first opening; etching the exposed substrate in the bottom of the first opening by using the spacer as a mask to form a second opening; forming an isolation layer in the second opening and a portion of the first opening; forming a gate dielectric layer on the surface of the substrate; and forming a conductive layer covering the substrate. | 05-14-2009 |
20090130853 | METHOD FOR FABRICATING A DEEP TRENCH IN A SUBSTRATE - The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate. | 05-21-2009 |
20090156009 | Method for manufacturing semiconductor device - Provided is a method of manufacturing a semiconductor device capable of providing a stable trench depth, including: forming, on a semiconductor substrate, a first film having a high etching selectivity with respect to the semiconductor substrate; forming, on the first film, a second film having a high etching selectivity with respect to the first film; etching a region of a part of the second film and the first film to expose a surface of the semiconductor substrate in the region; and etching the exposed surface of the semiconductor substrate to form a trench. | 06-18-2009 |
20090186485 | SUB-LITHOGRAPHIC PRINTING METHOD - A method to form sub-lithographic trench structures in a substrate and an integrated circuit comprising sub-lithographic trench structures in a substrate. The method includes forming sets of trenches with a lithographic mask and filling the sets of trenches with sets of step spacer blocks comprising two alternating spacer materials which are separately removable from each other. In one embodiment, the trench structures formed are one-nth the thickness of the lithographic mask's feature size. The size of the trench structures being dependent on the thickness and number of spacer material layers used to form the set of step spacer blocks. The number of spacer material layers being n/2 and the thickness of each spacer material layer being one-nth of the lithographic mask's feature size. | 07-23-2009 |
20090186486 | METHOD OF FORMING DAMASCENE PATTERNS OF SEMICONDUCTOR DEVICES - A method of forming damascene patterns of semiconductor devices comprise forming a first insulating layer and contact plugs, formed in the first insulating layer, over a semiconductor substrate, forming an etch barrier layer and a second insulating layer over the first insulating layer, forming damascene patterns in the second insulating layer, forming a mask layer over the second insulating layer of other region except a region in which the contact plugs are formed so that the damascene patterns are exposed through the region in which the contact plugs are formed, removing the etch barrier layer under the exposed damascene patterns using an etching process employing the mask layer, and removing the mask layer. | 07-23-2009 |
20090317975 | METHOD FOR FORMING AN 0N-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE - A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided and a hermetically sealed gap is formed therein to provide electro-static discharge protection for an integrated circuit. | 12-24-2009 |
20100009542 | SUBSTRATE PROCESSING METHOD - A substrate processing method that forms an opening, which has a size that fills the need for downsizing a semiconductor device and is to be transferred to an amorphous carbon film, in a photoresist film of a substrate to be processed. Deposit is accumulated on a side wall surface of the opening in the photoresist film using plasma produced from a deposition gas having a gas attachment coefficient S of 0.1 to 1.0 so as to reduce the opening width of the opening. | 01-14-2010 |
20100048023 | Methods for Manufacturing a Structure on a Substrate and Intermediate Product - Among other implementations, a method for manufacturing a structure on a substrate is described wherein at least one carrier structure is positioned on a substrate and at least one spacer structure is positioned on the sidewalls of the at least one carrier structure, the at least one carrier structure or the at least one spacer structure is subsequently removed and before or after the removal of the at least one spacer structure or the removal of the at least one carrier structure, an etch resistant layer is positioned in at least one of the following regions: a region not covered by the at least one carrier structure, a region not covered by the at least one spacer structure and a region not covered by the at least one carrier structure and the at least one spacer structure. | 02-25-2010 |
20100048024 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of semiconductor device comprises: sequentially laminating a third mask layer, a second mask layer, and a first mask layer on a processed layer; forming a fourth mask layer on the first mask layer; processing the first mask layer so as to have a line pattern form using the fourth mask layer as a mask; removing the first mask layer; processing the second mask layer so as to have a pair of line pattern forms using the pair of sidewall layers as a mask; forming a fifth mask layer on the third mask layer; forming a pair of opening portions in the third mask layer using the fifth mask layer as a mask; and forming a pair of groove portions on the processed layer using the third mask layer as a mask. | 02-25-2010 |
20100105210 | Method of making pillars using photoresist spacer mask - A method of making a device includes forming a first hard mask layer over an underlying layer, forming first features over the first hard mask layer, forming a first spacer layer over the first features, etching the first spacer layer to form a first spacer pattern and to expose top of the first features, removing the first features, patterning the first hard mask using the first spacer pattern as a mask to form first hard mask features, removing the first spacer pattern. The method also includes forming second features over the first hard mask features, forming a second spacer layer over the second features, etching the second spacer layer to form a second spacer pattern and to expose top of the second features, removing the second features, etching the first hard mask features using the second spacer pattern as a mask to form second hard mask features, and etching at least part of the underlying layer using the second hard mask features as a mask. | 04-29-2010 |
20100120253 | Post Etch Dielectric Film Re-Capping Layer - Methods for improving post etch in via or trench formation in semiconductor devices. A preferred embodiment comprises forming a re-capping layer over a dielectric film following an initial etch to form a feature in the dielectric film, followed by additional etch and etch back processing steps. The re-capping method provides protection for underlying films and prevents film damage post etch. Uniform feature profiles are maintained and critical dimension uniformity is obtained by use of the methods of the invention. The time dependent dielectric breakdown performance is increased. | 05-13-2010 |
20100120254 | Passivation Layer for a Circuit Device and Method of Manufacture - According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter | 05-13-2010 |
20100184295 | MULTIPLE DEPTH SHALLOW TRENCH ISOLATION PROCESS - A method for manufacturing a semiconductor die may have the steps of:—Providing a semiconductor substrate;—Processing the substrate to a point where shallow trench isolation (STI) can be formed;—Depositing at least one underlayer having a predefined thickness on the wafer;—Depositing a masking layer on top of the underlayer;—Shaping the masking layer to have areas of predefined depths;—Applying a photolithograthy process to expose all the areas where the trenches are to be formed; and—Etching the wafer to form silicon trenches wherein the depth of a trench depends on the location with respect to the masking layer area. | 07-22-2010 |
20100197141 | NOVEL SELF-ALIGNED STATIC RANDOM ACCESS MEMORY (SRAM) ON METAL GATE - A method for fabricating an integrated circuit providing an enlarged contact process window while reducing device size is disclosed. The method comprises providing a substrate including a first region and a second region, the first and second regions having one or more gate structures including a dummy gate layer; removing the dummy gate layer from at least one of the one or more gate structures in the first and second regions to form one or more trenches in the first and second regions; filling the one or more trenches in the first and second regions with a conductive layer; selectively etching back the conductive layer of the one or more gate structures in the second region of the substrate; forming a protective layer over the etched back conductive layer of the one or more gate structures in the second region; and forming one or more contact openings in the first and second regions. | 08-05-2010 |
20100285667 | METHOD TO PRESERVE THE CRITICAL DIMENSION (CD) OF AN INTERCONNECT STRUCTURE - A method of restoring the dielectric constant, loss and leakage of an exposed surface of a low k dielectric material caused during dry etching of the low k dielectric material prior to the removal of the damaged layer by wet etch chemistries is provided. Once restored, the surface of the dielectric material will no longer be susceptible to removal by the highly anisotropic wet etching process. However, the wet etch will still pose an advantage as it can remove any etch/ash residues at the bottom of a feature formed into the low k dielectric material. | 11-11-2010 |
20100304569 | METHOD OF FORMING A CONTACT HOLE - A method of forming a contact hole is provided. A pattern is formed in a photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a first opening. Another pattern is formed in another photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a second opening. The pattern having the first, and second openings is exchanged into the interlayer dielectric layer, and etching stop layer to form the contact hole. The present invention has twice exposure processes and twice etching processes to form the contact hole having small distance. | 12-02-2010 |
20100317195 | METHOD FOR FABRICATING AN APERTURE - A method for fabricating an aperture is disclosed. The method includes the steps of: depositing a dielectric layer and a hard mask on surface of a semiconductor substrate; patterning the hard mask by forming an aperture in the hard mask; utilizing a gas containing C | 12-16-2010 |
20110003479 | METHODS OF MAKING SELF-ALIGNED NANO-STRUCTURES - A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques. | 01-06-2011 |
20110014792 | FIN MASK AND METHOD FOR FABRICATING SADDLE TYPE FIN USING THE SAME - A fin mask for forming saddle type fins in each of active regions formed in an island shape having a certain size with a major axis and a minor axis includes a first fin mask of a line type, and a second fin mask of an island type, wherein the first fin mask and the second fin mask in combination expose saddle type fin regions and cover ends of the neighboring active regions along the major axis. | 01-20-2011 |
20110027998 | Method of Manufacturing A Nano Structure By Etching, Using A Substrate Containing Silicon - A method of manufacturing a nano structure by etching, using a substrate containing Si. A focused Ga ion or In ion beam is irradiated on the surface of the substrate containing Si. The Ga ions or the In ions are injected while sputtering away the surface of the substrate so that a layer containing Ga or In is formed on the surface of the substrate. Dry etching by a gas containing fluorine (F) is performed with the layer containing the Ga or the In formed on the surface of the substrate taken as an etching mask, and the nano structure is formed having a pattern of at least 2 μm tin in depth according to a predetermined line width. | 02-03-2011 |
20110034030 | METHOD OF FORMING MINUTE PATTERNS IN SEMICONDUCTOR DEVICE USING DOUBLE PATTERNING - A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns. | 02-10-2011 |
20110070738 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask. | 03-24-2011 |
20110117744 | PATTERN FORMING METHOD AND PATTERN FORMING APPARATUS - According to one embodiment, a first pattern is formed at first pattern coverage in a first region on a film to be processed and a second pattern is formed at second pattern coverage in a second region on the film to be processed. During the formation of the second pattern, a second film formed of a block copolymer containing film or the like is formed on the film to be processed and is self-assembled. A plurality of kinds of polymers contained in the self-assembled second film are selectively removed to leave at least one kind of polymer to form the second pattern to bring the second coverage close to the first pattern coverage. | 05-19-2011 |
20110195576 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer. | 08-11-2011 |
20110201204 | Precisely Tuning Feature Sizes on Hard Masks Via Plasma Treatment - Methods are provided for fabricating devices. A first layer is formed. A hardmask on the first layer is formed. Features on the hardmask are patterned. The sizes of features on the hardmask are reduced by applying a plasma treatment process to form reduced size features. Also, the size of features on the hardmask can be enlarged to form enlarged size features by applying the plasma treatment process and/or removing the oxidized part of the feature during plasma treatment process. Another method may include a first layer formed on a substrate and a second layer formed on the first layer. First features are patterned on the first layer, and second features are patterned on the second layer. A size of second features on the second layer is closed due to the different oxidation rate of the two layers during the plasma treatment process, to form a self-sealed channel and/or self-buried trench. | 08-18-2011 |
20110201205 | METHOD OF FORMING A DEEP TRENCH IN A SUBSTRATE - Methods of forming deep trenches in substrates are described. A method includes providing a substrate with a patterned film disposed thereon, the patterned film including a trench having a first width and a pair of sidewalls, the trench exposing the top surface of the substrate. The method also includes forming a material layer over the patterned film and conformal with the trench. The method also includes etching the material layer to form sidewall spacers along the pair of sidewalls of the trench, the sidewall spacers reducing the first width of the trench to a second width. The method also includes etching the substrate to form a deep trench in the substrate, the deep trench undercutting at least a portion of the sidewall spacers. | 08-18-2011 |
20110207329 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a mask layer on a material layer and forming a capping layer on the mask layer. The capping layer is a boron-containing layer with a higher resistance to an etching reaction of patterning process of the material layer. By adapting the boron-containing layer as the capping layer, the thickness of the mask layer can be thus reduced. Hence, a better gap filling for forming an interconnect metallization in the material layer could be achieved as well. | 08-25-2011 |
20110244688 | METHOD OF PRODUCING MASK - According to one embodiment, a method of producing a mask includes: a step of forming a pattern on a substrate; a step of forming a first film that covers the top surface and side surface of the pattern and contains a first material; a step of forming a second film containing a second material on the first film; a step of performing anisotropic etching of the first and second films in a way that forms a sidewall layer including the first and second films on the side surface of the pattern and removes the first and second films on any location other than the sidewall layer; a step of performing isotropic etching of the first film of the sidewall layer; and a step of removing the pattern. | 10-06-2011 |
20110244689 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first mask pattern on a substrate by using a material including a polymer having a protection group de-protectable by an acid, the first mask pattern having a plurality of holes; forming a capping layer on an exposed surface of the first mask pattern, the capping layer including an acid source; diffusing the acid source into the first mask pattern so that the protection group becomes de-protectable from the polymer in the first mask pattern; forming a second mask layer on the capping layer, the second mask layer separate from the first mask pattern and filling the plurality of holes in the first mask pattern; and forming a plurality of second mask patterns in the plurality of holes by removing the capping layer and the first mask pattern. | 10-06-2011 |
20110256726 | PLASMA ACTIVATED CONFORMAL FILM DEPOSITION - Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film. | 10-20-2011 |
20110275218 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a hard mask layer on a material layer and forming a capping layer on the hard mask layer. The capping layer does not react with oxygen gas during a photoresist ashing process. The capping layer is patterned by using a first resist pattern and a second resist pattern as etch masks. After the capping layer is patterned, the hard mask layer is patterned by using the patterned capping layer as an etch mask. | 11-10-2011 |
20110281434 | Methods of Forming Patterned Photoresist Layers Over Semiconductor Substrates - This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is provided. An antireflective coating is formed over the semiconductor substrate. The antireflective coating has an outer surface. The outer surface is treated with a basic fluid. A positive photoresist is applied onto the outer surface which has been treated with the basic treating fluid. The positive photoresist is patterned and developed effective to form a patterned photoresist layer having increased footing at a base region of said layer than would otherwise occur in the absence of said treating the outer surface. Other aspects and implementations are contemplated. | 11-17-2011 |
20110294296 | Using edges of self-assembled monolayers to form narrow features - The present invention provides a method for manufacturing a structure over a semiconductor substrate. To form a trench, a patterned layer is formed on a portion of a substrate such that the patterned layer forms a target area located adjacent an edge of the patterned layer. A self-assembled monolayer (SAM) is coupled to the substrate up to the patterned layer, but excluded from the patterned layer. The substrate is then removed within the target area. A wire is formed in a similar fashion except that the first SAM is exchanged with a second SAM in the target area. Then either the substrate outside of the target area is removed, or conductive metal crystals are grown within the target area. Such structures may be advantageously used in the manufacture of a number of active or passive electronic devices, such as a field effect transistor. | 12-01-2011 |
20120021605 | SEMICONDUCTOR DEVICE PRODUCING METHOD - In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist. | 01-26-2012 |
20120021606 | PROCESS FOR PRODUCING TWO INTERLEAVED PATTERNS ON A SUBSTRATE - A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern. | 01-26-2012 |
20120064723 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING DUAL DAMASCENE PROCESS - A method for fabricating a semiconductor device using a dual damascene process is provided. The method includes forming a dielectric layer over a conductive layer, forming a via hole exposing the conducting layer by selectively etching the dielectric layer, projecting a portion of the dielectric layer at an edge of the via hole by selectively etching the dielectric layer to a first depth, and forming a trench by selectively etching the dielectric layer to a second depth, wherein the trench is overlapped with the via hole to form a dual damascene pattern. | 03-15-2012 |
20120077344 | METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described. | 03-29-2012 |
20120083126 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes forming a partition line pattern and a partition pad pattern connected to an end part of the partition line pattern over the semiconductor substrate. Spacer insulation layers are formed at sidewalls of the partition line pattern and the partition pad pattern. A gap-filling layer is formed between the spacer insulation layers. A first cutting mask pattern is formed to expose a connecting part between the partition line pattern and the partition pad pattern. The partition line pattern and the gap-filling layer adjacent to the spacer insulation layer are removed using the first cutting mask pattern as a mask. A second cutting mask pattern including a first pattern and a second pattern are formed. The spacer insulation layer is removed using the second cutting mask pattern as a mask to form a gate trench in the substrate. | 04-05-2012 |
20120094497 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - The present method includes: forming a device isolation region in a substrate dividing the device isolation region into first and second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer. | 04-19-2012 |
20120129350 | METHOD FOR REDUCING WORDLINE BRIDGE RATE - The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) etching a metal-silicide layer and a POLY layer via a hard mask, wherein the metal-silicide layer is disposed on the POLY layer; (b) forming a POLY recess in the POLY layer; and (c) forming a liner film covering the metal-silicide layer. | 05-24-2012 |
20120149205 | METHOD FOR FABRICATING SIDE CONTACT IN SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes etching a substrate to form a body separated by a trench, forming liner layers that cover sidewalls of the body, forming a sacrificial layer that fills the trench and exposes an upper sidewall of each liner layer, forming a hard mask pattern that covers a first one of the liner layers having the exposed upper sidewalls, forming a barrier layer to be selectively grown over the exposed upper sidewalls of a second one of the liner layers, removing the hard mask pattern, removing a part of the sacrificial layer to expose a lower sidewall of a first one of the liner layers, and removing the lower sidewall of the first one of the liner layers to form a side contact. | 06-14-2012 |
20120164836 | INTEGRATED CIRCUIT FABRICATION METHODS UTILIZING EMBEDDED HARDMASK LAYERS FOR HIGH RESOLUTION PATTERNING - Embodiments of a method for fabricating integrated circuits are provided. In one embodiment, the method includes the steps of depositing a dielectric layer over a semiconductor device, forming a plurality of trimmed hardmask structures at predetermined locations over the dielectric layer, embedding the plurality of trimmed hardmask structures in a surrounding hardmask layer, removing the plurality of trimmed hardmask structures to create a plurality of openings through the surrounding hardmask layer, and etching the dielectric layer through the plurality of openings to form a plurality of etch features therein. | 06-28-2012 |
20120171867 | METHOD FOR FABRICATING FINE PATTERN BY USING SPACER PATTERNING TECHNOLOGY - A method for fabricating a fine pattern includes forming a line-shaped partition pattern on an underlayer, adhering a first spacer to the sides of the partition pattern, dividing the first spacer into two line patterns where one line pattern has one end bent by selectively etching the first spacer portion with a division region, adhering a second spacer, which has a connection protrusion filling the division region and connecting to the partition pattern, to the outer side of the two line patterns, and selectively removing the two line patterns. | 07-05-2012 |
20120190204 | NON-CONFORMAL HARDMASK DEPOSITION FOR THROUGH SILICON ETCH - The present invention provides a method to form deep features in a stacked semiconductor structure. Deposition of a non-conformal hardmask onto a patterned topography can form a hardmask to protect all but recessed areas with minimal integration steps. The invention enables etching deep features, even through multiple BEOL layers, without multiple additional process steps. | 07-26-2012 |
20120202349 | Photo-imageable Hardmask with Dual Tones for Microphotolithography - Disclosed is a method of making polysiloxane and polysilsesquioxane based hardmask respond to radiations with positive tone and negative tone simultaneously. Unradiated films are insoluble in developers, showing positivity tone. Radiated films are insoluble in developers as well, showing negative tone. Only half-way radiated films are soluble in developers. The dual-tone photo-imageable hardmask produces splitted patterns. Compositions of dual-tone photo-imageable hardmask based on the chemistry of polysiloxane and polysilsesquioxanes are disclosed as well. Further disclosed are processes of using photo-imageable hardmasks to create precursor structures on semiconductor substrates with or without an intermediate layer. | 08-09-2012 |
20120214310 | WIGGLING CONTROL FOR PSEUDO-HARDMASK - A method for etching features in an etch layer. A conditioning for a patterned pseudo-hardmask of amorphous carbon or polysilicon disposed over the etch layer is provided, where the conditioning comprises providing a fluorine free deposition gas comprising a hydrocarbon gas, forming a plasma from the fluorine free deposition gas, providing a bias less than 500 volts, and forming a deposition on top of the patterned pseudo-hardmask. The etch layer is etched through the patterned pseudo-hardmask. | 08-23-2012 |
20120214311 | Process of Multiple Exposures With Spin Castable Films - Methods of multiple exposure in the fields of deep ultraviolet photolithography, next generation lithography, and semiconductor fabrication comprise a spin-castable methodology for enabling multiple patterning by completing a standard lithography process for the first exposure, followed by spin casting an etch selective overcoat layer, applying a second photoresist, and subsequent lithography. Utilizing the etch selectivity of each layer, provides a cost-effective, high resolution patterning technique. The invention comprises a number of double or multiple patterning techniques, some aimed at achieving resolution benefits, as well as others that achieve cost savings, or both resolution and cost savings. These techniques include, but are not limited to, pitch splitting techniques, pattern decomposition techniques, and dual damascene structures. | 08-23-2012 |
20120220131 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor memory device includes forming a photoresist layer on a substrate, performing an exposure process such by illuminating a first area of the photoresist layer with a first amount of a light and illuminating a second area of the photoresist layer with a light of a second amount smaller than the first amount, removing the first area of the photoresist layer to form a photoresist pattern, and forming a capping layer on a surface of the photoresist pattern. | 08-30-2012 |
20120225559 | CAVITY OPEN PROCESS TO IMPROVE UNDERCUT - A process of forming a MEMS device with a device cavity underlapping an overlying dielectric layer stack having an etchable sublayer over an etch-resistant lower portion, including: etching through at least the etchable sublayer of the overlying dielectric layer stack in an access hole to expose a lateral face of the etchable sublayer, covering exposed surfaces of the etchable sublayer by protective material, and subsequently performing a cavity etch. A cavity etch mask may cover the exposed surfaces of the etchable sublayer. Alternatively, protective sidewalls may be formed by an etchback process to cover the exposed surfaces of the etchable sublayer. Alternatively, the exposed lateral face of the etchable sublayer may be recessed by an isotropic etch, than isolated by a reflow operation which causes edges of an access hole etch mask to drop and cover the exposed lateral face of the etchable sublayer. | 09-06-2012 |
20120264306 | Method of Forming Opening on Semiconductor Substrate - The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer. | 10-18-2012 |
20120276744 | Patterning Method for High Density Pillar Structures - A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features. | 11-01-2012 |
20120282777 | METHOD FOR INCREASING ADHESION BETWEEN POLYSILAZANE AND SILICON NITRIDE - A method for increasing adhesion between polysilazane and silicon nitride is disclosed, comprising, providing a substrate comprising a trench, forming a silicon nitride liner layer on a bottom surface and a sidewall of the trench, performing a treating process to the silicon nitride liner layer for producing a hydrophilic surface with OH groups that can increase adhesion between the silicon nitride liner layer and a subsequently formed polysilazane coating layer, and forming a polysilazane coating layer into the trench and on the silicon nitride liner layer. | 11-08-2012 |
20120289050 | METHOD OF ETCHING TRENCHES IN A SEMICONDUCTOR SUBSTRATE UTILIZING PULSED AND FLUOROCARBON-FREE PLASMA - A method of etching trenches in a semiconductor substrate. A patterned hard mask is formed over a semiconductor substrate. Using the patterned hard mask as an etching mask, a plasma etching process is then carried out to etch trenches into the semiconductor substrate not covered by the patterned hard mask, wherein the plasma etching process employs a fluorocarbon-free plasma etching chemistry and is performed under a plasma pulse output mode. | 11-15-2012 |
20120289051 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. According to an embodiment, the method includes forming a layer to be etched on a semiconductor substrate, and forming a photoresist pattern on the layer to be etched. A block copolymer including a hydrophobic radical and a hydrophilic radical is formed in the photoresist pattern, and the block copolymer is assembled to allow a polymer having the hydrophobic radical to be formed in a pillar pattern within a polymer having the hydrophilic radical. The polymer having the hydrophobic radical is then selectively removed. | 11-15-2012 |
20120302068 | METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT - A method for manufacturing a semiconductor integrated circuit includes providing a substrate having at least a metal hard mask formed thereon. Subsequently a patterning step is performed to the metal hard mask to form a patterned metal hard mask and followed by performing a H | 11-29-2012 |
20120309196 | MANUFACTURING METHOD FOR DUAL DAMASCENE STRUCTURE - A manufacturing method for a dual damascene structure includes providing a substrate having a dielectric layer, a first hard mask layer and a second hard mask layer sequentially formed thereon, performing a first double patterning process to sequentially form a plurality of first trench openings and a plurality of second trench openings in the second hard mask layer, performing a second double patterning process to sequentially form a plurality of first via openings and a plurality of second via openings in the fist hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings. | 12-06-2012 |
20120309197 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES - A method of forming a semiconductor structure includes forming an opening in a substrate. A dielectric layer is formed and substantially conformal to the opening. A sacrificial structure is formed within the opening, covering a portion of the dielectric layer. A portion of the dielectric layer is removed by using the sacrificial structure as an etch mask layer. The sacrificial structure is removed. | 12-06-2012 |
20120309198 | USE OF SPECTRUM TO SYNCHRONIZE RF SWITCHING WITH GAS SWITCHING DURING ETCH - A method for etching features into an etch layer in a plasma processing chamber is provided. An optically timed deposition phase is provided comprising providing a flow of deposition phase gas, detecting the presence of deposition gas within the plasma processing chamber, providing RF energy for forming a plasma from the deposition phase gas in the plasma processing chamber, and stopping the flow of the deposition gas into the plasma processing chamber. An optically timed etching phase is provided, comprising providing a flow of an etch gas, detecting the presence of the etch gas within the plasma processing chamber, providing RF energy for forming a plasma from the etch gas in the plasma processing chamber, and stopping the flow of the etch gas into the plasma processing chamber. | 12-06-2012 |
20120309199 | MANUFACTURING METHOD FOR DUAL DAMASCENE STRUCTURE - A manufacturing method for a dual damascene structure first includes providing a substrate having at least a dielectric layer, a first hard mask layer, a first cap layer, a second hard mask layer, and a second cap layer sequentially formed thereon, performing a first double patterning process to form a plurality of first trench openings and second trench openings in the second cap layer and the second hard mask, and the first layer being exposed in bottoms of the first trench openings and the second trench openings, performing a second double patterning process to form a plurality of first via openings and second via openings in the first cap layer and the first hard mask layer, and transferring the first trench openings, the second trench openings, the first via openings, and the second via openings to the dielectric layer to form a plurality of dual damascene openings. | 12-06-2012 |
20120309200 | METHOD FOR FABRICATING A BOTTOM OXIDE LAYER IN A TRENCH - A method for fabricating a bottom oxide layer in a trench ( | 12-06-2012 |
20120309201 | CRITICAL DIMENSION REDUCTION AND ROUGHNESS CONTROL - A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer. | 12-06-2012 |
20120322267 | METHOD OF PATTERNING A SUBSTRATE - In various embodiments, a method of patterning a substrate may include: forming an auxiliary layer on or above a substrate and forming a plasma etch mask layer on or above the auxiliary layer, wherein the auxiliary layer is configured such that it may be removed from the substrate more easily than the plasma etch mask layer; patterning the plasma etch mask layer and the auxiliary layer such that at least a portion of the substrate is exposed; patterning the substrate by means of a plasma etch process using the patterned plasma etch mask layer as a plasma etch mask. | 12-20-2012 |
20130005151 | METHOD FOR FORMING CONTACT HOLES - In an exemplary method for forming contact holes, a substrate overlaid with an etching stop layer and an interlayer dielectric layer in that order is firstly provided. A first etching process then is performed to form at least a first contact opening in the interlayer dielectric layer. A first carbon-containing dielectric layer subsequently is formed overlying the interlayer dielectric layer and filling into the first contact opening. After that, a first anti-reflective layer and a first patterned photo resist layer are sequentially formed in that order overlying the carbon-containing dielectric layer. Next, a second etching process is performed by using the first patterned photo resist layer as an etching mask to form at least a second contact opening in the interlayer dielectric layer. | 01-03-2013 |
20130005152 | INCREASED DEPOSITION EFFICIENCY AND HIGHER CHAMBER CONDUCTANCE WITH SOURCE POWER INCREASE IN AN INDUCTIVELY COUPLED PLASMA (ICP) CHAMBER - Embodiments described herein generally relate to a substrate processing system and related methods, such as an etching/deposition method. The method comprises (A) depositing a protective layer on a first layer disposed on a substrate in an etch reactor, wherein a plasma source power of 4,500 Watts or greater is applied while depositing the protective layer, (B) etching the protective layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the protective layer, and (C) etching the first layer in the etch reactor, wherein the plasma source power of 4,500 Watts or greater is applied while etching the first layer, wherein a time for the depositing a protective layer (A) comprises less than 30% of a total cycle time for the depositing a protective layer (A), the etching the protective layer (B), and the etching the first layer (C). | 01-03-2013 |
20130012026 | METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE AND DRAIN REGIONS OF CMOS TRANSISTORS - A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer. | 01-10-2013 |
20130023122 | METHOD OF MULTIPLE PATTERNING OF A LOW-K DIELECTRIC FILM - Methods of multiple patterning of low-k dielectric films are described. For example, a method includes forming and patterning a first mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. A second mask layer is formed and patterned above the first mask layer. A pattern of the second mask layer is transferred at least partially into the low-k dielectric layer by modifying first exposed portions of the low-k dielectric layer with a first plasma process and removing the modified portions of the low-k dielectric layer. Subsequently, a pattern of the first mask layer is transferred at least partially into the low-k dielectric layer by modifying second exposed portions of the low-k dielectric layer with a second plasma process and removing the modified portions of the low-k dielectric layer. | 01-24-2013 |
20130023123 | METHOD OF REMOVING A PHOTORESIST FROM A LOW-K DIELECTRIC FILM - Methods of removing photoresists from low-k dielectric films are described. For example, a method includes forming and patterning a photoresist layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Trenches are formed in the exposed portions of the low-k dielectric layer. A plurality of process cycles is performed to remove the photoresist layer. Each process cycle includes forming a silicon source layer on surfaces of the trenches of the low-k dielectric layer, and exposing the photoresist layer to an oxygen source to form an Si—O-containing layer on the surfaces of the trenches of the low-k dielectric layer and to remove at least a portion of the photoresist layer. | 01-24-2013 |
20130034964 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The present invention discloses a method of manufacturing a semiconductor device. In order to form a trench with a smaller width, patterns of various monomers are formed by utilizing self-assembly characteristics of a block copolymer comprising various monomers. A metal or metal nitride is deposited on a surface of the block copolymer, the metal or metallic nitride selectively depositing due to a preferential chemical affinity between various monomers and the metal or metal nitride. After reaching a certain thickness, the metal or metal nitride layer begins to grow laterally. Deposition can be stopped by controlling deposition time so that the metal or metal nitride layer grows laterally but does not completely cover the surface of the block copolymer. Etching is then conducted using the metal or metal nitride layer as a mask to obtain a trench with a very small width. | 02-07-2013 |
20130040463 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A mask layer is formed by: a step in which a first photoresist layer is formed, exposed, and developed on a substrate, thereby forming a first photoresist pattern; a step in which the first photoresist pattern is made insoluble; a step in which a second photoresist layer is formed, exposed, and developed on top of the first photoresist layer, thereby forming a second photoresist pattern that intersects the first photoresist pattern; a step in which the second photoresist pattern is made insoluble; and a step in which a third photoresist layer is formed, exposed, and developed on top of the first and second photoresist patterns, thereby forming a third photoresist pattern. | 02-14-2013 |
20130040464 | METHOD OF PATTERNING A LOW-K DIELECTRIC FILM - Methods of patterning low-k dielectric films are described. | 02-14-2013 |
20130052831 | METHOD OF PATTERNING HARD MASK LAYER FOR DEFINING DEEP TRENCH - A method of patterning a hard mask layer for defining a deep trench is described. A substrate formed with an isolation structure therein is provided. A hard mask layer is formed over the substrate provided. A patterned photoresist layer is formed over the hard mask layer, having therein a deep-trench opening pattern over the isolation structure. An etching gas not containing hydrogen is used to etch the hard mask layer with the patterned photoresist layer as a mask and thereby transfer the deep-trench opening pattern to the hard mask layer. | 02-28-2013 |
20130059442 | METHOD FOR ADJUSTING TRENCH DEPTH OF SUBSTRATE - A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer. | 03-07-2013 |
20130059443 | REDUCTION OF ETCH MICROLOADING FOR THROUGH SILICON VIAS - A method of making a support structure is provided. The method includes depositing a photoresist layer on a substrate of the support structure and patterning the photoresist layer. The method further includes etching the patterned photoresist layer. Etching the patterned photoresist includes forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate. Etching the patterned photoresist further includes forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate. A difference in cross-sectional area between TSVs in the first group of TSVs and TSVs in the second group of TSVs is less than 10%, and the first electrical interface is separated from the thermal interface. | 03-07-2013 |
20130078813 | PATTERN FORMING METHOD - The invention provides a pattern-formation process comprising a step of providing a substrate material having on a major surface a difficult-to-access recess formed by the presence of a 1 | 03-28-2013 |
20130115775 | METHOD OF FORMING WIDE TRENCHES USING A SACRIFICIAL SILICON SLAB - A method of forming an encapsulated wide trench includes providing a silicon on oxide insulator (SOI) wafer, defining a first side of a first sacrificial silicon slab by etching a first trench in a silicon layer of the SOI wafer, defining a second side of the first sacrificial silicon slab by etching a second trench in the silicon layer, forming a first sacrificial oxide portion in the first trench, forming a second sacrificial oxide portion in the second trench, forming a polysilicon layer above the first sacrificial oxide portion and the second sacrificial oxide portion, and etching the first sacrificial oxide portion and the second sacrificial oxide portion. | 05-09-2013 |
20130122709 | INVERSE SPACER PROCESSING - A method includes making a target feature of an integrated circuit by providing a main layer over a substrate, depositing a first mask layer over the main layer, patterning the first mask layer, forming sidewall spacers with a width (w) in adjoining sidewalls of the patterned first mask layer and exposing a top area of the patterned first mask layer, selectively removing the first mask layer and exposing a portion of the main layer between the sidewall spacers, depositing a second mask layer over the main layer between the sidewall spacers, selectively removing the sidewall spacers to form an opening and exposing another portion of the main layer in the opening, etching the main layer through the opening to form the target feature. | 05-16-2013 |
20130130502 | MICROMECHANICAL MEMBRANES AND RELATED STRUCTURES AND METHODS - Micromechanical membranes suitable for formation of mechanical resonating structures are described, as well as methods for making such membranes. The membranes may be formed by forming cavities in a substrate, and in some instances may be oxidized to provide desired mechanical properties. Mechanical resonating structures may be formed from the membrane and oxide structures. | 05-23-2013 |
20130137270 | METHOD FOR FORMING CONTACT HOLE - A method for forming contact holes includes following steps. A substrate including a dense region and an isolation region is provided. A material layer is formed on the substrate. Sacrificed patterns are formed on the material layer in the dense region, wherein there is a first opening between the two adjacent sacrificed patterns. A spacer is formed on each of two sides of each of the sacrificed patterns, wherein the spacers are separated from each other. The sacrificed patterns are removed to form a second opening between two adjacent spacers. A planar layer is formed to fill up the second openings. A first slit is formed in the planar layer, wherein the first slit exposes a portion of the material layer under the second openings. The portion of the material layer exposed by the first slit is removed to form third openings in the material layer. | 05-30-2013 |
20130157467 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer. | 06-20-2013 |
20130217233 | Methods for Controlling Line Dimensions in Spacer Alignment Double Patterning Semiconductor Processing - Methods for forming uniformly spaced and uniformly shaped fine lines in semiconductor processes using double patterning. Dummy lines are formed over a substrate. Sidewall spacer material is deposited over the top and sides of each of the dummy lines. Etching is performed to remove the top surface sidewall spacer material from the tops of the dummy lines. The dummy material is removed by selective etching leaving the spacer material. A photolithographic mask is formed defining inner lines that are desired for a substrate etching step, and temporary lines outside of the desired lines. The temporary lines are partially masked. The temporary lines are partially removed while the inner desired lines are retained. A transfer etch process then patterns an underlying mask layer corresponding to the inner desired lines, and the mask layer is used for etching lines in an underlying semiconductor substrate. | 08-22-2013 |
20130217234 | CLEANING SOLUTION AND DAMASCENE PROCESS USING THE SAME - A cleaning solution is provided. The cleaning solution includes an aliphatic polycarboxylic acid, a chain sulfonic acid substantially less than 4 wt % and an amine containing buffer agent. | 08-22-2013 |
20130244436 | MASKING TECHNIQUES AND CONTACT IMPRINT RETICLES FOR DENSE SEMICONDUCTOR FABRICATION - A reticle comprising isolated pillars is configured for use in imprint lithography. In some embodiments, on a first substrate a pattern of pillars pitch-multiplied in two dimensions is formed in an imprint reticle. The imprint reticle is brought in contact with a transfer layer overlying a series of mask layers, which in turn overlie a second substrate. The pattern in the reticle is transferred to the transfer layer, forming an imprinted pattern. The imprinted pattern is transferred to the second substrate to form densely-spaced holes in the substrate. In other embodiments, a reticle is patterned by e-beam lithography and spacer formations. The resultant pattern of closely-spaced pillars is used to form containers in an active integrated circuit substrate. | 09-19-2013 |
20130252431 | Method of Forming Trench in Semiconductor Substrate - The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask. | 09-26-2013 |
20130260562 | METHODS FOR FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method may include forming first hard mask patterns and second hard mask patterns extending in a first direction and repeatedly and alternately arranged on a lower layer, forming third mask patterns extending in a second direction perpendicular to the first direction on the first and second hard mask patterns, etching the first hard mask patterns using the third mask patterns to form first openings, forming filling patterns filling the first openings and gap regions between the third mask patterns, forming spacers on both sidewalls of each of the filling patterns, after removing the third mask patterns, and etching the second hard mask patterns using the filling patterns and the spacers to form second openings. | 10-03-2013 |
20130273742 | METHOD OF FORMING CONNECTION HOLES - The present invention provides a method of forming connection holes. The method utilizes two different gases to perform two etching processes for the interlayer dielectric layer so as to form connection holes. The etching rate of the interlayer dielectric layer in the first etching process using the first etching gas is proportional to the size of the openings which defines the connection hole while the etching rate of the interlayer dielectric layer in the second etching process using the second etching gas is inversely related with size of the openings. According to the present invention, the first etching gas and the second etching gas compensate for each other to eliminate the loading effect, thus the connection holes are formed with almost the same depth. Therefore the damage of the etching stopper layer due to the high etching rate in the larger connection holes can be avoided, which prevents the excessive variation of the connecting resistance and expands the process window. | 10-17-2013 |
20130337650 | METHOD OF MANUFACTURING DUAL DAMASCENE STRUCTURE - A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings. | 12-19-2013 |
20130337651 | Double Patterning Strategy for Contact Hole and Trench in Photolithography - A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer. | 12-19-2013 |
20140004705 | METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE BY USING DOUBLE PATTERNING PROCESS WHICH USES ACID DIFFUSION | 01-02-2014 |
20140011363 | ETCHING METHOD - A metal mask having an etching pattern having a very high verticality is formed, and an etching shape having a very high verticality is formed by etching a semiconductor with the metal mask as a mask. | 01-09-2014 |
20140017897 | ULTRA HIGH SELECTIVITY DOPED AMORPHOUS CARBON STRIPPABLE HARDMASK DEVELOPMENT AND INTEGRATION - Embodiments of the present invention generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron containing amorphous carbon layer on a semiconductor substrate. In one embodiment, a boron-containing amorphous carbon film is disclosed. The boron-containing amorphous carbon film comprises from about 10 to 60 atomic percentage of boron, from about 20 to about 50 atomic percentage of carbon, and from about 10 to about 30 atomic percentage of hydrogen. | 01-16-2014 |
20140057440 | METHODS OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes first preliminary holes over an etch target, the first preliminary holes arranged as a plurality of rows in a first direction, forming dielectric patterns each filling one of the first preliminary holes, sequentially forming a barrier layer and a sacrificial layer on the dielectric patterns, forming etch control patterns between the dielectric patterns, forming second preliminary holes by etching the sacrificial layer, each of the second preliminary holes being in a region defined by at least three dielectric patterns adjacent to each other, and etching the etch target layer corresponding to positions of the first and second preliminary holes to form contact holes. | 02-27-2014 |
20140065829 | TRENCH FORMATION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a trench formation method uses a plasma source to make a trench in a silicon substrate by alternately repeating a depositing step and an etching step. The method includes implementing the depositing step and the etching step to satisfy the formulas recited below, where a distance between the silicon substrate and a region where plasma is to be confined is x (mm), an RF power to induce the plasma is w (kW), a pressure of the depositing step is y (Pa), and a tolerable limit of fluctuation in a plane of the silicon substrate of a width of the trench to be made is z | 03-06-2014 |
20140087563 | METHOD FOR POSITIONING SPACERS IN PITCH MULTIPLICATION - Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed. | 03-27-2014 |
20140106568 | METHOD OF FORMING OPENING ON SEMICONDUCTOR SUBSTRATE - The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer. | 04-17-2014 |
20140113451 | METHOD FOR FORMING A PATTERN - One aspect of the present invention is directed to a method of forming a pattern. A first layer which comprises a polymerization initiator is selectively formed on a second layer of a substrate. A polymer layer is selectively formed on the first layer by subjecting an organic monomer to living radical polymerization using the polymerization initiator. The second layer is selectively etched using the polymer layer as a mask. | 04-24-2014 |
20140127909 | Methods Of Forming A Pattern On A Substrate - A method of forming a pattern on a substrate includes forming longitudinally elongated first lines and first sidewall spacers longitudinally along opposite sides of the first lines elevationally over an underlying substrate. Longitudinally elongated second lines and second sidewall spacers are formed longitudinally along opposite sides of the second lines. The second lines and the second sidewall spacers cross elevationally over the first lines and the first sidewall spacers. The second sidewall spacers are removed from crossing over the first lines. The first and second lines are removed in forming a pattern comprising portions of the first and second sidewall spacers over the underlying substrate. Other methods are disclosed. | 05-08-2014 |
20140134844 | METHOD FOR PROCESSING A DIE - In various embodiments, a method for processing a die is provided. The method may include forming a periodic structure at least one of over and in a carrier, the periodic structure including a plurality of structure elements; depositing masking material over the periodic structure; partially removing masking material to expose at least one structure element but not all of the structure elements; and removing the exposed at least one structure element. | 05-15-2014 |
20140134845 | METHOD OF FORMING CONTACT HOLE - A method of forming contact hole is disclosed, including the steps of: providing a semiconductor substrate having a first dielectric layer, a second dielectric layer and a third dielectric layer formed thereon in this order; forming a first contact hole through the third dielectric layer, the second dielectric layer and the first dielectric layer by using an etching process to expose the semiconductor substrate; removing the third dielectric layer; forming a fourth dielectric layer over the second dielectric layer, the fourth dielectric layer filling the first contact hole; forming a second contact hole through the fourth dielectric layer, the second dielectric layer and the first dielectric layer to expose the semiconductor substrate; and removing the fourth dielectric layer. The method is capable of improving the stability of the contact-hole formation process. | 05-15-2014 |
20140193975 | COMPOSITION FOR FORMING TITANIUM-CONTAINING RESIST UNDERLAYER FILM AND PATTERNING PROCESS - The invention provides a composition for forming a titanium-containing resist underlayer film comprising: as component (A), a silicon-containing compound obtained by hydrolysis and/or condensation of one or more kinds of silicon compounds shown by the following general formula (A-I) and, as component (B), a titanium-containing compound obtained by hydrolysis and/or condensation of one or more kinds of hydrolysable titanium compounds shown by the following general formula (B-I). There can be provided a composition for forming a titanium-containing resist underlayer film to form a resist underlayer film having an excellent adhesiveness in fine patterning and an excellent etching selectivity relative to a conventional organic film and a silicon-containing film. | 07-10-2014 |
20140193976 | METHODS OF FORMING CONTACT HOLES - Methods of forming contact holes include forming a first guide pattern over an etching target layer. The first guide pattern has first openings each extending in a first direction and each first opening arranged in a direction perpendicular to the first direction. A first BCP structure is formed in each first opening. The first BCP structure includes first material layers in the first direction at a first pitch in each of the first openings, and second material layers filling a remaining portion of each first opening. First holes are formed by removing the first material layers. A second guide pattern is formed over the first guide pattern and the second material layers, and the above processes are performed on the second guide pattern to form second holes. Portions of the etching target layer overlapped by the first holes or the second holes are removed to form a desired pattern. | 07-10-2014 |
20140235057 | PATTERN FORMING PROCESS - A pattern is formed by coating a resist composition comprising a resin comprising recurring units having an acid labile group, a photoacid generator, and a first organic solvent onto a processable substrate, prebaking, exposing, PEB, and developing in an organic solvent developer to form a negative pattern; heating the negative pattern to render it resistant to a second organic solvent; coating a solution of a resin having a carbon content of at least 75 wt % in the second organic solvent thereon, prebaking, and dry etching to effect image reversal for converting the negative pattern into a positive pattern. | 08-21-2014 |
20140235058 | Method for Forming a Power Semiconductor Device - A method for forming a semiconductor device includes providing a semiconductor body which has a main surface and a first n-type semiconductor region, forming a trench which extends from the main surface into the first n-type semiconductor region, and forming a dielectric layer having fixed negative charges on a surface of the trench, by performing at least one atomic layer deposition using an organometallic precursor. | 08-21-2014 |
20140235059 | DIARYLAMINE NOVOLAC RESIN - A novel diarylamine novolac resin such as a phenylnaphthylamine novolac resin, and further a resist underlayer film-forming composition in which the resin is used in a lithography process for manufacturing a semiconductor device. A polymer including a unit structure (A) of Formula (1): | 08-21-2014 |
20140242799 | PATTERN FORMATION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a pattern formation method includes forming a first mask layer including a first and a second concave pattern on a first surface of a substrate. The method can include providing a protection film in the first concave pattern. The method can include providing a self-assembling material in the second concave pattern. The method can include forming a first and a second phase in the second concave pattern by phase-separating the self-assembling material. The method can include removing the protection film together with the first phase to form a second mask layer having the first concave pattern and a third concave pattern. The third concave pattern is provided in the second concave pattern, and has an opening width narrower than an opening width of the second concave pattern. The method can include processing the substrate using the second mask layer as a mask. | 08-28-2014 |
20140256138 | METHOD AND EQUIPMENT FOR REMOVING PHOTORESIST RESIDUE AFTER DRY ETCH - A method for removing photoresist residue includes etching a photoresist layer disposed over a front side of a semiconductor substrate during fabrication of a semiconductor device, and exposing at least one of the front side and the back side of the semiconductor substrate to an atmosphere comprising active oxygen. The method further includes cleaning at least one of the front side and the back side of the semiconductor substrate with a cleaning fluid. | 09-11-2014 |
20140256139 | SELF-ALIGNED TRENCH OVER FIN - A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery. | 09-11-2014 |
20140273467 | Polycrystalline-silicon etch with low-peroxide apm - Polycrystalline silicon (poly-Si) can be thoroughly removed without significant effect on adjacent oxides by an aqueous solution of ammonium hydroxide with smaller concentrations of hydrogen peroxide than are normally used in ammonia-peroxide mixture (APM) formulations used for cleaning. The etching selectivity of poly-Si relative to oxides can be widely tuned by varying the hydrogen-peroxide concentration. Compared to other formulations used to remove poly-Si dummy gates in logic-node fabrication, such as TMAH, these aqueous solutions are less hazardous to workers and the environment. | 09-18-2014 |
20140273468 | PATTERNING METHOD FOR SEMICONDUCTOR DEVICE FABRICATION - A method includes forming a first pattern having a first opening on a semiconductor substrate. The first opening is then filled. A second pattern of a first and second feature, interposed by the filled opening, is formed on the semiconductor substrate. Spacer elements then are formed on sidewalls of the filled opening, the first feature and the second feature. After forming the spacer elements, the material comprising first and second features is removed to form a second opening and a third opening. The filled opening, the second opening and the third opening are used as a masking element to etch a target layer of the substrate. | 09-18-2014 |
20140273469 | METHODS OF FORMING TRENCH/VIA FEATURES IN AN UNDERLYING STRUCTURE USING A PROCESS THAT INCLUDES A MASKING LAYER FORMED BY A DIRECTED SELF-ASSEMBLY PROCESS - One illustrative method disclosed herein includes the steps of performing a directed self-assembly process to form a DSA masking layer, performing at least one process operation to remove at least one of the features of the DSA masking layer so as to thereby define a patterned DSA masking layer with a DSA masking pattern, performing at least one process operation to form a patterned transfer masking layer having a transfer masking pattern comprised of a plurality of features that define a plurality of openings in the transfer masking layer, wherein the transfer masking pattern is the inverse of the DSA masking pattern, and performing at least one etching process through the patterned transfer masking layer on a layer of material to form a plurality of trench/via features in the layer of material. | 09-18-2014 |
20140273470 | Stress-Controlled Formation of Tin Hard Mask - Disclosed is a method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N | 09-18-2014 |
20140273471 | METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming fine patterns includes patterning a hard mask layer and a buffer mask layer sequentially stacked on a lower mask layer to form first openings, forming sacrificial patterns filling the first openings and protruding from a top surface of the buffer mask layer, forming a spacer pattern filling a space between two adjacent sacrificial patterns and having gaps each of which exposes a portion of the buffer mask layer between at least three adjacent sacrificial patterns, etching portions of the buffer mask layer exposed by the gaps of the spacer pattern to form enlarged holes, etching portions of the hard mask layer exposed by the enlarged holes to form second openings, and subsequently etching the lower layer using the hard mask layer as an etch mask. | 09-18-2014 |
20140273472 | TRACK PROCESSING TO REMOVE ORGANIC FILMS IN DIRECTED SELF-ASSEMBLY CHEMO-EPITAXY APPLICATIONS - A method is provided for preparing a prepatterned substrate for use in DSA integration. In one example, the method includes removing a radiation-sensitive material pattern overlying a patterned cross-linked polystyrene copolymer layer by a) exposure to a solvent vapor, b) exposure to a liquid solvent, and c) repeating steps a)-b) until the radiation-sensitive material pattern is completely removed. In another example, the method includes removing a neutral layer by affecting removal of an underlying patterned radiation-sensitive material layer, which includes swelling the neutral layer; and removing the radiation-sensitive material pattern and the swollen neutral layer in portions by exposing the swollen layer and pattern to a developer solution. Swelling the neutral layer includes a) exposure to a solvent vapor; b) exposure to a liquid solvent; and c) repeating steps a)-b) until the neutral layer is sufficiently swollen to allow penetration of the developing solution through the swollen neutral layer. | 09-18-2014 |
20140295669 | PATTERN FORMING METHOD - According to one embodiment, a pattern forming method includes forming a first guide layer on a processed film, phase-separating a first self-assembly material with the use of the first guide layer to form a first self-assembly pattern including a first polymer portion and a second polymer portion, selectively removing the first polymer portion, forming a second guide layer with the use of the second polymer portion, and phase-separating a second self-assembly material with the use of the second guide layer to form a second self-assembly pattern including a third polymer portion and a fourth polymer portion. | 10-02-2014 |
20140315388 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a second insulating layer over a first insulating layer, forming a mask over the second insulating layer, after the forming the mask, a first etching of the second insulating layer which is not covered by the mask, and after the first etching, a second etching of the second insulating layer and the first insulating layer which are not covered by the mask. At the first etching, the second insulating layer left over the first insulating layer and the first insulating layer is not exposed. At the second etching, the left over second insulating layer and the first insulating layer are etched. The first insulating layer has a lower dielectric constant than the second insulating layer. A second etching condition of the second etching includes a larger flow rate of oxygen than a first etching condition of the first etching. | 10-23-2014 |
20140322916 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE USING VOIDS IN A SACRIFICIAL LAYER - A semiconductor device is fabricated by forming first holes arranged along a first direction on an etch-target layer, forming dielectric patterns in the first holes, conformally forming a barrier layer on the dielectric patterns, forming a sacrificial layer on the barrier layer to define a first void, partially removing the sacrificial layer to expose the first void, anisotropically etching the barrier layer to form second holes below the first void, and etching portions of the etch-target layer located below the first and second holes to form contact holes. The first void may be formed on a first gap region confined by at least three of the dielectric patterns disposed adjacent to each other, and the sacrificial layer may include a material having a low conformality. | 10-30-2014 |
20140329388 | METHODS OF PATTERNING FEATURES HAVING DIFFERING WIDTHS - Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer. | 11-06-2014 |
20140370711 | NITROGEN DOPED AMORPHOUS CARBON HARDMASK - Embodiments described herein generally relate to the fabrication of integrated circuits and more particularly to nitrogen doped amorphous carbon layers and processes for depositing nitrogen doped amorphous carbon layers on a semiconductor substrate. In one embodiment, a method of forming a nitrogen doped amorphous carbon layer on a substrate is provided. The method comprises positioning a substrate in a substrate processing chamber, introducing a nitrogen containing hydrocarbon source into the processing chamber, introducing a hydrocarbon source into the processing chamber, introducing a plasma-initiating gas into the processing chamber, generating a plasma in the processing chamber, and forming a nitrogen doped amorphous carbon layer on the substrate. | 12-18-2014 |
20140370712 | METHODS OF FORMING A PATTERN AND DEVICES FORMED BY THE SAME - The inventive concepts provide methods of forming a pattern. In the method, a block copolymer layer may be formed on a neutral layer having an uneven structure and then phase separation is induced. The neutral layer may have an affinity for all of a hydrophilic polymer and a hydrophobic polymer, so that vertical cultivation of phases of the block copolymer may be realized on the uneven structure. Thus, a self-assembled phenomenon may be induced. | 12-18-2014 |
20140370713 | METHOD OF FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region. The semiconductor device can be, for example, a NAND FLASH memory device. The semiconductor memory device can be variously classified according to the type of memory cells to be integrated in the cell array region, e.g., a DRAM, an SRAM, a PRAM, a RRAM, an MRAM, and a FRAM. In other embodiments, a MEMS device, an optoelectronic device, or a processor, such as CPU or DSP, may be provided on the semiconductor substrate. | 12-18-2014 |
20150017807 | METHODS OF FORMING PATTERNS - Methods of forming patterns are provided. The methods may include sequentially forming an etch-target layer and a photoresist layer on a substrate, exposing two first portions of the photoresist layer to light to transform the two first portions into two first photoresist patterns and exposing a second portion of the photoresist layer to light to transform the second portion into a second photoresist pattern disposed between the two first photoresist patterns. The method may also removing portions of the photoresist layer to leave the two first photoresist patterns and the second photo resist pattern on the etch-target layer such that the etch-target layer is exposed. | 01-15-2015 |
20150031208 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes the steps of forming a top surface nitride film on a top surface of a substrate and a bottom surface nitride film on a bottom surface of the substrate, forming a protective film on the top surface nitride film, removing the bottom surface nitride film by wet etching while the top surface nitride film is being protected by the protective film, removing the protective film after the removing of the bottom surface nitride film, patterning the top surface nitride film so as to form an opening in the top surface nitride film, and forming a second oxide film on the bottom surface of the substrate while forming a first oxide film on a surface portion of the substrate which is exposed by the opening. | 01-29-2015 |
20150031209 | METHOD FOR FORMING FEATURES WITH SUB-LITHOGRAPHIC PITCH USING DIRECTED SELF-ASSEMBLY OF POLYMER BLEND - There is provided a manufacturing method of a semiconductor device including forming a first pattern of first features, according to a lithography process, in a photoresist layer disposed on a substrate, the lithography process having a minimum printable dimension and a minimum printable pitch, applying an additional layer on the photoresist layer having the first pattern formed therein, forming a second pattern of second features in the additional layer, the second features concentric with the first features, and etching portions of the substrate exposed through the second pattern. Further, in the provided method, the first features include geometrical features separated by a distance less than the dimension of minimum printable feature, and the geometrical features are disposed at a pitch less than the minimum printable pitch. | 01-29-2015 |
20150044874 | PATTERN FORMATION METHOD - According to one embodiment, a pattern formation method includes: forming a first guide layer having of first openings exposing a surface of an underlayer, and the first openings being arranged in a first direction; forming a second guide layer on the underlayer and on the first guide layer, the second guide layer extending in the first direction, the second guide layer dividing each of the first openings into the first opening portion and the second opening portion, and the second guide layer being sandwiched by a first opening portion and a second opening portion; forming a block copolymer layer in each of the first opening portion and the second opening portion; forming a first layer and a second layer surrounded by the first layer in each of the first opening portion and the second opening portion by phase-separating the block copolymer layer; and removing the second layer. | 02-12-2015 |
20150056809 | DOUBLE PATTERNING METHOD - Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate. | 02-26-2015 |
20150064916 | Method For Integrated Circuit Patterning - A method of forming a target pattern includes forming a first trench in a substrate with a cut mask; forming a first plurality of lines over the substrate with a first main mask, wherein the first main mask includes at least one line that overlaps the first trench and is thereby cut into at least two lines by the first trench; forming a spacer layer over the substrate and the first plurality of lines and over sidewalls of the first plurality of lines; forming a patterned material layer over the spacer layer with a second main mask thereby the patterned material layer and the spacer layer collectively define a second plurality of trenches; removing at least a portion of the spacer layer to expose the first plurality of lines; and removing the first plurality of lines thereby resulting a patterned spacer layer over the substrate. | 03-05-2015 |
20150072529 | METHOD OF FORMING VIA HOLE - The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area. | 03-12-2015 |
20150087151 | Masking Process and Structures Formed Thereby - A method, e.g., of forming and using a mask, includes forming an inverse mask over a dielectric layer; forming a mask layer conformally over the inverse mask; removing horizontal portions of the mask layer; and after removing the horizontal portions, simultaneously etching the inverse mask and vertical portions of the mask layer. The etching the inverse mask is at a greater rate than the etching the vertical portions of the mask layer. The etching the inverse mask removes the inverse mask, and the etching the vertical portions of the mask layer forms a mask comprising rounded surfaces distal from the dielectric layer. Recesses are formed in the dielectric layer using the mask. Locations of the inverse mask correspond to fewer than all locations of the recesses. | 03-26-2015 |
20150087152 | METHOD OF MANUFACTURING HOWLLOW-STRUCTURE METAL GRATING - A method for making a hollow-structure metal grating is provided. The method includes the following steps. First, a substrate is provided. Second, a metal layer is located on a surface of the substrate. Third, a patterned mask layer is formed on a surface of the metal layer. The patterned mask layer is made of a chemical amplified photoresist. Fourth, the surface of the metal layer exposed out of the patterned mask layer is plasma etched. Lastly, the patterned mask layer on the surface of the metal layer is dissolved. | 03-26-2015 |
20150087153 | METHOD OF MANUFACTURING HOWLLOW-STRUCTURE METAL GRATING - A method for making a hollow-structure metal grating is provided. The method includes providing a substrate, forming a patterned mask layer on a surface of the substrate, applying a metal layer with a thickness greater than 10 nanometers on the patterned mask layer, and removing the patterned mask layer by a washing method using organic solvent. The patterned mask layer includes a plurality of first protruding structures and a plurality of first cavities arranged in intervals. | 03-26-2015 |
20150093901 | COMPOSITION FOR FORMING A SILICON-CONTAINING RESIST UNDER LAYER FILM AND PATTERNING PROCESS - A composition for forming a silicon-containing resist under layer film includes a silicon-containing compound which is obtained by hydrolysis, condensation or hydrolysis-condensation of a second silicon compound containing one or more compounds represented by the following general formula (1), | 04-02-2015 |
20150126034 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING TOPOGRAPHICAL FEATURES FOR DIRECTED SELF-ASSEMBLY - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming etch resistant fill control topographical features that overlie a semiconductor substrate. The etch resistant fill control topographical features define an etch resistant fill control confinement well. A block copolymer is deposited into the etch resistant fill control confinement well. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant fill control topographical features direct the etch resistant phase to form an etch resistant plug in the etch resistant fill control confinement well. | 05-07-2015 |
20150140824 | JIG, MANUFACTURING METHOD THEREOF, AND FLIP CHIP BONDING METHOD FOR CHIPS OF ULTRASOUND PROBE USING JIG - A jig includes a wafer including an accommodation groove configured to accommodate a capacitive micromachined ultrasonic transducer (cMUT) when flip chip bonding is performed, and a separation groove formed in a bottom surface of the accommodation groove, the separation groove having a bottom surface that is spaced apart from thin films of the cMUT that face the bottom surface of the separation groove when the cMUT is seated on portions of the bottom surface of the accommodation groove. | 05-21-2015 |
20150294976 | METHODS OF FORMING FINFET DEVICES IN DIFFERENT REGIONS OF AN INTEGRATED CIRCUIT PRODUCT - In one example, the method includes performing at least one process operation to form a first plurality of active fins and at least one sacrificial fin in a first area of a substrate while forming only a second plurality of active fins in a second area of said substrate, forming a fin removal masking layer that covers all of the active fins in both said first and second areas and exposes said at least one sacrificial fin in the first area, with the fin removal masking layer in position, performing at least one etching process to remove the at least one sacrificial fin in the first area and removing the fin removal masking layer. | 10-15-2015 |
20150311075 | Method for Integrated Circuit Patterning - Provided is a method of patterning a substrate. The method includes forming a resist layer over the substrate, wherein a layer of resist scum forms in between a first portion of the resist layer and the substrate. The method further includes patterning the resist layer to form a plurality of trenches in the first portion, wherein the layer of resist scum provides a floor for the plurality of trenches. The method further includes forming a first material layer in the plurality of trenches, wherein the first material layer has a higher etch resistance than the resist layer and the layer of resist scum. The method further includes etching the first material layer, the resist layer, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate. | 10-29-2015 |
20150318173 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is formed over a substrate. An interlayer is formed over the dielectric layer. A first photoresist layer with a first opening is formed over the interlayer and a second photoresist layer having a second opening is formed over the first photoresist layer. Spacers are formed along sidewalls of the first opening and the second opening. A first trench is formed in the interlayer by using the spacer along the first opening as an etch mask. A second trench is formed in the interlayer by using the spacer along the second opening as an etch mask. The first trench and the second trench are extended down into the dielectric layer as a lower portion and an upper portion, respectively, of a dielectric trench. | 11-05-2015 |
20150318181 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SELF-ALIGNED QUADRUPLE PATTERNING - Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a patternable structure having first and second regions and including upper and lower mandrel layers. The method etches upper mandrels from the upper mandrel layer in the first and second regions. The method includes forming first upper spacer structures having a first width adjacent upper mandrels in the first region and forming second upper spacer structures having a second width not equal to the first width adjacent upper mandrels in the second region. The method etches the lower mandrel layer using the first and second upper spacer structures as an etch mask to form lower mandrels. Further, the method includes forming spacers adjacent the lower mandrels and etching a material using the spacers as an etch mask to form variably spaced features. | 11-05-2015 |
20150339422 | STITCH-DERIVED VIA STRUCTURES AND METHODS OF GENERATING THE SAME - Via-level design shapes are mapped into stitch regions of line-level design shapes design in an overlying conductive line level. A via-catching design shape is provided in an underlying conductive line level for each stitch region that does not correspond to a via-level design shape. The shapes of the stitch regions and the via-catch design shapes can be adjusted to comply with design rule constraints. Further, stitches can be optionally moved into a neighboring line-level design shape to resolve design rule conflicts. The modified design layout can eliminate via-level design shapes once all via-level design shapes are replaced with a corresponding stitch region, thereby eliminating the need to provide a via level lithographic mask. A metal interconnect structure embodying the modified design layout can be formed by employing a set of hard mask layers and without employing a lithographic mask for a via level. | 11-26-2015 |
20150340232 | METHOD FOR FABRICATING A TEMPLATE OF CONDUCTORS ON A SUBSTRATE BY MEANS OF BLOCK COPOLYMERS - The method for fabricating patterns made from first material having: providing a substrate covered by a covering layer, forming a first mask by means of a self-assembled structure of block copolymers, the first mask having first patterns, making a second mask from the first mask, the second mask having a second series of patterns organized according to the first repetition pitch or an integral multiple of the first repetition pitch, the second series having less patterns than the first series, depositing and exposing a resin layer to form an intermediate mask on the first mask, the intermediate mask covering a part of the first patterns formed in the first mask and having second holes facing the first holes, etching the covering layer through the facing first and second holes to form third holes, filling the third holes with a first material to form the patterns made from first material. | 11-26-2015 |
20150340238 | METHODS OF REMOVING FINS FOR FINFET SEMICONDUCTOR DEVICES - One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed. | 11-26-2015 |
20150364337 | PATTERNING OF A HARD MASK MATERIAL - A method for processing a substrate includes providing the substrate including a photoresist/bottom anti-reflection coating (PR/BARC) layer, a hard mask layer, a stop layer, a carbon layer and a stack including a plurality of layers. The method includes defining a hole pattern including a plurality of holes in the PR/BARC layer using photolithography; transferring the hole pattern into the carbon layer; filling the plurality of holes in the hole pattern with oxide to create oxide pillars; using a planarization technique to remove the hard mask layer, a remaining portion of the PR/BARC layer and the stop layer; stripping the carbon layer to expose the oxide pillars; filling space between the oxide pillars with hard a mask material including metal; planarizing at least part of the hard mask material; and stripping the oxide pillars to expose the hole pattern in the hard mask material. | 12-17-2015 |
20150371861 | PROTECTIVE SILICON OXIDE PATTERNING - A method of patterning a substrate is described and include two possible layers which may be easily integrated into a photoresist patterning process flow and avoid an observed photoresist peeling problems. A conformal carbon layer or a conformal silicon-carbon-nitrogen layer may be formed between an underlying silicon oxide layer and an overlying photoresist layer. Either inserted layer may avoid remotely-excited fluorine etchants from diffusing through the photoresist and chemically degrading the silicon oxide. The conformal carbon layer may be removed at the same time as the photoresist and the conformal silicon-carbon-nitrogen layer may be removed at the same time as the silicon oxide, limiting process complexity. | 12-24-2015 |
20150380256 | Mechanisms for Forming Patterns Using Multiple Lithography Processes - The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench. | 12-31-2015 |
20150380259 | Mechanisms for Forming Patterns Using Multiple Lithography Processes - The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first feature in a first hard mask layer formed over the patterning-target layer; forming a second feature in a second hard mask layer formed over the patterning-target layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the first feature in the first hard mask layer within a first trench to formed a reshaped first feature; selectively removing a portion of the second feature in the second hard mask layer within a second trench to form a reshaped second feature; and transferring the reshaped first feature and the reshaped second feature to the patterning-target layer. | 12-31-2015 |
20160005604 | Manufacturing Method of Semiconductor Device - According to an embodiment, a manufacturing method of a semiconductor device includes: forming a first film on a processing target by using a first material; forming a second film on the first film by using a second material; selectively removing the second and first films to provide an opening pierced in the second and first films; selectively forming a metal film on an inner surface of the opening in the first film; and processing the processing target by using the metal film as a mask. | 01-07-2016 |
20160005617 | METHOD FOR INTEGRATED CIRCUIT PATTERNING - A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches. | 01-07-2016 |
20160005651 | WORKPIECE PROCESSING METHOD - Disclosed is a method of processing a workpiece so as to form an opening that extends from an oxide region to a base layer through a portion between the raised regions. The method includes: (1) a step of forming an opening in the oxide region to expose a second section between the raised regions; and (2) a step of etching a residue made of silicon oxide and existing within the opening and a second section. In the second step, a denatured region is formed by exposing the workpiece to plasma of a mixed gas including a hydrogen-containing gas and NF | 01-07-2016 |
20160013067 | METHODS FOR HIGH PRECISION PLASMA ETCHING OF SUBSTRATES | 01-14-2016 |
20160035565 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASSEMBLY CHEMOEPITAXY - Methods for directed self-assembly (DSA) using chemoepitaxy in the design and fabrication of integrated circuits are disclosed herein. An exemplary method includes forming an A or B-block attracting layer over a base semiconductor layer, forming a trench in the A or B-block attracting layer to expose a portion of the base semiconductor layer, and forming a neutral brush or mat or SAMs layer coating within the trench and over the base semiconductor layer. The method further includes forming a block copolymer layer over the neutral layer coating and over the A or B-block attracting layer and annealing the block copolymer layer to form a plurality of vertically-oriented, cylindrical structures within the block copolymer layer. | 02-04-2016 |
20160042114 | MULTIPLE-DEPTH TRENCH INTERCONNECT TECHNOLOGY AT ADVANCEDSEMICONDUCTOR NODES - A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire. | 02-11-2016 |
20160042965 | METHODS FOR FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE - The inventive concept provides methods for forming fine patterns of a semiconductor device. The method includes forming a buffer mask layer having first holes on a hard mask layer including a first region and a second region around the first region, forming first pillars filling the first holes and disposed on the buffer mask layer in the first region and second pillars disposed on the buffer mask layer in the second region, forming a block copolymer layer covering the first and second pillars on the buffer mask layer, phase-separating the block copolymer layer to form first block patterns spaced apart from the first and second pillars and a second block pattern surrounding the first and second pillars and the first block patterns, removing the first block patterns, and forming second holes in the buffer mask layer under the first block patterns. | 02-11-2016 |
20160064238 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a material layer on the substrate; forming a patterned first hard mask on the material layer; forming a patterned second hard mask on the material; utilizing the patterned first hard mask and the patterned second hard mask to remove part of the material layer for forming sacrificial mandrels; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; and using the sidewall spacers to remove part of the substrate. | 03-03-2016 |
20160064240 | Method for Integrated Circuit Patterning - A method includes forming a resist over a substrate, resulting in a layer of resist scum between the resist and the substrate. The method further includes forming trenches in the resist, wherein at least a portion of the layer of resist scum remains between the trenches and the substrate. The method further includes forming a first material layer in the trenches, wherein the first material layer has a higher etch resistance than the resist in an etching process. The method further includes performing the etching process to the first material layer, the resist, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate. | 03-03-2016 |
20160071741 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer made of a material different from a material of an etching target layer above the etching target layer. The method includes forming a plurality of first mask holes, sacrificial films being buried in the first mask holes, and a plurality of second mask holes, in the mask layer. The method includes retreating the sacrificial films in a depth direction of the first mask holes to expose portions of the first mask holes onto the sacrificial films. The method includes etching the etching target layer under the second mask holes using the mask layer and the sacrificial films as a mask, to form holes in the etching target layer under the second mask holes. | 03-10-2016 |
20160086794 | NITROGEN DOPED AMORPHOUS CARBON HARDMASK - Embodiments described herein generally relate to the fabrication of integrated circuits and more particularly to nitrogen doped amorphous carbon layers and processes for depositing nitrogen doped amorphous carbon layers on a semiconductor substrate. In one embodiment, a method of forming a nitrogen doped amorphous carbon layer on a substrate is provided. The method comprises positioning a substrate in a substrate processing chamber, introducing a nitrogen containing hydrocarbon source into the processing chamber, introducing a hydrocarbon source into the processing chamber, introducing a plasma-initiating gas into the processing chamber, generating a plasma in the processing chamber, and forming a nitrogen doped amorphous carbon layer on the substrate. | 03-24-2016 |
20160118400 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME - Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region. | 04-28-2016 |
20160141386 | METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH LOW SEALING LOSS - A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer. | 05-19-2016 |
20160155743 | Method for Forming Patterns of Semiconductor Device | 06-02-2016 |
20160181100 | Patterning a Substrate Using Grafting Polymer Material | 06-23-2016 |
20160181119 | PLASMA ETCHING METHOD | 06-23-2016 |
20160196982 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE | 07-07-2016 |
20160203992 | METHODS OF FORMING SEMICONDUCTOR DEVICES USING AUXILIARY LAYERS FOR TRIMMING MARGIN | 07-14-2016 |
20160203998 | ETCHING METHOD | 07-14-2016 |
20160254154 | METHODS OF FORMING PATTERNS WITH BLOCK COPOLYMER | 09-01-2016 |
20160254161 | Method for Patterning an Underlying Layer | 09-01-2016 |
20160254162 | SACRIFICIAL-FILM REMOVAL METHOD AND SUBSTRATE PROCESSING DEVICE | 09-01-2016 |
20160254191 | FIN PATTERNING METHODS FOR INCREASED PROCESS MARGIN | 09-01-2016 |
20160379836 | METHOD FOR FORMING A PATTERN - A method for forming a pattern includes steps of forming a patterned core layer on a substrate, conformally forming a spacer layer on the patterned core layer to form first concave portions, performing an etch back process to expose the patterned core layer, removing the exposed patterned core layer to form second concave portions, filling up the first concave portions and the second concave portions with a directed self-assembly material, and activating a directed self-assembly process, so that the directed self-assembly material is diffused to the perimeter of the concave portions to form a hole surrounding by the directed self-assembly material in each concave portions. | 12-29-2016 |
20160379843 | METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE - According to one embodiment, a method is disclosed for manufacturing an integrated circuit device, the method can include forming a mask member on a first film, the mask member having a pattern, performing a first etching on the first film using the mask member as a mask to form a recessed section in the first film, forming a second film covering an inner side surface of the recessed section. The second film has a film thickness of preventing blockage of the recessed section, and performing a second etching on the second film and the first film via the recessed section. The performing of the second etching includes performing a third etching in a condition of an etching rate at a place smaller in curvature radius in the recessed section being lower than an etching rate at a place larger in curvature radius in the recessed section. | 12-29-2016 |
20190148162 | Mechanisms for Forming Patterns Using Multiple Lithography Processes | 05-16-2019 |