Entries |
Document | Title | Date |
20080200025 | METHOD OF FORMING COMPOSITE OPENING AND METHOD OF DUAL DAMASCENE PROCESS USING THE SAME - A dual damascene process is provided. A dielectric layer is formed on a substrate and then a via opening is formed in the dielectric layer to expose a liner formed on the substrate. A gap fill (GF) layer is filled into the via opening and a resistant layer is formed on the substrate. A photolithographic process and an etching process are performed to form a trench in the dielectric layer and to remain the gap fill material having a top surface with a convex shape. In the etching process, an etching rate of the gap fill material layer is larger than that of the resistant layer. The gap fill material, the resistant layer, and the liner exposed by the via opening are removed. A conductive layer fills out the trench and the via opening. This invention is focusing on controlling etch-rate to avoid shielding effect when forming the composite opening. | 08-21-2008 |
20080206984 | CONDUCTIVE VIA FORMATION UTILIZING ELECTROPLATING - A method for forming a conductive via is discussed and includes forming a seed layer over a first side of a semiconductor substrate, wherein the semiconductor substrate includes a first side opposite a second side, forming a via hole in a semiconductor substrate from the second side of the semiconductor substrate, wherein the via hole exposes the seed layer; and electroplating a conductive via material in the via hole from the seed layer. In one embodiment, a continuous conductive layer is formed over and electrically coupled to the seed layer. The continuous conductive layer can serve as the current source while electroplating the conductive via material. | 08-28-2008 |
20080206985 | Method of fabricating a semiconductor device - Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region. | 08-28-2008 |
20080213993 | Method and Apparatus of Stress Relief in Semiconductor Structures - A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer. | 09-04-2008 |
20080233737 | METHOD OF FABRICATING INTERGRATED CIRCUIT CHIP - A method of manufacturing an integrated circuit (IC) chip is provided. The method includes the following steps. First, a substrate is provided. The substrate is divided into an internal region and an external region by a die seal ring region. A number of circuit units are then formed in the internal region on the substrate. Thereafter, a dielectric layer is formed over the substrate, interconnects are formed in the dielectric layer within the internal region, and a number of bonding pad structures are formed in the dielectric layer within the external region. Finally, a cutting process is performed along a number of scribed lines on the substrate to form a number of chips. The bonding pad structures are exposed at the sides of each chip. | 09-25-2008 |
20080254616 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed. | 10-16-2008 |
20080261392 | CONDUCTIVE VIA FORMATION - A method involves depositing a first electrically conductive material, using a deposition technique, into a via formed in a material, the via having a diameter at a surface of the material of less than about 10 μm and a depth of greater than about 50 μm, so as to form a seed layer within the via, then creating a thickening layer on top of the seed layer by electrolessly plating the seed layer with a second electrically conductive material without performing any activation process within the via between via formation and the creating the thickening layer, and then electroplating a conductor metal onto the thickening layer until a volume bounded by the thickening layer within the via is filled with the conductor metal. | 10-23-2008 |
20080280433 | Method for manufacturing semiconductor device - A four-layer structured hard mask composed of a SiC film, a first SiO | 11-13-2008 |
20080280434 | Enhanced Mechanical Strength Via Contacts - The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer. | 11-13-2008 |
20080286963 | Method for Producing Through-Contacts in Semi-Conductor Wafers - The invention relates to a method for producing vertical through-contacts (micro-vias) in semi-conductor wafers in order to produce semi-conductor components, i.e. contacts on the front side of the wafer through the semi-conductor wafer to the rear side of the wafer. The invention also relates to a method which comprises the following steps: blind holes on the contact connection points are laser drilled from the rear side of the wafer into the semi-conductor substrate, the wafer is cleaned, the semi-conductor substrate is plasma etched in a material selected manner until the active layer stack of the wafer is reached, the active layer stack of the wafer is plasma etched in a material selective manner until the contacts, which are to be connected to the rear side of the wafer, are reached, a plating base is applied to the rear side of the wafer and into the blind holes and gold is applied by electrodeposition onto the metallizied rear side of the wafer and the blind holes. | 11-20-2008 |
20080286964 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed. | 11-20-2008 |
20080305626 | METHOD OF FORMING SOLID BLIND VIAS THROUGH THE DIELECTRIC COATING ON HIGH DENSITY INTERCONNECT SUBSTRATE MATERIALS - A method is provided comprising: coating an electrically conductive core with a first removable material, creating openings in the first removable material to expose portions of the electrically conductive core, plating a conductive material onto the exposed portions of the electrically conductive core, coating the conductive material with a second removable material, removing the first removable material, electrophoretically coating the electrically conductive core with a dielectric coating, and removing the second removable material. | 12-11-2008 |
20080305627 | METHOD OF FORMING A CONTACT PLUG AND METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a contact plug includes the following processes. A dummy film is formed over a substrate. The dummy film may include amorphous carbon as a main material. At least one contact hole is formed in the dummy film. At least one contact plug is formed in the at least one contact hole. | 12-11-2008 |
20080305628 | SEMICONDUCTOR DEVICE WITH CONNECTING VIA AND DUMMY VIA AND METHOD OF MANUFACTURING THE SAME - An underlying interconnect including a first barrier metal layer, an interconnect metal layer and a second barrier metal layer is formed on a semiconductor substrate, and an interlayer dielectric is formed thereon. Etching is performed with a photoresist defining an opening for a first via, and an opening for a second via having a larger bottom area than the first via opening, so as to form a first via hole and a second via hole in the interlayer dielectric. Since the second via hole has a larger diameter than the second via hole, the second via hole is opened up prior to the second via hole, and the underlying interconnect is exposed first at the bottom of the second via hole. | 12-11-2008 |
20080318413 | METHOD FOR MAKING AN INTERCONNECT STRUCTURE AND INTERCONNECT COMPONENT RECOVERY PROCESS - A method is provided for making an interconnect structure. The method includes applying a removable layer to an electronic device or to a base insulative layer; applying an adhesive layer to the electronic device or to the base insulative layer; and securing the electronic device to the base insulative layer using the adhesive layer. | 12-25-2008 |
20080318414 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to embodiments includes forming an interlayer dielectric film with a damascene pattern over a semiconductor substrate having a lower metal wire. A seed layer may be formed over the interlayer dielectric film including the damascene pattern. Impurities generated during the formation of the seed layer be removed through an annealing process using H | 12-25-2008 |
20080318415 | INTERCONNECT STRUCTURES WITH ENCASING CAP AND METHODS OF MAKING THEREOF - A method of making an interconnect comprising: providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure. | 12-25-2008 |
20090004845 | Method for Making Semiconductor Structures Implementing Sacrificial Material - Methods of fabricating semiconductor structures on a substrate, where the substrate has transistors formed thereon, are provided. One method includes forming interconnect metallization structures in a plurality of levels. The forming of the interconnect metallization structures includes depositing a sacrificial layer and performing a process to etch trenches, vias, and stubs into the sacrificial layer. The method further includes filling and planarizing the trenches, vias, and stubs that were etched and then etching away the sacrificial layer throughout the plurality of levels of the interconnect metallization structures. The etching leaving a voided interconnect metallization structure that is structurally supported by stubs that are non-electrically functional. | 01-01-2009 |
20090004846 | WIRING BOARD, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The invention provides a wiring board having a small-scale and high-performance functional circuit while realizing a multi-layer wiring with a small number of steps. In addition, the invention provides a semiconductor device in which a display device is integrated with such high-performance functional circuit on the same substrate. According to the invention, first to third wirings, first and second interlayer insulating films and first and second contact holes are formed over a substrate having an insulating surface. The second wiring is wider than the first wiring, or the third wiring is wider than the first wiring or the second wiring. The second contact hole has a larger diameter than the first contact hole. | 01-01-2009 |
20090017612 | METHODS FOR FABRICATING ARRAY SUBSTRATES - Methods for fabricating array substrates are provided. A method for fabricating an array substrate includes forming a first metal layer over a substrate and then patterned by a first photolithography to forming a gate line, a gate electrode connecting the gate line, and a pad over the substrate. An insulating layer, a semiconductor layer, and an ohmic contact layer are formed over the substrate to cover the gate line, the gate electrode and the pad. The ohmic contact layer, the semiconductor layer, and portions of the insulating layer are patterned by a second photolithography to forming a semiconductor structure over the substrate and a via hole in the insulating layer over the pad to exposing a part of the pad. | 01-15-2009 |
20090017613 | METHOD OF MANUFACTURING INTERCONNECT SUBSTRATE AND SEMICONDUCTOR DEVICE - An interconnect substrate includes an interconnect, an insulating layer, a non-photosensitive resin layer, a photosensitive resin layer, a first electrode pad, and a second electrode pad. The non-photosensitive resin layer is constructed with a non-photosensitive insulating material. Also, the non-photosensitive resin layer has a first opening. The photosensitive resin layer is constructed with a photosensitive insulating material. Also, the photosensitive resin layer has a second opening. The opening area of the second opening is larger than that of the first opening. The first electrode pad is disposed on the first surface side of the insulating layer. The first electrode pad is exposed to the first opening. The second electrode pad is disposed on the second surface side of the insulating layer. The second electrode pad is exposed to the second opening. | 01-15-2009 |
20090017614 | SEMICONDUCTOR DEVICE - In order to block hydrogen ions produced when forming an interlayer insulating film by HDP-CVD or the like to thereby suppress an adverse effect of the hydrogen ions on a device, in a semiconductor device including a contact layer, a metal interconnection and an interlayer insulating film on a semiconductor substrate having a gate electrode formed thereon, the interlayer insulating film is formed on the metal interconnection by bias-applied plasma CVD using source gas containing hydrogen atoms, and a silicon oxynitride film is provided in the underlayer of the metal interconnection and the interlayer insulating film. | 01-15-2009 |
20090047779 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, including: forming a first conductive layer on a first insulating film; forming a second insulating film so as to cover the first conductive layer; forming a resist mask on the second insulating film; forming a hole reaching the first conductive layer in the second insulating film by means of first dry etching using the resist mask; removing the resist mask; removing the first conductive layer exposed at the bottom of the hole by means of second dry etching, so that the hole reaches the first insulating film and the first conductive layer exposes at a side surface within the hole; forming a conductive plug in contact with the first conductive layer exposed at the side surface within the hole by burying a conductive material in the hole; and forming a second conductive layer to be connected to the conductive plug on the second insulating film. | 02-19-2009 |
20090061619 | METHOD OF FABRICATING METAL LINE - A method of fabricating a metal line of a semiconductor device that prevents formation of serrations in a metal line to thereby increase operational reliability of a semiconductor device. The method includes forming a lower metal line in a semiconductor substrate; and then forming a first nitride layer as an etching stop layer over the semiconductor substrate including the lower metal line; and then forming a first insulating layer over the first nitride layer; and then forming a second nitride layer over the first insulating layer; and then forming a contact hole partially exposing the uppermost surface of the lower metal line by performing a first etching process; and then simultaneously forming a second insulating layer over the second nitride layer and a void in the contact hole; and then forming a trench corresponding spatially to the contact hole and partially exposing the uppermost surface of the lower metal line by performing a second etching process. | 03-05-2009 |
20090068833 | METHOD OF FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming a contact hole of a semiconductor device. According to the method of forming a contact hole of a semiconductor device, a semiconductor substrate in which gates and junctions are formed is provided. A self-aligned contact (SAC) nitride layer is formed on a surface of the gates. A pre-metal dielectric layer is formed on the SAC nitride layer. A contact hole is formed to thereby expose the junction between the gates. A passivation layer is formed on sidewalls of the contact hole. A contact plug is formed, thus gap-filling the contact hole. | 03-12-2009 |
20090068834 | METHOD OF FORMING A CONTACT PLUG OF A SEMICONDUCTOR DEVICE - In a method of forming a contact plug of a semiconductor device, a nitride layer is prevented from being broken by forming a passivation layer over the nitride layer when contact holes are formed by etching an insulating layer between select lines formed over a semiconductor substrate. In an etch process of forming the contact plug, the passivation layer formed on sidewalls of the select lines is formed twice to protect the sidewalls of the select lines. Accordingly, the sidewalls of the select lines can be prevented from being damaged. Consequently, a process margin necessary to form a contact plug can be increased and, therefore, a smaller contact plug can be formed. | 03-12-2009 |
20090075473 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device capable of improving electrical junction capability between a pad metal line and an upper metal line by removing a foreign substance present on the surface of the pad metal line prior to formation of the upper metal line. | 03-19-2009 |
20090075474 | METHODS FOR FORMING DUAL DAMASCENE WIRING USING POROGEN CONTAINING SACRIFICIAL VIA FILLER MATERIAL - Methods for fabricating dual damascene interconnect structures are provided in which a sacrificial material containing porogen (a pore forming agent) is used for filling via holes in an interlayer dielectric layer such that the sacrificial material can be transformed to porous material that can be quickly and efficiently removed from the via holes without damaging or removing the interlayer dielectric layer. | 03-19-2009 |
20090081864 | SiC Film for Semiconductor Processing - A silicon carbide (SiC) film for use in backend processing of integrated circuit manufacturing, is generated by including hydrogen in the reaction gas mixture. This SiC containing film is suitable for integration into etch stop layers, dielectric cap layers and hard mask layers in interconnects of integrated circuits. | 03-26-2009 |
20090093114 | METHOD OF FORMING A DUAL-DAMASCENE STRUCTURE USING AN UNDERLAYER - A method of forming a dual-damascene wire. The method includes forming a via opening in a dielectric layer, filling the via opening with a polymeric formation including at least about 6% by weight of solids of thermal acid generator; heating the polymeric underlayer to a temperature greater than room temperature but less than about 180° C.; lithographically forming a trench in the dielectric layer and filling the via opening and the trench with an electrical conductor, a top surface of the electrical conductor substantially co-planer with the top surface of the second dielectric capping layer. | 04-09-2009 |
20090098729 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes that can prevent formation of fences of reaction by-products around chain holes during a dual damascene process, so subsequent metal gap fill defects are prevented, making it possible to prevent device failure. The method may include forming a via hole in an interlayer insulating layer exposing a bottom anti-reflection coating, and then filling the via hole with a first material, and then removing a portion of the first material, and then forming an oxide film over the first material to refill the via hole, and then forming a trench by etching the interlayer insulating layer and the oxide film, and then opening the via hole by removing the first material in the via hole to the bottom anti-reflection coating, and then etching the bottom anti-reflection coating to expose the metal wire, and then filling the opened via hole and trench with metal. | 04-16-2009 |
20090104767 | METHODS FOR FABRICATING RESIDUE-FREE CONTACT OPENINGS - A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures on a semiconductor substrate. The via is formed through a dielectric layer and a barrier layer that are disposed over a metal-containing trace disposed on a semiconductor substrate. The sidewalls of the via may be coated with a residue layer including a distinct oxide polymer component and a distinct metal polymer component. The two-step cleaning process comprises subjecting the residue layer to a nitric acid dip that removes the metal polymer component to expose the oxide polymer component. The oxide polymer component is then subjected to a phosphoric acid dip that removes the oxide polymer component. The oxide polymer and metal polymer residues may also be removed during the fabrication of the via by removing them directly after their respective formations. | 04-23-2009 |
20090124076 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided, the method includes forming a coated film by coating a solution containing a solvent and an organic component above an insulating film located above a semiconductor substrate and having a recess, baking the coated film at a first temperature which does not accomplish cross-linking of the organic component to obtain an organic film precursor, polishing the organic film precursor using a slurry containing resin particles to leave the organic film precursor in the recess, baking the left organic film precursor at a second temperature which is higher than the first temperature to remove the solvent to obtain a first organic film embedded in the recess, forming a second organic film on the insulating film, thereby obtaining an underlying film, forming an intermediate layer and a resist film successively above the underlying film, and subjecting the resist film to patterning exposure. | 05-14-2009 |
20090130841 | METHOD FOR FORMING CONTACT IN SEMICONDUCTOR DEVICE - A method for forming a contact in a semiconductor device, comprises providing a substrate, forming a plurality of conductive patterns and a passivation layer surrounding the conductive patterns over the substrate, forming an insulation layer covering the conductive patterns and passivation layer, forming a mask pattern for a contact over the insulation layer, forming a first opening by performing an isotropic etch process on the insulation layer using the mask pattern as an etch mask, wherein the isotropic etch process is performed until the insulation layer meets the passivation layer, forming a barrier layer over a resultant structure of the first opening, exposing the insulation layer by performing an anisotropic etch process using the mask pattern as an etch mask, and forming a second opening exposing the substrate by performing a self aligned contact (SAC) process using the mask pattern and barrier layer as an etch mask. | 05-21-2009 |
20090130842 | Method of forming contact hole and method of manufacturing semiconductor memory device using the same - A contact hole forming method and a method of manufacturing semiconductor device using the same may include forming a layer on a substrate; anisotropically etching the layer to form a dummy contact hole exposing the substrate; isotropically etching a sidewall of the dummy contact hole to form a contact hole by alternatively and repeatedly supplying an etching solution including a fluoride salt in a low-polarity organic solvent and deionized water to the dummy contact hole. The methods increase reliability of semiconductor memory devices. | 05-21-2009 |
20090137113 | Method for fabricating a Microstructure - A method for fabricating a microstructure is to form at least one insulation layer including a micro-electro-mechanical structure therein over an upper surface of a silicon substrate. The micro-electro-mechanical structure includes at least one microstructure and a metal sacrificial structure that are independent with each other. In the metal sacrificial structure are formed a plurality of metal layers and a plurality of metal via layers connected to the respective metal layers. A barrier layer is formed over an upper surface of the insulation layer, and an etching stop layer is subsequently formed over a lower surface of the silicon substrate. An etching operation is carried out from the lower surface of the silicon substrate to form a space corresponding to the micro-electro-mechanical structure, and then the metal sacrificial structure is etched, thus achieving a microstructure suspension. | 05-28-2009 |
20090137114 | METHOD OF MAKING SEMICONDUCTOR DEVICE - A semiconductor device is manufactured by a method including forming a first interlayer insulating film. A first etching stopper film is formed on the first interlayer insulating film. A conductive layer is formed on the first etching stopper film. A second etching stopper film is formed to cover the conductive layer, an upper surface of the conductive layer and both side surfaces of the conductive layer. A second interlayer insulating film is formed on the second etching stopper film. A hole is formed penetrating the second interlayer insulating film in a direction of thickness and reaching the conductive layer. An interconnect is formed in the hole. The step of forming a hole includes etching the second interlayer insulating film under a first etching condition, and etching the second etching stopper film under a second etching condition different from the first etching condition. The second etching condition includes using an etching gas containing C, F, and H. | 05-28-2009 |
20090142920 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes can prevent defects of a semiconductor device due to the deterioration of electro migration (EM)/stress migration (SM) properties of the device as a result of metal corrosion and void generation in burying a novolac material. Embodiments can also prevent the generation of fencing in a metal wire structure. | 06-04-2009 |
20090142921 | METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES - In a first preferred embodiment of the present invention, conductive features are formed on a first dielectric etch stop layer, and a second dielectric material is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features is formed in a subtractive pattern and etch process, filled with a dielectric fill, and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer is deposited on the surface, then a third dielectric covers the dielectric etch stop layer. When a contact is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features. | 06-04-2009 |
20090170308 | METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE - A method for forming metal lines of a semiconductor device is disclosed. The metal line forming method includes forming plugs by perforating via-holes in an interlayer dielectric layer formed on a semiconductor substrate and burying a conductive material in the via-holes, sequentially forming at least two metal layers on the interlayer dielectric layer formed with the plugs, the metal layers having a difference in the size of metal grains of each metal layer, etching an uppermost first metal layer of the at least two metal layers using a photoresist pattern formed on the first metal layer as an etching mask using a first etching gas, and etching the partially etched first metal layer using a second etching gas. | 07-02-2009 |
20090191703 | PROCESS WITH SATURATION AT LOW ETCH AMOUNT FOR HIGH CONTACT BOTTOM CLEANING EFFICIENCY FOR CHEMICAL DRY CLEAN PROCESS - A method for removing oxides from the bottom surface of a contact hole is provided. The method provides efficient cleaning of the bottom surface without distortion of the contact hole upper and sidewall surfaces. | 07-30-2009 |
20090246951 | METHOD FOR PATTERNING A METALLIZATION LAYER BY REDUCING RESIST STRIP INDUCED DAMAGE OF THE DIELECTRIC MATERIAL - By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the hardmask may also be maintained so that the trench etch process may be performed with a high degree of etch selectivity during the patterning of openings in a metallization layer of a semiconductor device. | 10-01-2009 |
20090263964 | INTERCONNECTIONS FOR INTEGRATED CIRCUITS - An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects. A central region may be free of connection elements so that electro-migration properties of the connection structure are improved and the current-carrying capacity is increased | 10-22-2009 |
20090275195 | Interconnect Structure Having a Silicide/Germanide Cap Layer - An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide. | 11-05-2009 |
20090298280 | STRUCTURE AND METHOD FOR CREATING RELIABLE VIA CONTACTS FOR INTERCONNECT APPLICATIONS - A reliable and mechanical strong interconnect structure is provided that does not include gouging features in the bottom of the an opening, particularly at a via bottom. Instead, the interconnect structures of the present invention utilize a Co-containing buffer layer that is selectively deposited on exposed surfaces of the conductive features that are located in a lower interconnect level. The selective deposition is performed through at least one opening that is present in a dielectric material of an upper interconnect level. The selective deposition is performed by electroplating or electroless plating. The Co-containing buffer layer comprises Co and at least one of P and B. W may optionally be also present in the Co-containing buffer layer. | 12-03-2009 |
20090305499 | INTRALEVEL CONDUCTIVE LIGHT SHIELD - A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield. | 12-10-2009 |
20090311859 | METHOD FOR ENABLING HARD MASK FREE INTEGRATION OF ULTRA LOW-K MATERIALS AND STRUCTURES PRODUCED THEREBY - A method of fabricating an interconnect structure on a substrate includes steps of: providing a dielectric with at least one etched opening; filling the at least one etched opening with at least one conductive material; planarizing the conductive material to provide a planarized structure; subjecting the planarized structure to a plasma preclean process; and exposing the planarized structure to a silylating repair agent which is a silane derivative; and forming a dielectric cap layer on the planarized structure. | 12-17-2009 |
20100003814 | Interconnections Having Double Capping Layer and Method for Forming the Same - Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression. | 01-07-2010 |
20100003815 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and method for manufacturing the same is provided, capable of gap-filling a copper metal wiring while minimizing void generation. A semiconductor device according to an embodiment includes a copper sulfide layer formed on a first barrier metal formed in a via and trench; and a via plug and an upper metal wiring formed in the via hole and the trench, respectively, on the copper sulfide layer and an exposed lower metal wiring. | 01-07-2010 |
20100015797 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - When a tungsten film ( | 01-21-2010 |
20100022084 | Method for Forming Interconnect Structures - Methods of fabricating interconnect structures in a semiconductor integrated circuit (IC) are presented. A preferred embodiment comprises forming interconnect lines and vias through a dual-damascenes process. It includes forming a via dielectric layer, an etch stop layer directly over the via dielectric layer, and a trench dielectric layer over the etch stop layer. The etch stop layer is patterned through a first photolithography and etch process to form openings in the etch stop layer, prior to the formation of the trench dielectric layer. A second photolithography and etch process is performed after formation of the trench dielectric layer to create trench openings in the trench dielectric layer and via openings in the via dielectric layer, where the patterned etch stop layer acts as a hard-mask in forming vias in the via dielectric layer. | 01-28-2010 |
20100022085 | Method of Forming Support Structures for Semiconductor Devices - Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials. | 01-28-2010 |
20100029076 | METHOD OF MAKING AN INTERCONNECT STRUCTURE - A damascene process is described using a copper fill process to fill a trench ( | 02-04-2010 |
20100035426 | MULTI-LAYER CIRCUIT SUBSTRATE FABRICATION AND DESIGN METHODS PROVIDING IMPROVED TRANSMISSION LINE INTEGRITY AND INCREASED ROUTING DENSITY - An integrated circuit substrate is designed and fabricated with a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs. | 02-11-2010 |
20100081272 | Methods of Forming Electrical Interconnects Using Electroless Plating Techniques that Inhibit Void Formation - Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer. | 04-01-2010 |
20100112803 | Methods of Forming Integrated Circuit Devices Using Contact Hole Spacers to Improve Contact Isolation - Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material. This sequential etching of the first material at a faster rate than the second material may yield a contact hole having a recessed sidewall. | 05-06-2010 |
20100112804 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE EMBEDDED SUBSTRATE - A manufacturing method for a semiconductor device embedded substrate, includes: a first step including: a step of forming a connection terminal on an electrode pad formed on a semiconductor integrated circuit, a step of forming a first insulating layer on the semiconductor integrated circuit, a step of providing a plate-like body on the first insulating layer, a step of exposing a part of the connection terminal, and a step of removing the plate-like body to manufacture a semiconductor device; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; and a fifth step of forming a first wiring pattern electrically connected to the exposed portion on a surface of each of the first insulating layer and the second insulating layer. | 05-06-2010 |
20100112805 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - There is provided a semiconductor device and method of fabricating the same that employs an insulation film of a borazine-based compound to provided enhanced contact between a material for insulation and that for interconnection, increased mechanical strength, and other improved characteristics. The semiconductor device includes a first insulation layer having a recess with a first conductor layer buried therein, an etching stopper layer formed on the first insulation layer, a second insulation layer formed on the etching stopper layer, a third insulation layer formed on the second insulation layer, and a second conductor layer buried in a recess of the second and third insulation layers. The second and third insulation layers are grown by chemical vapor deposition with a carbon-containing borazine compound used as a source material and the third insulation layer is smaller in carbon content than the second insulation layer. | 05-06-2010 |
20100124820 | Method of Making a Contact in a Semiconductor Device - To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask. | 05-20-2010 |
20100130003 | Method of Forming Through-Silicon Vias - A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV. | 05-27-2010 |
20100130004 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant insulating film in the pad forming region is disposed in higher density than that of a Cu film serving as a via in the element forming region. Hereby, when an internal stress occurs, the stress is prevented from disproportionately concentrating on the via, and deterioration of a function of a wiring caused thereby can be avoided. | 05-27-2010 |
20100144138 | METHODS OF FORMING CONTACT STRUCTURES AND SEMICONDUCTOR DEVICES FABRICATED USING CONTACT STRUCTURES - Provided are methods of forming contact structures and semiconductor devices fabricated using the contact structures. The formation of a contact structure can include forming a first molding pattern on a substrate, forming an insulating layer to cover at least a sidewall of the first molding pattern, forming a second molding pattern to cover a sidewall of the insulating layer and spaced apart from the first molding pattern, removing a portion of the insulating layer between the first and second molding patterns to form a hole, and forming an insulating pattern between the first and second molding patterns, and forming a contact pattern in the hole. | 06-10-2010 |
20100151675 | WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - There are provided with a wiring structure and a method for manufacturing the same wherein in a wiring structure of multi-layered wiring in which a metal wiring is formed on a substrate forming a semiconductor element thereby obtaining connection of the element, no damage to insulation property between the abutting wirings by occurrence of leakage current and no deterioration of insulation resistance property between the abutting wirings are achieved in case that fine metal wiring is formed in a porous insulation film. The insulation barrier layer | 06-17-2010 |
20100159693 | Method of Forming Via Recess in Underlying Conductive Line - A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the conductive line at the via. The via recess in the conductive line has a depth ranging from about 100 angstroms to about 600 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example. | 06-24-2010 |
20100167525 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered. | 07-01-2010 |
20100173491 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of forming an insulating layer on an conductive layer; forming a first mask layer and a second mask layer on the insulating layer; forming a resist layer on the second mask layer; patterning the resist layer; patterning the second mask layer by using the resist layer as a mask; etching the first mask layer halfway through its thickness by using the resist layer and the second mask layer as a mask; removing the resist layer; etching a remaining portion of the first mask layer using the second mask layer as a mask; forming an interconnect groove by etching the insulating layer using the first mask layer as a mask; and forming an electrically conductive material into the interconnect groove, thereby forming an interconnect layer connected to the conductive layer. | 07-08-2010 |
20100190334 | THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor circuit structure includes a support substrate which carries an interconnect region and electronic circuitry. The semiconductor circuit structure includes a device substrate coupled to the interconnect region through a conductive bonding layer. The device substrate includes a planarized surface which faces the conductive bonding layer. The device substrate can carry laterally oriented semiconductor devices which are connected to the electronic circuitry carried by the support substrate. The device substrate can be processed to form vertically oriented semiconductor devices which are connected, through the interconnect region and conductive bonding layer, to the electronic circuitry carried by the support substrate. | 07-29-2010 |
20100197133 | METHOD OF FORMING A METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE BY USING A HARD MASK FOR DEFINING THE VIA SIZE - In a “via first/trench last” approach for forming metal lines and vias in a metallization system of a semiconductor device, a combination of two hard masks may be used, wherein the desired lateral size of the via openings may be defined on the basis of spacer elements, thereby resulting in significantly less demanding lithography conditions compared to conventional approaches. | 08-05-2010 |
20100203724 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other. | 08-12-2010 |
20100210103 | Method of manufacturing semiconductor device - There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate, forming a first insulating layer, a first redistribution layer, a second insulating layer, a second redistribution layer, and at least one of first processing, in which, after the first electrically conductive material is filled in the first opening to form a first via interconnect, the first redistribution layer is formed on the first insulating layer with the first electrically conductive material such that the first redistribution layer is electrically connected to the first via interconnect; or second processing, in which, after the second electrically conductive material is filled in the second opening to form a second via interconnect, the second redistribution layer is formed on the second insulating layer with the second electrically conductive material such that the second redistribution layer is electrically connected to the second via interconnect. | 08-19-2010 |
20100216303 | SEMICONDUCTOR DEVICE HAVING REINFORCED LOW-K INSULATING FILM AND ITS MANUFACTURE METHOD - A semiconductor device manufacture method has the steps of: (a) coating a low dielectric constant low-level insulating film above a semiconductor substrate formed with a plurality of semiconductor elements; (b) processing the low-level insulating film to increase a mechanical strength of the low-level insulating film; (c) coating a low dielectric constant high-level insulating film above the low-level insulating film; and (d) forming a buried wiring including a wiring pattern in the high-level insulating film and a via conductor in the low-level insulating film. The low-level insulating film and high-level insulating film are made from the same material. The process of increasing the mechanical strength includes an ultraviolet ray irradiation process or a hydrogen plasma applying process. | 08-26-2010 |
20100227471 | Pseudo Hybrid Structure for Low K Interconnect Integration - A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer ( | 09-09-2010 |
20100240212 | Method of manufacturing a semiconductor device - A semiconductor device manufacturing method includes a process for filling holes in a dielectric film with tungsten. The process deposits tungsten in the holes, partially etches the deposited tungsten, and then deposits additional tungsten in the holes. Voids that may be left by the first tungsten deposition step are made accessible by openings formed in the etching step, and are then filled in by the second tungsten deposition step. Tungsten hexafluoride may be used as both a deposition source gas and an etching gas, providing a simple and inexpensive process that is suitable for high-volume production. | 09-23-2010 |
20100261346 | CIRCUIT MANUFACTURING AND DESIGN TECHNIQUES FOR REFERENCE PLANE VOIDS WITH STRIP SEGMENT - Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor. | 10-14-2010 |
20100279502 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING A THIN FILM PROBE SHEET FOR USING THE SAME - A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested. | 11-04-2010 |
20100297843 | Method for Forming Vias in a Semiconductor Substrate and a Semiconductor Device having the Semiconductor Substrate - The present invention relates to a method for forming vias in a semiconductor substrate, including the following steps: (a) providing a semiconductor substrate having a first surface and a second surface; (b) forming a groove on the semiconductor substrate; (c) filling the groove with a conductive metal; (d) removing part of the semiconductor substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the semiconductor substrate; and (e) forming an insulating material in the accommodating space. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even. | 11-25-2010 |
20110003472 | WIRING SUBSTRATE FOR MOUNTING SEMICONDUCTORS, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE - A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates. | 01-06-2011 |
20110021020 | SEMICONDUCTOR DEVICE AND FABRICATION PROCESS THEREOF - A semiconductor device includes a first interconnection pattern embedded in a first insulation film, a second insulation film covering the first interconnection pattern over the first insulation film, an interconnection trench formed in an upper part of the second insulation film, a via-hole extending downward from the interconnection trench at a lower part of the second insulation film, the via-hole exposing the first interconnection pattern, a second interconnection pattern filling the interconnection trench, a via-plug extending downward in the via-hole from the second interconnection pattern and making a contact with the first interconnection pattern, and a barrier metal film formed between the second interconnection pattern and the interconnection trench, the barrier metal film covering a surface of the via-plug continuously, wherein the via-plug has a tip end part invading into the first interconnection pattern across a surface of said first interconnection pattern, the interconnection trench has a flat bottom surface, and the barrier metal film has a larger film thickness at the tip end part of the via-plug as compared with a sidewall surface of the via-plug. | 01-27-2011 |
20110021021 | METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE - A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are patterned to form a via hole exposing a portion of the liner layer. A gap-filling layer is filled in the via hole, having a height of ¼ to ½ of the depth of the via hole. A trench is formed in the metal hard mask layer and the dielectric layer. The gap-filling layer is removed to expose the portion of the liner layer, which is then removed. A metal layer is formed filling in the via hole and the trench, and then the metal hard mask layer is removed. | 01-27-2011 |
20110027986 | LOW COST METHOD OF FABRICATION OF VERTICAL INTERCONNECTIONS COMBINED TO METAL TOP ELECTRODES - A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit. | 02-03-2011 |
20110065272 | STACKED MULTILAYER STRUCTURE AND MANUFACTURING METHOD THEREOF - A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film. | 03-17-2011 |
20110086507 | METHOD FOR PROVIDING OXIDE LAYERS - A method for providing an oxide layer on a semiconductor substrate is disclosed. In one aspect, the method includes obtaining a semiconductor substrate. The substrate may have a three-dimensional structure, which may comprise at least one hole. The method may also include forming an oxide layer on the substrate, for example, on the three-dimensional structure, by anodizing the substrate in an acidic electrolyte solution. | 04-14-2011 |
20110086508 | SEMICONDUCTOR DEVICE HAVING METAL WIRINGS OF LAMINATED STRUCTURE - A semiconductor device that includes a metal wiring formed on the insulating film and having a main wiring portion laminated with a plurality of metal films and a metal protection film formed at least on the upper surfaces of the main wiring portion and made of a precious metal material. | 04-14-2011 |
20110092068 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first insulation film formed over a semiconductor substrate; and a plurality of first interconnects selectively formed in the first insulation film. A plurality of gaps are formed in part of the first insulation film located between adjacent ones of the first interconnects so that each of the gaps has a cylindrical shape extending vertically to a principal surface of the semiconductor substrate. A cap film is formed of metal or a material containing metal in upper part of each of the first interconnects. | 04-21-2011 |
20110104888 | SEMICONDUCTOR DEVICES HAVING REDISTRIBUTION STRUCTURES AND PACKAGES, AND METHODS OF FORMING THE SAME - Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad. | 05-05-2011 |
20110104889 | Methods of Forming Integrated Circuit Devices Using Contact Hole Spacers to Improve Contact Isolation - Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material. This sequential etching of the first material at a faster rate than the second material may yield a contact hole having a recessed sidewall. | 05-05-2011 |
20110143532 | Method of forming semiconductor cell structure, method of forming semiconductor device including the semiconductor cell structure, and method of forming semiconductor module including the semiconductor device - In a method of forming a semiconductor cell structure, a first insulating layer may be formed on a semiconductor substrate. A connection pattern may be formed in the first insulating layer. Second and third insulating layers may be sequentially formed on the connection pattern. The third insulating layer may be etched at least twice and the second insulating layer may be etched at least once to form a through hole in the second and third insulating layers. The through hole may expose the connection pattern. | 06-16-2011 |
20110171825 | Method of Fabricating Integrated Circuitry - The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated. | 07-14-2011 |
20110183513 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed. | 07-28-2011 |
20110256711 | MICROFEATURE WORKPIECES HAVING CONDUCTIVE INTERCONNECT STRUCTURES FORMED BY CHEMICALLY REACTIVE PROCESSES, AND ASSOCIATED SYSTEMS AND METHODS - Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a conductive lining on walls of a via in a microfeature workpiece, so that a space is located between opposing portions of the lining facing toward each other from opposing portions of the wall. The method can further include chemically reacting the lining with a reactive material to form a chemical compound from a constituent of the reactive material and a constituent of the lining. The method can still further include at least partially filling the space with the compound. In particular embodiments, the conductive lining includes copper, the reactive material includes sulfur hexafluoride, and the chemical compound that at least partially fills the space in the via includes copper sulfide. | 10-20-2011 |
20110306202 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure. | 12-15-2011 |
20120003830 | METHOD FOR MANUFACTURE OF INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PROTECTED CONDUCTIVE LAYERS FOR PADS - A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer. | 01-05-2012 |
20120021601 | Methods of Forming Through Substrate Interconnects - A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material. | 01-26-2012 |
20120021602 | LOW RESISTANCE AND RELIABLE COPPER INTERCONNECTS BY VARIABLE DOPING - A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity. | 01-26-2012 |
20120028459 | MANUFACTURING PROCESS OF CIRCUIT SUBSTRATE - A manufacturing process of a circuit substrate is provided. A conductive structure including a first patterned conductive layer, a first dielectric layer, a second dielectric layer, a first conductive layer, and a second conductive layer is provided. The first dielectric layer and the second dielectric layer are respectively disposed on two opposite surfaces of the first patterned conductive layer. The first conductive layer and the second conductive layer are respectively disposed on the first dielectric layer and the second dielectric layer. The first dielectric layer is between the first patterned conductive layer and the first conductive layer. The second dielectric layer is between the first patterned conductive layer and the second conductive layer. A conductive via is formed at the conductive structure. The first conductive layer and the second conductive layer are patterned to respectively form a second patterned conductive layer and a third patterned conductive layer. | 02-02-2012 |
20120028460 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member. | 02-02-2012 |
20120040525 | METHOD FOR FORMING INTERCONNECTION LEVELS OF AN INTEGRATED CIRCUIT - A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level including conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure. | 02-16-2012 |
20120070977 | Methods For Forming Contacts in Semiconductor Devices - Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance. | 03-22-2012 |
20120070978 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved. | 03-22-2012 |
20120083115 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT STRUCTURE AND A REINFORCING INSULATING FILM - A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first interconnect, a Cu silicide layer covering the upper portion of the first plug, a first porous MSQ film provided over the side wall from the first interconnect through the first plug and formed to cover the side wall of the first interconnect, the upper portion of the first interconnect, and the side wall of the first plug, and a first SiCN film disposed under the first porous MSQ film to contact with the lower portion of the side wall of the first interconnect and having the greater film density than the first porous MSQ film. | 04-05-2012 |
20120094482 | MICROELECTRONIC DEVICES AND METHODS FOR FILING VIAS IN MICROELECTRONIC DEVICES - Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece. | 04-19-2012 |
20120108054 | Dual Damascene Copper Process Using a Selected Mask - A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the via, and a second step to mask and expose the trench interconnection. The novel method for creating a dual damascene structure allows for a smaller number of processing steps, thus reducing the processing time needed to complete the dual damascene structure. In addition, a lower number of masks may be needed. The exemplary mask or reticle used within the process incorporates different regions possessing different transmission rates. During the exposing step, light from an exposing source passes through the mask to expose a portion of the photoresist layer on top of the wafer. Depending on the transmission rate of the different regions, different thickness of the photoresist layer are exposed and later removed by a developing solution, which allows a subsequent etch process to remove portions of both the dielectric layer and photoresist layer to create a dual damascene structure. | 05-03-2012 |
20120108055 | MANUFACTURING PROCESS OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate. | 05-03-2012 |
20120108056 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure. | 05-03-2012 |
20120115322 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a plurality of photoresist patterns over a substrate structure; forming an insulation layer for a spacer over a structure including the photoresist patterns; forming a plurality of spacers on sidewalls of the photoresist patterns by anisotropically etching the insulation layer, and forming a first opening through the insulation layer; and forming second openings in the insulation layer to expose the substrate structure. | 05-10-2012 |
20120129338 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - When a wiring structure is formed by a trench-first dual damascene method, a first hard mask for forming via holes and a second hard mask for forming wiring trenches are sequentially formed on an interlayer insulating film, openings are formed at the first hard mask while using the second hard mask as a mask, and thereafter, the openings are expanded in a lateral direction by an isotropic etching to form openings, via holes are formed by etching the interlayer insulating film while using the first hard mask and the second hard mask as masks, and wiring trenches communicating with the via holes are formed by etching the interlayer insulating film while using the second hard mask as a mask. | 05-24-2012 |
20120220119 | SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS - Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance. | 08-30-2012 |
20120225550 | HYBRID PITCH-SPLIT PATTERN-SPLIT LITHOGRAPHY PROCESS - An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks, using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern and which extends to a second point in the first instance of the parallel route tracks, laterally separated from the first point by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks. | 09-06-2012 |
20120225551 | PATTERN-SPLIT DECOMPOSITION STRATEGY FOR DOUBLE-PATTERNED LITHOGRAPHY PROCESS - An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, and forming a second interconnect pattern in the plurality of parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point in an instance of the first plurality of parallel route tracks, and the second interconnect pattern includes a second lead pattern which extends to a second point in the same instance of the plurality of parallel route tracks, such that the second point is laterally separated from the first point by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern. | 09-06-2012 |
20120225552 | TWO-TRACK CROSS-CONNECTS IN DOUBLE-PATTERNED METAL LAYERS USING A FORBIDDEN ZONE - An integrated circuit is formed by forming a first interconnect pattern in parallel route tracks, and forming a second interconnect pattern in alternating parallel route tracks. The first interconnect pattern includes a first lead pattern in the parallel route tracks, and the second interconnect pattern includes a second lead pattern in an immediately adjacent route track. The first interconnect pattern includes a crossover pattern which extends from the first lead pattern to the second lead pattern. An exclusion zone in the route track immediately adjacent to the crossover pattern is free of a lead pattern for a lateral distance of two to three times the width of the crossover pattern. Metal interconnect lines are form in the first interconnect pattern and the second interconnect pattern areas, including a continuous metal crossover line through the crossover pattern area. The exclusion zone is free of the metal interconnect lines. | 09-06-2012 |
20120231624 | Process for Producing Vertical Interconnections Through Structured Layers - A process is provided for producing at least one interconnecting well to achieve a conductive pathway between at least two connection layers of a component comprising a stack of at least one first substrate and one second substrate which are electrically insulated from one another, the process including defining a surface contact region of a surface connection layer over a surface of the stack and of at least one first contact region embedded in the stack starting from a first embedded connection layer of the first substrate. A region devoid of material is positioned between the first substrate and second substrates and which comprises a stage of producing a interconnecting well which passes through the second substrate and extends between the surface contact region and the first embedded contact region and passes through the region devoid of material, and also a first layer which covers the first embedded connection layer. | 09-13-2012 |
20120264289 | INTEGRATED CIRCUIT INTERCONNECT STRUCTURE - An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a dielectric and coupled to the first via at an opposite end thereof. The buffer metal segment includes a plurality of electrically insulating inter-dielectric (ILD) pads forming an ILD cheesing pattern thereon, to direct current. The IC interconnect structure further includes a second via positioned in a dielectric formed over the buffer metal segment and coupled to the buffer metal segment at one end and a metal power line formed in a dielectric and coupled to the second via at an opposite end thereof. The use of the ILD pads on the buffer metal segment enables a more even distribution of current along the metal power line. | 10-18-2012 |
20120270390 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP. | 10-25-2012 |
20120276735 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - An improved method of forming a semiconductor device including an interconnect layer formed using multilayer hard mask comprising metal mask and dielectric mask is provided. To form the second opening pattern being aligned to the first pattern, after the multilayer hard mask is used at the first step, then the dielectric mask is used to form a damascene structure in an insulator layer at the second step followed by removing the metal mask. | 11-01-2012 |
20120302057 | SELF ALIGNING VIA PATTERNING - A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch. | 11-29-2012 |
20130029485 | METHOD OF MAKING A DIE WITH RECESSED ALUMIUM DIE PADS - A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer. | 01-31-2013 |
20130034957 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device may include, but is not limited to, the following processes. A multi-layered structure is prepared over a semiconductor substrate. The multi-layered structure may include, but is not limited to, first and second patterns of a first insulating film, a second insulating film covering the first pattern of the first insulating film, and a first conductive film covering the second pattern of the first insulating film. The second insulating film and the first conductive film are polished under conditions that the first and second insulating films are greater in polishing rate than the first conductive film, to expose the first and second patterns of the first insulating film. | 02-07-2013 |
20130065390 | CHIPS HAVING REAR CONTACTS CONNECTED BY THROUGH VIAS TO FRONT CONTACTS - A method of fabricating a microelectronic unit can include providing a semiconductor element having front and rear surfaces, a plurality of conductive pads each having a top surface exposed at the front surface and a bottom surface remote from the top surface, and a first opening extending from the rear surface towards the front surface. The method can also include forming at least one second opening extending from the first opening towards the bottom surface of a respective one of the pads. The method can also include forming a conductive via, a conductive interconnect, and a contact, the conductive via in registration with and in contact with the conductive pad and extending within the second opening, the contact exposed at an exterior of the microelectronic unit, the conductive interconnect electrically connecting the conductive via with the contact and extending away from the via at least partly within the first opening. | 03-14-2013 |
20130102147 | Methods of Forming Conductive Structures in Dielectric Layers on an Integrated Circuit Device - One method disclosed herein includes the steps of forming a ULK material layer, forming a hard mask layer above the ULK material layer, forming a patterned photoresist layer above the hard mask layer, performing at least one etching process to define an opening in at least the ULK material layer for a conductive structure to be positioned in at least the ULK material layer, forming a fill material such that it overfills the opening, performing a process operation to remove the patterned photoresist layer and to remove the fill material positioned outside of the opening, removing the fill material from within the opening and, after removing the fill material from within the opening, forming a conductive structure in the opening. | 04-25-2013 |
20130157456 | METHODS RELATING TO THE FABRICATION OF DEVICES HAVING CONDUCTIVE SUBSTRATE VIAS WITH CATCH-PAD ETCH-STOPS - An electronic device having a conductive substrate via extending between a conductor on a rear face and a conductor over a front face of the substrate includes a multi-layered etch-stop beneath the front surface conductor. The etch-stop permits use of a single etchant to penetrate both the substrate and any overlying semiconductor and/or dielectric without attacking the overlying front surface conductor. This is especially important when the semiconductor and dielectric are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop is preferably a stack of N≧2 pairs of sub-layers, where a first sub-layer comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer comprises etch resistant material (e.g., Ni). In a further embodiment, where the device includes field effect transistors having feedback sensitive control gates, the etch-stop material is advantageously used to form gate shields. | 06-20-2013 |
20130157457 | INTERCONNECTS FOR STACKED NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure. | 06-20-2013 |
20130171817 | STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION - A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers. | 07-04-2013 |
20130196501 | METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC WORKPIECES AND MICROELECTRONIC WORKPIECES FORMED USING SUCH METHODS - Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment, for example, is directed to a method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic dies. The method can include forming a first opening in the substrate from a back side of the substrate toward a front side and in alignment with terminals of the dies. The first opening separates an island of substrate material from the substrate. The method can also include depositing an insulating material into at least a portion of the first opening, and then removing the island of substrate material to form a second opening. In several embodiments, the method may include constructing an electrically conductive interconnect in at least a portion of the second opening and in electrical contact with the terminal. | 08-01-2013 |
20130230981 | PATTERN FORMING METHOD - According to one embodiment, a pattern forming method comprises forming, on a metal layer and an insulating layer, an underlying layer the surface state of which is changeable by irradiation with a light ray, radiating the light ray to the underlying layer, thereby changing the surface state of a portion of the underlying layer above the metal layer, forming a block polymer layer on the underlying layer, forming, on the underlying layer, a directed self-assembly phase which contains a first polymer portion and a second polymer portion, the first polymer portion being positioned above the underlying layer portion the surface state of which has been changed by the radiation of the light ray, removing the first polymer portion, and the underlying layer portion underneath the first polymer portion to make a hole, and burying a conductive film into the hole. | 09-05-2013 |
20130244420 | OPTIMIZED ANNULAR COPPER TSV - The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench. | 09-19-2013 |
20130267088 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings. | 10-10-2013 |
20130267089 | FILM FOR FILLING THROUGH HOLE INTERCONNECTS AND POST PROCESSING FOR INTERCONNECT SUBSTRATES - A method for filling through hole interconnects in a substrate used in the manufacture of electronic devices uses a film filler material. The film comprises a resin matrix filled with conductive and/or dielectric particles, and can be a single or multi-layer film. The method comprises providing a substrate for an electronic device having one or more through hole interconnects; providing a film comprising at least one film filler material for the through hole interconnects; deposing the film filler material over the substrate; and pressing the film filler material into the through hole interconnects. | 10-10-2013 |
20130288474 | METHODS FOR FABRICATING DUAL DAMASCENE INTERCONNECT STRUCTURES - Methods for fabricating dual damascene interconnect structures are provided herein. In some embodiments, a method for fabricating a dual damascene interconnect structure may include etching a via into a substrate through a first photoresist layer; patterning a second photoresist layer atop the substrate to define a trench pattern, wherein the via is aligned within the trench pattern, and wherein a portion of undeveloped photoresist remains in the via after patterning; and etching the trench into the substrate to form a dual damascene pattern in the substrate. | 10-31-2013 |
20130316529 | METHOD OF FORMING A MICRO DEVICE TRANSFER HEAD WITH SILICON ELECTRODE - A micro device transfer head array and method of forming a micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect. A dielectric layer covers a top surface of each mesa structure. | 11-28-2013 |
20130316530 | Three-Dimensional Semiconductor Architecture - A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate. | 11-28-2013 |
20130323924 | METHODS OF FORMING A PATTERN IN A MATERIAL AND METHODS OF FORMING OPENINGS IN A MATERIAL TO BE PATTERNED - Methods of forming a pattern in a material and methods of forming openings in a material to be patterned are disclosed, such as a method that includes exposing first portions of a first material to radiation through at least two apertures of a mask arranged over the first material, shifting the mask so that the at least two apertures overlap a portion of the first portions of the first material, and exposing second portions of the first material to radiation through the at least two apertures. The first portions and the second portions will overlap in such a way that non-exposed portions of the first material are arranged between the first portions and second portions. The non-exposed or exposed portions of the first material may then be removed. The remaining first material may be used as a photoresist mask to form vias in an integrated circuit. The pattern of vias produced have the capability to exceed the current imaging resolution of a single exposure treatment. | 12-05-2013 |
20140017887 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1) | 01-16-2014 |
20140024211 | USE OF GRAPHENE TO LIMIT COPPER SURFACE OXIDATION, DIFFUSION AND ELECTROMIGRATION IN INTERCONNECT STRUCTURES - A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure. | 01-23-2014 |
20140030885 | METHOD FOR FORMING DUAL DAMASCENE OPENING - A method for forming a dual damascene opening includes the following steps. Firstly, a first hard mask layer with a trench pattern is formed over a material layer. Then, a dielectric layer is formed over the first hard mask layer and filled into an opening of the trench pattern. Then, a second hard mask layer with a via opening pattern is formed over the first hard mask layer and the dielectric layer. Then, a first etching process is performed, so that a via opening is at least formed in the dielectric layer. After the second hard mask layer is removed, a second etching process is performed. Consequently, a trench opening is formed in the material layer and the via opening is further extended into the material layer, wherein the via opening is located within the trench opening. | 01-30-2014 |
20140038410 | METHOD OF PRODUCING A SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT THROUGH THE SUBSTRATE - A semiconductor substrate ( | 02-06-2014 |
20140057432 | SEMICONDUCTOR DEVICE INCLUDING COPPER WIRING AND VIA WIRING HAVING LENGTH LONGER THAN WIDTH THEREOF AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes forming a first interconnect over the semiconductor substrate; forming an interlayer dielectric film over the first interconnect; forming a hole in the interlayer dielectric film such that the hole reaches the first interconnect; forming a trench in the interlayer dielectric film; and embedded a conductive film in the hole and the trench, thereby a via is formed in the hole and a second interconnect in the trench, wherein, in a planar view, the first interconnect extends in a first direction, wherein, in a planar view, the second interconnect extends in a second direction which is perpendicular to the first direction, and wherein a maximum width of the via in the second direction is larger than a maximum width of the via in the first direction. | 02-27-2014 |
20140057433 | PIXEL CAPACITORS - A technique comprising: forming laterally-extending switching circuitry of a device for controlling an overlying laterally-extending array of pixel conductors of said device; forming an electrically conductive laterally-extending patterned screen over said switching circuitry via a first insulating region, said patterned screen defining holes for receiving conductive interlayer connects between said switching circuitry and said array of pixel conductors; and thereafter: forming a second insulating region over said patterned screen, forming said array of pixel conductors over said patterned screen via said second insulating region for capacitative coupling with said patterned screen, forming through holes through at least said first and second insulating regions at the locations of said holes defined in said patterned screen, and forming said interlayer connects in said through holes; and wherein said patterned screen is configured such that the area of overlap between the array of pixel conductors and underlying conductive elements is substantially constant within a range of lateral positions of the pixel conductors relative to the switching circuitry, which range is greater in a first direction than 40% of the pitch of the pixel conductors in said first direction. | 02-27-2014 |
20140065817 | HIGH PERFORMANCE ON-CHIP VERTICAL COAXIAL CABLE, METHOD OF MANUFACTURE AND DESIGN STRUCTURE - A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface. | 03-06-2014 |
20140087555 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions. | 03-27-2014 |
20140094029 | METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS - A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero. | 04-03-2014 |
20140127897 | DUAL DAMASCENE PROCESS - A method for forming dual damascene structures in a semiconductor structure is disclosed. The method generally includes etching a substrate using a first hard mask to form a plurality of first trenches and vias, forming a set of first conductive lines and via interconnects, removing the first hard mask, etching the substrate using a second hard mask to form a plurality of second trenches and vias, and forming a set of second conductive lines and via interconnects. At least some of the first conductive lines are interspersed between some of the second conductive lines. A planarization process is used on the substrate after forming the first conductive lines and via interconnects before forming the second conductive lines and via interconnects. | 05-08-2014 |
20140141607 | CONTINUOUS VIA FOR POWER GRID - A power grid of a Very Large Scale Integration (VLSI) circuit includes a sandwich structure in a cell. The sandwich structure includes a first metal layer configured to carry current along a lateral axis, and a second metal layer, parallel to the first metal layer with a gap therebetween. The second metal layer carries current along a second lateral axis which is parallel to the lateral axis of the first metal layer. The sandwich structure also includes interconnect material disposed as a continuous via throughout the gap, the continuous via interconnecting the first metal layer and the second metal layer throughout the gap. | 05-22-2014 |
20140148005 | SEMICONDUCTOR DEVICE WITH SELF ALIGNED END-TO-END CONDUCTIVE LINE STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming semiconductor devices using damascene techniques provides self-aligned conductive lines that have an end-to-end spacing less than 60 nm without shorting. The method includes using at least one sacrificial hardmask layer to produce a mandrel and forming a void in the mandrel. The sacrificial hardmask layers are formed over a base material which is advantageously an insulating material. Another hardmask layer is also disposed over the base material and under the mandrel in some embodiments. Spacer material is formed alongside the mandrel and filling the void. The spacer material serves as a mask and at least one etching procedure is carried out to translate the pattern of the spacer material into the base material. The patterned base material includes trenches and raised portions. Conductive features are formed in the trenches using damascene techniques. | 05-29-2014 |
20140179098 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device includes a capacitor including a plurality of interconnection layers stacked over each other, the plurality of interconnection layers each including a plurality of electrode patterns extended in a first direction, a plurality of via parts provided between the plurality of interconnection layers and electrically interconnecting the plurality of the electrode patterns between the interconnection layers adjacent to each other, and an insulating films formed between the plurality of interconnection layers and the plurality of via parts. Each of the plurality of via parts is laid out, offset from a center of the electrode pattern in a second direction intersecting the first direction, and the plurality of electrode patterns has a larger line width at parts where the via parts are connected to, and a distance between the electrode patterns and the adjacent electrode patterns is reduced at the parts. | 06-26-2014 |
20140199832 | TITANIUM OXYNITRIDE HARD MASK FOR LITHOGRAPHIC PATTERNING - A vertical stack including a dielectric hard mask layer and a titanium nitride layer is formed over an interconnect-level dielectric material layer such as an organosilicate glass layer. The titanium nitride layer may be partially or fully converted into a titanium oxynitride layer, which is subsequently patterned with a first pattern. Alternately, the titanium nitride layer, with or without a titanium oxynitride layer thereupon, may be patterned with a line pattern, and physically exposed surface portions of the titanium nitride layer may be converted into titanium oxynitride. Titanium oxynitride provides etch resistance during transfer of a combined first and second pattern, but can be readily removed by a wet etch without causing surface damages to copper surfaces. A chamfer may be formed in the interconnect-level dielectric material layer by an anisotropic etch that employs any remnant portion of titanium nitride as an etch mask. | 07-17-2014 |
20140199833 | METHODS FOR PERFORMING A VIA REVEAL ETCHING PROCESS FOR FORMING THROUGH-SILICON VIAS IN A SUBSTRATE - The present disclosure provides methods for via reveal etching process to form through-silicon vias (TSVs) in a substrate. In one embodiment, a method for performing a via reveal process to form through-silicon vias in a substrate includes providing a substrate having partial through-silicon vias formed from a first surface of the substrate into a processing chamber, wherein the partial through-silicon vias formed in the substrate are blind vias, supplying an etching gas mixture including at least a fluorine containing gas and a chlorine containing gas into the processing chamber, and preferentially removing a portion of the substrate from a second surface of the substrate to expose the through-silicon vias until a desired length of the through-silicon vias is exposed from the second surface of the substrate. | 07-17-2014 |
20140206186 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer. | 07-24-2014 |
20140213050 | METHOD OF MAKING A DIE WITH RECESSED ALUMINUM DIE PADS - A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer. | 07-31-2014 |
20140248768 | Mask Assignment Optimization - A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines. | 09-04-2014 |
20140273433 | DOUBLE PATTERNING METHOD - Self-aligned double patterning methods that can be used in back-end-of-line (BEOL) processing and other stages of integrate circuit device manufacturing. In these methods, line termini are masked prior to self-aligned double patterning. The self-aligned double patterning involves forming a mandrel, the shape of which is determined by a lithographic mask. That same lithographic mask is used prior to self-aligned double patterning to trim the mask that determines the locations of line termini. The methods provide precise positioning of the line termini mask relative to the line locations determined by self-aligned double patterning. The methods forms consistent end-of-line shapes and allow line termini to be placed more closely together than would otherwise be feasible. | 09-18-2014 |
20140287579 | METHODS FOR FABRICATING DUAL DAMASCENE STRUCTURES IN LOW TEMPERATURE DIELECTRIC MATERIALS - Methods for fabricating dual damascene structures are provided herein. In some embodiments, a method for fabricating a dual damascene interconnect structure may include patterning a first mask layer atop a substrate disposed in a process chamber, wherein the substrate includes one or more low temperature dielectric layers to define a first etch pattern, and wherein the one or more low temperature dielectric layers are formed atop the substrate at a temperature below about 180 degrees Celsius; etching the first etch pattern into the one or more low temperature dielectric layers using an inductively coupled plasma formed by a power source capable of providing power within a range from about 10 watts to about 10,000 watts at a frequency of about 2 MHz to about 13.5 MHz; patterning a second mask layer atop the substrate to define a second etch pattern, wherein the first etch pattern and the second etch pattern are aligned; and etching the second etch pattern into the one or more low temperature dielectric layers to form a dual damascene pattern in the substrate, wherein a pressure of the process chamber during etching of the first etch pattern and the second etch pattern is about 10 mTorr to about 1000 mTorr. | 09-25-2014 |
20140295662 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device and methods directed toward preventing a leakage current between a contact plug and a line adjacent to the contact plug, and minimizing capacitance between adjacent lines. | 10-02-2014 |
20140322911 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A method of forming a semiconductor device may include forming a contact mold layer on a substrate; forming an interconnection mold layer on the contact mold layer that includes a material having an etching selectivity with respect to the contact mold layer; forming grooves in the interconnection mold layer that extend in a first direction and expose the contact mold layer; forming holes in the contact mold layer connected to the grooves by etching a part of the contact mold layer exposed by the groove; and forming contact portions in the holes and interconnections in the groove. A diffusion coefficient of mobile atoms in the contact mold layer is greater than a diffusion coefficient of mobile atoms in a nitride. | 10-30-2014 |
20140329384 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to each of the interconnects. A protrusion is formed at a portion of the each of the interconnects connected to the contact via to protrude in a direction of the arrangement. A recess is formed at a portion of the each of the interconnects separated from the portion having the protrusion to recede in the direction of the arrangement. The protrusion formed on one interconnect of two mutually-adjacent interconnects among the plurality of interconnects is opposed to the recess formed in one other interconnect of the two mutually-adjacent interconnects. In the each of the interconnects, the portion having the recess is separated from portions on two sides of the portion having the recess and is separated also from the portion having the protrusion. | 11-06-2014 |
20140342550 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE BY DAMASCENE PROCESS - A method for fabricating a semiconductor device includes forming a plurality of isolation patterns, isolated from each other by a plurality of trenches, over an underlying structure; forming a plurality of conductive lines filled in the trenches, forming contact holes by removing first portions of the isolation patterns, wherein the contact holes are defined by the plurality of conductive lines and second portions of the isolation patterns that remain after removing of the first portions of the isolation patterns, and forming plugs filled in the contact holes. | 11-20-2014 |
20140349478 | METHOD INCLUDING AN ETCHING OF A PORTION OF AN INTERLAYER DIELECTRIC IN A SEMICONDUCTOR STRUCTURE, A DEGAS PROCESS AND A PRECLEAN PROCESS - A method includes providing a semiconductor structure. The semiconductor structure includes a substrate having a frontside and a backside, an electrically conductive feature including copper provided at the frontside of the substrate and a low-k interlayer dielectric provided over the electrically conductive feature. A portion of the interlayer dielectric is etched. In the etch process, a surface of the electrically conductive feature is exposed. A degas process is performed, wherein the semiconductor structure is exposed to a first gas, and wherein the semiconductor structure is heated from the backside and from the frontside. A preclean process may be performed. The preclean process may include a first phase wherein the semiconductor structure is exposed to a substantially non-ionized second gas and a second phase wherein the semiconductor structure is exposed to a plasma created from the second gas. | 11-27-2014 |
20140349479 | METHOD INCLUDING A REMOVAL OF A HARDMASK FROM A SEMICONDUCTOR STRUCTURE AND RINSING THE SEMICONDUCTOR STRUCTURE WITH AN ALKALINE RINSE SOLUTION - A method includes providing a semiconductor structure. The semiconductor structure includes an electrically conductive feature including a first metal, a dielectric material provided over the electrically conductive feature and a hardmask. The hardmask includes a hardmask material and is provided over the dielectric material. An opening is provided in the interlayer dielectric and the hardmask. A portion of the electrically conductive feature is exposed at a bottom of the opening. The hardmask is removed. The removal of the hardmask includes exposing the semiconductor structure to an etching solution including hydrogen peroxide and a corrosion inhibitor. After the removal of the hardmask, the semiconductor structure is rinsed. Rinsing the semiconductor structure includes exposing the semiconductor structure to an alkaline rinse solution. | 11-27-2014 |
20150011084 | METHOD OF MAKING INTERCONNECT STRUCTURE - A method of making a semiconductor device including forming a first adhesion layer over a substrate. The method further includes forming a second adhesion layer over the first adhesion layer, where the second adhesion layer is formed using an inert gas with a first flow rate under a first RF power. Additionally, the method includes forming a low-k dielectric layer over the second adhesion layer, where the low-k dielectric layer is formed using the inert gas with a second flow rate under a second RF power under at least one of the following two conditions: 1) the second flow rate is different from the first flow rate; or 2) the second RF power is different from the first RF power. Furthermore, the method includes forming an opening in the dielectric layer, the second adhesion layer, and the first adhesion layer. Additionally, the method includes forming a conductor in the opening. | 01-08-2015 |
20150093892 | MICROELECTRONIC DEVICES WITH THROUGH-SUBSTRATE INTERCONNECTS AND ASSOCIATED METHODS OF MANUFACTURING - Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer. | 04-02-2015 |
20150132945 | Methods of Fabricating Semiconductor Devices Including Interlayer Wiring Structures - Semiconductor devices and methods of fabricating the same are disclosed. The methods include forming a first interlayer insulating layer and a conductive contact plug that penetrates the first interlayer insulating layer, forming a second interlayer insulating layer and a first interlayer wiring on the first interlayer insulating layer. The first interlayer wiring penetrates the second interlayer insulating layer and overlaps the first metal contact plug. The second interlayer insulating layer is etched using the first interlayer wiring as a mask until the first metal contact plug is exposed, and an exposed portion of the conductive contact plug is etched using the first interlayer wiring as the mask. | 05-14-2015 |
20150140807 | VIAS IN POROUS SUBSTRATES - A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction. | 05-21-2015 |
20150303110 | MICROFEATURE WORKPIECES HAVING INTERCONNECTS AND CONDUCTIVE BACKPLANES, AND ASSOCIATED SYSTEMS AND METHODS - Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals. The device further includes a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate. One or more of the interconnects are electrically coupled to the conductive layer at the back side of the semiconductor substrate. | 10-22-2015 |
20150311116 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads | 10-29-2015 |
20150318206 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE - One or more techniques or systems for forming a semiconductor structure having a gap are provided herein. In some embodiments, a gap is formed between a first etch stop layer (ESL) and an ESL seal region. For example, the gap is formed by removing a portion of a low-k (LK) dielectric region above an oxide region and removing the oxide region. In some embodiments, the oxide region below the LK dielectric region facilitates removal of the LK dielectric region, at least because the oxide region enhances a bottom etch rate of a bottom of the LK dielectric region such that the bottom etch rate is similar to a wall etch rate of a wall of the LK dielectric region. | 11-05-2015 |
20150357338 | METHODS AND STRUCTURES FOR MULTIPORT MEMORY DEVICES - A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate. | 12-10-2015 |
20150368597 | STRIPPING SOLUTION THAT IS USED FOR REMOVAL OF TITANIUM OR A TITANIUM COMPOUND AND METHOD OF WIRING FORMATION - A stripping solution that is used for removal of titanium or a titanium compound, whereby superior stripping removal performance of the solution can be stably maintained when the solution is continuously circulated, and a method of wiring formation using the stripping solution. The stripping solution includes a basic compound, hydrogen peroxide, water, and at least one of an alkali metal silicate and a bisphosphonate compound. The titanium compound may be titanium nitride, and the stripping solution may be used for removal of a hard mask including titanium or a titanium compound. | 12-24-2015 |
20160020214 | SRAM LAYOUT FOR DOUBLE PATTERNING - An integrated circuit with a SAR SRAM cell with power routed in metal-1. An integrated circuit with a SAR SRAM cell that has power routed in Metal-1 and has metal-1 and metal-2 integrated circuit and SAR SRAM cell patterns which are DPT compatible. A process of forming an integrated circuit with a SAR SRAM cell with DPT compatible integrated circuit and SAR SRAM cell metal-1 and metal-2 patterns. | 01-21-2016 |
20160027690 | SEMICONDUCTOR DEVICE - The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer. | 01-28-2016 |
20160049329 | Long-term heat treated integrated circuit arrangements and methods for producing the same - An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment. | 02-18-2016 |
20160064248 | DOUBLE PATTERNING METHOD - In some embodiments, the disclosure relates to a method of forming an integrated circuit device. The method is performed by forming a first mask layer over a substrate and a second mask layer over the first mask layer. The second mask layer is patterned to form cut regions. A mandrel is formed over the first mask layer and the cut regions, and the first mask layer is etched using the mandrel form a patterned first mask. The substrate is etched according to the patterned first mask and the cut regions to form trenches in the substrate, and the trenches are filled with conductive metal to form conductive lines. | 03-03-2016 |
20160071763 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, at first, while a resist pattern is used as a mask, a first set of one of the first layers and one of the second layers, which is an uppermost set in a stacked body and is exposed, is etched. Then, a hardening layer having a predetermined thickness is formed on an upper side of the resist pattern. Thereafter, slimming is performed to the resist pattern in its in-plane direction perpendicular to its thickness direction. The slimming is completed after the hardening layer is entirely removed or at the same time when the hardening layer is entirely removed. Then, while the resist pattern is used as a mask, a set of one of the first layers and one of the second layers is etched at an exposed area of the stacked body. | 03-10-2016 |
20160079115 | Methods for Fabricating Semiconductor Devices Using Liner Layers to Avoid Damage to Underlying Patterns - A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer. | 03-17-2016 |
20160093513 | SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHODS - A method for forming a semiconductor device includes providing a semiconductor structure which has a substrate and N sub-stack structures numbered from 1 to N, where N is an integer. Each sub-stack structure includes two sub-stacks, and a mask layer overlying the N sub-stack structures. The method also includes repeatedly removing a portion of the mask layer and removing exposed portions of the sub-stack structures to form a first stepped structure, and forming first spacers on sidewalls of the mask layer and the sub-stack structures in the stepped structure, each spacer covering a portion of the exposure portions of the sub-stack structures. The method further includes using the mask layer and the first spacers as masks to remove exposed portions of an upper sub-stack in the first stepped structure, and removing the mask layer and the spacers to form a second stepped structure. | 03-31-2016 |
20160093524 | MULTIHEIGHT ELECTRICALLY CONDUCTIVE VIA CONTACTS FOR A MULTILEVEL INTERCONNECT STRUCTURE - A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of alternating sacrificial layers and insulating layers located over a major surface of a substrate. A contact mask having contact mask openings is provided over the stack, and a first over mask having first over mask openings is provided over the contact mask. A subset of the contact mask openings is substantially aligned with the first over mask openings. Contact openings are formed through the stack, wherein each of the contact openings extends substantially perpendicular to the major surface of the substrate to a respective one of the sacrificial layers. A plurality of electrically conductive via contacts is formed in the plurality of the contact openings. | 03-31-2016 |
20160099170 | METHODS OF FORMING A STACK OF ELECTRODES AND THREE-DIMENSIONAL SEMICONDUCTOR DEVICES FABRICATED THEREBY - Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other. | 04-07-2016 |
20160104619 | Self-aligned Double Patterning - A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer and masking layers over the dielectric layer. A thin spacer layer is used to form spacers alongside a pattern. A reverse image of the spacer pattern is formed and an enlargement process is used to slightly widen the pattern. The widened pattern is subsequently used to pattern an underlying layer. This process may be used to form a pattern in a dielectric layer, which openings may then be filled with a conductive material. | 04-14-2016 |
20160104642 | SELF-ALIGNED VIA AND PLUG PATTERNING WITH PHOTOBUCKETS FOR BACK END OF LINE (BEOL) INTERCONNECTS - Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material. | 04-14-2016 |
20160111330 | METHOD FOR PRODUCING INTERCONNECTIONS FOR 3D INTEGRATED CIRCUIT - Method for producing one or more connection elements for integrated circuit including the formation of sacrificial elements passing through a porous layer formed between two superimposed levels of transistors, then the removal of the sacrificial elements through the porous layer and their replacement by a conductor material before or after having produced a higher level transistor. | 04-21-2016 |
20160133510 | METHOD OF FABRICATING INTEGRATED CIRCUIT - A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern and a first alignment mark and a second reticle is used to form a second pattern and a second alignment mark in a same layer. A third reticle is aligned to the first alignment mark and the second alignment mark, to obtain an overlay correction value; additionally, a third reticle is aligned to the first alignment mark to obtain a first overlay correction value, a third reticle is aligned to the second alignment mark to obtain a second overlay correction value, and a total overlay correction value is obtained by trading off the first overlay correction value and the second overlay correction value. The third reticle is used to form a third pattern by aligning the third reticle with the total overlay correction value. | 05-12-2016 |
20160141302 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes stacked groups each including interlayer insulating patterns and conductive patterns and stacked in at least two tiers, wherein the insulating patterns and the conductive patterns are alternately stacked over a substrate and separated by slits, and a support body including holes and formed between the stacked groups. | 05-19-2016 |
20160148836 | Vias and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor device includes a first metal line in a first insulating layer, and a via having a portion surrounding a portion of a first sidewall of the first metal line. | 05-26-2016 |
20160162621 | METHODS FOR RETARGETING VIAS AND FOR FABRICATING SEMICONDUCTOR DEVICES WITH RETARGETED VIAS - Methods for retargeting a via and for fabricating a semiconductor device with a retargeted via are provided. In one embodiment, a method for retargeting a via includes drawing a lower metal layer shape, drawing a via shape for overlying the lower metal layer shape, and drawing an upper metal layer shape for overlying the via shape to create an interconnection area between the via shape and the upper metal layer shape. The method includes determining a potential area loss of the interconnection area during integrated circuit fabrication processing. The method further includes enlarging the via shape to compensate for the potential area loss. | 06-09-2016 |
20160254267 | MEMORY METAL SCHEME | 09-01-2016 |