Class / Patent application number | Description | Number of patent applications / Date published |
438594000 | Tunnelling dielectric layer | 49 |
20080233729 | METHOD OF FORMING MICRO PATTERN IN SEMICONDUCTOR DEVICE - A method of forming a fine pattern in a semiconductor device includes forming an target layer, a hard mask layer and first sacrificial patterns on a semiconductor substrate; forming an insulating layer and a second sacrificial layer on the hard mask layer and the first sacrificial patterns; performing the first etch process so as to allow the second sacrificial layer remain on the insulating layer between the first sacrificial patterns for forming second sacrificial patterns; removing the insulating layer placed on the first sacrificial patterns and between the first and second sacrificial patterns; etch the hard mask layer through the second etch process utilizing the first and second sacrificial patterns as the etch mask to form a mask pattern; and etch the target layer through the third etch process utilizing the hard mask pattern as the etch mask. | 09-25-2008 |
20080242074 | Method of Forming Gate Pattern of Flash Memory Device - A method of forming a gate pattern of a flash memory device may include forming a tunnel dielectric layer, a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, a metal electrode layer, and a hard mask film over a semiconductor substrate. The metal electrode layer may be etched such that a positive slope of an upper sidewall may be formed larger than a positive slope of a lower sidewall of the metal electrode layer. The conductive layer for the control gate, the dielectric layer, and the conductive layer for the floating gate may then be etched. High molecular weight argon gas, for example, may be used to improve an anisotropic etch characteristic of plasma. Over etch of a metal electrode layer may be decreased to reduce a bowing profile. Resistance of word lines can be decreased and electrical properties can be improved. | 10-02-2008 |
20080242075 | METHOD FOR FORMING NON-VOLATILE MEMORY DEVICES - According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability. | 10-02-2008 |
20080254607 | INTEGRATION APPROACH TO FORM THE CORE FLOATING GATE FOR FLASH MEMORY USING AN AMORPHOUS CARBON HARD MASK AND ARF LITHOGRAPHY - Systems and methods are described that facilitate integrating ArF core patterning of floating gate structures in a flash memory device followed by KrF periphery gate patterning using a hard mask comprising a material such as amorphous carbon to facilitate core gate construction. The amorphous carbon hard mask can facilitate preparing such core gate structures while protecting periphery gate stacks such that the periphery stacks are ready for immediate KrF lithography upon completion of core gate formation without requiring additional resist deposition between core and periphery etches. | 10-16-2008 |
20080299755 | METHODS OF FABRICATING NON-VOLATILE MEMORY DEVICES INCLUDING A CHLORINE CURED TUNNEL OXIDE LAYER - Fabrication of a nonvolatile memory device includes sequentially forming a tunnel oxide layer, a first conductive layer, and a nitride layer on a semiconductor substrate. A stacked pattern is formed from the tunnel oxide layer, the first conductive layer, and the nitride layer and a trench is formed in the semiconductor substrate adjacent to the stacked pattern. An oxidation process is performed to form a sidewall oxide layer on a sidewall of the trench and the first conductive layer. Chlorine is introduced into at least a portion of the stacked pattern subjected to the oxidation process. Introducing Cl into the stacked pattern may at least partially cure defects that are caused therein during fabrication of the structure. | 12-04-2008 |
20080311734 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A non-volatile semiconductor storage device having a high-dielectric-constant insulator and a manufacturing method thereof suitable for miniaturization are disclosed. According to one aspect of the present invention, it is provided a semiconductor storage device comprising a semiconductor substrate, a plurality of first conductor layers formed on the semiconductor substrate through a first insulator, an isolation formed between the plurality of first conductor layers, a silicon oxide film formed on the first conductor layer, a high-dielectric-constant insulator formed on the silicon oxide film and the isolation and being diffused silicon and oxygen at least in a surface thereof contacting with the silicon oxide film, and a second conductor film formed above the high-dielectric-constant insulator. | 12-18-2008 |
20080318406 | SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In a split gate type nonvolatile memory device and a method of fabricating the same. A supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level. | 12-25-2008 |
20090011588 | Flash Memory and Methods of Fabricating Flash Memory - Flash memory and methods of fabricating flash memory are disclosed. A disclosed method comprises: forming a first floating gate; and extending the first floating gate by forming a second floating gate adjacent a first sidewall of the floating gate. The second floating gate extends upward above the first floating gate. The method also includes depositing a dielectric layer on the first floating gate and the second floating gate; and forming a control gate on the dielectric layer. | 01-08-2009 |
20090011589 | METHOD OF MANUFACTURING SPLIT GATE TYPE NONVOLATILE MEMORY DEVICE - A method of manufacturing a split gate type nonvolatile semiconductor memory device in which control gates are formed by a self aligning process. | 01-08-2009 |
20090023279 | METHOD OF FABRICATING FLASH MEMORY DEVICE - The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. The method of the present invention can improve interference between neighboring word lines and, thus improve the reliability of a device. Accordingly, a robust high-speed device can be implemented. | 01-22-2009 |
20090023280 | METHOD FOR FORMING HIGH-K CHARGE STORAGE DEVICE - Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking layer preferably comprised of a lower hafnium oxide storage layer and an upper oxide storage layer. We form a gate electrode over the top blocking layer. We pattern the layers to form a gate structure and form source/drain regions to complete the memory device. In a second example embodiment, we form a floating gate non-volatile memory device comprised of: a bottom tunnel layer comprised essentially of silicon oxide; a charge storage layer comprised of a tantalum oxide; a top blocking layer comprised essentially of silicon oxide; and a gate electrode. The embodiments also comprise anneals and nitridation steps. | 01-22-2009 |
20090047778 | PLASMA OXIDATION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A plasma oxidation processing method is performed, on a structural object including a silicon layer and a refractory metal-containing layer, to form a silicon oxide film. A first plasma oxidation process is performed by use of a process gas including at least hydrogen gas and oxygen gas and a process pressure of 1.33 to 66.67 Pa. A second plasma oxidation process is performed by use of a process gas including at least hydrogen gas and oxygen gas and a process pressure of 133.3 to 1,333 Pa, after the first plasma oxidation process. | 02-19-2009 |
20090053885 | MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE USING INSULATING FILM AS CHARGE STORAGE LAYER - A manufacturing method of a semiconductor memory device includes forming a first gate electrode having a charge storage layer, a block layer, and a control gate electrode on a first region of a semiconductor substrate, forming a second gate electrode on a second region of the semiconductor substrate, forming a protective insulating film on a side surface of the block layer, exposing the first region while covering the second region on the semiconductor substrate with a photoresist, using the photoresist, the first gate electrode, and the protective insulating film as masks to implant an impurity into the first region of the semiconductor substrate, and removing the photoresist by wet etching which uses a mixed solution containing H | 02-26-2009 |
20090061612 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench. | 03-05-2009 |
20090061613 | Method of forming aluminum oxide layer and method of manufacturing charge trap memory device using the same - Provided is a method of forming an aluminum oxide layer and a method of manufacturing a charge trap memory device using the same. The method of forming an aluminum oxide layer may include forming an amorphous aluminum oxide layer on an underlying layer, forming a crystalline auxiliary layer on the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer. Forming the crystalline auxiliary layer may include forming an amorphous auxiliary layer on the amorphous aluminum oxide layer; and crystallizing the amorphous auxiliary layer. | 03-05-2009 |
20090068829 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprising forming a conductive layer on a semiconductor substrate; forming a metal layer on the conductive layer; performing a first etching process for patterning the metal layer on a first area to form first metal layer patterns at relatively wide intervals until the conductive layer of the first area is exposed; performing a second etching process for forming an etching-obstructing layer on the first area and patterning the metal layer on a second area to form second metal layer patterns at relatively narrow intervals until the conductive layer of the second area is exposed; removing the etching-obstructing layer; and removing an exposed area of the conductive layer to form a conductive pattern. | 03-12-2009 |
20090098722 | METHOD OF FORMING A SEMICONDUCTOR MEMORY DEVICE - A method of forming a semiconductor memory device includes forming a tunnel insulating layer on a semiconductor substrate, and forming a silicon layer, including metal material, on the tunnel insulating layer. Accordingly, an increase in the strain energy of the conductive layer may be prohibited and, therefore, the growth of grains constituting the conductive layer may be prevented. Furthermore, a threshold voltage distribution characteristic and electrical properties of a semiconductor memory device may be improved. | 04-16-2009 |
20090117728 | METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE - A method for fabricating a nonvolatile memory device includes forming a tunneling insulation layer and a conductive layer for a floating gate over a substrate, partially etching the conductive layer, the tunneling insulation layer, and the substrate to form a trench, forming an isolation layer filling a portion of the trench, forming spacers on both sidewalls of the conductive layer not covered by the isolation layer, recessing a portion of the exposed isolation layer using the spacers as an etch barrier layer to form wing spacers, removing the spacers, performing a primary cleaning process on the resulting substrate using a mixed solution of H | 05-07-2009 |
20090130835 | METHOD OF MANUFACTURING INVERTED T-SHAPED FLOATING GATE MEMORY - A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T-shape, a U-shape, a trapezoid shape, or a double inverted T-shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T-shape, such that a top contour is a non-flat segment. | 05-21-2009 |
20090130836 | METHOD OF FABRICATING FLASH CELL - A method of fabricating a flash cell of a semiconductor device includes depositing a damage-prevention film on and/or over a hard mask pattern to prevent damage to an ONO film of a gate pattern when removing the hard mask using a vapor process chamber (VPC) process. | 05-21-2009 |
20090142914 | Method for Manufacturing Semiconductor Device - Disclosed are methods for manufacturing a semiconductor device, capable of inhibiting an undercut from occurring in a dielectric layer formed between a floating gate and a control gate. In one method, the dielectric layer can be protected using a covering of a nitride layer that can be used as a hard mask for gate patterning in a flash memory device. In another method, the gate stack can be inhibited from being damaged by changing the material of the hard mask used to etch the gate stack. For example, an LTO can be used as the hardmask. | 06-04-2009 |
20090215256 | Inverted T-Shaped Floating Gate Memory and Method for Fabricating the Same - A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T shape, a trapezoid shape, or a double inverted T shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T shape, such that a top contour is not a flat line segment. | 08-27-2009 |
20090233434 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - In semiconductor devices and methods of manufacturing semiconductor devices, a zirconium source having zirconium, carbon and nitrogen is provided onto a substrate to form an adsorption layer of the zirconium source on the substrate. A first purging process is performed to remove a non-adsorbed portion of the zirconium source. An oxidizing gas is provided onto the adsorption layer to form an oxidized adsorption layer of the zirconium source on the substrate. A second purging process is performed to remove a non-reacted portion of the oxidizing gas. A nitriding gas is provided on the oxidized adsorption layer to form a zirconium carbo-oxynitride layer on the substrate, and a third purging process is provided to remove a non-reacted portion of the nitriding gas. | 09-17-2009 |
20090246949 | Methods of manufacturing semiconductor devices - In a semiconductor device and a method of manufacturing a semiconductor device, a lower electrode is formed on a semiconductor substrate. A first zirconium oxide layer is formed on the lower electrode by performing a first deposition process using a first zirconium source and a first oxidizing gas. A zirconium carbo-oxynitride layer is formed on the first zirconium oxide layer by performing a second deposition process using a second zirconium source, a second oxidizing gas and a nitriding gas, and an upper electrode is formed on the zirconium carbo-oxynitride layer. A zirconium oxide-based composite layer having a high dielectric constant and a thin equivalent oxide thickness can be obtained. | 10-01-2009 |
20090263962 | NON-VOLATILE MEMORY CELL DEVICE AND METHODS - A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer. | 10-22-2009 |
20100081267 | METHOD FOR FORMING SELF-ALIGNED DIELECTRIC CAP ABOVE FLOATING GATE - A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates. | 04-01-2010 |
20100190330 | NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR DEVICE - A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed. | 07-29-2010 |
20100197130 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film. | 08-05-2010 |
20100227469 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device. According to the invention, a floating gate can be formed and a distance between cells can be secured sufficiently by using one conductive layer without using a SA-STI process that cannot be applied to the manufacture process of high-integrated semiconductor devices. It is therefore possible to minimize an interference phenomenon between neighboring cells. Furthermore, an isolation film is etched after a photoresist film covering only a high-voltage transistor region is formed, or a gate oxide film is formed after a semiconductor substrate is etched at a thickness, which is the same as that of the gate oxide film of the high-voltage transistor region, so that a step between the cell region and the high-voltage transistor region is the same. Accordingly, the coupling ratio can be increased even by the gate oxide film of the high-voltage transistor region, which is thicker than the tunnel oxide film of the cell region. In addition, damage to a tunnel oxide film, a semiconductor substrate or a floating gate while an isolation film is etched at a predetermined depth in order to control the EFH can be prevented by controlling the EFH in such a manner than conductive layer spacers are formed on sidewalls of the floating gate and the isolation film is further etched. | 09-09-2010 |
20110159681 | Nonvolatile Memory Device and Method of Manufacturing the Same - A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming tunnel insulating patterns to expose portions of the semiconductor substrate by removing portions of the tunnel insulating layer formed over isolation regions of the semiconductor substrate, forming a first conductive layer of single crystalline material over the tunnel insulating patterns and exposed portions of the semiconductor substrate, and forming a second conductive layer over the first conductive layer. | 06-30-2011 |
20110217835 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH SIDEWALL CONDUCTIVE PATTERNS - A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern. | 09-08-2011 |
20110250747 | MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY DEVICES - Provided are a method for manufacturing a memory device and a memory device manufactured by the method. The memory device may be a flash memory device. The method for manufacturing the memory device may include sequentially stacking a tunnel dielectric, a floating gate conductive layer, an inter-gate dielectric, and a control gate conductive layer on a semiconductor substrate; anisotropically etching the floating gate conductive layer, the inter-gate dielectric, and the control gate conductive layer to form gate structures. The gate structures may be separated by regions where top surfaces of the tunnel dielectric are exposed, the exposed top surfaces being damaged during formation of the gate structures. The method includes reacting the exposed top surfaces of the tunnel dielectric damaged during the formation of the gate structures with a reaction gas comprising ammonium fluoride to form a reaction by-product on the exposed top surfaces of the tunnel dielectric, and removing the reaction by-product. | 10-13-2011 |
20110287625 | METHODS OF FORMING A PATTERN, METHODS OF FORMING A GATE STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - A method of forming a pattern in a semiconductor device includes forming an etching object layer on a substrate, the etching object layer is an oxide that is substantially free of impurities. A mask is formed on the etching object layer, the mask is an oxide that includes impurities. The etching object layer is patterned using the mask as an etching mask and then the mask is removed. The mask is removed using an etchant having an etching selectivity to an oxide that is substantially free of impurities and an oxide that includes impurities during removing of the mask to limit damage to the patterned etching object layer during removal of the mask. | 11-24-2011 |
20110312172 | Methods of Forming Patterns and Methods of Manufacturing Semiconductor Devices Using the Same - In a method forming patterns, a layer on a substrate is patterned by a first etching process using an etch mask to form a plurality of first preliminary patterns and a plurality of second preliminary patterns. The second preliminary patterns are spaced apart from each other at a second distance larger than a first distance at which the first preliminary patterns are spaced apart. First and second coating layers are formed on sidewalls of the first and second preliminary patterns, respectively, and the first and second coating layers and portions of the first and second preliminary patterns are removed by a second etching process using the etch mask to form a plurality of first patterns and a plurality of second patterns. The first patterns have widths that are smaller than widths of the first preliminary patterns. The first patterns may have generally vertical sidewalls relative to the substrate. | 12-22-2011 |
20110312173 | Method of Fabricating a Semiconductor Device - The invention relates to semiconductor devices and a method of fabricating the same. In accordance with a method of fabricating a semiconductor device according to an aspect of the invention, a tunnel insulating layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer are sequentially stacked over a semiconductor substrate. The gate electrode layer, the second conductive layer, the dielectric layer, and the first conductive layer are patterned so that the first conductive layer partially remains to prevent the tunnel insulating layer from being exposed. Sidewalls of the gate electrode layer are etched. A first passivation layer is formed on the entire surface including the sidewalls of the gate electrode layer. At this time, a thickness of the first passivation layer formed on the sidewalls of the gate electrode layer is thicker than that of the first passivation layer formed in other areas. A cleaning process is performed to thereby remove byproducts occurring in the etch process. A gate pattern is formed by etching the first passivation layer, the first conductive layer, and the tunnel insulating layer. | 12-22-2011 |
20120070976 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein. | 03-22-2012 |
20120135596 | METHOD OF REMOVING NANOCRYSTALS - A method for forming a semiconductor structure includes providing a semiconductor layer, forming nanocrystals over the semiconductor layer, and using a solution comprising pure water, hydrogen peroxide, and ammonium hydroxide to remove at least a portion of the nanocrystals. A ratio by volume of pure water to ammonium hydroxide of the solution may be equivalent to or less than a ratio by volume of 10:1 of pure water to ammonium hydroxide when ammonium hydroxide has a concentration of 29% ammonia by weight. The step of using the solution to remove the at least a portion of the nanocrystals may be performed at a temperature of 50 degrees Celsius or more. | 05-31-2012 |
20120225547 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region. | 09-06-2012 |
20130095646 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 04-18-2013 |
20130115766 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method, a tunnel insulating film and a first conductive film are formed on a semiconductor layer. A trench is formed. A first sacrifice film is buried in the trench. A second sacrifice film having density higher than that of the first sacrifice film is formed on the first sacrifice film in the trench. An insulating film is formed on the first conductive film and the second sacrifice film. A second conductive film is formed on the insulating film. The second sacrifice film is exposed. The first sacrifice film and the second sacrifice film are removed. | 05-09-2013 |
20130164929 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction. | 06-27-2013 |
20130171815 | MANUFACTURING METHOD OF FLASH MEMORY STRUCTURE WITH STRESS AREA - In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory. | 07-04-2013 |
20130337643 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes etching a substrate to form a field trench defining an active region and a lower gate pattern on the active region, the lower gate pattern including a tunneling insulating pattern and a lower gate electrode pattern, filling a field insulating material in the field trench to form a field region, forming an upper gate pattern on the lower gate pattern, sequentially forming a stopping layer and a buffer layer on the field region and the upper gate pattern, forming a first resistive pattern on the buffer layer of the field region, and forming a second resistive pattern on the buffer layer on the upper gate pattern, forming an interlayer insulating layer covering the first and second resistive patterns, and performing a planarization process to remove a top surface of the interlayer insulating layer and to remove the second resistive pattern. | 12-19-2013 |
20140057425 | GATE TUNABLE TUNNEL DIODE - A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode includes a tunnel dielectric formed on the graphene electrode and a tunnel electrode formed on the tunnel dielectric. | 02-27-2014 |
20140057426 | NON-VOLATILE MEMORY STRUCTURE EMPLOYING HIGH-K GATE DIELECTRIC AND METAL GATE - A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region. | 02-27-2014 |
20150031198 | PATTERN FORMING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed. | 01-29-2015 |
20150099354 | SEMICONDUCTOR DEVICE - A semiconductor device includes vertical channel layers, control gates and interlayer insulating layers stacked alternately with each other on the substrate and surrounding the vertical channel layers, floating gates interposed between the vertical channel layers and the control gates and separated from each other by the interlayer insulating layers, and charge blocking layers interposed between the floating gates and the control gates. | 04-09-2015 |
20150348790 | METHODS AND APPARATUSES INCLUDING MEMORY CELLS WITH AIR GAPS AND OTHER LOW DIELECTRIC CONSTANT MATERIALS - Various embodiments include methods of forming memory cells. In one embodiment, a first dielectric material and a second dielectric material are formed on a substrate. A conductive material is formed between the first dielectric material and the second dielectric material. An opening is formed through the first dielectric material, the second dielectric material, and the conductive material. The conductive material is recessed laterally from the opening to form a recessed control gate and to expose portions of the first dielectric material and the second dielectric material. Portions of a third dielectric material are formed over the exposed portions of the first dielectric material and the second dielectric material and a charge storage element is formed between the portions of the third dielectric material and adjacent to the recessed control gate. Portions of the third dielectric material are substantially removed. Additional methods, as well as apparatuses, are disclosed. | 12-03-2015 |
20160020099 | PATTERN FORMING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, first, an embedment material is embedded between linear core material patterns in such a manner that a height thereof becomes lower than a height of each of the core material patterns. Then, a shrink agent is supplied and solidified on the embedment material. Subsequently, the solidified shrink agent and the embedment material are removed and a spacer film is formed on an object of processing. Then, the spacer film is etched-back and a spacer pattern is formed by removal of the core material patterns. The solidified shrink agent which is formed in such a manner that a width of the spacer pattern becomes narrow in a region corresponding to a position where the shrink agent, in a sectional surface vertical to an extended direction of the spacer pattern is supplied is removed. | 01-21-2016 |