Class / Patent application number | Description | Number of patent applications / Date published |
438264000 | Tunneling insulator | 61 |
20080220578 | METHOD OF FABRICATING A NON-VOLATILE MEMORY DEVICE - In a method of fabricating a non-volatile memory device, a semiconductor substrate includes an isolation layer formed in an isolation region, a tunnel insulating layer and a first conductive layer for a floating gate formed in an active region, and a dielectric layer, a second conductive layer for a control gate, and a gate hard mask formed over the first conductive layer including the isolation layer. The second conductive layer is patterned using the gate hard mask as an etch mask. The dielectric layer is patterned so that the first conductive layer, which is exposed as the dielectric layer is etched, is also etched. The first conductive layer is patterned along a pattern of the gate hard mask. Accordingly, at the time of gate patterning, micro bridges between the floating gates can be prevented and a 2-bit failure between neighboring cells is less likely. | 09-11-2008 |
20080242026 | Method of manufacturing a semiconductor memory device having a floating gate - A method of manufacturing a semiconductor memory device which includes forming a conductive layer for a floating gate above a semiconductor layer intervening a gate insulating film therebetween, then, forming, over the conductive layer, a first spacer comprising a first silicon oxide material and a second spacer adjacent with the first spacer and comprising a second silicon oxide material, the second silicon oxide material having an etching rate lower than that of the first silicon oxide material, selectively removing the conductive layer by using the first and the second spacers as a mask, and removing the first spacer to expose a portion of the conductive layer. Since the etching rate for the second spacer is lower compared with the etching rate for the first spacer, the etching amount of the second spacer caused upon removal of the first spacer can be suppressed and, as a result, the productivity and the reliability of the semiconductor memory device can be improved. | 10-02-2008 |
20080242027 | Non-Volatile Memory Integrated Circuit - A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell. | 10-02-2008 |
20080293200 | Method of fabricating nonvolatile semiconductor memory device - In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer. | 11-27-2008 |
20080305594 | METHOD FOR FABRICATING NON-VOLATILE MEMORY - A method for fabricating a non-volatile memory is provided. Parallel-arranged isolation structures are disposed in a substrate and protrude from the surface of the substrate to define active regions. Mask layers intersecting the isolation structures are deposited on the substrate. The surface of the mask layers is higher than that of the isolation structures. Doped regions are formed in the substrate. Insulating layers are deposited on the substrate between the mask layers. The insulating layers and the mask layers have different etch selectivities. The mask layers are removed to expose the substrate. A tunneling dielectric layer is formed on the substrate. A floating gate is deposited on the substrate surrounded by the isolation structures and the insulating layers. The surface of the floating gate is lower than that of the isolation structures. An inter-gate dielectric layer is deposited on the substrate. A control gate is disposed between the insulating layers. | 12-11-2008 |
20080318381 | METHODS OF FORMING HIGH DENSITY SEMICONDUCTOR DEVICES USING RECURSIVE SPACER TECHNIQUE - High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements. | 12-25-2008 |
20080318382 | METHODS FOR FABRICATING TUNNELING OXIDE LAYER AND FLASH MEMORY DEVICE - A method for manufacturing a tunneling oxide layer including the following steps: forming a tunneling oxide layer on a semiconductor substrate by in-situ steam generation oxidation; performing a annealing on the tunneling oxide layer. There is also provided a method for manufacturing a flash memory device. According to the invention, the dangling bonds between silicon oxide in a tunneling oxide layer and silicon adjacent to a semiconductor substrate interface are terminated by performing a annealing on a tunneling oxide layer, thereby improving the erase rate of the tunneling oxide layer. | 12-25-2008 |
20090004796 | METHOD OF MANUFACTURING NON-VOLATILE MEMORY - A method of manufacturing a non-volatile memory includes providing a substrate and forming a patterned mask layer, a tunnel dielectric layer, and a first conductive layer on the substrate. The first conductive layer on the mask layer is removed to form second conductive layers disposed on the sidewall of the mask layer and the substrate. The mask layer is then removed and a source region is formed. Subsequently, an inter-gate dielectric layer and a third conductive layer are formed on the substrate. The third conductive layer is patterned to cover the source region and a portion of the second conductive layer on both sides of the source region. A portion of the inter-gate dielectric layer and the second conductive layers are then removed. After that, a dielectric layer, a fourth conductive layer, and a drain region are formed, respectively. | 01-01-2009 |
20090035905 | INSITU FORMATION OF INVERSE FLOATING GATE POLY STRUCTURES - Briefly, in accordance with one or more embodiments, a method of making an inverse-t shaped floating gate in a non-volatile memory cell or the like is disclosed. | 02-05-2009 |
20090035906 | Method of manufacturing a non-volatile semiconductor device - Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern. | 02-05-2009 |
20090047765 | METHOD OF MANUFACTURING NON-VOLATILE MEMORY - A method of manufacturing a non-volatile memory is provided. In the method, a first dielectric layer, a first conductive layer, and a first cap layer are formed sequentially on a substrate. The first cap layer and the first conductive layer are patterned to form first gate structures. A second dielectric layer is formed on the sidewall of the first gate structures, and a portion of the first dielectric layer is removed to expose the substrate between the first gate structures. An epitaxy layer is formed on the substrate between two first gate structures. A third dielectric layer is formed on the epitaxy layer. A second conductive layer is formed on the third dielectric layer. The first cap layer and a portion of the first conductive layer are removed to form second gate structures. Finally, a doped region is formed in the substrate at two sides of the second gate structures. | 02-19-2009 |
20090053867 | PLASMA TREATED METAL SILICIDE LAYER FORMATION - Devices and methods for plasma treated metal silicide layer formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a metal layer on a silicon substrate, exposing the metal layer to a plasma, and thermally treating the silicon substrate and the metal layer to form a metal silicide layer. | 02-26-2009 |
20090081838 | SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A semiconductor memory includes memory cell transistors including a tunnel insulating film, a floating gate electrode, a first insulating film, a control gate electrode, and a first metal salicide film; low-voltage transistors having a first p-type source region and a first p-type drain region, a first gate insulating film, and a first gate electrode of an n conductivity type having the same dose of a first p-type impurity as with the first p-type source region; and high-voltage transistors having a second p-type source region and a second p-type drain region, a second gate insulating film thicker than the first gate insulating film, and a second gate electrode of an n conductivity type having the same dose of a second p-type impurity as with the second p-type source region. | 03-26-2009 |
20090098700 | METHOD OF FABRICATING A NON-VOLATILE MEMORY DEVICE - A method of fabricating a non-volatile memory device prevents the threshold voltage of a program-inhibited cell from rising by preventing hot carriers, generated in a semiconductor substrate near a select line, from being injected into a floating gate of the program-inhibited cell. The program-inhibited cell shares a word line adjacent to the select line such that a trench is formed in the semiconductor substrate between the select line and the adjacent word line to increase a distance between the select line and the word line. | 04-16-2009 |
20090233406 | METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - A method of fabricating a semiconductor memory device to protect a tunneling insulating layer from etching-damage includes the steps of forming sequentially a tunnel insulating layer, a first conductive layer, a dielectric layer and a second conductive layer on a semiconductor substrate; etching the second conductive layer, the dielectric layer and the first conductive layer to form gate patterns, the first conductive layer remaining on the tunnel insulating layer between the gate patterns to prevent the tunnel insulating layer from being exposed; performing a cleaning process to remove impurities generated in the etching step; performing an ion implanting process to mono-crystallize the first conductive layer remaining on the tunnel insulating layer; and performing an oxidation process to form an oxide layer on top and side walls of the gate patterns and to convert the mono-crystallized first conductive layer into an insulating layer. | 09-17-2009 |
20090269893 | Semiconductor integrated circuit device and method of producing the same - A semiconductor integrated circuit device includes a substrate, a nonvolatile memory device formed in a memory cell region of the substrate, and a semiconductor device formed in a device region of the substrate. The nonvolatile memory device has a multilayer gate electrode structure including a tunnel insulating film and a floating gate electrode formed thereon. The floating gate electrode has sidewall surfaces covered with a protection insulating film. The semiconductor device has a gate insulating film and a gate electrode formed thereon. A bird's beak structure is formed of a thermal oxide film at an interface of the tunnel insulating film and the floating gate electrode, the bird's beak structure penetrating into the floating gate electrode along the interface from the sidewall faces of the floating gate electrode, and the gate insulating film is interposed between the substrate and the gate electrode to have a substantially uniform thickness. | 10-29-2009 |
20090269894 | Semiconductor device and method of fabricating the same cross-reference to related applications - A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, a source/drain diffusion layer formed in the semiconductor substrate at both sides of the gate electrode, and a channel region formed in the semiconductor substrate between a source and a drain of the source/drain diffusion layer and arranged below the gate insulating film, wherein an upper surface of the source/drain diffusion layer is positioned below a bottom surface of the gate electrode, and an upper surface of the channel region is positioned below the upper surface of the source/drain diffusion layer. | 10-29-2009 |
20090317952 | Memory Device and Method for Manufacturing the Same - A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage. The split gate EEPROM cell includes a semiconductor substrate having a trench; a tunneling oxide layer at sidewalls of the trench; a floating gate, a dielectric layer and a control gate in sequence on the tunneling oxide layer; a buffer dielectric layer at sidewalls of the floating gate and the control gate; a source junction in the semiconductor substrate at the bottom surface of the trench; a source electrode in the trench between opposing buffer dielectric layers, electrically connected to the source junction; and a drain junction on the surface of the semiconductor substrate outside the trench. | 12-24-2009 |
20090317953 | Memory Device and Method for Manufacturing the Same - A split gate (flash) EEPROM cell and a method for manufacturing the same is disclosed, in which a control gate and a floating gate are formed in a vertical structure, to minimize a size of the cell, to obtain a high coupling ratio, and to lower a programming voltage. The split gate EEPROM cell includes a semiconductor substrate having a trench; a tunneling oxide layer at sidewalls of the trench; a floating gate, a dielectric layer and a control gate in sequence on the tunneling oxide layer; a buffer dielectric layer at sidewalls of the floating gate and the control gate; a source junction in the semiconductor substrate at the bottom surface of the trench; a source electrode in the trench between opposing buffer dielectric layers, electrically connected to the source junction; and a drain junction on the surface of the semiconductor substrate outside the trench. | 12-24-2009 |
20100041193 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a floating gate electrode which is selectively formed on a main surface of a first conductivity type with a first gate insulating film interposed therebetween, a control gate electrode formed on the floating gate electrode with a second gate insulating film interposed therebetween, and source/drain regions of a second conductivity type which are formed in the main surface of the substrate in correspondence with the respective gate electrodes. The first gate electrode has a three-layer structure in which a silicon nitride film is held between silicon oxide films, and the silicon nitride film includes triple coordinate nitrogen bonds. | 02-18-2010 |
20100105180 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING IMPROVED PUNCH-THROUGH RESISTANCE AND PRODUCTION METHOD THEREOF, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING A LOW-VOLTAGE TRANSISTOR AND HIGH-VOLTAGE TRANSISTOR - An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well. | 04-29-2010 |
20100221881 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an aspect of the invention, there is provided a semiconductor device including a plurality of memory cells, comprising a plurality of floating gate electrodes which are formed on a tunnel insulating film formed on a semiconductor substrate and have an upper portion which is narrower in a channel width direction than a lower portion, an interelectrode insulating film formed on the floating gate electrodes, and a control gate electrode which is formed on the interelectrode insulating film formed on the floating gate electrodes and partially buried between the floating gate electrodes opposing each other. | 09-02-2010 |
20110003446 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes an insulating layer, a channel structure, an insulating structure and a gate. The channel structure includes a channel bridge for connecting two platforms. The bottom of the channel bridge is separated from the insulating layer by a distance, and the channel bridge has a plurality of separated doping regions. The insulating structure wraps around the channel bridge, and the gate wraps around the insulating structure. | 01-06-2011 |
20110039380 | Method for Forming a Floating Gate Non-Volatile Memory Cell - Method for manufacturing a non-volatile memory comprising at least one array of memory cells on a substrate of a semiconductor material, the memory cells being self-aligned to and separated from each other by STI structures, the memory cells comprising a floating gate having an inverted-T shape in a cross section along the array of memory cells, wherein the inverted T shape is formed by oxidizing an upper part of the sidewalls of the floating gates thereby forming sacrificial oxide, and subsequently removing the sacrificial oxide simultaneously with further etching back the STI structures. | 02-17-2011 |
20110076816 | SPLIT GATE NON-VOLATILE FLASH MEMORY CELL HAVING A FLOATING GATE, CONTROL GATE, SELECT GATE AND AN ERASE GATE WITH AN OVERHANG OVER THE FLOATING GATE, ARRAY AND METHOD OF MANUFACTURING - An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency. | 03-31-2011 |
20110086483 | NON-VOLATILE MEMORY DEVICE FOR 2-BIT OPERATION AND METHOD OF FABRICATING THE SAME - A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern. | 04-14-2011 |
20110097862 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATION OF THE SAME - A semiconductor memory device includes a first memory cell transistor. The first memory cell transistor includes a tunnel insulation film provided on a semiconductor substrate, a floating electrode provided on the tunnel insulation film, an inter-gate insulation film provided on the floating electrode, and a control electrode provided on the inter-gate insulation film. The floating electrode includes a first floating electrode provided on the tunnel insulation film and a second floating electrode provided on one end portion of the first floating electrode, the floating electrode having an L-shaped cross section in a wiring direction of the control electrode. | 04-28-2011 |
20110159649 | NON-VOLATILE STORAGE WITH SUBSTRATE CUT-OUT AND PROCESS OF FABRICATING - Shallow trench isolation regions are positioned between NAND strings (or other types of non-volatile storage). These isolation regions include sections that form concave cut-out shapes in the substrate for the NAND string (or other types of non-volatile storage). The floating gates (or other charge storage devices) of the NAND strings hang over the sections of the isolation region that form the concave cut-out shape in the substrate. To manufacture such a structure, a two step etching process is used to form the isolation regions. In the first step, isotropic etching is used to remove substrate material in multiple directions, including removing substrate material underneath the floating gates. In the second step, anisotropic etching is used to create the lower part of the isolation region. | 06-30-2011 |
20110165746 | Novel Profile of Flash Memory Cells - A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate. | 07-07-2011 |
20110177661 | METHODS OF MANUFACTURING NOR-TYPE NONVOLATILE MEMORY DEVICES INCLUDING IMPURITY EXPANSION REGIONS - Methods of manufacturing NOR-type flash memory device include forming a tunnel oxide layer on a substrate, forming a first conductive layer on the tunnel oxide layer, forming first mask patterns parallel to one another on the first conductive layer in a y direction of the substrate, and selectively removing the first conductive layer and the tunnel oxide layer using the first mask patterns as an etch mask. Thus, first conductive patterns and tunnel oxide patterns are formed, and first trenches are formed to expose the surface of the substrate between the first conductive patterns and the tunnel oxide patterns. A photoresist pattern is formed to open at least one of the first trenches, and impurity ions are implanted using the photoresist pattern as a first ion implantation mask to form an impurity region extending in a y direction of the substrate. The photoresist pattern is removed. The substrate is annealed to diffuse the impurity region, thereby forming an impurity expansion region further expanding in an x direction of the substrate. The substrate is selectively removed using the first mask patterns as an etch mask to form second trenches corresponding to the first trenches. Isolation layers are formed to define active regions in the second trenches. | 07-21-2011 |
20110250727 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing flash memory device is provided and includes the following steps. First, a substrate is provided. Then, a stacked gate structure is formed on the substrate. Subsequently, a first oxide layer is formed on the stacked gate structure. Following that, a nitride spacer is formed on the first oxide layer, wherein a nitrogen atom-introducing treatment is performed after the forming of the first oxide layer and before the forming of the nitride spacer. Accordingly, the nitrogen atom-introducing treatment of the presentation invention can improve the data retention reliability of the flash memory device. | 10-13-2011 |
20120058614 | PRE-METAL DEPOSITION CLEAN PROCESS - A process of forming an integrated circuit including an MOS transistor, in which a pre-metal deposition cleanup prior to depositing metal for silicide formation includes an HF etch, a first SC | 03-08-2012 |
20120064681 | Semiconductor Memory Device And Method Of Forming The Same - Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening. | 03-15-2012 |
20120122282 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing semiconductor devices includes forming a plurality of lines arranged in a direction over a semiconductor substrate, forming mask patterns over the semiconductor substrate wherein the mask patterns intersect the lines, and forming junctions in the semiconductor substrate between the lines by performing an ion implantation process. | 05-17-2012 |
20120142153 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method of fabricating a non-volatile memory device is provided. The method includes sequentially forming a tunnel insulation layer and a first polysilicon layer on a substrate, patterning the first polysilicon layer and the tunnel insulation layer, forming a dielectric layer to cover the patterned first polysilicon layer and the patterned tunnel insulation layer, forming a gate insulation layer on the substrate where the substrate is exposed, forming a second polysilicon layer to cover the dielectric layer, and forming a first floating gate and a second floating gate a fixed distance apart from each other, the forming of the first and second floating gates including etching middle portions of the second polysilicon layer, the dielectric layer, the patterned first polysilicon layer, and the patterned tunnel insulation layer, and separating the etched layers into two parts. | 06-07-2012 |
20120184076 | FLASH MEMORY STRUCTURE WITH ENHANCED CAPACITIVE COUPLING COEFFICIENT RATIO (CCCR) AND METHOD FOR FABRICATION THEREOF - A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio. | 07-19-2012 |
20120231593 | METHOD FOR FABRICATING 3D-NONVOLATILE MEMORY DEVICE - A method for fabricating a 3D-nonvolatile memory device includes forming a sub-channel over a substrate, forming a stacked layer over the substrate, the stacked layer including a plurality of interlayer dielectric layers that are alternatively stacked with conductive layers, selectively etching the stacked layer to form a first open region exposing the sub-channel, forming a main-channel conductive layer to gap-fill the first open region, selectively etching the stacked layer and the main-channel conductive layer to form a second open region defining a plurality of main channels, and forming an isolation layer to gap-fill the second open region. | 09-13-2012 |
20120270373 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device includes: a memory cell transistor which has a floating gate, a control gate, and a source and a drain formed in a semiconductor substrate on both sides of the floating gate via a channel area; and a selecting transistor which has a select gate and a source and a drain formed in the semiconductor substrate on both sides of the select gate, wherein the source of the selecting transistor is connected to the drain of the memory cell transistor, the source of the memory cell transistor has an N-type first impurity diffusion layer, an N-type second impurity diffusion layer deeper than the first impurity diffusion layer, and an N-type third impurity diffusion layer which is shallower than the second impurity diffusion layer, and an impurity density of the second impurity diffusion layer is lower than that of the third impurity diffusion layer. | 10-25-2012 |
20120289011 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor integrated circuit device includes defining a first area by forming a separating area on a substrate, and forming a tunnel film in the first area, a floating gate on the tunnel film, a first electrode in the separating area, a first film on the floating gate, a second film on the first electrode, a control gate on the first film, a second electrode on the second film, and source and drain areas in the first area. The method includes forming a first interlayer film to cover the control gate and the second electrode, forming, in the first interlayer film, a conductive via plug reaching the second electrode, and forming, on the first interlayer film, a second wiring electrically coupled to the second electrode via the conductive via plug, and a first wiring that is capacitively-coupled to the second wiring and to the second electrode. | 11-15-2012 |
20130005098 | SEMICONDUCTOR DEVICE HAVING A CONTACT PLUG CONNECTING TO A SILICIDE FILM FORMED ON A DIFFUSION REGION OF A FLASH MEMORY CELL - A method for manufacturing a semiconductor device includes the steps of forming a flash memory cell provided with a floating gate, an intermediate insulating film, and a control gate, forming first and second impurity diffusion regions, thermally oxidizing surfaces of a silicon substrate and the floating gate, etching a tunnel insulating film in a partial region through a window of a resist pattern; forming a metal silicide layer on the first impurity diffusion region in the partial region, forming an interlayer insulating film covering the flash memory cell, and forming, in a first hole of the interlayer insulating film, a conductive plug connected to the metal silicide layer. | 01-03-2013 |
20130095622 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Methods of manufacturing a semiconductor device are provided. Patterns having a recess region defined therebetween are formed on a substrate, and then a silicon precursor having an organic ligand is provided on the substrate to absorb silicon on sidewalls and a bottom surface of the recess region to form a silicon monolayer on the patterns having the recess region defined therebetween. A silicon layer without void and cutting is formed on the silicon monolayer. | 04-18-2013 |
20130203228 | METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE - A method of fabricating a non-volatile memory is provided. A tunneling dielectric layer and a first patterned conductive layer are sequentially formed on a substrate. A patterned inter-gate dielectric layer and a second patterned conductive layer are stacked on a first surface of the first patterned conductive layer, and a second surface of the first patterned conductive layer is exposed. The second surface is adjacent to the first surface. The substrate is covered by a passivation layer, and a first sidewall of the first patterned conductive layer is exposed. A recess is formed on the first sidewall of the first patterned conductive layer, such that the first sidewall has a sharp corner. A portion of the passivation layer on the second surface is removed, such that the sharp corner of the first patterned conductive layer is exposed. | 08-08-2013 |
20130237024 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 09-12-2013 |
20130252389 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the silicon substrate side, a floating gate arranged so as to surround the outer periphery of the channel region with a tunnel insulating film interposed between the floating gate and the channel region, a control gate arranged so as to surround the outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate, and a control gate line electrically connected to the control gate and extending in a predetermined direction. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the lower and inner side surfaces of the control gate and between the floating gate and the lower surface of the control gate line. | 09-26-2013 |
20130260521 | MEMORY ARRAY WITH AN AIR GAP BETWEEN MEMORY CELLS AND THE FORMATION THEREOF - A method of forming a memory array includes forming a dielectric over a semiconductor, forming a charge-storage structure over the dielectric, forming an isolation region through the dielectric and the charge-storage structure and extending into the semiconductor, recessing the isolation region to a level below a level of an upper surface of the dielectric and at or above a level of an upper surface of the semiconductor, forming an access line over the charge-storage structure and the recessed isolation region, and forming an air gap over the recessed isolation region so that the air gap passes through the charge-storage structure, so that the air gap extends to and terminates at a bottom surface of the access line, and so that the entire air gap is between the bottom surface of the access line and the upper surface of the semiconductor. | 10-03-2013 |
20130323896 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes gate structures including first insulation layers that are alternately stacked with control gate layers over a substrate, wherein the gate structures extend in a first direction, channel lines that each extend over the gate structures in a second direction different from the first direction, a memory layer formed between the gate structures and the channel lines and arranged to trap charges by electrically insulating the gate structures from the channel lines, bit line contacts forming rows that each extend in the first direction and contacting top surfaces of the channel lines, source lines that each extend in the first direction and contact the top surfaces of the channel lines, wherein the source lines alternate with the rows of bit line contacts, and bit lines that are each formed over the bit line contacts and extend in the second direction. | 12-05-2013 |
20130330894 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness. | 12-12-2013 |
20140030860 | MANUFACTURING METHOD OF TUNNEL OXIDE OF NOR FLASH MEMORY - A manufacturing method of tunnel oxide of NOR flash memory controls the temperature and thickness of tunnel oxide in a gate structure to prevent a channel region to change its doping concentration and range due to a high-temperature manufacturing process, so as to overcome the leakage current and improve the reliability of storing data. | 01-30-2014 |
20140045307 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 02-13-2014 |
20140045308 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor storage device according to the present invention includes: a semiconductor substrate; an embedded insulator embedded in a trench formed in the semiconductor substrate and having an upper portion protruding above a top surface of the semiconductor substrate; a first insulating film formed on the top surface of the semiconductor substrate; a floating gate formed on the first insulating film at a side of the embedded insulator, having a side portion arching out above the embedded insulator, and having a side surface made of a flat surface and a curved surface continuing below the flat surface; a second insulating film contacting an upper surface, the flat surface and the curved surface of the floating gate; and a control gate opposing the upper surface, the flat surface and the curved surface of the floating gate across the second insulating film. | 02-13-2014 |
20140162417 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device according to an embodiment, includes forming a silicon (Si) film containing carbon (C) in an upper portion thereof above a semiconductor substrate, performing element isolation of the Si film and the semiconductor substrate to make a width dimension of the Si film narrow in a first region and a width dimension of the Si film wide in a second region, after the element isolation, exposing a side face of the Si film in at least the first region, and diffusing boron (B) into the Si film from the side face of the Si film in the first region. | 06-12-2014 |
20140322875 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer. | 10-30-2014 |
20140322876 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer. | 10-30-2014 |
20150024562 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor. | 01-22-2015 |
20150072488 | THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers. | 03-12-2015 |
20150099337 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate; a channel layer projecting from a surface of the substrate, in a direction perpendicular to the surface; a tunnel dielectric layer surrounding the channel layer; a plurality of interlayer dielectric layers and a plurality of control gate electrodes alternately formed along the channel layer; floating gate electrodes interposed between the tunnel dielectric layer and the plurality of control gate electrodes, the floating gate electrodes comprising a metal-semiconductor compound; and a charge blocking layer interposed between each of the plurality of control gate electrodes and each of the plurality of floating gate electrodes. | 04-09-2015 |
20150380423 | METHODS OF MAKING THREE DIMENSIONAL NAND DEVICES - A method of making a monolithic three dimensional NAND string includes providing a first stack of alternating first material layers and second material layers over a major surface of a substrate. The first material layers include first silicon oxide layers, the second material layers include second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide when exposed to the same etching medium. The first stack includes a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening. The method also includes selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers. | 12-31-2015 |
20160035742 | SPACER PASSIVATION FOR HIGH-ASPECT RATIO OPENING FILM REMOVAL AND CLEANING - A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening in the stack such that a damaged region is located on a bottom surface of the at least one opening, forming a masking layer on a sidewall of the at least one opening while the bottom surface of the at least one opening is not covered by the masking layer, and further etching the bottom surface of the at least one opening remove the damaged region. | 02-04-2016 |
20160163875 | Silicide Process Using OD Spacers - A device includes a semiconductor substrate including an active region. The active region includes a first sidewall. An isolation region extends from a top surface of the semiconductor substrate into the semiconductor substrate. The isolation region has a second sidewall, wherein a lower portion of the first sidewall joins a lower portion of the second sidewall to form an interface. A dielectric spacer is disposed on an upper portion of the first sidewall. A silicide region is over and contacting the active region. A sidewall of the silicide region contacts the dielectric spacer, and the dielectric spacer has a top surface substantially lower than a top surface of the silicide region. | 06-09-2016 |
20160172367 | MANUFACTURING METHOD OF NON-VOLATILE MEMORY | 06-16-2016 |
20160181271 | METHODS OF FABRICATING MEMORY DEVICE WITH SPACED-APART SEMICONDUCTOR CHARGE STORAGE REGIONS | 06-23-2016 |