Entries |
Document | Title | Date |
20080206930 | SYSTEMS AND METHODS FOR COMPRESSING AN ENCAPSULANT ADJACENT A SEMICONDUCTOR WORKPIECE - Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece are disclosed. A method in accordance with one aspect includes placing a semiconductor workpiece and an encapsulant in a mold cavity and driving some of the encapsulant from the mold cavity to an overflow chamber. The method can further include applying pressure to the encapsulant in the mold cavity via pressure applied to the encapsulant in the overflow chamber. | 08-28-2008 |
20080220567 | Semiconductor Component and Production Method - A semiconductor component is disclosed. In one embodiment, the semiconductor component includes a semiconductor chip, which is arranged on a substrate, and a housing, which at least partially surrounds the semiconductor chip. The substrate is at least partly provided with a layer of polymer foam. | 09-11-2008 |
20080220568 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device in the form of a resin sealed semiconductor package is disclosed, wherein a gate terminal connected to a gate pad electrode formed on a surface of a semiconductor chip and a source terminal connected to a source pad electrode formed on the chip surface exposed to a back surface of a sealing resin portion, a first portion of a drain terminal connected to a back-surface drain electrode of the semiconductor chip is exposed to an upper surface of the sealing resin portion, and a second portion of the drain terminal formed integrally with the first portion of the drain terminal is exposed to the back surface of the sealing resin portion. When forming the sealing resin portion in such a semiconductor device, first the sealing resin portion is formed so as to also cover an upper surface of the first portion of the drain terminal and thereafter the upper surface side of the sealing resin portion is polished by liquid honing, thereby allowing the upper surface of the first portion of the drain terminal to be exposed on the upper surface of the sealing resin portion. Both heat dissipating property and production yield of the semiconductor device are improved. | 09-11-2008 |
20080242004 | INKJET PRINTED WIREBONDS, ENCAPSULANT AND SHIELDING - A method of connecting a chip to a package in a semiconductor device includes printing an encapsulant to a predetermined thickness on at least a portion of the chip and package and printing a layer of conductive material on the encapsulant in a predetermined pattern between the chip and package. The printed conductive material conforms to an upper surface of the encapsulant such that the encapsulant defines a distance from the printed conductive material to the chip and package. The method further includes printing a second layer of encapsulant over the printed conductive material curing at least the second layer of encapsulant. | 10-02-2008 |
20080242005 | Method for manufacturing semiconductor device - In the present application, is disclosed a method of manufacturing a flexible semiconductor device having an excellent reliability and tolerance to the loading of external pressure. The method includes the steps of: forming a separation layer over a substrate having an insulating surface; forming an element layer including a semiconductor element comprising a non-single crystal semiconductor layer, over the separation layer; forming an organic resin layer over the element layer; providing a fibrous body formed of an organic compound or an inorganic compound on the organic resin layer; heating the organic resin layer; and separating the element layer from the separation layer. This method allows the formation of a flexible semiconductor device having a sealing layer in which the fibrous body is impregnated with the organic resin. | 10-02-2008 |
20080254575 | ENCAPSULATION METHOD AND APPARATUS - A method and apparatus for encapsulating items such as electronic devices. A mold material is dispensed onto the electronic device and the device is situated between first and second molds. One mold is moved towards the other so as to vary the size of a cavity defined by the first and second molds. A vacuum is applied to the cavity and the vacuum is varied in response to the size of the cavity. The vacuum can be varied in response to a predetermined vacuum profile. For example, in certain embodiments the vacuum is varied in response to the position of the first mold relative to the second mold, wherein the vacuum is increased as the cavity height is reduced. | 10-16-2008 |
20080261353 | Underfill film having thermally conductive sheet - An underfill film for an electronic device includes a thermally conductive sheet. The electronic device may include a printed circuit board, an electrical component, an underfill, and the thermally conductive sheet. The underfill is situated between the circuit board and the component. The thermally conductive sheet is situated within the underfill, and together with the underfill, constitutes the underfill film. The device may include solder bumps affixing the component to the circuit board, the underfill film having holes within which the solder bumps are aligned. There may be solder bumps on the underside of the circuit board promoting heat dissipation. There may be heat sinks on the circuit board to which the thermally conductive sheet is affixed promoting heat dissipation. The thermally conductive sheet may be affixed to a chassis promoting heat dissipation. The thermally conductive sheet thus promotes heat dissipation from the component to at least the circuit board. | 10-23-2008 |
20080268579 | SEMICONDUCTOR CHIP PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor chip package capable of improving reliability at a chip interconnection portion and improving reliability in a solder joint by reducing thermal and mechanical stresses at an external portion of the package including a solder ball land, and a method of fabricating the package are provided. The method of fabricating a semiconductor chip package includes providing a substrate; forming a first underfill on a first portion of the substrate; forming a second underfill at a chip interconnection portion of the substrate; and mounting a semiconductor chip on the chip interconnection portion using conductive bumps. In the method, the second underfill is formed of a material having a modulus higher than the first underfill. | 10-30-2008 |
20080268580 | METHOD FOR LOW-TEMPERATURE SEALING OF A CAVITY UNDER VACUUM OR UNDER CONTROLLED ATMOSPHERE - This method for sealing a cavity of a component placed in the chamber is carried out by physical vapour deposition (PVD) of germanium or silicon. | 10-30-2008 |
20080305587 | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument - A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes. | 12-11-2008 |
20080311706 | Method for manufacturing semiconductor device - To provide a method for manufacturing a highly-reliable semiconductor device, which is not damaged by external local pressure, with a high yield, a semiconductor device is manufactured by forming an element substrate having a semiconductor element formed using a single-crystal semiconductor substrate or an SOI substrate, providing the element substrate with a fibrous body formed from an organic compound or an inorganic compound, applying a composition containing an organic resin to the element substrate and the fibrous body so that the fibrous body is impregnated with the organic resin, and heating to provide the element substrate with a sealing layer in which the fibrous body formed from an organic compound or an inorganic compound is contained. | 12-18-2008 |
20080311707 | Process for producing a functional device-mounted module - The present disclosure provides an optical functional device-mounted module which needs no expensive or special members, can be reduced in size, and provide a producing process thereof. A bank to dam a liquid sealing resin is provided on a substrate around an optical functional device, the substrate being formed with a predetermined wiring pattern and having the optical functional device mounted thereon. The liquid sealing resin is filled between the functional device and the bank by dropping the liquid sealing resin therebetween. A package component member having a light transmission hole corresponding to an optical function part of the optical functional device is brought into contact with the bank such that the light transmission hole is opposed to the function part of the optical functional device, thereby causing the package component member to contact with the liquid sealing resin. The package component member is fixed onto the substrate by curing the liquid sealing resin and the bank is finally cut off and removed. | 12-18-2008 |
20090004785 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF PACKAGE - A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the bottom mold cap plate to form a projection of mold compound on the bottom surface of the substrate. | 01-01-2009 |
20090017582 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - This invention includes a method for manufacturing a semiconductor device by which implementation of a finer pitch for a semiconductor chip can be handled, and the creation of voids inside an under-filling resin can be reduced in order to realize highly reliable flip-chip mounting. It involves a step in which multiple electrodes arranged two-dimensionally on one side of a semiconductor chip are connected to corresponding conductive regions on a substrate; a step in which an under-filling resin is injected between the one surface of the semiconductor chip and the substrate; and a step in which the under-filling resin is melted at a temperature higher than its glass transition temperature while under a prescribed pressure and cured. | 01-15-2009 |
20090017583 | DOUBLE ENCAPSULATED SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A double encapsulated semiconductor package and manufacturing methods of forming the same are provided. Embodiments of the semiconductor package include a complex chip having normal and random pads formed on its active surface, the complex chip being attached to a first surface of a wiring substrate. First and second windows are formed in the wiring substrate to respectively expose the normal and random pads, and to allow bonding wires to be connected to the normal and random pads with the wiring substrate. A first resin encapsulation portion is formed by a molding method in the first window and a second resin encapsulation portion is formed by a potting method in the second window. | 01-15-2009 |
20090023253 | Semiconductor Device and Method of Making Same - A method for manufacturing a semiconductor device that includes a housing, formed of a polyamide-series thermoplastic resin, and a semiconductor package sealed in the housing, which is formed of a thermosetting epoxy resin. The surface of the package is modified by UV-irradiation to have adhesive properties to polyamide. A plurality of connector terminals extend from the package and housing in parallel. A portion of the terminals is also sealed in the housing together with the package. Thus, the device is easily produced by insert molding and has excellent moisture resistance. | 01-22-2009 |
20090029506 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device | 01-29-2009 |
20090035895 | CHIP PACKAGE AND CHIP PACKAGING PROCESS THEREOF - A chip package comprises a substrate, a chip, a conductive layer and a molding compound. The substrate has a carrying surface and at least a ground pad disposed on the carrying surface. The chip has an active surface and a back surface opposite thereto. The chip is bonded to the substrate with the active surface facing towards the carrying surface of the substrate, wherein the ground pad is disposed outside of the chip. The conductive layer covers the chip and a portion of the carrying surface, and electrically connects to the ground pad. The molding compound is disposed on the carrying surface of the substrate and encapsulates the chip and the conductive layer. | 02-05-2009 |
20090035896 | HIGH POWER MCM PACKAGE WITH IMPROVED PLANARITY AND HEAT DISSIPATION - A structure and a manufacturing method providing improved coplanarity accommodation and heat dissipation in a multi-chip module. One of the components in a multi-chip module (MCM) is provided with a recess formed in its respective top surface; and a film is applied so as to cover the top surfaces of the components and so that any excess film can enter into the recess. The recess is preferably a peripheral groove. Then when molding material is injected, it may surround and seal the side surfaces of the components, while not substantially covering the top surfaces that are covered by the film. Since the recess receives any excess film material that may be present, it may prevent such excess film material from covering the respective side surfaces of the corresponding component and creating a void between the component and the molding material. This advantageous effect of the invention is particularly useful when the top component surface in which the recess is formed is higher above the circuit substrate than the respective top surface of another one of the components. | 02-05-2009 |
20090061566 | SEMICONDUCTOR PACKAGE HAVING A GRID ARRAY OF PIN-ATTACHED BALLS - Semiconductor chip ( | 03-05-2009 |
20090068798 | IMAGER DIE PACKAGE AND METHODS OF PACKAGING AN IMAGER DIE ON A TEMPORARY CARRIER - Methods for fabricating an imager die package and resulting die packages are disclosed. An imager die packaging process may include dicing through a fabrication substrate comprising a plurality of imager die. Thereafter, known good die (KGD) qualified from the imager die are repopulated, face down on a high temperature-compatible temporary carrier, the KGD on the temporary carrier are encapsulated and thereafter removed as a reconstructed wafer from the temporary carrier. Furthermore, a first plurality of discrete conductive elements on a back side of the reconstructed wafer may be partially exposed and, optionally, a second plurality of discrete conductive elements may be applied to the first plurality of discrete conductive elements. The encapsulated KGD are then singulated. | 03-12-2009 |
20090068799 | MANUFACTURING PROCESS FOR A QUAD FLAT NON-LEADED CHIP PACKAGE STRUCTURE - A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a conductive layer having a plurality of recesses and a patterned solder resist layer on the conductive layer are provided, wherein the patterned solder resist layer covers the recesses of the conductive layer. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer is between the chips and the conductive layer. The chips are electrically connected to the conductive layer by a plurality of bonding wires. At least one molding compound is formed to encapsulate the conductive layer, the patterned solder resist layer, the chips and the bonding wires. A part of the conductive layer exposed by the patterned solder resist layer is removed so as to form a patterned conductive layer. Then, the molding compound and the patterned conductive layer are separated. | 03-12-2009 |
20090081831 | WARPAGE CONTROL USING A PACKAGE CARRIER ASSEMBLY - A method for curing an encapsulant that surrounds a plurality of integrated circuits on a strip that forms a strip assembly is provided. The strip assembly is composed of units for packaging and the units each have edges defining a perimeter of the unit. The strip assembly is placed on a shelf. Pressure from deformable material or springs is applied to the strip assembly in regions of the strip. The regions are located at one of a group of locations consisting of along unit edges and centered between unit edges. Heat of sufficient temperature is applied for a sufficient duration to cure the encapsulant. The step of applying pressure continues during the application of heat for curing. | 03-26-2009 |
20090081832 | METHOD OF REDUCING WIRE BOND PROFILE HEIGHT IN INTEGRATED CIRCUITS MOUNTED TO CIRCUIT BOARDS - A method of profiling a wire bond between a contact pad on a die, and a conductor on a supporting structure, by electrically connecting the contact pad on the die to the conductor on the supporting structure with a wire bond, the wire bond extending in an arc from the contact pad to the conductor, pushing on the wire bond to collapse the arc and plastically deform the wire bond, and then releasing the wire bonds such that the plastic deformation maintains the wire bond in a flatter profile shape. The strength of the wire bond is known to be relatively small; of the order of 3 to 5 grams force. However, the Applicant's work has found that the wire bond structure is robust enough to withstand a certain degree of work hardening from plastic deformation. The arc of the wire bond can be deformed into a flatter profile without compromising the electrical connection with the PCB. | 03-26-2009 |
20090081833 | WIRE BOND ENCAPSULANT APPLICATION CONTROL - A method of applying encapsulant to a die mounted to a support structure by providing a die mounted to the support structure, the die having a back surface in contact with the support structure and an active surface opposing the back surface, the active surface having electrical contact pads, positioning a barrier proximate the electrical contact pads and spaced from the active surface to define a gap and, depositing a bead of encapsulant onto the electrical contact pads such that one side of the bead contacts the barrier and a portion of the bead extends into the gap and onto the active surface. Placing a barrier over the active surface so that it defines a narrow gap allows the geometry of the encapsulant front (the line of contact between the encapsulant and the active surface) can be more closely controlled. Any variation in the flowrate of encapsulant from the needle tends to cause bulges or valleys in the height of the bead and or the PCB side of the bead. The fluidic resistance generated by the gap between the barrier and the active surface means that the amount of encapsulant that flows into the gap and onto the active surface is almost constant. The reduced flow variations make the encapsulant front closely correspond to the shape of the barrier. Greater control of the encapsulant front allows the functional elements of the active surface of the die to be closer to the contact pads. | 03-26-2009 |
20090081834 | METHOD OF APPLYING ENCAPSULANT TO WIRE BONDS - A method of applying encapsulant to wire bonds between a die and conductors on a supporting substrate, by forming a bead of the encapsulant on a profiling surface, positioning the profiling surface such that the bead contacts the die and, moving the profiling surface relative to the die to cover the wire bonds with the encapsulant. Wiping the encapsulant over the wire bonds with a profiling surface provides control of the encapsulant front as well as the height of the encapsulant relative to the die. The movement of the profiling surface relative to the die can closely controlled to shape the encapsulant to a desired form. Using the example of a printhead die, the encapsulant can be shaped to present an inclined face rising from the nozzle surface to a high point over the wire bonds. This can be used by the printhead maintenance facilities to maintain contact pressure on the wiping mechanism. However, it will be appreciated that the encapsulant can be shaped to have ridges, gutters, grooves and so on by using a particular shape of profiling surface and relative movement with the die. | 03-26-2009 |
20090098688 | IMPRINT METHOD, CHIP PRODUCTION PROCESS, AND IMPRINT APPARATUS - An imprint method is constituted by a step of curing a resin material formed on a substrate in a state in which an imprint pattern of a mold is in contact or proximity with the resin material, and a step of parting the mold from the cured resin material. The parting is effected while irradiating an entire area in which the imprint pattern of the mold is formed and the cured resin material with an electromagnetic wave for ionizing gaseous molecules in an atmosphere in which the mold and the cured resin material are placed. | 04-16-2009 |
20090104736 | Stacked Packaging Improvements - A plurality of microelectronic assemblies ( | 04-23-2009 |
20090137086 | METHOD FOR MAKING A DEVICE INCLUDING PLACING A SEMICONDUCTOR CHIP ON A SUBSTRATE - A method for making a device is disclosed. One embodiment provides a substrate having a first element protruding from the substrate. A semiconductor chip has a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. The semiconductor chip is placed over the first element of the substrate with the first surface of the semiconductor chip facing the substrate. The second electrode of the semiconductor chip is electrically coupled to the substrate, and the substrate is at least partially removed. | 05-28-2009 |
20090155960 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH OFFSET STACKING AND ANTI-FLASH STRUCTURE - An integrated circuit package system includes: mounting a device structure in an offset location over a carrier with the device structure having a bond pad and a contact pad; connecting an electrical interconnect between the bond pad and the carrier; forming an anti-flash structure over the device structure with the anti-flash structure exposing the contact pad; and forming a package encapsulation adjacent to the anti-flash structure and over the carrier. | 06-18-2009 |
20090155961 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PACKAGE INTEGRATION - An integrated circuit package system comprising: providing a base substrate; attaching a base integrated circuit die over the base substrate; forming a support over the base substrate near only one edge of the base substrate; and attaching a stack substrate over the support and the base integrated circuit die. | 06-18-2009 |
20090170247 | MAGNETIC PARTICLES FOR LOW TEMPERATURE CURE OF UNDERFILL - Electronic devices and methods for fabricating electronic devices are described. One embodiment includes a method comprising providing a first body and a second body, and electrically coupling the first body to the second body using a plurality of solder bumps, wherein a gap remains between the first body and the second body. The method also includes placing an underfill material into the gap between the first body and the second body, the underfill material comprising magnetic particles in a polymer composition. The method also includes curing the underfill material in the gap by applying a magnetic field powered by alternating current, to induce heat in the magnetic particles, wherein the heat in the magnetic particles heats the polymer composition, and the magnetic field is applied for a sufficient time to cure the polymer composition. Other embodiments are described and claimed. | 07-02-2009 |
20090176336 | Method of Manufacturing a Semiconductor Device - The objective of the invention is to provide a method of manufacturing a semiconductor device that allows individual molding of plural semiconductor chips carried on a surface of the substrate. It includes the following process steps: a process step in which plural semiconductor elements | 07-09-2009 |
20090186454 | Method for manufacturing electronic device - A method for manufacturing an electronic device with a plurality of lead frames for individually supporting an electronic component | 07-23-2009 |
20090197375 | Metal-resin-boned structured body and resin-encapsulated semiconductor device, and fabrication method for them - A fabrication method for a metal-base/polymer-resin bonded structured body according to the present invention includes the steps of: (1) applying, to a surface of the metal base, a solution containing an organometallic compound decomposable at 350° C. or lower; (2) baking the applied solution in an oxidizing atmosphere to form, on the surface of the metal base, a coating containing an oxide of the metal of the organometallic compound; (3) providing the polymer resin on the coating; and (4) hardening the polymer resin to provide the metal-base/polymer-resin bonded structured body. | 08-06-2009 |
20090246918 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method of manufacturing a semiconductor device in which a semiconductor element is mounted on a wiring circuit board and a clearance between the wiring circuit board and the semiconductor element is sealed with a sealing material, the method including: a sealing material arranging step of arranging the sealing material on at least one of a terminal-provided surface of the semiconductor element and a terminal-provided surface of the wiring circuit board; a sealing step of pressing the semiconductor element to the wiring circuit board under such a condition that a terminal of the semiconductor element and a terminal of the wiring circuit board are opposed with each other via the sealing material at a reduced pressure of 13300 Pa (absolute pressure) or less, thereby combining the semiconductor element with the wiring circuit board; and subsequent to the sealing step, a terminal connecting step of heating and fusing at least one of the terminal of the semiconductor element and the terminal of the wiring circuit board at an atmospheric pressure, thereby connecting the terminal of the semiconductor element and the terminal of the wiring circuit board. | 10-01-2009 |
20090263940 | MOLDING CLEANING SHEET AND METHOD OF PRODUCING SEMICONDUCTOR DEVICES USING THE SAME - A cleaning sheet ( | 10-22-2009 |
20090269891 | THERMAL ENHANCED PACKAGE - A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector. | 10-29-2009 |
20090275175 | MODIFIED CHIP ATTACH PROCESS - A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time. | 11-05-2009 |
20090291532 | METHOD OF RESIN ENCAPSULATION MOLDING FOR ELECTRONIC PART - A resin encapsulation molding apparatus comprises die assembly of triple die structure and mold release film for covering two cavities respectively corresponding to two substrates. Each of the two cavities comprises inferior die cavity face, cavity side face and cavity face consisting of communication channel face. The mold release film in the state of being tensioned covers each of the two cavities along the morphology thereof. In this condition, molten resin is injected into the two cavities. The molten resin is evenly distributed into the two cavities through communication channel communicating the two cavities with each other. Thereafter, the multiple electronic parts on the two substrates are almost simultaneously immersed in the molten resin within the two cavities and are compression molded. | 11-26-2009 |
20090325349 | SEMICONDUCTOR ENCAPSULATION MATERIAL AND METHOD FOR ENCAPSULATING SEMICONDUCTOR USING THE SAME - A semiconductor encapsulation material of the present invention contains a glass for metal coating which has a strain point of 480° C. or higher, a temperature corresponding to a viscosity of 10 | 12-31-2009 |
20100003790 | METHOD FOR PRODUCING A MICROMECHANICAL COMPONENT HAVING A THIN-LAYER CAPPING - A capping technology is provided in which, despite the fact that structures which are surrounded by a silicon-germanium filling layer are exposed using ClF | 01-07-2010 |
20100041184 | Molding apparatus for manufacturing a semiconductor device and method using the same - A molding apparatus including an upper half having a substrate mounting plate; and a lower half coupled with the upper half to form a cavity there between, wherein the substrate mounting plate faces the cavity, wherein the lower half includes a projecting part which has a top surface which faces the cavity and which projects from the bottom surface of the lower half toward a substantial center point of the substrate mounting plate, wherein the substrate mounting plate is adjustably mounted on the upper half and movable toward the lower half, and wherein the upper half includes a clamp mounted thereon which surrounds the projecting part when the upper and lower halves are coupled with each other. | 02-18-2010 |
20100055848 | Inspection of underfill in integrated circuit package - In inspecting for quality of underfill material dispensed in an IC package, a camera image is captured for the IC package having the underfill material dispensed between an IC die and a package substrate. A data processor analyzes the camera image to determine an occurrence of an unacceptable condition of the underfill material. Pre-heating and/or post-heating of the package substrate before and/or after dispensing the underfill material by a contact-less heater ensures uniform spreading of the underfill material. | 03-04-2010 |
20100055849 | METHOD OF ENCAPSULATING WIRE BONDS - A method encapsulating wire bonds that extend between a die and conductors on a supporting substrate, by contacting an edge of a profiling blade with the encapsulant material to form a bead of the encapsulant on the edge, positioning the edge such that the bead contacts the die and, moving the profiling blade relative to the die to cover the wire bonds with the encapsulant. Wiping the encapsulant over the wire bonds with a profiling blade provides control of the encapsulant front as well as the height of the encapsulant relative to the die. The movement of the profiling surface relative to the die can closely controlled to shape the encapsulant to a desired form. Using the example of a printhead die, the encapsulant can be shaped to present an inclined face rising from the nozzle surface to a high point over the wire bonds. This can be used by the printhead maintenance facilities to maintain contact pressure on the wiping mechanism. However, it will be appreciated that the encapsulant can be shaped to have ridges, gutters, grooves and so on by using a particular shape of profiling blade edge and relative movement with the die. | 03-04-2010 |
20100062572 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor chip which is mounted on a wiring substrate and which is electrically connected to the wiring substrate is disposed in a sealing apparatus. A sealing resin material made of a thermosetting resin composition is supplied into the sealing apparatus. The sealing resin material contains a solid foreign matter having a cured product of a thermosetting resin, and includes particulates of the thermosetting resin composition pulverized with the solid foreign matter, a granulation powder of the particulates, or a preform of the particulates. The semiconductor chip is resin sealed by using the sealing resin material. | 03-11-2010 |
20100075465 | METHOD OF REDUCING VOIDS IN ENCAPSULANT - A method of reducing voids within a bead of encapsulant material deposited on a series of wire bonds connecting a micro-electronic device with die contact pads extending along one edge, and a plurality of conductors on a support structure such that the wire bonds extend across a gap defined between the edge of the micro-electronic device and the plurality of conductors. The method has the steps of depositing at least one transverse bead of encapsulant in the gap extending at an angle to the edge of the micro-electronic device, and, depositing at least one longitudinal bead of encapsulant in the gap extending parallel to the edge of the micro-electronic device. | 03-25-2010 |
20100075466 | METHOD OF FORMING ASSYMETRICAL ENCAPSULANT BEAD - A method of forming an asymmetrical encapsulant bead on a series of wire bonds electrically connecting a micro-electronic device to a series of conductors, the micro-electronic device having a planar active surface. The method has the steps of positioning the die and the wire bonds beneath an encapsulant jetter that jets drops of encapsulant on to the wire bonds, the drops of encapsulant following a vertical trajectory, tilting the die such that the active surface is inclined to the horizontal and, jetting the drops of encapsulant to form a bead of encapsulant material covering the series of wire bonds, the bead having a cross sectional profile that is asymmetrical about an axis parallel to a normal to the active surface. | 03-25-2010 |
20100081237 | Integrated Circuit Assemblies and Methods for Encapsulating a Semiconductor Device - A seal is formed by compressing a cured layer of a composition applied on a substrate. The composition is any liquid, liquefiable, or mastic, which, after application to a surface, is converted or cured to a compressible solid film. The composition includes a flexible polymer as a binding material. The layer on the substrate eliminates the need for a gasket on a contact surface of a mold. The contact surface of the mold compresses the layer during an encapsulation process. The layer remains on the substrate in a finished product. A minimum separation or wall thickness of the mold is defined by the material properties of the mold. The seal eliminates yield loss due to leakage of an encapsulant and reduces maintenance costs associated with the procurement and repeated installation of gaskets on mold tooling. | 04-01-2010 |
20100093135 | STRATIFIED UNDERFILL METHOD FOR AN IC PACKAGE - A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board. | 04-15-2010 |
20100099223 | INTEGRATED CIRCUIT DEVICE AND METHOD - An integrated circuit device includes a semiconductor chip with a metallization layer on the chip. A gas-phase deposited insulation layer is disposed on the metallization layer. | 04-22-2010 |
20100099224 | METHOD FOR MANUFACTURING ANTENNA AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides an antenna with low resistance and a semiconductor device having an antenna whose communication distance is improved. A fluid containing conductive particles is applied over an object. After curing the fluid containing the conductive particles, the fluid is irradiated with a laser to form an antenna. As a method for applying the fluid containing the conductive particles, screen printing, spin coating, dipping, or a droplet discharging method is used. Further, a solid laser having a wavelength of 1 nm or more and 380 nm or less is used as the laser. | 04-22-2010 |
20100124803 | WIRE BOND ENCAPSULANT CONTROL METHOD - A method of depositing encapsulant on a line of wire bonds to a die is described, the die having a back surface in contact with the support structure and an active surface opposing the back surface, the active surface having electrical contact pads and functional elements spaced from the contact pads. The method involves the steps of providing a die mounted to the support structure, positioning a barrier between the contact pads and the functional elements, the barrier being proximate to, but spaced from the active surface, depositing a bead of encapsulant onto the electrical contact pads while the barrier remains stationary such that the barrier prevents the encapsulant from contacting the functional elements, removing the barrier when the bead of encapsulant has been deposited. The fluidic resistance generated by the gap between the barrier and the active surface means that the amount of encapsulant that flows into the gap and onto the active surface is almost constant. The reduced flow variations make the encapsulant front closely correspond to the shape of the barrier. Greater control of the encapsulant front allows the functional elements of the active surface of the die to be closer to the contact pads. | 05-20-2010 |
20100144101 | Semiconductor Device and Method of Forming Conductive Posts Embedded in Photosensitive Encapsulant - A semiconductor package includes a post carrier having a base plate and plurality of conductive posts. A photosensitive encapsulant is deposited over the base plate of the post carrier and around the conductive posts. The photosensitive encapsulant is etched to expose a portion of the base plate of the post carrier. A semiconductor die is mounted to the base plate of the post carrier within the etched portions of the photosensitive encapsulant. A second encapsulant is deposited over the semiconductor die. A first circuit build-up layer is formed over the second encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. The base plate of the post carrier is removed and a second circuit build-up layer is formed over the semiconductor die and the photosensitive encapsulant opposite the first circuit build-up layer. The second circuit build-up layer is electrically connected to the conductive posts. | 06-10-2010 |
20100167471 | REDUCING WARPAGE FOR FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump. | 07-01-2010 |
20100178736 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - One method includes fabricating a semiconductor device including providing a dielectric layer. At least one semiconductor chip is provided defining a first surface including contact elements and a second surface opposite to the first surface. The semiconductor chip is placed onto the dielectric layer with the first surface facing the dielectric layer. An encapsulant material is applied over the second surface of the semiconductor chip in a reel-to-reel process. | 07-15-2010 |
20100178737 | Semiconductor IC and Its Manufacturing Method, and Module with Embedded Semiconductor IC and Its Manufacturing Method - A semiconductor IC includes a semiconductor IC main body having a predetermined circuit formed on a main surface, a metal layer selectively provided on substantially the whole back surface of the semiconductor IC main body excluding the periphery. According to the present invention, the metal layer provided on the semiconductor IC main body can dissipate heat at a high level. Because the metal layer is selectively provided, even when the semiconductor IC main body is thinned by polishing, warpage does not occur easily in a wafer state. The metal layer is selectively provided at the center of the back surface of the semiconductor IC. Therefore, a laminate of a semiconductor wafer and a thick metal does not need to be diced. As a result, chipping on the disconnected surface can be prevented effectively. | 07-15-2010 |
20100190302 | Electronic Packages with Fine Particle Wetting and Non-Wetting Zones - Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics. | 07-29-2010 |
20100203685 | SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP - Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate. | 08-12-2010 |
20100227437 | SEMICONDUCTOR DEVICES GROWN IN SPHERICAL CAVITY ARRAYS AND ITS PREPARATION METHOD - A method for fabricating an array of semiconductor devices comprising the steps of providing a non-metallic substrate, placing a layer of spheres on said substrate, reducing diameter of the spheres, encapsulating the spheres in a matrix of rigid material, finishing an upper surface of said matrix to expose a portion of said spheres, removing the spheres to form an array of cavities within said matrix, and forming features in said cavities in contact with said substrate so as to form the device. | 09-09-2010 |
20100279471 | UNDERFILL DISPENSING SYSTEM FOR INTEGRATED CIRCUITS - A system for dispensing an underfill material between an integrated circuit (IC) chip and a substrate includes a platform at which the underfill material is supplied. The IC chip and the substrate are mounted at the periphery of the platform. The platform rotates and facilitates the movement of the underfill material toward the IC chip and the substrate. The system further includes a Bernoulli tube that is located proximate to the IC chip and the substrate. The Bernoulli tube generates a low pressure in the proximity of the IC packages. The low pressure facilitates the dispensing of the underfill material between the IC chip and the substrate. | 11-04-2010 |
20100304536 | DAM COMPOSITION FOR USE WITH MULTILAYER SEMICONDUCTOR PACKAGE UNDERFILL MATERIAL, AND FABRICATION OF MULTILAYER SEMICONDUCTOR PACKAGE USING THE SAME - A composition comprising (A) an epoxy resin, (B) a curing agent, (C) an inorganic filler having an average particle size of 0.1-10 μm and a maximum particle size of up to 75 μm, and (D) a surface-silylated silica having an average particle size of 0.005 μm to less than 0.1 μm is suited as a dam composition for use with a underfill material in the fabrication of multilayer semiconductor packages. | 12-02-2010 |
20100311209 | METHOD O ENCAPSULATING A WAFER LEVEL MICRODEVICE - The present invention discloses a method of encapsulating a wafer level microdevice, which includes: fabricating a microdevice on top side of a first silicon wafer; depositing a first capping carbon film on the top side of the first silicon wafer; implementing a backside fabricating process of wafer from bottom side of the first silicon wafer by carrying the top side of the first silicon wafer through the first capping carbon film; removing the first capping carbon film by selective gaseous reaction with carbon; and encapsulating an encapsulation wafer onto the top side of the first silicon wafer. The present invention deposits and removes the first capping carbon film by means of chemical technology, thereby protecting the microdevice on the top side of the first wafer during implementing the backside fabricating process of wafer. The top side does not need to be protected through the encapsulation wafer before implementing the backside fabricating process of wafer, which makes the wafer thinner and convenient to be handled. | 12-09-2010 |
20100323479 | Semiconductor Component with Surface Mountable Devices and Method for Producing the Same - A semiconductor component including: a substrate, at least one semiconductor chip arranged on the substrate and at least one passive device likewise arranged on the substrate. The passive device is mounted with its underside on the substrate. The semiconductor component further includes an interspace disposed between the underside of the passive device and the substrate. The interspace is filled with an underfilling material. In order to avoid the solder pumping effect, the upper side and the lateral sides of the passive device are also embedded in a plastic compound. | 12-23-2010 |
20100330748 | METHOD OF ENCAPSULATING AN ENVIRONMENTALLY SENSITIVE DEVICE - Methods of encapsulating an environmentally sensitive device. The methods involve temporarily laminating a flexible substrate to a rigid support using a reversible adhesive for processing, reversing the reversible adhesive, and removing the device from the rigid support. | 12-30-2010 |
20100330749 | INTERCONNECTS FOR PACKAGED SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING SUCH DEVICES - Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects. | 12-30-2010 |
20110003440 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device or a substrate is described. The method includes providing a chip attached to a carrier or providing a substrate. A foil is held over the chip and the carrier or the substrate. A laser beam is directed onto the foil, and substance at the foil is ablated and deposited on the chip and the carrier or on the substrate. | 01-06-2011 |
20110033987 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a method for manufacturing a semiconductor device which suppresses an influence on a semiconductor element due to entry of an impurity element, moisture, or the like from outside even in the case of thinning or removing a substrate after forming a semiconductor element over the substrate. A feature is to form an insulating film functioning as a protective film on at least one side of the substrate by performing surface treatment on the substrate, to form a semiconductor element such as a thin film transistor over the insulating film, and to thin the substrate. As the surface treatment, addition of an impurity element or plasma treatment is performed on the substrate. As a means for thinning the substrate, the substrate can be partially removed by performing grinding treatment, polishing treatment, or the like on the other side of the substrate. | 02-10-2011 |
20110053321 | METHOD OF FABRICATING AND ENCAPSULATING MEMS DEVICES - A method of fabricating and encapsulating MEMS devices is disclosed, using least two carbon films as the dual sacrificial layers sandwiching a MEMS structural film which is anchored onto a substrate and covered by an encapsulating film containing a plurality of thru-film sacrificial release holes. The dual sacrificial carbon films are selectively removed via plasma-enhanced oxygen or nitrogen ashing through the thru-film sacrificial release holes for releasing the MEMS structural film inside a cavity formed between the encapsulating film and the substrate. The thru-film sacrificial release holes, preferably with a relative high asperity ratio, are then sealed off by depositing a hole-sealing film in a physical vapor deposition process or a chemical vapor deposition process or combination. | 03-03-2011 |
20110065242 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE USING A FLUXING UNDERFILL COMPOSITION APPLIED TO SOLDER BALLS IN A DIP PROCESS - The present invention relates to a method of fabricating a semiconductor package or circuit assembly using an fluxing underfill composition applied to solder contact points in a dip process. | 03-17-2011 |
20110076809 | Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings - A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. | 03-31-2011 |
20110097856 | METHOD OF MANUFACTURING WAFER LEVEL PACKAGE - Disclosed is a method of manufacturing a wafer level package, which includes arranging semiconductor dies on a carrier, forming a protective layer between the semiconductor dies of the carrier through screen printing, primarily heat hardening the protective layer, simultaneously pressing and secondarily heat hardening the protective layer, and removing the carrier, so that a thickness difference between the semiconductor dies and the protective layer is not formed and the warping of the wafer level package is reduced. | 04-28-2011 |
20110117706 | PROTECTIVE TAPE JOINING METHOD AND PROTECTIVE TAPE JOINING APPARATUS - A cooling plate having a cooling pipe mounted therein in a serpentine shape is placed in a stack manner on a rear face of a chuck table for suction-holding a rear face of the semiconductor wafer. A coolant is circulated through the cooling pipe, thereby cooling the chuck table. The semiconductor wafer is suction-held while the chuck table is cooled. In addition, the protective tape is joined to the semiconductor wafer while the chuck table is cooled. That is, the protective tape is joined to the surface of the semiconductor wafer while being cooled indirectly via the semiconductor wafer cooled in advance through direct contact to the chuck table during joining of the protective tape. | 05-19-2011 |
20110143501 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - Provided is a method of producing a semiconductor device having a structure wherein a semiconductor chip | 06-16-2011 |
20110143502 | Method for Low Stress Flip-Chip Assembly of Fine-Pitch Semiconductor Devices - A device including a first body ( | 06-16-2011 |
20110171786 | Mold resin sealing device and molding method - A mold resin sealing device for sealing a surface of a semiconductor wafer with a mold resin, includes: a first mold die; and a second mold die disposed opposite to the first mold die, the second mold die having a second surface; wherein the first mold die includes a first part having a first surface facing the second surface of the second mold die and having an opening in a central region of the first surface; and a first step-like movable part capable of moving in the opening in both directions so that the first step-like movable part moves toward and away from the second mold die. | 07-14-2011 |
20110183474 | ELECTRONIC DEVICE AND MANUFACTURING METHOD OF THE SAME - A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component | 07-28-2011 |
20110223721 | METHOD OF MANUFACTURE OF INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-TIER CONDUCTIVE INTERCONNECTS - A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a planar surface and a cavity therein, a first barrier between the planar surface and a first interconnect, and a second barrier between the cavity and a second interconnect; providing a substrate; mounting an integrated circuit over the substrate; mounting the carrier to the substrate with the first interconnect and the second interconnect attached to the substrate and with the planar surface over the integrated circuit; forming an encapsulation between the substrate and the carrier covering the integrated circuit, the encapsulation having an encapsulation recess under the planar surface and over the integrated circuit; and removing a portion of the carrier to expose the encapsulation, a portion of the first barrier to form a first contact pad, and a portion of the second barrier to form a second contact pad. | 09-15-2011 |
20110223722 | CAPILLARY-FLOW UNDERFILL COMPOSITIONS, PACKAGES CONTAINING SAME, AND SYSTEMS CONTAINING SAME - An underfill composition is formulated to increase the surface tension thereof for use in capillary underfilling of an integrated circuit die that is coupled to a mounting substrate. A method includes mixing a surface tension-increasing additive with a bulk polymer and a hardener and allowing the underfill composition to flow between the integrated circuit die and the mounting substrate. An article is achieved by the method. The article can be assembled into a computing system. | 09-15-2011 |
20110230015 | Semiconductor Device, Manufacturing Method of Semiconductor Device, and RFID Tag - The present invention provides a semiconductor device which is formed at low cost and has a great versatility, a manufacturing method thereof, and further a semiconductor device with an improved yield, and a manufacturing method thereof. A structure, which has a base including a plurality of depressions having different shapes or sizes, and a plurality of IC chips which are disposed in the depressions and which fit the depressions, is formed. A semiconductor device which selectively includes a function in accordance with an application, by using the base including the plurality of depressions and the IC chips which fit the depressions, can be manufactured at low cost. | 09-22-2011 |
20110244636 | MANUFACTURING METHOD OF SEMICONDUCTOR CHIP-EMBEDDED WIRING SUBSTRATE - With respect to a substrate including a first film, on a surface of which a pad is formed, a second film made of thermoplastic resin is a thermal compression bonded to a pad formation surface of the substrate. A stud bump formed on a semiconductor chip is stuffed into the second film while melting the second film and is pressure welded to the pad by application of pressure and heat. The melted second film seals between the semiconductor chip and the substrate. Then, multiple resin films are stacked with the substrate and the second film to form a stacked body. In a pressurizing and heating process, the multiple resin films, the substrate and the second film are integrated at one time so that the stud bump is bonded to the pad. | 10-06-2011 |
20110244637 | MOLD AND SUBSTRATE FOR USE WITH MOLD | 10-06-2011 |
20110275181 | SEMICONDUCTOR PACKAGE HAVING AN ANTENNA WITH REDUCED AREA AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes an electromagnetic shielding member for shielding electromagnetic waves. An antenna is disposed on an upper face of the electromagnetic shielding member and includes an antenna part with a plurality of conductive particles electrically connected with each other and an insulation part disposed on the upper face of the electromagnetic shielding member and insulating the antenna part. Ball lands are disposed on the electromagnetic shielding member and are electrically connected with the antenna part. A Radio Frequency Identification (RFID) chip is electrically connected to the ball lands. | 11-10-2011 |
20110281403 | Method For Encapsulating Semiconductor Dies - The present invention describes two methods ( | 11-17-2011 |
20110281404 | METHOD OF SEALING A SEMICONDUCTOR ELEMENT WITH AN EPOXY RESIN COMPOSITION - A method of sealing a semiconductor element which involves applying an epoxy resin composition including an epoxy resin and a phenolic resin obtained by reacting phenol, a biphenyl compound represented by the general formula (3) and benzaldehyde to a semiconductor element and curing the composition to seal the semiconductor element: | 11-17-2011 |
20110281405 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being aligned with the through-holes. An encapsulant material is applied over the semiconductor chip. | 11-17-2011 |
20120021568 | METHOD OF MANUFACTURING CIRCUIT DEVICE - Provided is a method of manufacturing a circuit device in which a circuit element is resin-sealed with sealing resins formed integrally with each other. In the present invention, a resin sheet and a circuit board are housed in a cavity of a mold, and thereafter a first sealing resin formed of a tablet in melted form is injected into the cavity. At the time of injecting the first sealing resin, a second sealing resin formed of the resin sheet in melted form is not yet cured and is maintained in liquid form. Accordingly, the injected first sealing resin and the second sealing resin are mixed at the boundary therebetween, preventing the generation of a gap in the boundary portion and therefore preventing the deterioration of the moisture resistance and withstand voltage at the boundary portion. | 01-26-2012 |
20120028420 | METHOD FOR REUSE OF WAFERS FOR GROWTH OF VERTICALLY-ALIGNED WIRE ARRAYS - Reusing a Si wafer for the formation of wire arrays by transferring the wire arrays to a polymer matrix, reusing a patterned oxide for several array growths, and finally polishing and reoxidizing the wafer surface and reapplying the patterned oxide. | 02-02-2012 |
20120040500 | Semiconductor Molding Chamber - A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer. | 02-16-2012 |
20120045871 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - Provided are a semiconductor package of a semiconductor chip, a semiconductor module, an electronic system, and methods of manufacturing the same. The method includes mounting a semiconductor chip on a package substrate, forming a molding member on the semiconductor chip, forming via holes penetrating the molding member to expose a portion of a top surface of the semiconductor chip, the via holes being arranged in a lattice shape in a plan view, and forming thermally conductive via plugs in the via holes. | 02-23-2012 |
20120064673 | METHOD FOR FABRICATING A SEMICONDUCTOR CHIP PANEL - The method includes providing a plurality of semiconductor chips and placing the plurality of semiconductor chips on a carrier. A compression molding apparatus is provided that includes a first tool and a second tool. The carrier is placed on the first tool of the compression molding apparatus and the semiconductor chips are encapsulated in a mold material by compression molding. During compression molding a heat transfer from the first tool to an upper surface of the carrier is delayed. | 03-15-2012 |
20120064674 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING A MOVABLE SWITCHING ELEMENT - Semiconductor structures including a movable switching element having a base disposed on a conductive pad, a body extending from the base, and an end laterally adjacent and spaced apart from a conductive contact are disclosed. Upon application of a threshold voltage, the movable switching element may deform toward the conductive contact via an electrical field, establishing electrical contact between the conductive pad and the conductive contact. Various methods may be used to form such semiconductor structures, and switching devices including such semiconductor structures. Memory devices and electronic systems include such switching devices. | 03-15-2012 |
20120070941 | MODULE WITH SILICON-BASED LAYER - The invention concerns a module comprising a carrier element, a semiconductor device mounted on said carrier element and a silicon-based insulating layer. The silicon-based insulating layer is arranged on the side of the carrier element opposite to the semiconductor device. The invention further concerns a module comprising a semiconductor device, a mold compound at least partly covering the semiconductor device and a silicon-based passivation layer. The silicon-based passivation layer covers at least partly the periphery of the mold compound. | 03-22-2012 |
20120070942 | PROCESS FOR FORMING THIN FILM ENCAPSULATION LAYERS - A thin film environmental barrier encapsulation process includes providing an electronic device on a substrate, a first reactant gaseous material, a second reactant gaseous material, an inert gaseous material; and a delivery head through which the reactant gaseous materials and the inert gaseous material are simultaneously directed toward the electronic device and the substrate. One or more of the reactant gaseous materials and the inert gaseous material flows through the delivery head. The flow of the one or more of the reactant gaseous materials and the inert gaseous material generates a pressure to create a gas fluid bearing that maintains a substantially uniform distance between the delivery head and the substrate. Relative motion between the delivery head and the substrate causes the second reactant gaseous material to react with at least a portion of the electronic device and the substrate that has been treated with the first reactant gaseous material. | 03-22-2012 |
20120070943 | CHIP PACKAGING METHOD AND STRUCTURE THEREOF - The present invention relates to a chip packaging method and structure, in which bonding pads provided on the chip are connected by a plurality of metal wires via bonding, each of the metal wires is bending in the middle part to be higher than a predetermined height, and its ends are respectively electrically connected with two of the bonding pads. A molding layer is packaged on the chip and the molding layer is higher than the predetermined height. The molding layer is sliced at the predetermined height. Two upper breakpoints of each metal wire are exposed and a substrate is attached onto the molding layer. A plurality of circuit contacts of the substrate are respectively electrically coupled with the upper breakpoints. Whereby, the invention is capable of reducing the length of the metal wires in order to improve transmission speed, but also to reduce the volume of the packaging structure. | 03-22-2012 |
20120083074 | FLEXIBLE SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads. | 04-05-2012 |
20120088338 | INTEGRATED CIRCUIT TAMPERING PROTECTION AND REVERSE ENGINEERING PREVENTION COATINGS AND METHODS - A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited. | 04-12-2012 |
20120108015 | UNDERFILL FLOW GUIDE STRUCTURES AND METHOD OF USING SAME - Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes. | 05-03-2012 |
20120115281 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which is excellent in high-temperature high-humidity reliability without decreasing moldability and curability is provided. The method includes sealing a semiconductor element in resin using a semiconductor-sealing epoxy resin composition; and then performing a heating treatment. The semiconductor-sealing epoxy resin composition contains (A) an epoxy resin of formula (1): | 05-10-2012 |
20120164796 | Method of Manufacturing a Printable Composition of a Liquid or Gel Suspension of Diodes - An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary method of making a liquid or gel suspension of diodes comprises: adding a viscosity modifier to a plurality of diodes in a first solvent; and mixing the plurality of diodes, the first solvent and the viscosity modifier to form the liquid or gel suspension of the plurality of diodes. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns. | 06-28-2012 |
20120164797 | Method of Manufacturing a Light Emitting, Power Generating or Other Electronic Apparatus - An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary method of fabricating an electronic device comprises: depositing one or more first conductors; and depositing a plurality of diodes suspended in a mixture of a first solvent and a viscosity modifier. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns. | 06-28-2012 |
20120178219 | METHODS FOR VACUUM ASSISTED UNDERFILLING - Methods for applying an underfill with vacuum assistance. The method may include dispensing the underfill onto a substrate proximate to at least one exterior edge of an electronic device attached to the substrate. A space between the electronic device and the substrate is evacuated through at least one gap in the underfill. The method further includes heating the underfill to cause the underfill to flow into the space. Because a vacuum condition is supplied in the open portion of the space before flow is initiated, the incidence of underfill voiding is lowered. | 07-12-2012 |
20120178220 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The yield of semiconductor devices is improved. In an upper die of a resin molding die including a pair of the upper die and a lower die, by lengthening the radius of the cross section of an inner peripheral surface of a second corner part facing an injection gate of a cavity more than that of the other corner part, a void contained in a resin in resin injection can be pushed out into an air vent without allowing the void to remain in the second corner part of the cavity. Consequently, the occurrence of the void in the cavity can be prevented and then the occurrence of the appearance defect of the semiconductor device can be prevented. | 07-12-2012 |
20120184071 | SURFACE COATING METHOD, SEMICONDUCTOR DEVICE, AND CIRCUIT BOARD PACKAGE - To provide a surface coating method, which contains applying a surface coating material to a layered structure so as to cover at least a surface of an insulating film of the layered structure, to form a coating on the surface of the insulating film, wherein the surface coating material contains a water-soluble resin, an organic solvent, and water, and wherein the layered structure contains the insulating film exposed to an outer surface, and a patterned metal wiring exposed to an outer surface. | 07-19-2012 |
20120184072 | METHODS FOR MANUFACTURING SUPERJUNCTION SEMICONDUCTOR DEVICE HAVING A DIELECTRIC TERMINATION - A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided. | 07-19-2012 |
20120208326 | Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings - A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. | 08-16-2012 |
20120208327 | IMPRINT APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE - According to one embodiment, an imprint apparatus includes an ejection unit, an ejection command generating unit, a determining unit, a prohibition command generating unit, and an ejection control unit. The ejection unit ejects a resin material. The ejection command generating unit generates an ejection command based on a drop recipe. The determining unit determines the presence or absence of a processing target substrate in an ejection destination of the resin material. The prohibition command generating unit, when the processing target substrate is not present in an ejection destination, generates an ejection prohibition command. The ejection control unit gives priority to the ejection prohibition command over the ejection command. | 08-16-2012 |
20120231586 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A method of manufacturing includes arranging an integral resin sleeve formed by integrating a plurality of sleeve parts so that the sleeve parts are respectively fitted with a plurality of electrode terminals. There is a press-fitting of the sleeve parts to the electrode terminals by performing mold clamping on molds to apply a force downward on the integral resin sleeve. Further, there is a filling of a molding resin into a hollow cavity of the molds. | 09-13-2012 |
20120252170 | PACKAGED ELECTRONIC DEVICES HAVING DIE ATTACH REGIONS WITH SELECTIVE THIN DIELECTRIC LAYER - A method for forming a packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. A second dielectric layer is formed on the top substrate surface of the package substrate. An IC die which is mounted to the top substrate surface of the package substrate. An underfill layer is formed between the IC die and the die attach region. | 10-04-2012 |
20120270371 | Method for Encapsulating Microelectronic Devices - According to an embodiment disclosed herein, a microelectronic device to be encapsulated is built on, or alternatively in, a substrate. The device is then coated with a sacrificial layer. A lid layer is deposited over the sacrificial layer, and then appropriately perforated to optimize the removal of the sacrificial layer. The sacrificial layer is then removed using one of several etching or other processes. The perforations in the lid layer are then sealed using a viscous sealing material, thereby fixing the environment that encapsulates the device. The sealing material is then cured or hardened. An optional moisture barrier may be deposited over the cured sealing layer to provide further protection for the encapsulation if needed. | 10-25-2012 |
20120282739 | MANUFACTURING A FILLING OF A GAP IN SEMICONDUCTOR DEVICES - A method for manufacturing a filling in a gap region between a first surface and a second surface includes applying a suspension comprising a carrier fluid and filler particles in the gap region between the first and the second surface; and withholding filler particles by a barrier element in the gap region to form a path of attached filler particles between the first surface and the second surface. | 11-08-2012 |
20120282740 | ELECTRONIC DEVICE AND PROCESS FOR MANUFACTURING ELECTRONIC DEVICE - The electronic device, which allows inhibiting the breaking-away of the element from the frame member, even if the temperature change of the electronic device is repeated, and the process for manufacturing the electronic device, are achieved. An electronic device includes a photo-sensitive element formed in a wafer, a frame member installed on the wafer to surround a functional unit, and an encapsulating resin layer filling a circumference of the frame member. | 11-08-2012 |
20120295405 | METHODS FOR VACUUM ASSISTED UNDERFILLING - Methods for applying an underfill with vacuum assistance. The method may include dispensing the underfill onto a substrate proximate to at least one exterior edge of an electronic device attached to the substrate. A space between the electronic device and the substrate is evacuated through at least one gap in the underfill. The method further includes heating the underfill to cause the underfill to flow into the space. Because a vacuum condition is supplied in the open portion of the space before flow is initiated, the incidence of underfill voiding is lowered. | 11-22-2012 |
20120302011 | CHARGING-FREE ELECTRON BEAM CURE OF DIELECTRIC MATERIAL - An ultra low-k dielectric material layer is formed on a semiconductor substrate. In one embodiment, a grid of wires is placed at a distance above a top surface of the ultra low-k dielectric material layer and is electrically biased such that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. In another embodiment, a polymeric conductive layer is formed directly on the ultra low-k dielectric material layer and is electrically biased so that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. By maintaining the total electron emission coefficient at 1.0, charging of the substrate is avoided, thus protecting any device on the substrate from any adverse changes in electrical characteristics. | 11-29-2012 |
20120302012 | METHOD FOR FABRICATING PACKAGING SUBSTRATE WITH EMBEDDED SEMICONDUCTOR COMPONENT - A packaging substrate with an embedded semiconductor component and a method of fabricating the same are provided, including: fixing a semiconductor chip with electrode pads to an assisting layer with apertures through an adhesive member, wherein each of the electrode pads has a bump formed thereon, each of the apertures is filled with a filling material, and the bumps correspond to the apertures, respectively; forming a first dielectric layer on the assisting layer to encapsulate the semiconductor chip; removing the bumps and the filling material to form vias; and forming a first wiring layer on the first dielectric layer and forming first conductive vias in the vias to provide electrical connections between the electrode pads and the first wiring layer, wherein the first wiring layer comprises a plurality of conductive lands formed right on the first conductive vias, respectively. | 11-29-2012 |
20120309134 | Implantable Microelectronic Device and Method of Manufacture - An implantable hermetically sealed microelectronic device and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device to an aperture in the hermetic layer. In a preferred embodiment, one or more patterned titanium layers are formed over the device contact pad, and one or more platinum layers are formed over the titanium layers, such that the top surface of the upper platinum layer defines an external, biocompatible electrical contact for the device. Preferably, the bottom conductive layer is larger than the contact pad on the device, and a layer in the stack defines a shoulder. | 12-06-2012 |
20120322212 | WIRELESS CHIP AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to reduce the cost of a wireless chip, further, to reduce the cost of a wireless chip by enabling the mass production of a wireless chip, and furthermore, to provide a downsized and lightweight wireless chip. A wireless chip in which a thin film integrated circuit peeled from a glass substrate or a quartz substrate is formed between a first base material and a second base material is provided according to the invention. As compared with a wireless chip formed from a silicon substrate, the wireless chip according to the invention realizes downsizing, thinness, and lightweight. The thin film integrated circuit included in the wireless chip according to the invention at least has an n-type thin film transistor having an LDD (Lightly Doped Drain) structure, a p-type thin film transistor having a single drain structure, and a conductive layer functioning as an antenna. | 12-20-2012 |
20130029459 | METHOD FOR MAKING SCHOTTKY BARRIER DIODE - A method for making a Schottky barrier diode includes the following steps. A first metal layer, a second metal layer and a carbon nanotube composite material are provided. The carbon nanotube composite material is applied on the first metal layer and the second metal layer to form a semiconductor layer. The carbon nanotube composite material includes an insulated polymer and a number of carbon nanotubes dispersed in the insulated polymer. The semiconductor layer is in Schottky contact with the first metal layer and in ohmic contact with the second metal layer. | 01-31-2013 |
20130045575 | EPOXY ENCAPSULATING AND LAMINATION ADHESIVE AND METHOD OF MAKING SAME - An adhesive includes an epoxy resin and a hardener. The hardener includes trioxdiamine, diaminodicyclohexylmethane, toluene diamine, and bisphenol-A dianhydride. | 02-21-2013 |
20130052777 | BACK SIDE ALIGNMENT STRUCTURE AND MANUFACTURING METHOD FOR THREE-DIMENSIONAL SEMICONDUCTOR DEVICE PACKAGES - A mechanism for accurate alignment of semiconductor package back side interconnect processing is provided. As semiconductor die are placed in position for an encapsulated panel, two or more alignment die having fiducial markings formed on the back, or non-active, side of those die are also placed in the panel. Once all the die and other components have been placed for the panel, the panel is encapsulated using an encapsulant. Excess encapsulant, if any, is removed by a process such as backgrinding. The back grinding process exposes the back side of the alignment die and the fiducial features on those alignment die. The fiducial features on the alignment die can then be used for alignment of backside processing operations on the panel. | 02-28-2013 |
20130078769 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device for improving production efficiency and the flexibility of production design thereof is provided. The method includes preparing semiconductor chips having a first main surface on which an electroconductive member is formed, preparing a supporting structure in which over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order, arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to the first main surfaces of the semiconductor chips, laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips, and curing the radiation curable pressure-sensitive adhesive layer by irradiating from the support side to peel the radiation curable pressure-sensitive adhesive layer and the first thermosetting resin layer from each other. | 03-28-2013 |
20130078770 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A method for producing a semiconductor device, including a semiconductor chip, for improving production efficiency and the flexibility of production design is provided. The method comprises: preparing a semiconductor chip having a first main surface on which an electroconductive member is formed; preparing a supporting structure in which, over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order; arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to a second main surface of the semiconductor chips opposite to the first main surface; laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips; and curing the radiation curable pressure-sensitive adhesive layer by irradiating from the support side to peel the radiation curable pressure-sensitive adhesive layer from the first thermosetting resin layer. | 03-28-2013 |
20130095615 | MANUFACTURING METHOD OF PACKAGE STRUCTURE - A manufacturing method of a package structure is provided. In the manufacturing method, a metal substrate having a seed layer is provided. A patterned circuit layer is formed on a portion of the seed layer. A first patterned dry film layer is formed on the other portion of the seed layer. A surface treatment layer is electroplated on the patterned circuit layer with use of the first patterned dry film layer as an electroplating mask. The first patterned dry film layer is removed. A chip bonding process is performed to electrically connect a chip to the surface treatment layer. An encapsulant is formed on the metal substrate. The encapsulant encapsulates the chip, the surface treatment layer, and the patterned circuit layer. The metal substrate and the seed layer are removed to expose a bottom surface of the encapsulant and a lower surface of the patterned circuit layer. | 04-18-2013 |
20130109138 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE | 05-02-2013 |
20130115738 | PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer. | 05-09-2013 |
20130122660 | SENSOR DEVICE AND METHOD - A sensor device and method. One embodiment provides a first semiconductor chip having a sensing region. A porous structure element is attached to the first semiconductor chip. A first region of the porous structure element faces the sensing region of the first semiconductor chip. An encapsulation material partially encapsulates the first semiconductor chip and the porous structure element. | 05-16-2013 |
20130122661 | UNDERFILL FLOW GUIDE STRUCTURES AND METHOD OF USING SAME - Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes. | 05-16-2013 |
20130122662 | ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT - A method of manufacturing an electronic component, wherein a resin including colored particles composing dots in a dot pattern which will act as an authentication pattern is flowed in and solidified over the electronic component, thereby fixing the colored particles. | 05-16-2013 |
20130137222 | Method for Stacking Semiconductor Dies - A system and method for stacking semiconductor dies is disclosed. A preferred embodiment comprises forming through-silicon vias through the wafer, protecting a rim edge of the wafer, and then removing the unprotected portions so that the rim edge has a greater thickness than the thinned wafer. This thickness helps the fragile wafer survive further transport and process steps. The rim edge is then preferably removed during singulation of the individual dies from the wafer. | 05-30-2013 |
20130143368 | SEMICONDUCTOR DEVICE - A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier. | 06-06-2013 |
20130143369 | CHIP IDENTIFICATION FOR ORGANIC LAMINATE PACKAGING AND METHODS OF MANUFACTURE - A chip identification for organic laminate packaging and methods of manufacture is provided. The method includes forming a material on a wafer which comprises a plurality of chips. The method further includes modifying the material to provide a unique identification for each of the plurality of chips on the wafer. The organic laminate structure includes a chip with a device and a material placed on the chip which is modified to have a unique identification mark for the chip. | 06-06-2013 |
20130157418 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base carrier; forming a conductive post on the base carrier, the conductive post having a top protrusion with a protrusion top side; mounting a base integrated circuit over the base carrier; and forming a base encapsulation over the base integrated circuit, the base encapsulation having an encapsulation top side and an encapsulation recess with the conductive post partially exposed within the encapsulation recess, the encapsulation top side above the protrusion top side. | 06-20-2013 |
20130157419 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The objective of the present invention is to provide a method of manufacturing a semiconductor device having less contamination of a semiconductor chip and good productivity. The present invention is a method of manufacturing a semiconductor device having a semiconductor chip, with the steps of preparing a plurality of semiconductor chips, preparing a resin sheet having a thermosetting resin layer, arranging the plurality of semiconductor chips on the thermosetting resin layer, arranging a cover film on the plurality of semiconductor chips, and embedding the plurality of semiconductor chips in the thermosetting resin layer by a pressure applied through the arranged cover film, in which the contact angle of the cover film to water is 90° or less. | 06-20-2013 |
20130178018 | SEMICONDUCTOR MODULE, MOLDING APPARATUS, AND MOLDING METHOD - A semiconductor module includes a plurality of semiconductor elements, a first tabular electrode coupled to one face side of the plurality of semiconductor elements, a second tabular electrode coupled to the other face side of the plurality of semiconductor elements, and a molding material that encapsulates the plurality of semiconductor elements between the first electrode and the second electrode. A protrusion extending toward the second electrode is provided in a circumferential edge portion of the first electrode, and the protrusion surrounds the molding material. | 07-11-2013 |
20130196474 | MATERIALS AND PROCESSES FOR RELEASING PRINTABLE COMPOUND SEMICONDUCTOR DEVICES - A method of fabricating transferable semiconductor devices includes providing a release layer including indium aluminum phosphide on a substrate, and providing a support layer on the release layer. The support layer and the substrate include respective materials, such as arsenide-based materials, such that the release layer has an etching selectivity relative to the support layer and the substrate. At least one device layer is provided on the support layer. The release layer is selectively etched without substantially etching the support layer and the substrate. Related structures and methods are also discussed. | 08-01-2013 |
20130210199 | METHOD FOR DEPOSITING AN ENCAPSULATING FILM - A method and apparatus for depositing a material layer, such as encapsulating film, onto a substrate is described. In one embodiment, an encapsulating film formation method includes delivering a gas mixture into a processing chamber, the gas mixture comprising a silicone-containing gas, a first nitrogen-containing gas, a second nitrogen-containing gas and hydrogen gas; energizing the gas mixture within the processing chamber by applying between about 0.350 watts/cm | 08-15-2013 |
20130244383 | CURABLE PROTECTANT FOR ELECTRONIC ASSEMBLIES - Latent thermal initiators and protectant compositions that remain shelf stable at elevated temperatures, yet readily cure during a solder bump reflow process or other high temperature processing. The thermal initiators comprise thermally labile cation-anion pairs where the blocked cation prevents cure at low temperatures, and the unblocked cation initiates cure at high temperatures. Also provided is a method of making a preferred initiator comprising the cation [N-(4-methylbenzyl)-N,N-dimethylanalinium] and the anion [N(SO | 09-19-2013 |
20130244384 | SOLDERING RELIEF METHOD AND SEMICONDUCTOR DEVICE EMPLOYING SAME - A semiconductor device includes a substrate having a first side and a second side, the second side having a mounting location for at least one semiconductor element, and the first side having a plurality of locations electrically connected to locations on the second side. A plurality of electrically conductive interconnects are provided at the locations, each having a first end attached at the location and a second end spaced from the substrate, and an encapsulant partially encapsulates the plurality of interconnects and has a surface lying in a first plane. The second ends are located on the side of the first plane opposite from the substrate first side, an annular space in the encapsulant surrounds each of the plurality of electrically conductive interconnects, and the annular space has a bottom located between the first plane and the substrate first side. Also a method for making such a semiconductor device. | 09-19-2013 |
20130252383 | FABRICATION METHOD OF WAFER LEVEL SEMICONDUCTOR PACKAGE AND FABRICATION METHOD OF WAFER LEVEL PACKAGING SUBSTRATE - A fabrication method of a wafer level semiconductor package includes: forming on a carrier a first dielectric layer having first openings exposing portions of the carrier; forming a circuit layer on the first dielectric layer, a portion of the circuit layer being formed in the first openings; forming on the first dielectric layer and the circuit layer a second dielectric layer having second openings exposing portions of the circuit layer; forming conductive bumps in the second openings; mounting a semiconductor component on the conductive bumps; forming an encapsulant for encapsulating the semiconductor component; and removing the carrier to expose the circuit layer. By detecting the yield rate of the circuit layer before mounting the semiconductor component, the invention avoids discarding good semiconductor components together with packages as occurs in the prior art, thereby saving the fabrication cost and improving the product yield. | 09-26-2013 |
20130273698 | Methods for Forming Through Vias - Methods for forming through vias in an integrated circuit package are disclosed. A substrate having a first surface is covered with an encapsulation layer of uncured material; the method includes inserting an upper mold tool having a first plurality of pillars into the encapsulation layer to imprint through vias extending to the first surface of the substrate; curing the encapsulation layer and the through vias; removing the upper mold tool from the encapsulation layer; and disposing conductor material within the through vias to make electrical connectors within the through vias. In additional methods, a method for forming an encapsulation layer using an upper and lower mold tool to form through vias and a mold cavity is disclosed. | 10-17-2013 |
20130323886 | Semiconductor Molding Chamber - A system and method for a semiconductor molding chamber is disclosed. An embodiment comprises a top molding portion and a bottom molding portion that form a cavity between them into which a semiconductor wafer is placed. The semiconductor molding chamber has a first set of vacuum tubes which hold and fix the position of the semiconductor wafer and a second set of vacuum tubes which evacuate the cavity of extraneous ambient gasses. The encapsulant may then be placed over the semiconductor wafer in order to encapsulate the semiconductor wafer. | 12-05-2013 |
20130337616 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND UNDERFILL EQUIPMENT FOR THE SAME - A method of fabricating a semiconductor device comprises loading a circuit board including a semiconductor chip into underfill equipment, positioning the circuit board on a depositing chuck of the underfill equipment, filling an underfill material in a space between the semiconductor chip and the circuit board placed on the depositing chuck; transferring the circuit board including the underfill material so that it is positioned on a post-treatment chuck of the underfill equipment; heating the underfill material of the circuit board placed on the post-treatment chuck in a vacuum state, and unloading the circuit board, of which the underfill material has been heated in the vacuum state, from the underfill equipment. | 12-19-2013 |
20140004665 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 01-02-2014 |
20140024178 | MAGNETICALLY SEALED WAFER PLATING JIG SYSTEM AND METHOD - A wafer plating jig system comprising an electrically insulating wafer plating jig base having a plurality of overlapping cavities of different depths, each cavity configured to receive a semiconductor wafer of a different size and an electrically conductive cover plate comprising an open center surrounded by a support, the cover plate comprising an electrical conductor surrounding the open center and with at least one of the overlapping cavities of the wafer plating jig base. | 01-23-2014 |
20140024179 | PRODUCING METHOD OF SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a preparing step of preparing a board formed with a concave portion, a terminal disposed in or around the concave portion, and a semiconductor element disposed in the concave portion; a wire-bonding step of connecting the terminal to the semiconductor element with a wire; a pressure-welding step of pressure-welding an encapsulating sheet to the board so as to be in close contact with the upper surface of a portion around the concave portion and to be separated from the upper surface of the concave portion under a reduced pressure atmosphere; and an atmosphere releasing step of releasing the board and the encapsulating sheet under an atmospheric pressure atmosphere. | 01-23-2014 |
20140024180 | INTERFACE ADHESION IMPROVEMENT METHOD - Embodiments of the invention provide methods of an interface adhesion improvement methods used on a transparent substrate for OLED or thin film transistor applications. In one embodiment, a method of forming a buffer layer on a surface of a substrate includes providing a substrate having an planarization material disposed thereon in a processing chamber, supplying a buffer layer gas mixture including a silicon containing gas into the processing chamber, controlling a substrate temperature less than about 100 degrees Celsius, forming a buffer layer on the planarization material, supplying an encapsulating barrier layer deposition gas mixture including a silicon containing gas and a nitrogen containing gas into the processing chamber, and forming an encapsulating barrier layer on the buffer layer. | 01-23-2014 |
20140038364 | METHOD OF ENCAPSULATING A MICROELECTRONIC DEVICE - Method of encapsulating at least one microelectronic device, comprising at least the following steps:
| 02-06-2014 |
20140057396 | Method of Manufacturing a Component Comprising Cutting a Carrier - A method of manufacturing a component is disclosed. An embodiment of the method comprises dicing a carrier in a plurality of components, the carrier being disposed on a support carrier, after dicing, placing a connection layer on the carrier and removing the components from the support carrier. | 02-27-2014 |
20140106512 | MICROCHIP CHARGE PATTERNING - A method of forming a charge pattern on a microchip includes depositing a material on the surface of the microchip, and using an external device to develop charge in the material. | 04-17-2014 |
20140127866 | Package Structures Including a Capacitor and Methods of Forming the Same - A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side. | 05-08-2014 |
20140147975 | SEMICONDUCTOR DEVICE PACKAGE - Forming a packaged semiconductor device includes placing a semiconductor die attached to a carrier into a mold cavity having an injection port, wherein the semiconductor die has an encapsulant exclusion region on a top surface of the semiconductor die within an outer perimeter of the top surface; and flowing an encapsulant over the semiconductor die and carrier from the injection port, wherein the encapsulant flows around the encapsulant exclusion region to surround the encapsulant exclusion region without covering the encapsulant exclusion region. The encapsulant exclusion region has a first length corresponding to a single longest distance across the encapsulant exclusion region, wherein the first length is aligned, within 30 degrees, to a line defined by a shortest distance between an entry point of the injection port into the mold cavity and an outer perimeter of the encapsulant exclusion region. | 05-29-2014 |
20140199812 | BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS - A method of forming a chip package includes providing a chip with a plurality of first copper post bumps having a first height of copper post. The method also includes providing a substrate with a plurality of second copper post bumps having a second height of copper post. The method further includes bonding the plurality of first copper post bumps to the plurality of second copper post bumps by reflowing solder layers on the plurality of first copper post bumps and the plurality of second copper post bumps together to form a first copper post bump structure of the chip package. The first copper post bump structure has a standoff, wherein a ratio of a sum of the first height of copper post and the second height of copper post to the standoff is equal to or greater than about 0.6 and less than 1. | 07-17-2014 |
20140206154 | SEMICONDUCTOR DEVICE COMPRISING A PASSIVE COMPONENT OF CAPACITORS AND PROCESS FOR FABRICATION - A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block. | 07-24-2014 |
20140213021 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials. | 07-31-2014 |
20140220744 | METHOD OF MAKING WIRE BOND VIAS AND MICROELECTRONIC PACKAGE HAVING WIRE BOND VIAS - Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate. | 08-07-2014 |
20140220745 | LAMINATING SYSTEM - It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used. | 08-07-2014 |
20140273356 | SEMICONDUCTOR DEVICES AND METHODS OF MAKING THE SAME - In one embodiment, methods for making semiconductor devices are disclosed. | 09-18-2014 |
20140315355 | MANUFACTURING METHOD OF WAFER LEVEL PACKAGE - The present invention provides a method for manufacturing a semiconductor package structure, including (i) providing a carrier plate; (ii) disposing a die on the carrier plate; (iii) forming a plurality of bonding wires having a first end and a second end; (iv) forming an encapsulant covering the die and the bonding wires and exposing a portion of each of the bonding wires from a first surface thereof; (v) removing the carrier plate; (vi) forming a patterned conductive layer on a second surface of the encapsulant opposite to the first surface; (vii) electrically connecting the second ends of the bonding wires to the active surface of the die via the patterned conductive layer; and (viii) forming a plurality of first external connection terminals on the first surface of the encapsulant respectively covering the portions of the bonding wires exposed from the encapsulant. | 10-23-2014 |
20140315356 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a manufacturing method of a semiconductor device, a semiconductor chip is sealed with a resin, and then a laser is applied to remove the resin so that a part of the semiconductor chip is exposed. The semiconductor chip is made of a material that has a lower absorptivity of the laser than the resin and is not melted by the laser. The laser has a wavelength that passes through the semiconductor chip and has a lower absorptivity in the semiconductor chip than in the resin. The laser is applied to the resin from a side adjacent to one of plate surfaces of the semiconductor chip, so that the resin sealing the one of the plate surfaces is sublimated and removed and at least a part of the resin sealing the other of the plate surfaces is subsequently sublimated and removed by the laser having passed through the semiconductor chip. | 10-23-2014 |
20140329363 | FIBER-CONTAINING RESIN SUBSTRATE, SEALED SUBSTRATE HAVING SEMICONDUCTOR DEVICE MOUNTED THEREON, SEALED WAFER HAVING SEMICONDUCTOR DEVICE FORMED THEREON, A SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - A fiber-containing resin substrate for collectively sealing a semiconductor devices mounting surface of a substrate having the semiconductor devices mounted thereon or a semiconductor devices forming surface of a wafer having semiconductor devices formed thereon, includes: a resin-impregnated fiber base material obtained by impregnating a fiber base material with a thermosetting resin and semi-curing or curing the thermosetting resin; and an uncured resin layer containing an uncured thermosetting resin and formed on one side of the resin-impregnated fiber base material. There can be a fiber-containing resin substrate that enables suppressing warp of a wafer and delamination of semiconductor devices even though a large-diameter wafer or a large-diameter substrate made of a metal and the like is sealed, enables collectively sealing a semiconductor devices mounting surface of the substrate or a semiconductor devices forming surface of the wafer, and has excellent heat resistance or moisture resistance after sealing. | 11-06-2014 |
20140342509 | Module and Assembly with Dual DC-Links for Three-Level NPC Applications - A power semiconductor module has four power terminals. An IGBT has a collector connected to the first power terminal and an emitter coupled to the third power terminal. An anti-parallel diode is coupled in parallel with the IGBT. A DC-link is connected between the second and fourth power terminals. The DC-link may involve two diodes and two IGBTs, where the IGBTs are connected in a common collector configuration. The first and second power terminals are disposed in a first line along one side of the module, and the third and fourth power terminals are disposed in a second line along the opposite side of the module. Two identical instances of the module can be interconnected together to form a three-level NPC phase leg having low stray inductances, where the phase leg has two parallel DC-links. | 11-20-2014 |
20140349448 | SILICON-BASED ELECTRONICS WITH DISABLING FEATURE - Silicon-based circuitry is dissolved or otherwise disabled in a controlled manner by reactive materials provided beneath the insulating layer on which the circuitry is formed. Heat and/or light induced acid generating materials are provided for corroding one or more circuitry components. Additionally and/or alternatively, gas-producing materials are deposited in compartments beneath the insulating layer. The gas-producing materials cause pressure to rise within the compartments, damaging the chip. Chemical reactions within the chip may be facilitated by heating elements and/or light generating elements embedded within the chip and actuated by triggering circuits. | 11-27-2014 |
20140357025 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode. | 12-04-2014 |
20140363929 | BUMPLESS BUILD-UP LAYER PACKAGE WARPAGE REDUCTION - The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer. | 12-11-2014 |
20140377915 | Pre-mold for a magnet semiconductor assembly group and method of producing the same - A method of manufacturing pre-molds for a magnet semiconductor assembly group is provided, wherein the method comprises forming a plurality of permanent magnetizable elements on a carrier structure in a sensor-free area of the carrier structure by applying a permanent magnetizable molding material on the carrier structure. | 12-25-2014 |
20140377916 | METHODS TO PREVENT FILLER ENTRAPMENT IN MICROELECTRONIC DEVICE TO MICROELECTRONIC SUBSTRATE INTERCONNECTION STRUCTURES - Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures. | 12-25-2014 |
20150050783 | Molding Chamber Apparatus and Curing Method - An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component. | 02-19-2015 |
20150056757 | CURABLE ENCAPSULANTS AND USE THEREOF - The present invention relates to curable barrier encapsulants or sealants for electronic devices that have pressure sensitive adhesive properties. The encapsulants are especially suitable for organic electronic devices that require lower laminating temperature profiles. The encapsulant protects active organic/polymeric components within an organic electronic device from environmental elements, such as moisture and oxygen. | 02-26-2015 |
20150064851 | PRE-APPLIED UNDERFILL - Underfill structures useful as pre-applied underfill materials comprise a polymer layer having a first polymer region and a second polymer region, wherein the second polymer region comprises inorganic filler. Electronic assemblies comprising a chip or die and a substrate are formed using such multi-layer structured pre-applied underfill. | 03-05-2015 |
20150072479 | ABLATION METHOD AND RECIPE FOR WAFER LEVEL UNDERFILL MATERIAL PATTERNING AND REMOVAL - Introducing an underfill material over contact pads on a surface of an integrated circuit substrate; and ablating the introduced underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation. A method including first ablating an underfill material to expose an area of contact pads on a substrate using temporally coherent electromagnetic radiation; introducing a solder to the exposed area of the contact pads; and second ablating the underfill material using temporally coherent electromagnetic radiation. A method including introducing an underfill material over contact pads on a surface of an integrated circuit substrate; defining an opening in the underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation; introducing a solder material to the exposed area of the contact pads; and after introducing the solder, removing the sacrificial material. | 03-12-2015 |
20150099332 | RESIN COMPOSITION, SUBSTRATE AND METHOD OF MANUFACTURING ELECTRONIC DEVICE - Provided are a resin composition and a substrate that are capable of being used for producing an electronic device including thin-film transistors having an excellent switching property. The resin composition contains an aromatic polyamide and a solvent dissolving the aromatic polyamide. The resin composition is used to form a layer, and a total light transmittance of the layer in a wavelength of 355 nm is 10% or less. Further, a method of manufacturing the electronic device using such a substrate is also provided. | 04-09-2015 |
20150104909 | APPARATUS AND METHOD FOR SELF-ALIGNING CHIP PLACEMENT AND LEVELING - An approach is provided for aligning and leveling a chip package portion. The approach involves filling, at least partially, a reservoir formed between a first sidewall portion having a first slanted surface and a second sidewall portion having a second slanted surface with a fluid. The approach also involves placing a chip package portion into the reservoir. The approach further involves draining the fluid from the reservoir to cause the chip package portion to align with respect to a center of the reservoir. The chip package portion aligns with respect to the center of the reservoir and levels based on a relationship between the chip package portion, an angle of the first slanted surface, an angle of the second slanted surface, and the fluid. The chip package portion is secured in the aligned and leveled state by a molding compound. | 04-16-2015 |
20150118802 | DUAL CORNER TOP GATE MOLDING - A mold die includes a side wall forming a hollow cavity and opposing first and second axial ends. The side wall has first and second openings respectively at the first and second axial ends. Each of the first and second openings accesses the hollow cavity. A main wall is coupled to the side wall at the first end thereof and spans the first opening. A center of the main wall is aligned with a longitudinal axis of the side wall. The main wall defines a plane oriented generally perpendicularly with respect to the longitudinal axis of the side wall. First and second gates are formed through the main wall to access the hollow cavity. The first and second gates define a first line lying in the plane of the main wall. The center of the main wall is located on the first line between the first and second gates. | 04-30-2015 |
20150125999 | APPARATUS AND METHOD OF ATTACHING SOLDER BALL AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE INCLUDING SOLDER BALL - Provided are apparatuses configured to attach a solder ball, methods of attaching a solder ball, and methods of fabricating a semiconductor package including the same. An apparatus configured to attach a solder ball includes a chuck configured to receive a package substrate on which solder balls are provided; a shielding mask configured to shield the package substrate and including holes configured to expose the solder balls; and a heater configured to melt the solder balls exposed through the holes. | 05-07-2015 |
20150147852 | VACUUM CARRIER MODULE, METHOD OF USING AND PROCESS OF MAKING THE SAME - A vacuum carrier module includes a substrate having at least one hole and an edge region. There is at least one support on a top surface of the substrate. Further, a gel film is adhered to the edge region of the substrate. The at least one hole fluidly connects a reservoir located above the top surface of the substrate. A method of using a vacuum carrier module includes planarizing a gel film by passing an alignment material through a hole in a substrate to contact a first surface of the gel film, positioning at least one chip on a second surface of the gel film opposite the first surface. The method further includes encasing the at least one chip in a molding material and applying a vacuum to the first surface of the gel film. | 05-28-2015 |
20150325461 | Method of Packaging Semiconductor Devices and Apparatus for Performing the Same - Provided is a method of packaging semiconductor devices mounted on a flexible substrate having a longitudinally extending tape shape and including packaging areas arranged along the extending direction thereof. An empty area, on which a semiconductor device is not mounted, is detected from among the packaging areas. When the empty area is detected, a heat dissipation paint composition is applied on the semiconductor devices mounted on the remaining packaging areas except for the empty area to form first heat dissipation layers. When the empty is not detected, the heat dissipation paint composition is applied on the semiconductor devices mounted on the packaging areas to form second heat dissipation layers. Here, the first dissipation layers are formed by a potting process, and the second heat dissipation layers are formed by a screen printing process. | 11-12-2015 |
20150344730 | PRIMER COMPOSITION, METHOD OF FORMING A PRIMER LAYER ON A SEMICONDUCTOR DEVICE, AND METHOD OF ENCAPSULATING A SEMICONDUCTOR DEVICE - A primer composition is provided. The primer composition includes at least one bi- or multi-functional benzoxazine compound; and at least one compound including a functional group having affinity for a metallic surface, and a cross-linkable group. A method of forming a primer layer on a semiconductor device, and a method of encapsulating a semiconductor device are also provided. | 12-03-2015 |
20150371916 | PRE-APPLIED UNDERFILL - Underfill structures useful as pre-applied underfill materials comprise a polymer layer having a first filled polymer region having a first viscosity and a second filled polymer region having a second viscosity, wherein the first viscosity is less than the second viscosity. Electronic assemblies comprising a chip or die and a substrate are formed using such multi-layer structured pre-applied underfill. | 12-24-2015 |
20150380375 | MICROELECTRONIC PACKAGE HAVING WIRE BOND VIAS AND STIFFENING LAYER - Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate. | 12-31-2015 |
20160005966 | Methods of Forming Structures - Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides. | 01-07-2016 |
20160013145 | DEVICE WITH PILLAR-SHAPED COMPONENTS | 01-14-2016 |
20160017191 | UNDERFILL MATERIAL AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - An underfill film material and a method for manufacturing a semiconductor device using the same which enables voidless mounting and favorable solder bonding properties are provided. An underfill material is used which contains an epoxy resin, an acid anhydride, an acrylic resin and an organic peroxide, the underfill material exhibits non-Bingham fluidity at a temperature ranging from 60° C. to 100° C., a storage modulus G′ measured by dynamic viscosity measurement has an inflection point in an angular frequency region below 10E+02 rad/s, and the storage modulus G′ in the angular frequency below the inflection point is 10E+05 Pa or more and 10E+06 Pa or less. This enables voidless packaging and excellent solder connection properties. | 01-21-2016 |
20160020120 | APPARATUS AND METHODS FOR MICRO-TRANSFER-PRINTING - In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed. | 01-21-2016 |
20160027666 | TWO STEP METHOD OF RAPID CURING A SEMICONDUCTOR POLYMER LAYER - A semiconductor device and method of making the semiconductor device is described. A semiconductor die can be provided. A polymer layer can be formed over the semiconductor die. A via can be formed in the polymer layer. The polymer layer can be cross-linked in a first process, after forming the via, by exposing the polymer layer to ultraviolet (UV) radiation to form a sidewall of the via with via sidewall slope greater than or equal to 45 degrees and to further form a cross-linked via sidewall surface. The polymer layer can be thermally cured in a second process after the first process, wherein a maximum ramp-up rate from room temperature to a peak temperature of the second process is greater than 10 degrees Celsius per minute. | 01-28-2016 |
20160035592 | ADHERING DEVICE AND METHOD FOR PRODUCING ELECTRONIC DEVICE - The adhering device includes a first mold member having a first cavity in which an adhering preform, which includes an electronic component and a resin sheet disposed to face the electronic component in spaced-apart relation, is accomodated; an elastic member disposed to face the resin sheet so that a first enclosed space can be formed with the first cavity; and a differential pressure generation means connected to the first mold member for allowing the air pressure of the first enclosed space to be lower than the air pressure of a space opposite to the first enclosed space relative to the elastic member. The adhering device is configured such that by operating the differential pressure generation means, the elastic member moves towards the first cavity side, the adhering perform is pressed in the direction facing the electronic component and the resin sheet, thereby adhering the resin sheet to the electronic component. | 02-04-2016 |
20160035593 | DEVICES AND METHODS RELATED TO SUPPORT FOR PACKAGING SUBSTRATE PANEL HAVING CAVITIES - Devices and methods related to support for packaging substrate panel having cavities. In some embodiments, a device for fabricating radio-frequency (RF) modules can include a support plate having a receiving side configured to receive a packaging substrate panel having a plurality of pockets. The receiving side can include a plurality of support features. Each support feature can be dimensioned to fit at least partially into the corresponding pocket and provide support for a portion of the packaging substrate panel associated with the pocket. Among others, such a device can allow formation of an overmold on the side of packaging substrate panel opposite from the pockets, without mechanical deformation of the packaging substrate panel. | 02-04-2016 |
20160043045 | PAD STRUCTURE OF A SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE PAD STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE PAD STRUCTUR - A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion—to provide high roughness and firm connection. | 02-11-2016 |
20160049343 | METHOD FOR MANUFACTURING COMPOSITE BODY AND COMPOSITION - Provided is a method for manufacturing a composite body, the method containing: a composition preparation process of preparing a composition that contains a polymer having a cationic functional group and having a weight average molecular weight of from 2,000 to 1,000,000, and that has a pH of from 2.0 to 11.0; a composite member preparation process of preparing a composite member that includes a member A and a member B, a surface of the member B having a defined isoelectric point, and that satisfies a relationship: the isoelectric point of a surface of the member B< the pH of the composition02-18-2016 | |
20160082718 | Methods with Inkjet Processes and Their Application - A method a described which includes depositing a first component of a multicomponent system by means of an inkjet process, and depositing a second component of the multicomponent system by means of an inkjet process. | 03-24-2016 |
20160086827 | METHODS FOR FORMING COLOR IMAGES ON MEMORY DEVICES AND MEMORY DEVICES FORMED THEREBY - A memory device including graphical content and a method of making the memory device with graphical content are disclosed. The graphical content is formed on a release media. The release media and the unencapsulated memory device are placed in a mold and encapsulated. During the encapsulation and curing of the molding compound, the graphical content is transferred from the release media to the encapsulated memory device. | 03-24-2016 |
20160099159 | SIMULTANEOUS INDEPENDENTLY CONTROLLED DUAL SIDE PCB MOLDING TECHNIQUE - Molding assemblies and methods for dual side package molding are described. In an embodiment, a molding compound is injected into a front cavity with a first actuator, and a molding compound is injected into a back cavity with a second actuator, with the first and second actuator assemblies being independently controlled. In an embodiment, the molding compound flows through a through-hole in a molding substrate from a front side of the molding substrate to a back side of the molding substrate, and into the back cavity. | 04-07-2016 |
20160111588 | ENCAPSULATED FLEXIBLE ELECTRONIC DEVICE, AND CORRESPONDING MANUFACTURING METHOD - The disclosure relates to an encapsulated flexible electronic device comprising a flexible electronic device, wherein the flexible electronic device is protected by a protective coating layer, a first cover sheet and a second cover sheet being made of patterned and developed dry photoresist films. The encapsulated flexible electronic device may be used to directly realize different type of electronic devices, such as smart sensor devices. | 04-21-2016 |
20160111690 | DISPLAY PANEL AND METHOD FOR FABRICATION THEREOF - A display panel is provided. The display panel includes a substrate, a pixel array, a peripheral circuit, and a protective layer. The substrate includes a display region and a non-display region. The pixel array is located in the display region of the substrate. The peripheral circuit is located in the non-display region. The protective layer is located in the display region and the non-display region. The peripheral circuit and the pixel array are covered by the protective layer. The protective layer in the non-display region has a plurality of openings, which expose the substrate. The apertures of the openings is between 1 μm and 1 mm, and the spacing between the openings is 10 μm and 1 cm. | 04-21-2016 |
20160118297 | Metal Pads with Openings in Integrated Circuits - A device includes a metal pad, and a passivation layer including portions overlapping edge portions of the metal pad. A Post-Passivation-Interconnect (PPI) includes a trace portion overlying the passivation layer, and a pad portion connected to the trace portion. A polymer layer includes an upper portion over the PPI, and a plug portion extending into, and encircled by, the pad portion of the PPI. | 04-28-2016 |
20160133543 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 05-12-2016 |
20160148820 | PACKAGE-ON-PACKAGE STRUCTURES AND METHODS OF MANUFACTURE THEREOF - A method for manufacturing a package-on-package structure may include: providing a support structure having a package attached to an inclined surface of the support structure, the package comprising: a first chip package; a second chip package disposed over the first chip package; and a standoff gap between the first chip package and the second chip package, wherein a first side of the package is disposed higher on the inclined surface of the support structure than a second side of the package; and dispensing an underfill into the standoff gap, the underfill flowing through the standoff gap from the first side of the package to the second side of the package. | 05-26-2016 |
20160152821 | RESIN COMPOSITION FOR SEMICONDUCTOR ENCAPSULATION AND SEMICONDUCTOR ENCAPSULATION METHOD USING SAME | 06-02-2016 |
20160168351 | NARROW-GAP FLIP CHIP UNDERFILL COMPOSITION | 06-16-2016 |
20160181126 | METHOD FOR MANUFACTURING MULTI-CHIP PACKAGE | 06-23-2016 |
20160189984 | METHODS FOR VACUUM ASSISTED UNDERFILLING - Methods for applying an underfill with vacuum assistance. The method includes receiving a substrate with the surface at least partially covered by a glass-like film that has a top surface of reduced roughness relative to the surface of the substrate, providing the underfill on the top surface of the glass-like film along an exterior edge of the electronic device, evacuating the space to provide a vacuum condition in the open portion of the space, and heating the underfill to cause flow of the underfill toward the exterior edge and into the open portion of the space, wherein the glass-like film reduces trapping of gas under the underfill. | 06-30-2016 |
20160189985 | MOLD RELEASE FILM AND PROCESS FOR PRODUCING SEMICONDUCTOR PACKAGE - To provide a mold release film which is excellent in releasability and capable of suppressing contamination of a mold or a resin-encapsulation portion by the mold release film and which is capable of forming a resin-encapsulation portion excellent in adhesion to an ink layer, and a process for producing a semiconductor package using the mold release film. A mold release film to be disposed on a cavity surface of a mold in a method for producing a semiconductor package wherein a semiconductor element is disposed in the mold and encapsulated with a curable resin to form a resin-encapsulation portion, characterized in that it has a first surface to be in contact with the curable resin at the time of forming the resin-encapsulation portion, and a second surface to be in contact with the cavity surface, at least the first surface is made of a fluororesin, and in a specific test method, F/Al is from 0.2 to 4, or F/(C+F+O) is from 0.1 to 0.3. | 06-30-2016 |
20160189986 | MOLD RELEASE FILM AND PROCESS FOR PRODUCING SEMICONDUCTOR PACKAGE - A mold release film to be disposed on a cavity surface of a mold in a method for producing a semiconductor package wherein a semiconductor element is disposed in the mold and encapsulated with a curable resin to form a resin-encapsulation portion, characterized in that it has a first surface to be in contact with the curable resin at the time of forming the resin-encapsulation portion, and a second surface to be in contact with the cavity surface, at least one of the first surface and the second surface has irregularities formed thereon, and the surface having irregularities formed thereon, has an arithmetic mean roughness (Ra) of from 1.3 to 2.5 μm and a peak count (RPc) of from 80 to 200; and a process for producing a semiconductor package by using the mold release film. | 06-30-2016 |
20160196990 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE | 07-07-2016 |
20160379847 | Method for Fabricating a Semiconductor Chip Panel - A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each including a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips. | 12-29-2016 |
20160379940 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements. | 12-29-2016 |