Entries |
Document | Title | Date |
20080293189 | METHOD OF MANUFACTURING CHIP INTEGRATED SUBSTRATE - There are provided the steps of connecting a chip component | 11-27-2008 |
20080299708 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device has an element formed in the chip region of a substrate, a plurality of interlayer insulating films formed on the substrate, a wire formed in the interlayer insulating films in the chip region, and a plug formed in the interlayer insulating films in the chip region and connecting to the wire. A seal ring extending through the plurality of interlayer insulating films and continuously surrounding the chip region is formed in the peripheral portion of the chip region. A stress absorbing wall extending through the plurality of interlayer insulating films and discretely surrounding the seal ring is formed outside the seal ring. | 12-04-2008 |
20080318365 | FORMATION OF ALPHA PARTICLE SHIELDS IN CHIP PACKAGING - A structure fabrication method. First, an integrated circuit including N chip electric pads is provided electrically connected to a plurality of devices on the integrated circuit. Then, an interposing shield having a top side and a bottom side and having N electric conductors in the interposing shield is provided being exposed to a surrounding ambient at the top side but not at the bottom side. Next, the integrated circuit is bonded to the top side of the interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors. Next, the bottom side of the interposing shield is polished so as to expose the N electric conductors to the surrounding ambient at the bottom side of the interposing shield. Then, N solder bumps are formed on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors. | 12-25-2008 |
20090035893 | SEMICONDUCTOR ELEMENT AND A PRODUCING METHOD FOR THE SAME, AND A SEMICONDUCTOR DEVICE AND A PRODUCING METHOD FOR THE SAME - A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder. | 02-05-2009 |
20090035894 | Apparatus and method for bonding silicon wafer to conductive substrate - A system and method is disclosed for bonding a substrate to a semiconductor die that is prone to curling when subjected to an elevated temperature in a solder reflow oven, for example, thereby improving the electrical and mechanical bonding for large dies, wafers, chips, and photovoltaic cells. In one embodiment, the substrate is adapted to curl to the same degree as the die to form a uniform gap between the substrate and die across the boundary there between. In another embodiment, solder used to bond the die and substrate is applied such that the volume deposited varies based on the expected gap between the die and substrate when heated to the melting temperature of the solder. | 02-05-2009 |
20090047755 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREFOR - A semiconductor package that has a superior high frequency characteristics and that can obtain a large area for an internal wiring pattern is provided. According to the present invention, a semiconductor package includes: a multilayer printed wiring board | 02-19-2009 |
20090068795 | Production methods of electronic devices - A method of producing an electronic device having mounted thereon a microelectromechanical system element. The method includes forming a micromachine component and electronic component for operation of the micromachine component on a substrate to form the system element, and bonding to the substrate a lid covering an active surface of the substrate and provided with wiring patterns to define an operating space for the micromachine component and electrically connecting the electronic component and the wiring patterns of the lid at a bonded part of the substrate and the lid. | 03-12-2009 |
20090104735 | SEMICONDUCTOR PACKAGE HAVING INCREASED RESISTANCE TO ELECTROSTATIC DISCHARGE - Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The package includes a ESD shield attached to the substrate. The ESD shield configured to increase the ESD hardness of the package. The ESD shield can further serve to stiffen the package to prevent warping and operate as a heat spreader. | 04-23-2009 |
20090137085 | METHOD OF MANUFACTURING A WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via hole formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film, the second interconnection being connected to the first interconnection via the via conductor. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via conductor, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, and has a warped shape such that when the wiring substrate is left at rest on a horizontal plate, at least a central part of each side of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised, where each of the sides extends along a second direction perpendicular to a first direction in the plane surface of the substrate. | 05-28-2009 |
20090176334 | Method for forming a die-attach layer during semiconductor packaging processes - Disclosed is a method for forming a die-attach layer during semiconductor packaging processes. A chip carrier includes a substrate core and a stiffener. Top surface of the substrate core includes a plurality of die-attaching units and a peripheral area enclosed by the stiffener. A non-planar printing stencil is also provided. When the non-planar printing stencil is pressed against the chip carrier, the non-planar printing stencil is compliantly in contact with the substrate core and the stiffener and a plurality of printing openings of the non-planar printing stencil exposes the substrate core within the die-attaching units. During stencil printing, die-attach material fills in the printing openings to directly adhere to the substrate core. Therefore, the warpage of the substrate core is restrained to avoid bleeding of die-attach material so that die-attach materials can be formed as a die-attach layer with a uniform thickness on core-exposed chip carrier with lower costs. Additionally, the chip carrier will not be deformed during semiconductor packaging processes. | 07-09-2009 |
20090186452 | DUAL METAL STUD BUMPING FOR FLIP CHIP APPLICATIONS - A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer. | 07-23-2009 |
20090246917 | LINKED CHIP ATTACH AND UNDERFILL - A method for attaching an integrated circuit chip to a package substrate includes placing the integrated circuit onto the package substrate, and performing reflow to attach the integrated circuit to the package substrate. The temperature of the integrated circuit and package assembly is maintained at or above a predetermined temperature prior to dispensing an underfill between the package substrate and the integrated circuit. An underfill material is dispensed between the package substrate and the integrated circuit. The underfill material is cured to a first level of curing in the integrated circuit and package assembly. The underfill material is cooled in the integrated circuit and package assembly, and the underfill material is cured to a second level of curing in which the second level of curing is greater than the first level of curing. | 10-01-2009 |
20090269886 | Manufacturing Method of Semiconductor Device - A manufacturing method of a semiconductor device is provided, which includes a process in which a transistor is formed over a first substrate; a process in which a first insulating layer is formed over the transistor; a process in which a first conductive layer connected to a source or a drain of the transistor is formed; a process in which a second substrate provided with an second insulating layer is arranged so that the first insulating layer is attached to the second insulating layer; a process in which the second insulating layer is separated from the second substrate; and a process in which a third substrate provided with a second conductive layer which functions as an antenna is arranged so that the first conductive layer is electrically connected to the second conductive layer. | 10-29-2009 |
20090269887 | Apparatus for Manufacturing Semiconductor Package for Wide Lead Frame and Method of Constructing Semiconductor Package Using the Same - An apparatus for manufacturing a semiconductor package includes an index rail transferring a lead frame in forward and backward directions, the lead frame having a first surface and a second surface that is opposite to the first surface, a loader portion connected to an end portion of the index rail and supplying the lead frame to the index rail, a frame driving portion connected to the opposite end portion of the end portion of the index rail and rotating the lead frame around a normal to the first surface, and a die attach portion attaching a semiconductor chip on the lead frame supplied to the index rail. | 10-29-2009 |
20090275174 | Soldering Container and Production Method of Semiconductor Device - A soldering container configured to be conveyed by a conveyance mechanism during soldering in a state accommodating a soldering subject. The container includes a sealable container body for accommodating the soldering subject. The container body includes at least one communication passage enabling communication between the inside and outside of the container body. The container body is configured to be connectable to an atmospheric adjustment device for adjusting an internal atmosphere of the container body through the communication passage. | 11-05-2009 |
20090286358 | Method of fabricating integrated circuits, integrated circuit component mask layout set, and component photomask set - A method of fabricating integrated circuits includes the steps of: a) with reference to a physical design of a hardware unit, preparing an integrated circuit component mask layout set associated with component photomasks suitable for fabricating an array of the hardware units on a wafer; b) preparing the component photomasks with reference to the integrated circuit component mask layout set; c) forming the array of the hardware units and interconnections between adjacent hardware units on the wafer using the component photomasks prepared in step b) ; and d) cutting the wafer along selected ones of the scribe lines so as to form a plurality of integrated circuit dies. Each of the integrated circuit dies is independently selected from a single-type including only one of the hardware units, and a multi-type including a plurality of the hardware units that are interconnected electrically via uncut ones of the conductive paths. | 11-19-2009 |
20090291530 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa. | 11-26-2009 |
20090298236 | Integrated Module for Data Processing System - An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias. | 12-03-2009 |
20090305466 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package is provided, which can improve the quality of plating through reduction of plating deviation, and improve molding and soldering efficiencies in forming a molding compound and packaging the semiconductor package onto a printed circuit board. | 12-10-2009 |
20090317946 | METHOD FOR PROVIDING AND REMOVING DISCHARGING INTERCONNECT FOR CHIP-ON-GLASS OUTPUT LEADS AND STRUCTURES THEREOF - Microelectronic devices may be fabricated while being protected from damage by electrostatic discharge. In one embodiment, a shorting circuit is connected to elements of the microelectronic device, where the microelectronic device is part of a chip-on-glass system. In one aspect of this embodiment, a portion of the shorting circuit is in an area of a substrate where a microchip is bonded. In another embodiment, shorting links of the shorting circuit are comprised of a fusible material, where the fusible material may be disabled by an electrical current capable of fusing the shorting links. | 12-24-2009 |
20100035384 | METHODS OF FABRICATING A CIRCUIT STRUCTURE WITH A STRENGTHENING STRUCTURE OVER THE BACK SURFACE OF A CHIP LAYER - Methods of fabricating a circuit structure are provided. The fabrication method includes: forming a chip layer, which includes obtaining at least one chip and disposing a structural material around and physically contacting the side surface(s) of each chip in the chip layer. The structural material has an upper surface substantially coplanar with or parallel to an upper surface of each chip and defines at least a portion of a front surface of the chip layer, and has a lower surface substantially coplanar with or parallel to a lower surface of each chip, which defines at least portion of a back surface of the chip layer. The method further includes forming at least one strengthening structure over the back surface of the chip layer. The strengthening structure is formed to strengthen an interface between the chip(s) and the structural material. | 02-11-2010 |
20100041182 | METHOD, SYSTEM, AND APPARATUS FOR A SECURE BUS ON A PRINTED CIRCUIT BOARD - A method, apparatus, and system, the apparatus including, in some embodiments, a printed circuit board (PCB), an integrated circuit (IC) positioned over and electrically connected to the PCB, a chip positioned between the PCB and the IC, and a closed boundary barrier between and contacting the PCB and the IC to define an inner containment area that completely contains the chip within the inner containment area. | 02-18-2010 |
20100047970 | INTEGRATED CONDUCTIVE STRUCTURES AND FABRICATION METHODS THEREOF FACILITATING IMPLEMENTING A CELL PHONE OR OTHER ELECTRONIC SYSTEM - Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer. | 02-25-2010 |
20100099222 | Solder Joint Flip Chip Interconnection Having Relief Structure - A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system. | 04-22-2010 |
20100105173 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE PROVIDED WITH FLIP-CHIP MOUNTED SEMICONDUCTOR ELEMENT - A method for manufacturing a semiconductor device by mounting a semiconductor element on a circuit board, the semiconductor element having a first electrode made of a first material on a semiconductor substrate, the circuit board having a second electrode made of a second material on an insulating substrate, the method includes
| 04-29-2010 |
20100112759 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE EMBEDDED SUBSTRATE - A manufacturing method for a semiconductor device embedded substrate, includes: a first step of preparing a semiconductor device having a first insulating layer; a second step of arranging the semiconductor device on one surface of a support body; a third step of forming a second insulating layer on the one surface of the support body; a fourth step of removing the support body; a fifth step of forming a third insulating layer on a surface of each of the semiconductor device and the second insulating layer; a sixth step of mounting a wiring substrate on a surface of each of the semiconductor device and the second insulating layer; a seventh step of forming a via-hole in the second insulating layer and the third insulating layer; and an eighth step of forming a second wiring pattern on a surface of each of the first insulating layer and the second insulating layer. | 05-06-2010 |
20100120205 | MANUFACTURING METHOD OF WIRING BOARD AND SEMICONDUCTOR DEVICE - A manufacturing method of a wiring board and a semiconductor device at low cost and by a simple process, without performing complicated steps many times is proposed. Furthermore, a manufacturing method of a wiring board at low cost and with fewer adverse effects on the environment, and a manufacturing method of a semiconductor device using the wiring board are proposed. A pattern of a conductive material is formed over a first substrate, a conductive film is formed over the pattern by an electrolytic plating process, the pattern and the conductive film are separated, an IC chip including at least one thin film transistor is formed over a second substrate, and the conductive film is electrically connected to the IC chip. | 05-13-2010 |
20100129962 | ELECTRONIC PACKAGE STRUCTURE AND METHOD - An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken. | 05-27-2010 |
20100136748 | Flexible diode package and method of manufacturing - A single step packaging process that both melts a solder and also cures an adhesive about a microelectronic circuit. The process finds technical advantages by simplifying packaging of a die that may be coupled to a planar flexible lead, which leads to a lower production cost and quicker manufacturing time. The planar flexible lead may be adapted to bend and flex during mechanical stress and during extreme temperature cycling, and allow direct mounting of the device to a member by easily welding or soldering. The invention may comprise a flexible solar cell diode that can be closely positioned on solar panels at an extremely low cost. | 06-03-2010 |
20100151630 | Methods of Forming Integrated Circuit Packages, and Methods of Assembling Integrated Circuit Packages - Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages. | 06-17-2010 |
20100184257 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a method of manufacturing a semiconductor device. The method includes the successive steps of: (a) providing a semiconductor substrate; (b) forming a plurality of semiconductor chips having electrode pads on the semiconductor substrate; (c) forming internal connection terminals on the electrode pads; (d) forming an insulating layer on the plurality of semiconductor chips to cover the internal connection terminals; (e) forming a metal layer on the insulating layer; (f) pushing a whole area of the metal layer to bring the metal layer into contact with upper end portions of the internal connection terminals; (g) pushing portions of the metal layer which contact the upper end portions of the internal connection terminals, thereby forming first recesses in the internal connection terminals, and thereby forming second recesses in the metal layer; and (h) forming wiring patterns by etching the metal layer. | 07-22-2010 |
20100190298 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, and bonding the semiconductor element and the base by applying heat having a temperature of 200 to 900° C. to the semiconductor device and the base. | 07-29-2010 |
20100190299 | Semiconductor Device with Two or More Bond Pad Connections for Each Input/Output Cell and Method of Manufacture Thereof - A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least second bond pads comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least second bond pads, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component. | 07-29-2010 |
20100203680 | METHOD FOR MANUFACTURING SEMICONDUCTOR - A method for manufacturing a high quality semiconductor device having a through via structure. A substrate is manufactured with an oxide layer including a window region in a region in which a through via is formed. The substrate is bonded with another substrate to form an SOI substrate. The SOI substrate is ground to reduce its thickness. An island region is formed in a region at which a TSV (Through Silicon Via) structure is formed. A device and a TSV are coupled by a wire. The silicon substrate at a bottom side of the SOI substrate is removed to expose the island region from the bottom. A back contact for the TSV is formed in the window region, which is formed in a buried oxide layer. | 08-12-2010 |
20100210072 | Buffer coating having a physical mixture of high toughness polymer and a low shrinkage polymer - Embodiments of buffer coatings for semiconductor and integrated circuit manufacturing are presented herein. | 08-19-2010 |
20100248429 | METHOD FOR MANUFACTURING SEMICONDUCTOR MODULES - In a method for making a semiconductor module, a bump electrode and a recess are formed by etching a copper sheet. An insulating resin layer is formed, in the recess, up to a position lower than the height of the bump electrode, and then a semiconductor device and the copper sheet, including a wiring layer formed integrally with the bump electrode, are press-bonded together. The wiring layer is warped to protrude toward the semiconductor device, which assures the electrical connection between the bump electrodes and device electrodes. | 09-30-2010 |
20100273297 | CHIP PACKAGING METHOD - In a method for mounting a chip on a substrate, a plurality of grooves are defined in the substrate. A plurality of pads are formed in the grooves. A height of each of the plurality of pads is less than a depth of each corresponding groove. The chip configured with a plurality of soldering balls is positioned on the substrate with the plurality of soldering balls being received in the plurality of grooves and contacting the plurality of pads respectively. The chip is mounted onto the substrate by a melting process. | 10-28-2010 |
20100273298 | Method of Making Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers - A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of elongated parallel catalyst strips on a horizontal surface, and growing carbon nanotubes from the catalyst in the presence of a directional flow of reactant gases. | 10-28-2010 |
20100323477 | INTERCONNECTIONS OF AN INTEGRATED ELECTRONIC CIRCUIT - A method to fabricate an integrated electronic circuit includes superimposing insulating layers and metal elements distributed within said insulating layers. Each insulating layer comprises a first level within which the metal elements lie substantially in the plane of the first level, and a second level traversed by the metal elements in a direction substantially perpendicular to the plane of the second level, so as to come into contact with at least one metal element of the first level. The levels also comprise insulation zones for insulating the metal elements from each other. In one insulating layer, at least one of the levels comprises at least two insulation zones respectively realized of a first material and a second material which are different from each other. | 12-23-2010 |
20110003438 | THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURE - A method of forming a semiconductor structure includes coupling a semiconductor structure to an interconnect region through a bonding region. The interconnect region includes a conductive line in communication with the bonding region. The bonding region includes a metal layer which covers the interconnect region. The semiconductor structure is processed to form a vertically oriented semiconductor device. | 01-06-2011 |
20110014750 | CAP AND SUBSTRATE ELECTRICAL CONNECTION AT WAFER LEVEL - A cap and substrate having an electrical connection at a wafer level includes providing a substrate and forming an electrically conductive ground structure in the substrate and electrically coupled to the substrate. An electrically conductive path to the ground structure is formed in the substrate. A top cap is then provided, wherein the top cap includes an electrically conductive surface. The top cap is bonded to the substrate so that the electrically conductive surface of the top cap is electrically coupled to the path to the ground structure. | 01-20-2011 |
20110014751 | MANUFACTURING PROCESS FOR EMBEDDED SEMICONDUCTOR DEVICE - A manufacturing process for an embedded semiconductor device is provided. In the manufacturing process, at least one insulation layer and a substrate are stacked to each other, and a third metal layer is laminated on the insulation layer to embed a semiconductor device in the insulation layer. The substrate has a base, a first circuit layer, a second circuit layer, and at least a first conductive structure passing through the base and electrically connected to the first circuit layer and the second circuit layer. In addition, the third metal layer is patterned to form a third circuit layer having a plurality of third pads. | 01-20-2011 |
20110033982 | Lead-forming die and method of manufacturing semiconductor device utilizing lead-forming die - Provided is that a lead-forming die includes an upper die and a lower die disposed so as to oppose the upper die; a supporting unit for semiconductor package, provided on an upper face of the lower die; a moving unit provided on a lower face of the upper die and movable in a direction that the upper die and the lower die oppose each other; a plurality of shafts supported by the moving unit so as to axially move with respect thereto; a presser provided above the supporting unit for semiconductor package, and at a lower end portion of the shaft; and a locking device that stops a movement of the shaft, provided between the upper die and the moving unit. | 02-10-2011 |
20110033983 | SEMICONDUCTOR DEVICE - The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. | 02-10-2011 |
20110039375 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To aim at improvement of reliability of a semiconductor device of flip chip connection type. | 02-17-2011 |
20110053319 | Method for Fabricating a Circuit Substrate Assembly and a Power Electronics Module Comprising an Anchoring Structure for Producing a Changing Temperature-Stable Solder Bond - A power semiconductor module is fabricated by providing a circuit substrate with a metal surface and an insulating substrate comprising an insulation carrier featuring a bottom side provided with a bottom metallization layer. An anchoring structure is provided comprising a plurality of oblong pillars each featuring a first end facing away from the insulation carrier, at least a subset of the pillars being distributed over the anchoring structure in its entirety, it applying for each of the pillars of the subset that from a sidewall thereof no or a maximum of three elongated bonding webs each extend to a sidewall of another pillar where they are bonded thereto. The anchoring structure is positioned between the insulation carrier and metal surface, after which the metal surface is soldered to the bottom metallization layer and anchoring structure by means of a solder packing all interstices between the metal surface and bottom metallization layer with the solder. | 03-03-2011 |
20110081749 | SURFACE MODIFICATION FOR HANDLING WAFER THINNING PROCESS - A wafer is provided with a through via extending a portion of a substrate, an interconnect structure electrically connecting the through via, and a polyimide layer formed on the interconnect structure. Surface modification of the polyimide layer is the formation of a thin dielectric film on the polyimide layer by coating, plasma treatment, chemical treatment, or deposition methods. The thin dielectric film is adhered strongly to the polyimide layer, which can reduce the adhesion between the wafer surface and an adhesive layer formed in subsequent carrier attaching process. | 04-07-2011 |
20110092024 | STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips, each semiconductor chip having a first face, a second face opposite to the first face, and a circuit part. A through portion passes through the first and second faces of the semiconductor chip. A recess part is formed in a portion of the second face where the second face and the through portion meet. A through electrode is electrically connected to the circuit part and is disposed inside of the through portion. A connection member is disposed in the recess part to electrically connect the through electrodes of adjacent stacked semiconductor chips. And the semiconductor chip module is mounted to a substrate. The stacked semiconductor package prevents both gaps between semiconductor chips and misalignment of the through electrode. | 04-21-2011 |
20110092025 | IC CARD AND BOOKING-ACCOUNT SYSTEM USING THE IC CARD - It is an object of the present invention to provide a highly sophisticated functional IC card that can ensure security by preventing forgery such as changing a picture of a face, and display other images as well as the picture of a face. An IC card comprising a display device and a plurality of thin film integrated circuits; wherein driving of the display device is controlled by the plurality of thin film integrated circuits; a semiconductor element used for the plurality of thin film integrated circuits and the display device is formed by using a polycrystalline semiconductor film; the plurality of thin film integrated circuits are laminated; the display device and the plurality of thin film integrated circuits are equipped for the same printed wiring board; and the IC card has a thickness of from 0.05 mm to 1 mm. | 04-21-2011 |
20110104858 | METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT MOUNTED WIRING BOARD - A semiconductor element sealed substrate including a semiconductor element covered by an insulating layer is fabricated while a wiring substrate formed by stacking wiring layers is fabricated by a process different from the process of fabricating the semiconductor element sealed substrate. Next, the semiconductor element sealed substrate and the wiring substrate are stacked on each other in such a way that electrode terminals of the semiconductor element and corresponding conductive bumps on the outermost wiring layer face each other. The electrode terminals and the conductive bumps are thus connected to each other. | 05-05-2011 |
20110136298 | METHOD OF MANUFACTURING A WIRING BOARD - A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires. | 06-09-2011 |
20110151627 | OVERCOMING LAMINATE WARPAGE AND MISALIGNMENT IN FLIP-CHIP PACKAGES - An apparatus, system, and method are disclosed for connecting an integrated circuit device to a substrate. A plurality of standard diameter pillars and three or more increased diameter pillars are disposed on an integrated circuit device. The increased diameter pillars have a diameter that is greater than the standard diameter pillars and a height that is similar to the standard diameter pillars. The standard diameter pillars and the increased diameter pillars form a pattern on the integrated circuit device that corresponds to contact pads on a substrate opposite the integrated circuit device. A first group of solder bumps is disposed between the standard diameter pillars and the contact pads. A second group of solder bumps is disposed between the increased diameter pillars and the contact pads. The second group of solder bumps has pre-connection heights that are greater than pre-connection heights of the first group of solder bumps. | 06-23-2011 |
20110212576 | SEMICONDUCTOR HETEROSTRUCTURE NANOWIRE DEVICES - Nanowire devices comprising core-shell or segmented nanowires are provided. In these nanowire devices, strain can be used as a tool to form metallic portions in nanowires made from compound semiconductor materials, and/or to create nanowires in which embedded quantum dots experience negative hydrostatic pressure or high positive hydrostatic pressure, whereby a phase transitions may occur, and/or to create exciton crystals. | 09-01-2011 |
20110223718 | SEMICONDUCTOR DEVICE AND AUTOMOTIVE AC GENERATOR - A semiconductor device includes a semiconductor element, a support member bonded to a first surface of the semiconductor element with a first bonding material and a lead electrode bonded to a second surface of the semiconductor element supported on the support member with a second bonding material, and further including a method of producing the semiconductor device. Respective connecting parts of the support member and the lead electrode are Ni-plated and each of the first and the second bonding material is a Sn solder having a Cu | 09-15-2011 |
20110244632 | Reduction of Mechanical Stress in Metal Stacks of Sophisticated Semiconductor Devices During Die-Substrate Soldering by an Enhanced Cool Down Regime - In a reflow process for connecting a semiconductor die and a package substrate, the temperature gradient and thus the thermally induced mechanical forces in a sensitive metallization system of the semiconductor die may be reduced during the cooling phase. To this end, one or more heating intervals may be introduced into the cooling phase, thereby efficiently reducing the temperature difference. In other cases, the central region may additionally be cooled by providing appropriate locally restricted mechanisms, such as a locally restricted gas flow and the like. Consequently, desired short overall process times may be obtain without contributing to increased yield losses when processing sophisticated metallization systems on the basis of a lead-free contact regime. | 10-06-2011 |
20110269270 | STACKABLE LAYER CONTAINING BALL GRID ARRAY PACKAGE - Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package. | 11-03-2011 |
20110287586 | MEMS Switch Capping and Passivation Method - A MEMS switch with a platinum-series contact is capped through a process that also passivates the contact by controlling, over time, the amount of oxygen in the environment, pressures and temperatures. Some embodiments passivate a contact in an oxygenated atmosphere at a first temperature and pressure, before hermetically sealing the cap at a higher temperature and pressure. Some embodiments hermetically seal the cap at a temperature below which passivating dioxides will form, thus trapping oxygen within the volume defined by the cap, and later passivate the contact with the trapped oxygen at a higher temperature. | 11-24-2011 |
20110318883 | POWER SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF - A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided. | 12-29-2011 |
20120009738 | MISALIGNMENT CORRECTION FOR EMBEDDED MICROELECTRONIC DIE APPLICATIONS - The present disclosure relates to the field of integrated circuit packaging and, more particularly, to packages using embedded microelectronic die applications, such a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of alignment correction of microelectronic dice within the bumpless build-up layer packages. This alignment correction may comprise characterizing the misalignment of each microelectronic die mounted on a carrier and forwarding this characterization, along with data regarding the orientation of the carrier, to processing equipment that can compensate for the misalignment of each microelectronic die. | 01-12-2012 |
20120021565 | METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE - A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface. | 01-26-2012 |
20120088334 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE - Disclosed herein is a method for manufacturing a semiconductor package which uses a base member | 04-12-2012 |
20120088335 | MANUFACTURING METHOD OF THE ELECTRONIC COMPONENT - Manufacturing method of an electronic component including connecting one lead of a pair of leads to a surface parallel with a pn connection layer of an electronic element having a structure where the p-type layer and the n-type layer are connected by the pn connection layer provided between the p-type layer and the n-type layer, connecting another lead to another surface parallel with the pn connection layer; and forming a supporting part of the pair of the leads that is connected to and supporting the electronic element, and an electrode part functioning as an electrode, by bending the pair of the leads to an outside. | 04-12-2012 |
20120088336 | SEMICONDUCTOR PACKAGE HAVING AN IMPROVED CONNECTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package having an improved connection structure and a method for manufacturing the same is described. The semiconductor package includes a substrate having a substrate body, connection pads that are located on one surface of the substrate body, and ball lands that are located on the other surface of the substrate body opposite the one surface. The ball lands are electrically connected to the connection pads. A semiconductor chip having bumps that are formed to correspond to the connection pads is connected to the substrate. An anisotropic conductive member having an insulation element is interposed between the substrate and the semiconductor chip to connect the substrate and the semiconductor chip. Electrically flowable conductive particles within the insulation element flow in the insulation element according to applied electric fields so as to arrange the electrically flowable conductive particles between the connection pads and the bumps. | 04-12-2012 |
20120094443 | PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS - Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device. | 04-19-2012 |
20120178215 | Nitride Crystal with Removable Surface Layer and Methods of Manufacture - A nitride crystal or wafer with a removable surface layer comprises a high quality nitride base crystal, a release layer, and a high quality epitaxial layer. The release layer has a large optical absorption coefficient at wavelengths where the base crystal is substantially transparent and may be etched under conditions where the nitride base crystal and the high quality epitaxial layer are not. The high quality epitaxial layer may be removed from the nitride base crystal by laser liftoff or by chemical etching after deposition of at least one epitaxial device layer. The nitride crystal with a removable surface layer is useful as a substrate for a light emitting diode, a laser diode, a transistor, a photodetector, a solar cell, or for photoelectrochemical water splitting for hydrogen generation. | 07-12-2012 |
20120202322 | ASSEMBLY JIG FOR A SEMICONDUCTOR DEVICE AND ASSEMBLY METHOD FOR A SEMICONDUCTOR DEVICE - In aspects of the assembly jig and method of the invention, when a packaging substrate is curved concaving upward at temperatures of melting solder, the gap between the assembly jig and the packaging substrate can be made smaller than the dimension of the sum of the thickness of the semiconductor chip and the thickness of the melted solder by allowing a part of the bottom surface of the chip positioning piece to become always, or substantially always, in contact with the upper surface of the packaging substrate owing to the weight of the chip positioning jig itself. As a consequence, the semiconductor chip does not slip aside out of the opening of the chip positioning piece. Therefore, the semiconductor chip can be positioned accurately on the packaging substrate. | 08-09-2012 |
20120252167 | POTTED INTEGRATED CIRCUIT DEVICE WITH ALUMINUM CASE - An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing. | 10-04-2012 |
20120270369 | Methods for Lead Free Solder Interconnections for Integrated Circuits - Methods for forming lead free solder interconnections for integrated circuits. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of material is formed on the input/output terminal of the integrated circuit. A lead free solder connector is formed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. An intermetallic compound is formed at the interface between the cap layer and the lead free solder connector. A solder connection is formed between input/output terminal of the integrated circuit and the metal finish pad that is less than 0.5 weight percent copper, and the intermetallic compound is substantially free of copper. | 10-25-2012 |
20120282737 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate | 11-08-2012 |
20120302009 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a technology of suppressing, in forming an initial ball by using an easily oxidizable conductive wire and pressing the initial ball onto a pad to form a press-bonded ball, an initial ball from having a shape defect, thereby reducing damage to the pad. To achieve this, a ball formation unit is equipped with a gas outlet portion for discharging an antioxidant gas and a discharging path through this gas outlet portion is placed in a direction different from a direction of introducing the antioxidant gas into a ball formation portion. Such a structure widens a region for discharging the antioxidant gas, making it possible to prevent a gas flow supplied from the side of one side surface of the ball formation portion from being reflected by the other side surface facing with the one side surface and thereby forming a turbulent flow. | 11-29-2012 |
20120322210 | SEMICONDUCTOR DEVICE AND MANUFACTURING OF THE SEMICONDUCTOR DEVICE - A semiconductor device. In one embodiment the device includes a carrier. A first material is deposited on the carrier. The first material has an elastic modulus of less than 100 MPa. A semiconductor chip is placed over the first material. A second material is deposited on the semiconductor chip, the second material being electrically insulating. A metal layer is placed over the second material. | 12-20-2012 |
20130005092 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - A semiconductor package includes a base substrate, a semiconductor chip mounted on the base substrate and including bonding pads, first and second connection terminals disposed adjacent to the semiconductor chip on the base substrate and electrically connected to the bonding pads, a first ball land disposed on the base substrate and electrically connected to the first connection terminal, a second ball land spaced apart from the connection terminals, the first ball land disposed between the second ball land and at least one of the first and second connection terminals, a first insulating layer covering the first ball land but exposing at least a part of the second ball land, and a first conductive wire extending onto the first insulating layer and connecting the second connection terminal to the second ball land. | 01-03-2013 |
20130011972 | METHOD OF PRODUCING LAMINATED DEVICE - A method of producing a laminate insert package includes providing a first metal layer, printing a first dielectric layer on the first metal layer, providing a second metal layer, printing a second dielectric layer on the second metal layer, and printing a dielectric spacer layer on the first dielectric layer. At least one semiconductor chip is attached to either the first or the second metal layer. A first layer assembly comprising the first metal layer, the first dielectric layer, the dielectric spacer layer and a second layer assembly comprising the second metal layer and the second dielectric layer are brought together. The first and second layer assemblies are laminated to form a laminate insert package, whereby the at least one semiconductor chip is embedded within the laminate insert package. | 01-10-2013 |
20130034936 | STRUCTURE AND METHOD FOR POWER FIELD EFFECT TRANSISTOR - Methods for fabricating a packaged semiconductor device includes providing a metal plate having a single flat first surface and a parallel second surface. The flat first surface ending in four sawed plate sides. The plate having on the second surface at least one mesa of the same metal and a linear array of insular mesas. The at least one mesa is raised from the second surface. A single terminal of a semiconductor chip is attached to the second plate surface. | 02-07-2013 |
20130045571 | METHOD FOR FABRICATING ELECTRONIC DEVICE PACKAGE - A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed. | 02-21-2013 |
20130059420 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In regard to a semiconductor device having a multilayered wiring board where a semiconductor chip is embedded inside, a technology which allows the multilayered wiring board to be made thinner is provided. A feature of the present invention is that, in a semiconductor device where bump electrodes are formed over a main surface (element forming surface) of a semiconductor chip embedded in a chip-embedded wiring board, an insulating film is formed over a back surface (a surface on the side opposite to the main surface) of the semiconductor chip. As a result, it becomes unnecessary to form a prepreg over the back surface of the semiconductor chip. Therefore, an effect of thinning the chip-embedded wiring board in which the semiconductor chip is embedded is obtained. | 03-07-2013 |
20130084679 | METHOD FOR PRODUCING A POWER SEMICONDUCTOR ARRANGEMENT - In a method for producing a power semiconductor arrangement, a dielectric insulation carrier with a top side and a top metallization layer arranged on the top side are provided. Also provided are a semiconductor chip and at least one electrically conductive contact pin, each pin having a first end and an opposite second end. The semiconductor chip is sintered or diffussion soldered to the top metallization layer. Between the first end and the top metallization layer an electrically conductive connection is formed, in which electrically conductive connection material of the contact pin is in direct physical contact with the material of the top metallization layer. | 04-04-2013 |
20130122655 | Embedded Wafer-Level Bonding Approaches - A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer. | 05-16-2013 |
20130130445 | ACTIVE AREA BONDING COMPATIBLE HIGH CURRENT STRUCTURES - A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer. | 05-23-2013 |
20130137220 | METHOD OF MANUFACTURING GaN-BASED SEMICONDUCTOR DEVICE - A method of manufacturing a GaN-based semiconductor device includes the steps of: preparing a composite substrate including: a support substrate having a thermal expansion coefficient at a ratio of not less than 0.8 and not more than 1.2 relative to a thermal expansion coefficient of GaN; and a GaN layer bonded to the support substrate, using an ion implantation separation method; growing at least one GaN-based semiconductor layer on the GaN layer of the composite substrate; and removing the support substrate of the composite substrate by dissolving the support substrate. Thus, the method of manufacturing a GaN-based semiconductor device is provided by which GaN-based semiconductor devices having excellent characteristics can be manufactured at a high yield ratio. | 05-30-2013 |
20130143364 | METHOD OF PROCESSING SOLDER BUMP BY VACUUM ANNEALING - A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate. | 06-06-2013 |
20130143365 | Resin Sealed Semiconductor Device And Manufacturing Method Therefor - A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal is thermoplastically bonded at an area to the inside of the thermoplastic resin case. | 06-06-2013 |
20130157417 | METHOD OF MANUFACTURING SUBSTRATE FOR MOUNTING ELECTRONIC DEVICE - A method of manufacturing a substrate for mounting an electronic device, includes forming at least one through-hole in a plate-shaped substrate body in a thickness direction thereof. An electrode substrate having at least one core on an upper surface thereof is formed such that the at least one core corresponds to the at least one through-hole. The electrode substrate is coupled to the substrate body by inserting the at least one core into the at least one through-hole. A portion of the coupled electrode substrate is removed except for the at least one core. | 06-20-2013 |
20130171774 | STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced. | 07-04-2013 |
20130203218 | Method for Producing a Composite and a Power Semiconductor Module - A composite is produced by providing a first and a second joining partner, a connecting means, a sealing means, a reactor having a pressure chamber, and a heating element. The two joining partners and the connecting means are arranged in the pressure chamber such that the connecting means is situated between the first joining partner and the second joining partner. A gas-tight region is then produced, in which the connecting means is arranged. Afterward, a gas pressure of at least 20 bar is produced in the pressure chamber outside the gas-tight region. The gas pressure acts on the gas-tight region and presses the first joining partner, the second joining partner and the connecting means together. The joining partners and the connecting means are then heated by means of the heating element to a predefined maximum temperature of at least 210° C. and then cooled. | 08-08-2013 |
20130252379 | METHOD FOR MAKING HIGH-SPEED CERAMIC MODULES WITH HYBRID REFERENCING SCHEME FOR IMPROVED PERFORMANCE AND REDUCED COST - A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below and adjacent to the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas The Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines. | 09-26-2013 |
20130252380 | METHOD FOR FABRICATING PACKAGING STRUCTURE HAVING EMBEDDED SEMICONDUCTOR ELEMENT - A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate. | 09-26-2013 |
20130267066 | Semiconductor Packages and Methods of Fabricating the Same - Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a semiconductor chip having a bonding pad, a metal line electrically connected to the semiconductor chip and having a terminal contacting an external terminal, an insulation layer covering the metal line and having an opening that defines the terminal, and a molding layer molding the semiconductor chip, wherein the molding layer includes a recess pattern exposing the bonding pad and extending from the bonding pad to the terminal, and the metal line is embedded in the recess pattern to contact the bonding pad. | 10-10-2013 |
20130295722 | Method of Forming an Integrated Circuit Package Including a Direct Connect Pad, A Blind Via, and a Bond Pad Electrically Coupled to the Direct Connect Pad - A method for forming an integrated circuit package is disclosed. A flex circuit is form by forming a direct connect pad on a first side of a dielectric layer. After forming the direct connect pad, an opening from a second side of the dielectric layer is formed to expose the direct connect pad. A blind via is formed within the opening in the dielectric layer. A first conductor is formed within the opening. A bond pad of a semiconductor die is electrically coupled with the direct connect pad using a second conductor, wherein the bond pad and the second conductor directly overlie the direct connect pad. | 11-07-2013 |
20130309815 | ISOSTRESS GRID ARRAY AND METHOD OF FABRICATION THEREOF - An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate. The non-uniformity of length in the wire columns reduces stress in the package leads after attachment of the package to a carrier substrate, such as a printed circuit board. | 11-21-2013 |
20130330882 | Integrated Circuit Packages, Methods of Forming Integrated Circuit Packages, And Methods of Assembling Integrated Circuit Packages - Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages. | 12-12-2013 |
20140004660 | System and Method for Forming Uniform Rigid Interconnect Structures | 01-02-2014 |
20140004661 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 01-02-2014 |
20140045302 | Manufacturing Method of Submount - A submount and a manufacturing method thereof are provided. The submount, on which at least a semiconductor die is disposed, is mounted on a circuit board. The submount includes a substrate made of a conductive material or a semiconducting material, a plurality of conductive film patterns, and an insulating film pattern. A surface of the substrate includes a die-bonding area and a plurality of conductive areas. The conductive film patterns are individually distributed in the respective conductive areas. The insulating film pattern is disposed between the conductive film pattern and the insulating film pattern, but is not disposed in the die-bonding area. Furthermore, the semiconductor die is disposed in the die-bonding area and is electrically connected with the conductive film patterns. Because the insulating film pattern is not being disposed in the die-bonding area of the submount, the submount structure has improved heat transfer efficiency. | 02-13-2014 |
20140051212 | METHOD OF FABRICATING A PACKAGE SUBSTRATE - A method of fabricating a package substrate, includes forming a cavity in at least one region of an upper surface of a wafer, the cavity including a chip mounting region, forming a through-hole penetrating through the wafer and a via filling the through-hole, forming a first wiring layer and a second wiring layer spaced apart from the first wiring layer, which are extended into the cavity, and mounting a chip in the cavity to be connected to the first wiring layer and the second wiring layer. | 02-20-2014 |
20140065771 | DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING - Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly. | 03-06-2014 |
20140113414 | SEMICONDUCTOR MOUNTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MOUNTING DEVICE - A semiconductor mounting device including a first substrate having first insulation layers, first conductor layers formed on the first insulation layers and via conductors connecting the first conductor layers, a second substrate having a core substrate, second conductor layers, through-hole conductors and buildup layers having second insulation layers and third conductor layers, first bumps connecting the first and second substrates and formed on the outermost first conductor layer on the outermost first insulation layer, and second bumps positioned to connect a semiconductor element and formed on the outermost third conductor layer on the outermost second insulation layer. The second substrate has greater thickness than the first substrate, the second conductor layers are formed on surfaces of the core substrate, respectively, the through-hole conductors are formed through the core substrate and connecting the second conductor layers, and the buildup layers are formed on the core substrate and second conductor layers, respectively. | 04-24-2014 |
20140127863 | METHOD OF FORMING A PLURALITY OF BUMPS ON A SUBSTRATE AND METHOD OF FORMING A CHIP PACKAGE - A method of forming a plurality of bump structures on a substrate includes forming an under bump metallurgy (UBM) layer on the substrate, wherein the UBM layer contacts metal pads on the substrate. The method further includes forming a photoresist layer over the UBM layer, wherein the photoresist layer defines openings for forming the plurality of bump structures. The method further includes plating a plurality of layers in the openings, wherein the metal layers are part of the plurality of bump structures. The method further includes planarizing the plurality of bump structures after the metal layers are plated to a targeted height from a surface of the substrate. | 05-08-2014 |
20140179066 | PACKAGING STRUCTURE - A method of assembling a packaging structure is provided and includes directly electrically interconnecting respective active surfaces of first and second chips in a face-to-face arrangement, electrically interconnecting at least one of the respective sidewalls of the first and second chips to a common chip and orienting the respective active surfaces of the first and second chips transversely with respect to the common chip. | 06-26-2014 |
20140206149 | PREFORM INCLUDING A GROOVE EXTENDING TO AN EDGE OF THE PREFORM - Embodiments include but are not limited to apparatuses and systems including a die or a preform including at least one groove configured to extend from at least one via of the die to an edge of the die. Other embodiments may be described and claimed. | 07-24-2014 |
20140256090 | SELECTIVE AREA HEATING FOR 3D CHIP STACK - A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively. | 09-11-2014 |
20140256091 | METHODS FOR BONDING A DIE AND A SUBSTRATE - Embodiments of methods for forming a semiconductor device that includes a die and a substrate include pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate, and performing a bonding operation to form a die attach layer between the die and the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon. | 09-11-2014 |
20140287556 | METHODS OF FORMING BUMP AND SEMICONDUCTOR DEVICE WITH THE SAME - Provided are methods of forming a bump and a semiconductor device with the same. The method may include providing a substrate with pads, forming a bump maker layer to cover the pads and include a resin and solder particles, thermally treating the bump maker layer to aggregate the solder particles onto the pads, removing the resin to expose the aggregated solder particles, forming a resin layer to cover the aggregated solder particles, and reflowing the aggregated solder particles to form bumps on the pads. | 09-25-2014 |
20150364435 | PACKAGE METHOD - A package method comprises the steps of: providing a metal carrier having a first surface and a second surface opposite to the first surface; forming a first wiring layer on the second surface of the metal carrier; forming a first conductive pillar layer on the first wiring layer; forming a dielectric material layer covering the first wiring layer, the first conductive pillar layer and the second surface of the metal carrier; exposing one end of the first conductive pillar layer; forming a second wiring layer on the exposed end of the first conductive pillar layer; forming a solder resist layer on the dielectric material layer and the second wiring layer; removing the metal carrier. | 12-17-2015 |
20160148819 | Method for Producing a Material-Bonding Connection between a Semiconductor Chip and a Metal Layer - A method for producing a material-bonding connection between a semiconductor chip and a metal layer is disclosed. For this purpose, a semiconductor chip, a metal layer, which has a chip mounting portion, and also a bonding medium containing a metal powder are provided. The metal powder is sintered in a sintering process. In this case, throughout a prescribed sintering time, the prescribed requirements are met, that the bonding medium is arranged between the semiconductor chip and the metal layer and extends right through from the semiconductor chip to the metal layer, that the semiconductor chip and the metal layer are pressed against one another in a pressing-pressure range that lies above a minimum pressing pressure, that the bonding medium is kept in a temperature range that lies above a minimum temperature and that a sound signal is introduced into the bonding medium. | 05-26-2016 |
20160190091 | LASER ASSISTED TRANSFER WELDING PROCESS - A method of printing transferable components includes pressing a stamp including at least one transferable semiconductor component thereon on a target substrate such that the at least one transferable component and a surface of the target substrate contact opposite surfaces of a conductive eutectic layer. During pressing of the stamp on the target substrate, the at least one transferable component is exposed to electromagnetic radiation that is directed through the transfer stamp to reflow the eutectic layer. The stamp is then separated from the target substrate to delaminate the at least one transferable component from the stamp and print the at least one transferable component onto the surface of the target substrate. Related systems and methods are also discussed. | 06-30-2016 |