Entries |
Document | Title | Date |
20080241969 | In-line lithography and etch system - The invention can provide a method of processing a wafer using Site-Dependent (S-D) processing sequences that can include S-D creation procedures, S-D evaluation procedures, and S-D transfer sequences. The S-D creation procedures can be performed using S-D processing elements, the S-D evaluation procedures can be performed using S-D evaluation elements, and S-D transfer sequences can be performed using site-dependent transfer subsystems. Site-dependent data can be stored in site-dependent libraries and/or databases. | 10-02-2008 |
20080241970 | Method and apparatus for performing a site-dependent dual damascene procedure - The present invention includes a method of performing a dual damascene procedure using Site-Dependent (S-D) procedures, the method including receiving a plurality of wafers and associated data by a S-D transfer subsystem coupled to a lithography-related subsystem, determining S-D wafer data for each wafer, establishing a first Dual Damascene processing sequence, determining a first set of S-D processing wafers to be processed, establishing real-time operational states for a plurality of first S-D processing elements in the lithography-related subsystem, transferring a first number of the first set of S-D processing wafers to a first number of the first S-D processing elements in the lithography-related subsystem and delaying other S-D wafers in the first set of S-D processing wafers for a first amount of time. | 10-02-2008 |
20080241971 | Method and apparatus for performing a site-dependent dual patterning procedure - The present invention includes a method of performing a double-patterning (DP) processing sequence using a plurality of Site-Dependent (S-D) procedures, the method including receiving a first set of wafers by one or more subsystems in a processing system, creating one or more first patterned layers on a first set of patterned wafers, establishing first confidence data for the first set of patterned wafers, establishing a first set of high confidence wafers, creating one or more second patterned layers on a second set of patterned wafers, establishing second confidence data for the second set of patterned wafers and establishing a second set of high confidence wafers. | 10-02-2008 |
20080248597 | Methods for determining a dose of an impurity implanted in a semiconductor substrate and an apparatus for same - Methods of determining a total impurity dose for a plasma doping process, and an apparatus configured to determine same. A total ion dose implanted in a semiconductor substrate is directly measured, such as by utilizing a Faraday cup. A ratio of impurity-based ion species to non-impurity-based ion species in a plasma generated by the plasma doping process and a ratio of each impurity-based ion species to a total impurity-based ion species in the plasma are directly measured. The ratios may be directly measured by ion mass spectroscopy. The total ion dose and the ratios are used to determine the total impurity dose. The apparatus includes an ion detector, an ion mass spectrometer, a dosimeter, and software. | 10-09-2008 |
20080280379 | METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE AND MANUFACTURING SYSTEM USING THE SAME - Provided is a method of manufacturing a thin film transistor substrate and a manufacturing system using the same, wherein the production of corrosive substances is reduced during the process of manufacturing the thin film transistor substrate. The method includes providing an etching unit with an insulation substrate on which a thin metal film has been deposited, and dry-etching the insulation substrate so as to form a predetermined circuit pattern; providing a waiting unit with the insulation substrate waiting to be cleaned; performing a preliminary cleaning operation by a cleaning unit having a plurality of nozzles while the insulation substrate waits and checking the preliminary cleaning operation; and performing a main cleaning operation with regard to the insulation substrate based on the result of the check. | 11-13-2008 |
20080318344 | INDICATION OF THE END-POINT REACTION BETWEEN XeF2 AND MOLYBDENUM - Embodiments of the present invention relate to methods and systems for making a microelectromechanical system comprising supplying an etchant to etch one or more sacrificial structures of the system. | 12-25-2008 |
20090004761 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units | 01-01-2009 |
20090011523 | Processing method and processing apparatus - A processing method of subjecting at least two stacked films, which comprise a first film and a second film of a target object to be processed, to a removing process by wet etching comprises bringing a first process liquid into contact with the first film of the target object, thereby etching the first film, determining whether the first film has been removed or not, switching the first process liquid to a second process liquid differing in a condition from the first process liquid when it has been determined that the first film has been removed, and bringing the second process liquid into contact with the second film, thereby etching the second film. | 01-08-2009 |
20090029486 | Substrate Processing Apparatus and Substrate Processing Method - A substrate processing apparatus has: a process chamber in which a substrate is processed; a heating device that optically heats the substrate accommodated in the process chamber from an outer periphery side of the substrate; a cooling device that cools the outer periphery side of the substrate by flowing a fluid in a vicinity of an outer periphery of the substrate optically heated by the heating device; a temperature detection portion that detects a temperature inside the process chamber; and a heating control portion that controls the heating device and the cooling device in such a manner so as to provide a temperature difference between a center portion of the substrate and an end portion of the substrate while maintaining a temperature at the center portion at a pre-determined temperature according to the temperature detected by the temperature detection portion. | 01-29-2009 |
20090029487 | SEMICONDUCTOR PRODUCTION METHOD AND SEMICONDUCTOR PRODUCTION DEVICE - The objective of the present invention is to prevent the variation in an ashing rate according to a temporal change within an ashing chamber. Then, in order to maintain the ashing rate, the decrease in the number of oxygen atoms in ashing gas within a process chamber | 01-29-2009 |
20090029488 | Soldering method for mounting semiconductor device on wiring board to ensure invariable gap therebetween, and soldering apparatus therefor - In a soldering method for mounting a semiconductor device on a wiring board, a plurality of solid-phase solders are provided between the semiconductor device and the wiring board, and are thermally melted to thereby produce a plurality of liquid-phase solders therebetween. A constant force is exerted on the liquid-phase solders by relatively moving the semiconductor device with respect to the wiring board so that an invariable gap is determined between the semiconductor device and the wiring board. | 01-29-2009 |
20090042320 | METHODS FOR LIQUID TRANSFER COATING OF THREE-DIMENSIONAL SUBSTRATES - Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate. Additional features may include filling the micro cavities of the substrate with a filling material, removing the filling material to expose only the substrate surfaces to be coated, coating the substrate with a layer of liquid coating material, and removing said filling material from the micro cavities of the substrate. | 02-12-2009 |
20090061539 | Substrate holding structure and method of producing semiconductor device using the same - A substrate holding structure includes a wafer stage having a first main surface and a second main surface opposite to the first main surface. A substrate placing area is defined on the first main surface. The substrate holding structure further includes a static capacity measurement electrode having a center circular electrode and at least one circular ring electrode for measuring a combined capacity among a substrate to be placed in the substrate placing area, the center circular electrode, and the circular ring electrode; at least one temperature measurement unit; an electrode control unit connected to the center circular electrode and the circular ring electrode; a temperature control unit connected to the temperature measurement unit and the temperature adjustment unit; a storage unit; a calculation unit connected to the storage unit; and a control unit connected to the electrode control unit and the temperature control unit. | 03-05-2009 |
20090068765 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes performing positioning between a transfer position of a pattern forming surface of a transfer original plate on which a pattern to be transferred is formed and a transferred position of a transferred surface of a transferred substrate to which the pattern is to be transferred; contacting the pattern forming surface with the transferred surface; and partly correcting the positional deviation between the transfer position of the pattern forming surface and the transferred position of the transferred surface in the in-plane direction, after the positioning is performed. | 03-12-2009 |
20090081810 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus has a fluid supply means | 03-26-2009 |
20090081811 | DISTRIBUTED POWER ARRANGEMENTS FOR LOCALIZING POWER DELIVERY - A distributed power arrangement to provide local power delivery in a plasma processing system during substrate processing is provided. The distributed power arrangement includes a set of direct current (DC) power supply units. The distributed power arrangement also includes a plurality of power generators, which is configured to receive power from the set of DC power supply units. Each power generator of the plurality of power generators is coupled to a set of electrical elements, thereby enabling the each power generator of the plurality of power generators to control the local power delivery. | 03-26-2009 |
20090130780 | SEMICONDUCTOR PROCESSING SYSTEM AND METHOD OF PROCESSING A SEMICONDUCTOR WAFER - A method of processing semiconductor wafers includes applying reactive gas through a plurality of inlets to the semiconductor wafers. The method further includes removing exhaust gas resulting from the step of applying reactive gas. The removing of the exhaust gas is through a plurality of outlets coupled to a manifold. The manifold combines the exhaust gas from the plurality of outlets. The method further includes measuring a pressure in each outlet of the plurality of outlets during the step of removing. | 05-21-2009 |
20090130781 | METHOD FOR SIMULTANEOUSLY PRODUCING MULTIPLE WAFERS DURING A SINGLE EPITAXIAL GROWTH RUN AND SEMICONDUCTOR STRUCTURE GROWN THEREBY - HVPE method for simultaneously fabricating multiple Group III nitride semiconductor structures during a single reactor run. A HVPE reactor includes a reactor tube, a growth zone, a heating element and a plurality of gas blocks. A substrate holder is capable of holding multiple substrates and can be a single or multi-level substrate holder. The gas delivery blocks are independently controllable. Gas flows from the delivery blocks are mixed to provide a substantially uniform gas environment within the growth zone. The substrate holder can be controlled, e.g., rotated and/or tilted, for uniform material growth. Multiple Group III nitride semiconductor structures can be grown on each substrate during a single fabrication run of the HVPE reactor. Growth on different substrates is substantially uniform and can be performed on larger area substrates, such as 3-12″ substrates. | 05-21-2009 |
20090142858 | Power-Measured Pulses for Thermal Trimming - A circuit for trimming a thermally-trimmable resistor, measuring a temperature coefficient of resistance of the thermally-trimmable resistor, and annealing a thermally-trimmable resistor post-trimming, the circuit comprising: a thermally-isolated area on a substrate housing the thermally-trimmable resistor; heating circuitry for applying a signal to a heating resistor; and a constant-power module adapted to maintain power dissipated in the heating resistor substantially constant over a duration of the signal by varying at least one parameter of the signal as a result of a change in resistance of the heating resistor during the signal. | 06-04-2009 |
20090148963 | Metal Wiring and Method of Manufacturing the Same, and Metal Wiring Substrate and Method of Manufacturing the Same - A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle α in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate. | 06-11-2009 |
20090162950 | DRY ETCHING EQUIPMENT AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A dry etching equipment includes a topography simulator and a control section. The topography simulator controls an amount of deposition species incident upon a sidewall to be processed in accordance with a wafer opening ratio and a solid angle of a local pattern, the deposition amount being represented by a product of a reaction product flux and the solid angle. The control section compares a database obtained by the topography simulator with an actual measured value detected from an etching condition during dry etching to calculate a correction value for etching process, and indicates the correction value to an etching chamber in the dry etching equipment. The dry etching equipment corrects in real time a parameter for the etching process conducted in the etching chamber. | 06-25-2009 |
20090186424 | PATTERN GENERATION METHOD, COMPUTER-READABLE RECORDING MEDIUM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A pattern generation method includes: acquiring a first design constraint for first patterns to be formed on a process target film by a first process, the first design constraint using, as indices, a pattern width of an arbitrary one of the first patterns, and a space between the arbitrary pattern and a pattern adjacent to the arbitrary pattern; correcting the first design constraint in accordance with pattern conversion by the second process, and thereby acquiring a second design constraint for the second pattern which uses, as indices, two patterns on both sides of a predetermined pattern space of the second pattern; judging whether the design pattern fulfils the second design constraint; and changing the design pattern so as to correspond to a value allowed by the second design constraint when the design constraint is not fulfilled. | 07-23-2009 |
20090197351 | LASER PROCESSING METHOD - In a laser beam processing method, when a laser beam is emitted along a second predetermined dividing line to form a second groove intersecting a first groove previously formed, the power output of the laser beam is allowed to be a first power output in a first interval, that is, until the second predetermined dividing line reaches a position immediately before the first groove. In a second interval from the position close to the first groove to the first groove reached by the second predetermined dividing line, the power output of the laser beam is set to a second power output lower than the first power output. Thus, overheat on the periphery of the second interval can be suppressed. | 08-06-2009 |
20090197352 | Substrate processing method and film forming method - A substrate processing method in a processing chamber, has: accommodating a substrate into a processing chamber; and processing the substrate in the processing chamber on the basis of a correlation of a preset temperature of a heating device, a flow rate of fluid supplied by a cooling device and a temperature deviation between the center side of the substrate accommodated in the processing chamber and the outer peripheral side of the substrate while the substrate accommodated in the processing chamber is optically heated from an outer periphery side of the substrate at a corrected preset temperature by the heating device and the fluid is supplied to the outside of the processing chamber at the flow rate based on the correlation concerned to cool the outer peripheral side of the substrate by the cooling device. | 08-06-2009 |
20090215201 | METHOD FOR CONTROLLING SPATIAL TEMPERATURE DISTRIBUTION ACROSS A SEMICONDUCTOR WAFER - A chuck for a plasma processor comprises a temperature-controlled base, a thermal insulator, a flat support, and a heater. The temperature-controlled base is controlled in operation a temperature below the desired temperature of a workpiece. The thermal insulator is disposed over at least a portion of the temperature-controlled base. The flat support holds a workpiece and is disposed over the thermal insulator. A heater is embedded within the flat support and/or mounted to an underside of the flat support. The heater includes a plurality of heating elements that heat a plurality of corresponding heating zones. The power supplied and/or temperature of each heating element is controlled independently. The heater and flat support have a combined temperature rate change of at least 1° C. per second. | 08-27-2009 |
20090239313 | Integrated Circuit Chip Design Flow Methodology Including Insertion of On-Chip or Scribe Line Wireless Process Monitoring and Feedback Circuitry - Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring circuitry. These embodiments use a library of pre-qualified intra-process monitoring circuits and a cross-correlation table that links different monitoring circuits with different IC chip components. Specifically, these embodiments analyze integrated circuit chip design data to identify the components designed into the chip. Then, one or more intra-process monitoring circuits are selected from the library and the design data is modified to include the selected monitoring circuit(s). | 09-24-2009 |
20090253221 | METHOD OF MEASURING NITROGEN CONTENT, METHOD OF FORMING SILICON OXYNITRIDE FILM AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The total film thickness T1N of silicon oxynitride film and silicon oxide film remaining as its underlying layer is measured. A measurement target substrate is re-oxidized, and, after the re-oxidization, the total film thickness (T2N) of the silicon oxynitride film, silicon oxide film and silicon oxide film resulting from the re-oxidization on the target substrate is measured. Separately, a reference substrate provided with silicon oxide film is re-oxidized, and, after the re-oxidization, the total film thickness T2 of the silicon oxide film and silicon oxide film resulting from the re-oxidization on the reference substrate is measured. Re-oxidization rate reduction ratio RORR of the measurement target substrate is calculated by the following formula (1) from the values of total film thicknesses T1N, T2N and T2. The nitrogen concentration of the silicon oxynitride film of the target substrate is determined from the calculated re-oxidization rate reduction ratio RORR. RORR (%)={(T2−T2N)/(T2−T1N)}×100 (1). | 10-08-2009 |
20090258444 | APPARATUS AND METHODS FOR MANUFACTURING THIN-FILM SOLAR CELLS - Improved methods and apparatus for forming thin-film layers of semiconductor material absorber layers on a substrate web. According to the present teachings, a semiconductor layer may be formed in a multi-zone process whereby various layers are deposited sequentially onto a moving substrate web. | 10-15-2009 |
20090263919 | PLASMA OXIDATION PROCESSING METHOD - A plasma oxidation process is performed to form a silicon oxide film on the surface of a target object by use of plasma with an O( | 10-22-2009 |
20090269861 | Device and method for manufacturing a semiconductor wafer - In order to manufacture an epitaxial wafer having satisfactory flatness over its entire surface, epitaxial layers are experimentally grown upon actual wafer samples under various different layer formation conditions, the thickness profiles are measured over the entire surfaces of these wafers before and after growth of the layers, and, from the differences thereof, layer thickness profiles over the entire areas of the epitaxial layers under the various different layer formation conditions are ascertained and stored. Thereafter, the thickness profile of a substrate wafer is measured over its entire area, this is added to each of the layer thickness profiles under the various different layer formation conditions which have been stored, and the planarities of the manufactured wafers which would be manufactured under these various different layer formation conditions are predicted. And one set of processing conditions is selected which is predicted to satisfy a required flatness specification, and an epitaxial layer is actually grown upon the substrate wafer under these processing conditions. | 10-29-2009 |
20090275149 | METHODS AND SYSTEMS FOR CONTROLLING CRITICAL DIMENSIONS IN TRACK LITHOGRAPHY TOOLS - A method of controlling wafer critical dimension (CD) uniformity on a track lithography tool includes obtaining a CD map for a wafer. The CD map includes a plurality of CD data points correlated with a multi-zone heater geometry map. The multi-zone heater includes a plurality of heater zones. The method also includes determining a CD value for a first heater zone of the plurality of heater zones based on one or more of the CD data points and computing a difference between the determined CD value for the first heater zone and a target CD value for the first heater zone. The method further includes determining a temperature variation for the first heater zone based, in part, on the computed difference and a temperature sensitivity of a photoresist deposited on the wafer and modifying a temperature of the first heater zone based, in part, on the temperature variation. | 11-05-2009 |
20090275150 | FILM FORMATION APPARATUS AND METHOD FOR SEMICONDUCTOR PROCESS - A film formation apparatus for a semiconductor process includes a source gas supply circuit to supply into a process container a source gas for depositing a thin film on target substrates, and a mixture gas supply circuit to supply into the process container a mixture gas containing a doping gas for doping the thin film with an impurity and a dilution gas for diluting the doping gas. The mixture gas supply circuit includes a gas mixture tank disposed outside the process container to mix the doping gas with the dilution gas to form the mixture gas, a mixture gas supply line to supply the mixture gas from the gas mixture tank into the process container, a doping gas supply circuit to supply the doping gas into the gas mixture tank, and a dilution gas supply circuit to supply the dilution gas into the gas mixture tank. | 11-05-2009 |
20090280579 | METHOD OF CONTROLLING EMBEDDED MATERIAL/GATE PROXIMITY - A method that includes forming a gate of a semiconductor device on a substrate and forming a recess for an embedded silicon-straining material in source and drain regions for the gate. In this method, a proximity value, which is defined as a distance between the gate and a closest edge of the recess, is controlled by controlling formation of an oxide layer provided beneath the gate. The method can also include feedforward control of process steps in the formation of the recess based upon values measured during the formation of the recess. The method can also apply feedback control to adjust a subsequent recess formation process performed on a subsequent semiconductor device based on the comparison between a measured proximity value and a target proximity value to decrease a difference between a proximity value of the subsequent semiconductor device and the target proximity value. | 11-12-2009 |
20090286331 | METHOD FOR SIMULATENOUSLY PRODUCING MULTIPLE WAFERS DURING A SINGLE EPITAXIAL GROWTH RUN AND SEMICONDUCTOR STRUCTURE GROWN THEREBY - HVPE method for simultaneously fabricating multiple Group III nitride semiconductor structures during a single reactor run. A HVPE reactor includes a reactor tube, a growth zone, a heating element and a plurality of gas blocks. A substrate holder is capable of holding multiple substrates and can be a single or multi-level substrate holder. The gas delivery blocks are independently controllable. Gas flows from the delivery blocks are mixed to provide a substantially uniform gas environment within the growth zone. The substrate holder can be controlled, e.g., rotated and/or tilted, for uniform material growth. Multiple Group III nitride semiconductor structures can be grown on each substrate during a single fabrication run of the HVPE reactor. Growth on different substrates is substantially uniform and can be performed on larger area substrates, such as 3-12″ substrates. | 11-19-2009 |
20090311807 | THERMAL PROCESSING APPARATUS AND THERMAL PROCESSING METHOD FOR OBJECT TO BE PROCESSED - The present invention is a thermal processing apparatus comprising: a processing vessel capable of being evacuated, the processing vessel also being capable of accommodating, in addition to a plurality of objects, an object for temperature measurement equipped with an elastic wave device; a holding unit configured to be loaded into and unloaded from the processing vessel, while the holding unit holding the plurality of objects to be processed and the object for temperature measurement; a gas introduction unit configured to introduce a gas into the processing vessel; a heating unit configured to heat the plurality of objects to be processed and the object for temperature measurement that are accommodated in the processing vessel; a first conductive member configured to function as a transmitter antenna connected to a transmitter through a radiofrequency line, for transmitting an electric wave for measurement toward the elastic wave device accommodated in the processing vessel; a second conductive member configured to function as a receiver antenna connected to a receiver through a radiofrequency line, for receiving an electric wave dependent on a temperature of the elastic wave device which is emitted from the elastic wave device accommodated in the processing vessel; a temperature analysis part configured to obtain a temperature of the object for temperature measurement based on the electric wave received by the receiver antenna; and a temperature control part configured to control the heating unit; wherein: the first conductive member is disposed as a part of a thermal processing part in the processing vessel; and the second conductive member is disposed as a part of a thermal processing part in the processing vessel. | 12-17-2009 |
20090317924 | METHOD FOR OPTIMIZING THE ROUTING OF WAFERS/LOTS BASED ON YIELD - A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from tools processing the wafers or wafer lots. A system for increasing overall yield in semiconductor manufacturing includes a module for routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from the tools processing the wafers or wafer lots. | 12-24-2009 |
20100003769 | METHOD RELATING TO THE ACCURATE POSITIONING OF A SEMICONDUCTOR WAFER - Disclosed is a method involving repeatedly measuring a pressure within a flow of processing gas that is provided in a semiconductor processing apparatus for treatment of a semiconductor substrate, such as a semiconductor wafer. The flow of processing gas is made to extend between a surface of the substrate and a surface of a processing body. From the pressure measurements the occurrence of an event that is related to a variation in the position of the substrate's surface relative to the surface of the processing body is determined. | 01-07-2010 |
20100003770 | ELEMENTAL ANALYSIS METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Protons are entered into a substrate to be analyzed at a proton incident angle larger than 0° and smaller 90°. Excited by the entered protons and emitted from the substrate to be analyzed, the characteristic X-ray is measured by an energy dispersive X-ray detector and the like. Impurity elements present in the substrate to be analyzed are identified based on the measured characteristic X-ray. The in-plane distribution in the substrate can be obtained by scanning the proton beam. The in-depth distribution can be obtained by entering protons at different proton incident angles. The elemental analysis method can be applied to semiconductor device manufacturing processes to analyze metal contamination or quantify a conductivity determining impurity element on an inline basis and with a high degree of accuracy. | 01-07-2010 |
20100009468 | METHOD OF MANUFACTURE FOR SEMICONDUCTOR PACKAGE WITH FLOW CONTROLLER - A semiconductor package can comprise a die stack attached to a substrate, with bond wires electrically connecting the two. Often multiple die stacks are adhered to a single substrate so that several semiconductor packages can be manufactured at once. A molding compound flow controller is optimally associated with the substrate or semiconductor package at one or more various locations. Flow controllers can control or direct the flow of the molding compound during the encapsulation process. Flow controllers can be sized, shaped, and positioned in order to smooth out the flow of the molding compound, such that the speed of the flow is substantially equivalent over areas of the substrate containing dies and over areas of the substrate without dies. In this manner, defects such as voids in the encapsulation, wire sweeping, and wire shorts can be substantially avoided during encapsulation. | 01-14-2010 |
20100015733 | METHOD AND DEVICE FOR MONITORING A HEAT TREATMENT OF A MICROTECHNOLOGICAL SUBSTRATE - A method of monitoring a heat treatment of a microtechnological substrate includes placement of the substrate to be treated in a heating zone and applying a heat treatment to the substrate, under predetermined temperature conditions, while monitoring the change over the course of time in the vibratory state of the substrate, and detecting a fracture in the substrate by detecting a peak characteristic in the vibratory state over the course of time. | 01-21-2010 |
20100035366 | Production of VDMOS-Transistors Having Optimized Gate Contact - The invention relates to a method for producing VDMOS transistors in which a specific layer arrangement and a specific method sequence allow setting up an improved gate contact when simultaneously producing source and gate contacts using a single contact hole mask (photo mask). | 02-11-2010 |
20100047932 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING PROGRAM, AND COMPUTER READABLE RECORDING MEDIUM HAVING SUBSTRATE PROCESSING PROGRAM THEREIN - Disclosed is a substrate processing apparatus to supply processing liquid having a predetermined flow rate and concentration to a substrate processing unit of the substrate processing apparatus with high accuracy. The substrate processing apparatus processes substrates in a plurality of substrate processing units by using the processing liquid supplied from a processing liquid supply part. If the flow rate of the processing liquid simultaneously used by the substrate processing units is less than a control flow rate that is controllable at the processing liquid supply part, the processing liquid is supplied from the processing liquid supply part such that the flow rate of the processing liquid is substantially identical to the control flow rate. If the flow rate of the processing liquid simultaneously used by the substrate processing units is substantially identical to the control flow rate that is controllable at the processing liquid supply part, the processing liquid having the flow rate simultaneously used by the substrate processing units is supplied from the processing liquid supply part. | 02-25-2010 |
20100062546 | METHOD OF MANUFACTURING SOI SUBSTRATE - An object of the present invention is to improve use efficiency of a semiconductor substrate without lowering efficiency of a fabrication process. Another object of the present invention is to achieve cost reduction by effective use of a semiconductor substrate whose thickness is reduced due to repeated use in a process of manufacturing an SOI substrate. In a process of manufacturing an SOI substrate, a semiconductor substrate is used as a bond substrate a predetermined number of times, or as long as it meets predetermined conditions. In a case where a first single crystal semiconductor substrate cannot be used as a bond substrate, it is bonded to a second single crystal semiconductor substrate. Then, a stacked-layer substrate formed from the first single crystal semiconductor substrate and the second single crystal semiconductor substrate bonded to each other is used as a bond substrate in a process of manufacturing an SOI substrate. | 03-11-2010 |
20100062547 | TECHNIQUE FOR MONITORING AND CONTROLLING A PLASMA PROCESS WITH AN ION MOBILITY SPECTROMETER - A plasma processing apparatus includes a process chamber, a platen positioned in the process chamber for supporting a workpiece, a source configured to generate a plasma in the process chamber, and a monitoring system including an ion mobility spectrometer configured to monitor a condition of the plasma. A monitoring method including generating a plasma in a process chamber of a plasma processing apparatus, supporting a workpiece on a platen in the process chamber, and monitoring a condition of the plasma with an ion mobility spectrometer is also provided. | 03-11-2010 |
20100081217 | DEFECT INSPECTION APPARATUS, DEFECT INSPECTION METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A defect inspection method includes generating and applies a charged beam to a sample with patterns; controlling a shape of the charged beam so that a beam width in a first direction perpendicular to an optical axis differs from a beam width in a second direction perpendicular to the optical axis and the first direction, while substantially maintaining a cross-sectional area of the beam; scanning the sample with the charged beam having the controlled shape; and detecting charged particles from the sample by irradiation of the charged beam and detects a defect of the patterns. Assuming that the beam width of the charged beam in the first direction is smaller than that in the second direction, the first direction is set to a direction in which an interval between adjacent patterns becomes a minimum value and the sample is scanned in the second direction. | 04-01-2010 |
20100093111 | METHOD FOR MANUFACTURING ELECTRONIC DEVICE USING PLASMA REACTOR PROCESSING SYSTEM - To enable change of a concentration of atmosphere in a process chamber and realize a plasma reaction process required for manufacturing a liquid crystal device and a semiconductor device with a high yield at a low cost. | 04-15-2010 |
20100105153 | METHOD FOR MEASURING EXPANSION/CONTRACTION, METHOD FOR PROCESSING SUBSTRATE, METHOD FOR PRODUCING DEVICE, APPARATUS FOR MEASURING EXPANSION/CONTRACTION, AND APPARATUS FOR PROCESSING SUBSTRATE - An expansion/contraction measuring apparatus includes a transport section which transports a flexible substrate along a surface of the substrate; a detecting section detecting first and second marks which are formed on the substrate while being separated from each other by a predetermined spacing distance in a transport direction of the substrate and which are moved, in accordance with the transport of the substrate, to first and second detection areas disposed on a transport route for the substrate respectively; a substrate length setting section which sets a length of the substrate along the transport route between the first and second detection areas to a reference length; and a deriving section which derives information about expansion/contraction of the substrate in relation to the transport direction based on a detection result of the first and second marks. Accordingly, the expansion/contraction state of an expandable/contractible substrate is measured highly accurately. | 04-29-2010 |
20100112729 | CONTACT PATTERNING METHOD WITH TRANSITION ETCH FEEDBACK - A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole. | 05-06-2010 |
20100136714 | Device for processing substrate and method of manufacturing semiconductor device - Provided is a substrate processing apparatus and a method of manufacturing a semiconductor device, which are hard to cause a defect in processing a substrate owing to that a pressure inside a process chamber is not kept constant, and which enable a better processing of a substrate. The substrate processing apparatus has: a process chamber for processing a substrate; a reactive gas-supplying module for supplying a reactive gas into the process chamber; a reactive gas-supplying line for supplying the reactive gas from the reactive gas-supplying module into the process chamber; an exhaust line for exhausting an inside of the process chamber; a pump provided in the exhaust line for vacuumizing the inside of the process chamber; a pressure-adjusting valve provided in the exhaust line for adjusting a pressure in the process chamber; a first pressure-measuring instrument for measuring an inside pressure of the process chamber; a second pressure-measuring instrument for measuring a differential pressure between the inside pressure of the process chamber and an outside pressure thereof; and a controller which controls the pressure-adjusting valve based on a value of the inside pressure of the process chamber measured by the first pressure-measuring instrument so as to keep the inside pressure of the process chamber constant, and controls the reactive gas-supplying module based on a value of the differential pressure measured by the second pressure-measuring instrument so as to allow supply of the reactive gas into the process chamber in a case of the inside pressure of the process chamber being smaller than the outside pressure thereof, and so as to preclude supply of the reactive gas into the process chamber in a case of the inside pressure of the process chamber being larger than the outside pressure thereof when processing the substrate. | 06-03-2010 |
20100167424 | VARIABLE THICKNESS SINGLE MASK ETCH PROCESS - The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semiconductor body (e.g., wafer). An etch mask layer (e.g., photoresist) is then formed above the adjustable film layer and is selectively patterned by a reticleless exposure system (e.g., DMD exposure system). The selective patterning subjects different regions of the etch mask layer to varying exposure times dependent upon the thickness of the underlying adjustable film. The more etching needed to provide the underlying film to a nominal thickness, the longer the exposure of the etch mask. Therefore, the resultant etch mask, after exposure, comprises a topology allowing for various degrees of selective etching of the underlying film resulting in a uniform film. | 07-01-2010 |
20100167425 | METHOD OF PRODUCING BONDED SILICON WAFER - A bonded silicon wafer is produced by a method comprising a step of implanting oxygen ions from one surface of a silicon wafer for active layer to form an oxygen ion implanted layer, a step of bonding the one surface of the silicon wafer for active layer to one surface of a silicon wafer for support layer and then conducting a heat treatment for strengthening the bonding to form a silicon wafer composite, a step of polishing a silicon portion at a side of the silicon wafer for active layer in the silicon wafer composite on a rotating platen having a polishing means and stopping the polishing at a time of detecting change of physical properties on the rotating platen resulting from the exposure of at least a part of the oxygen ion implanted layer and a step of removing the oxygen ion implanted layer. | 07-01-2010 |
20100167426 | PLASMA ETCHING APPARATUS AND PLASMA ETCHING METHOD - The invention provides a method for overcoming the drawbacks of deteriorated throughput, deteriorated reproducibility and plasma discharge instability when continuous discharge is performed during multiple steps of plasma etching. The present invention provides a gas switching method for switching from gas supply source | 07-01-2010 |
20100197047 | METHOD FOR MANUFACTURING SIMOX WAFER - At oxygen ion implanting steps in manufacture of a SIMOX wafer, a path is formed inside or on a back surface of wafer holding means, and oxygen ions are implanted while heating an outer peripheral portion of the wafer that is in contact with the wafer holding means by flowing a heated fluid through this path. An in-plane temperature of a wafer held at the time of ion implantation is prevented from becoming uneven, and in-plane film thicknesses of both an SOI layer and a BOX layer are uniformed. | 08-05-2010 |
20100197048 | METHOD OF PRODUCING SEMICONDUCTOR - In a conventional SGT production method, during dry etching for forming a pillar-shaped silicon layer and a gate electrode, an etching amount cannot be controlled using an end-point detection process, which causes difficulty in producing an SGT while stabilizing a height dimension of the pillar-shaped silicon layer, and a gate length. In an SGT production method of the present invention, a hard mask for use in dry etching for forming a pillar-shaped silicon layer is formed in a layered structure comprising a first hard mask and a second hard mask, to allow the end-point detection process to be used during the dry etching for the pillar-shaped silicon layer. In addition, a gate conductive film for use in dry etching for forming a gate electrode is formed in a layered structure comprising a first gate conductive film and a second gate conductive film, to allow the end-point detection process to be used during the dry etching for the gate electrode. | 08-05-2010 |
20100221849 | METHOD AND SYSTEM FOR CONTROLLING AN IMPLANTATION PROCESS - A method for implant uniformity is provided that includes determining a variation of critical dimensions (CD) of a semiconductor wafer, moving the semiconductor wafer in a two-dimensional mode during an implantation process, and controlling a velocity of the movement of the semiconductor wafer so that an implant dose to the semiconductor wafer is varied based on the variation of CD. | 09-02-2010 |
20100240154 | TEMPERATURE CONTROL DEVICE, TEMPERATURE CONTROL METHOD, AND SUBSTRATE PROCESSING APPARATUS - Provided is a temperature control device for controlling a temperature of a member to be exposed to plasma in a substrate processing apparatus. The substrate processing apparatus includes a mounting electrode for mounting a target substrate and a facing electrode positioned to face the mounting electrode, excites a processing gas supplied between the mounting electrode and the facing electrode into plasma, and performs a plasma process on the target substrate with the plasma. The temperature control device includes a heating layer configured to heat a heating target member, a heat insulating layer positioned in contact with an opposite surface to a heating layer's surface facing the heating target member, and a cooling layer positioned in contact with an opposite surface to a heat insulating layer's surface facing the heating layer. | 09-23-2010 |
20100248396 | HEAT TREATMENT APPARATUS AND CONTROL METHOD THEREFOR - A heat treatment apparatus includes a processing chamber having a gate valve at a sidewall and a cover at a ceiling via a sealing member; a gate valve heating unit provided at the gate valve; a processing chamber heating unit provided at a sidewall of the processing chamber; and a temperature controller that controls a set temperature for the sidewall of the processing chamber adjacent to the gate valve to be lower than a set temperature for an opposite sidewall of the processing chamber from the gate valve by controlling the processing chamber heating unit. The two set temperatures are set to be higher than a sublimation temperature of a reaction by-product, or higher than a condensation temperature of the gas, and the two set temperatures are also set to be lower than a temperature at which an amount of a gas permeating the sealing member increases. | 09-30-2010 |
20100273277 | RAPID THERMAL PROCESSING SYSTEMS AND METHODS FOR TREATING MICROELECTRONIC SUBSTRATES - Rapid thermal processing systems and associated methods are disclosed herein. In one embodiment, a method for heating a microelectronic substrate include generating a plasma, applying the generated plasma to a surface of the microelectronic substrate, and raising a temperature of the microelectronic substrate with the generated plasma applied to the surface of the microelectronic substrate. The method further includes continuing to apply the generated plasma until the microelectronic substrate reaches a desired temperature. | 10-28-2010 |
20100279435 | TEMPERATURE CONTROL OF CHEMICAL MECHANICAL POLISHING - A chemical mechanical polishing apparatus including a platen for holding a pad having a polishing surface, a subsystem for holding a substrate and the polishing surface together during a polishing step, and a temperature sensor oriented to measure a temperature of the polishing surface, wherein the subsystem accepts the temperature measured by the sensor and is programmed to vary a polishing process parameter in response to the measured temperature. In an aspect, a chemical mechanical polishing apparatus having a platen for holding a pad having a polishing surface, a fluid delivery system for transporting a fluid from a source to the polishing surface, and a temperature controller which during operation controls the temperature of the fluid transported by the delivery system. | 11-04-2010 |
20100291713 | METHOD OF FORMING HIGHLY CONFORMAL AMORPHOUS CARBON LAYER - A method of forming a conformal amorphous hydrogenated carbon layer on an irregular surface of a semiconductor substrate includes: vaporizing a hydrocarbon-containing precursor; introducing the vaporized precursor and an argon gas into a CVD reaction chamber inside which the semiconductor substrate is placed; depositing a conformal amorphous hydrogenated carbon layer on the irregular surface of the semiconductor substrate by plasma CVD; and controlling the deposition of the conformal ratio of the depositing conformal amorphous hydrogenated carbon layer. The controlling includes (a) adjusting a step coverage of the conformal amorphous hydrogenated carbon layer to about 30% or higher as a function of substrate temperature, and (b) adjusting a conformal ratio of the conformal amorphous hydrogenated carbon layer to about 0.9 to about 1.1 as a function of RF power and/or argon gas flow rate, | 11-18-2010 |
20100297781 | METHOD FOR MANUFACTURING MEMS STRUCTURES - A method for manufacturing MEMS structures having at least one functional layer of silicon that contains structures that are exposed by removing a sacrificial layer, at least one sacrificial layer and at least one functional layer being deposited such that they grow in a monocrystalline manner, and the sacrificial layer is made up of a silicon-germanium mixed layer. | 11-25-2010 |
20100297782 | TECHNIQUES FOR PROCESSING A SUBSTRATE - Herein, an improved technique for processing a substrate is disclosed. In one particular exemplary embodiment, the technique may be realized with a system for processing one or more substrates. The system may comprise an ion source for generating ions of desired species, the ions generated from the ion source being directed toward the one or more substrates along an ion beam path; a substrate support for supporting the one or more substrates; a mask disposed between the ion source and the substrate support, the mask comprising a finger defining one or more apertures through which a portion of the ions traveling along the ion beam path pass; and a first detector for detecting ions, the first detector being fixedly positioned relative to the one or more substrates. | 11-25-2010 |
20100297783 | Plasma Processing Method - A method for performing a plasma process using a plasma processing apparatus which includes a vacuum process chamber, an exhaust device, a mass flow controller supplying a process gas, a stage electrode which receives and holds a workpiece by adsorption, a transfer device, and a high-frequency electrical source. The method includes a first step of performing the plasma process for the workpiece in the vacuum process chamber by a corresponding recipe of predetermined recipes, a second step of acquiring apparatus parameters showing the condition of the plasma processing apparatus when a specific recipe of the predetermined recipes is executed to diagnose whether the condition of the plasma processing apparatus is good or not based on the acquired apparatus parameters. | 11-25-2010 |
20100330709 | WAFER TEMPERATURE CORRECTION SYSTEM FOR ION IMPLANTATION DEVICE - To provide an ion implantation device capable of correcting the temperature of the wafer. The ion implantation device of the present invention has: an irradiation means that radiates ions; a retention means that includes a disk | 12-30-2010 |
20100330710 | METHODS FOR CONSTRUCTING AN OPTIMAL ENDPOINT ALGORITHM - A method for automatically identifying an optimal endpoint algorithm for qualifying a process endpoint during substrate processing within a plasma processing system is provided. The method includes receiving sensor data from a plurality of sensors during substrate processing of at least one substrate within the plasma processing system, wherein the sensor data includes a plurality of signal streams from a plurality of sensor channels. The method also includes identifying an endpoint domain, wherein the endpoint domain is an approximate period within which the process endpoint is expected to occur. The method further includes analyzing the sensor data to generate a set of potential endpoint signatures. The method yet also includes converting the set of potential endpoint signatures into a set of optimal endpoint algorithms. The method yet further includes importing one optimal endpoint algorithm of the set of optimal endpoint algorithms into production environment. | 12-30-2010 |
20110033956 | SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF CONFIRMING OPERATION OF LIQUID FLOWRATE CONTROL DEVICE - A substrate processing apparatus, a method of manufacturing a semiconductor device, and a method of confirming an operation of a liquid flowrate control device are provided. The substrate processing apparatus comprises: a process chamber accommodating a substrate; a liquid source supply system supplying a liquid source into the process chamber; a solvent supply system supplying a solvent having a vapor pressure greater than that of the liquid source into the process chamber; a liquid flowrate control device controlling flowrates of the liquid source and the solvent; and a controller controlling the liquid source supply system, the solvent supply system, and the liquid flowrate control device so that the solvent is supplied into the liquid flowrate control device than the solvent supply system to confirm an operation of the liquid flowrate control device before the liquid source supply system supplies the liquid source into the process chamber. | 02-10-2011 |
20110045611 | METHOD OF INITIATING MOLECULAR BONDING - The invention relates to a method of initiating molecular bonding, comprising bringing one face ( | 02-24-2011 |
20110053294 | UV IRRADIANCE MONITORING IN SEMICONDUCTOR PROCESSING USING A TEMPERATURE DEPENDENT SIGNAL - In a UV process tool for semiconductor processing, a temperature-dependent signal may be used as a monitor signal for determining the momentary irradiance of the UV radiation source. Consequently, a fast and reliable monitoring and/or controlling of the irradiance of UV process tools may be accomplished. | 03-03-2011 |
20110070665 | DC and RF Hybrid Processing System - The invention can provide apparatus and methods for processing substrates and/or wafers in real-time using at least one Direct Current (DC)/Radio Frequency (RF) Hybrid (DC/RFH) processing system and associated Direct Current/Radio Frequency Hybrid (DC/RFH) procedures and DC/RFH process parameters and/or DC/RFH models. | 03-24-2011 |
20110076786 | Method and apparatus for controlled thermal processing - A materials processing system comprises a thermal processing chamber including a heating source, a first noncontacting thermal measurement device positioned to measure temperature on a first area of the material being processed, and, a second noncontacting thermal measurement device positioned to measure temperature on a second area of the material being processed, the first device being relatively more sensitive to changes in surface emissivity than the second device. By comparing the outputs of the two devices, emissivity changes can be detected and used as a proxy for some physical change in the workpiece and thereby determine when the desired process has been completed. The system may be used to develop a process recipe, or it may be part of a system for real-time process control based on emissivity changes. Applicable processes include heating, annealing, dopant activation, silicide formation, carburization, nitridation, sintering, oxidation, vapor deposition, metallization, and plating. | 03-31-2011 |
20110076787 | Method and apparatus for uniform microwave treatment of semiconductor wafers - A microwave heating system comprises a microwave applicator cavity; a microwave power supply to deliver power to the applicator cavity; a dielectric support to support a generally planar workpiece; a dielectric gas manifold to supply a controlled flow of inert gas proximate to the periphery of the workpiece to provide differential cooling to the edge relative to the center; a first temperature measuring device configured to measure the temperature near the center of the workpiece; and, a second temperature measuring device configured to measure the temperature near the edge of the workpiece. The gas flow is controlled to minimize the temperature difference from center to edge, and may be recipe driven or controlled in real time, based on the two temperature measurements. The method is particularly useful for monolithic semiconductor wafers, various semiconducting films on substrates, and dielectric films on semiconducting wafers. | 03-31-2011 |
20110097822 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE WITH UNIFORM TOPOLOGY - A method of manufacturing a semiconductor device to have uniform topology includes forming an interlayer insulating layer on a semiconductor device, carrying out an ion implantation process by varying an amount of ion-implantation according to a height profile of the interlayer insulating layer, and planarizing the interlayer insulating layer. | 04-28-2011 |
20110097823 | APPARATUS FOR FORMING THIN FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR FILM - An apparatus including a vacuum chamber having a substrate holding unit that holds a substrate and a plasma electrode facing the substrate, a first gas supply unit that supplies a H | 04-28-2011 |
20110117679 | SACRIFICIAL OFFSET PROTECTION FILM FOR A FINFET DEVICE - A method for fabricating a semiconductor device is disclosed. An exemplary embodiment of the method includes providing a substrate; forming a fin structure over the substrate; forming a gate structure, wherein the gate structure overlies a portion of the fin structure; forming a sacrificial-offset-protection layer over another portion of the fin structure; and thereafter performing an implantation process. | 05-19-2011 |
20110136267 | METHOD OF CONTROLLING FILM THINNING OF SEMICONDUCTOR WAFER FOR SOLID-STATE IMAGE SENSING DEVICE - The thickness of a semiconductor wafer layer, extending from a mirror-finished surface thereof to a solid-state image sensing device, is measured. Based on the residual thickness data, plasma etching is performed from the mirror-finished surface until a predetermined thickness is reached by controlling the plasma etching amount. By doing this, it is possible to reduce variation in the thickness of the solid-state image sensing device at low cost without causing an increase in the number of processes. | 06-09-2011 |
20110136268 | PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING POLISHING METAL-CONTAINING LAYERS - A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed. | 06-09-2011 |
20110143461 | IN VACUUM OPTICAL WAFER HEATER FOR CRYOGENIC PROCESSING - A vacuum assembly used for warming processed substrates above the dew point to prevent unwanted moisture on the processed substrate surfaces as well as reducing negative impact on manufacturing throughput. The vacuum assembly includes a processing chamber, a substrate handling robot, and a heater which may be an optical heater. The processing chamber is configured to cryogenically process one or more substrates. The transfer chamber is connected to the processing chamber and houses the substrate handling robot. The substrate handling robot is configured to displace one or more substrates from the processing chamber to the transfer chamber. The heater is connected to the transfer chamber above the substrate handling robot such that the heater emits energy incident on the substrate when the substrate handling robot displaces the substrate in the transfer chamber. | 06-16-2011 |
20110171758 | RECLAMATION OF SCRAP MATERIALS FOR LED MANUFACTURING - A method for reclamation of scrap materials during the formation of Group III-V materials by metal-organic chemical vapor deposition (MOCVD) processes and/or hydride vapor phase epitaxial (HVPE) processes is provided. More specifically, embodiments described herein generally relate to methods for repairing or replacing defective films or layers during the formation of devices formed by these materials. By periodic testing of the layers during the formation process, low-quality layers that may result in low-quality or defective devices may be detected prior to completion of the device. These low-quality layers may be partially or completely removed and redeposited to reclaim the substrate and any remaining high-quality layers that were previously deposited under the low-quality layer. | 07-14-2011 |
20110171759 | Lithographic Apparatus and Device Manufacturing Method - Data from the piezo-electric sensors in the mounts for the projection system can be used in the control loops for other parts of the lithographic apparatus, for example the mask table, the substrate table or the air mounts for the frame bearing the projection system. Information from, for example, a geophone, which is used to measure the absolute velocity of the frame bearing the projection system, can be used in the control loop for the piezo-electric actuator in the mount for the projection system. | 07-14-2011 |
20110177622 | APPARATUS AND METHODS OF MIXING AND DEPOSITING THIN FILM PHOTOVOLTAIC COMPOSITIONS - Improved methods and apparatus for forming thin-film layers of semiconductor material absorber layers on a substrate web. According to the present teachings, a semiconductor layer may be formed in a multi-zone process whereby various layers are deposited sequentially onto a moving substrate web. At least one layer is deposited from a mixed gallium indium source. | 07-21-2011 |
20110177623 | Active Tribology Management of CMP Polishing Material - An arrangement and method for managing the tribology associated with a chemical mechanical planarization (CMP) process continuously monitors and modifies the properties of a polishing slurry in order to assist in controlling the removal rate associated with the CMP process. The viscosity of slurry as it leaves the CMP system (“spent slurry”) and the material removal rate associated with the semiconductor wafer are measured, and then the viscosity of the incoming slurry is adjusted if the measured material removal rate differs from a desired removal rate. If the removal rate is considered to be too fast, the viscosity of the fresh slurry being dispensed onto polishing pad is decreased; alternatively, if the removal rate is too slow, the viscosity is increased. As an alternative to modifying the viscosity of the slurry (or, perhaps in addition to modifying the viscosity), a lubricant may be added to the slurry to slow down the removal rate. | 07-21-2011 |
20110183443 | CONTACT PATTERNING METHOD WITH TRANSITION ETCH FEEDBACK - A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole. | 07-28-2011 |
20110201134 | CAPACITIVELY COUPLED PLASMA REACTOR WITH MAGNETIC PLASMA CONTROL - A plasma reactor includes a vacuum enclosure including a side wall and a ceiling defining a vacuum chamber, and a workpiece support within the chamber and facing the ceiling for supporting a planar workpiece, the workpiece support and the ceiling together defining a processing region between the workpiece support and the ceiling. Process gas inlets furnish a process gas into the chamber. A plasma source power electrode is connected to an RF power generator for capacitively coupling plasma source power into the chamber for maintaining a plasma within the chamber. The reactor further includes at least a first overhead solenoidal electromagnet adjacent the ceiling, the overhead solenoidal electromagnet, the ceiling, the side wall and the workpiece support being located along a common axis of symmetry. A current source is connected to the first solenoidal electromagnet and furnishes a first electric current in the first solenoidal electromagnet whereby to generate within the chamber a magnetic field which is a function of the first electric current, the first electric current having a value such that the magnetic field increases uniformity of plasma ion density radial distribution about the axis of symmetry near a surface of the workpiece support. | 08-18-2011 |
20110201135 | Method of Reducing Contamination by Providing a Removable Polymer Protection Film During Microstructure Processing - By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process. | 08-18-2011 |
20110207241 | Formation method of metallic electrode of semiconductor device and metallic electrode formation apparatus - A formation method of a metallic electrode of a semiconductor device is disclosed. The method includes: acquiring data about surface shape of a surface part of a semiconductor substrate; and causing a deformation device to deform the semiconductor substrate based on the data so that a distance between a cutting plane and the surface part falls within a required accuracy in cutting amount. In deforming the semiconductor substrate, multiple actuators are used as the deformation device. A pitch of the multiple actuators is set to a value that is greater than one-half of wavelength of spatial frequency of a thickness distribution of the semiconductor substrate and that is less than or equal to the wavelength. | 08-25-2011 |
20110207242 | METHOD OF MANUFACTURE OF AN INTEGRATED CIRCUIT PACKAGE - A method of manufacturing an integrated circuit, IC, package comprising radio frequency, RF, components, the method comprising:
| 08-25-2011 |
20110207243 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - There is provided a means for uniformly controlling the in-plane temperature of a semiconductor wafer at high speed in a high heat input etching process. A refrigerant channel structure in a circular shape is formed in a sample stage. Due to a fact that a heat transfer coefficient of a refrigerant is largely changed from a refrigerant supply port to a refrigerant outlet port, the cross sections of the channel structure is structured so as to be increased from a first channel areas towards a second channel areas in order to make the heat transfer coefficient of the refrigerant constant in the refrigerant channel structure. Thereby, the heat transfer coefficient of the refrigerant is prevented from increasing by reducing the flow rate of the refrigerant at a dry degree area where the heat transfer coefficient of the refrigerant is increased. Further, the cross section of the channel structure is structured so as to be reduced from the second channel areas towards a third channel areas, and thereby the heat transfer coefficient of the refrigerant is prevented from decreasing. Accordingly, the heat transfer coefficient of the refrigerant can be uniformed in the channel structure. | 08-25-2011 |
20110223693 | HEAT TREATMENT APPARATUS AND METHOD OF PROCESSING SUBSTRATE - There are provided a heat treatment apparatus and a method of processing a substrate, which can control uniformity in thickness of a film formed on a substrate. The heat treatment apparatus includes a processing chamber configured to process a substrate; a heating device configured to heat the substrate from a circumferential side of the substrate accommodated in the processing chamber; a cooling gas channel installed between the heating device and the processing chamber; a cooling device configured to flow a cooling gas into the cooling gas channel; a plurality of cooling gas inhalation passages configured to independently communicate with the cooling gas channel in regions into which the heating device is horizontally divided, and installed between the cooling device and the cooling gas channel; first pressure detectors installed respectively in the plurality of cooling gas inhalation passages; and a control unit configured to control the cooling device based on a first pressure value detected by the first pressure detectors. | 09-15-2011 |
20110229987 | METHOD FOR LOW TEMPERATURE ION IMPLANTATION - Techniques for low temperature ion implantation are provided to improve throughput. Specifically, the pressure of the backside gas may temporarily, continually or continuously increase before the starting of the implant process, such that the wafer may be quickly cooled down from room temperature to be essentially equal to the prescribed implant temperature. Further, after the vacuum venting process, the wafer may wait an extra time in the load lock chamber before the wafer is moved out the ion implanter, in order to allow the wafer temperature to reach a higher temperature quickly for minimizing water condensation on the wafer surface. Furthermore, to accurately monitor the wafer temperature during a period of changing wafer temperature, a non-contact type temperature measuring device may be used to monitor wafer temperature in a real time manner with minimized condensation. | 09-22-2011 |
20110244601 | METHOD FOR PRODUCING A SUBSTRATE INCLUDING A STEP OF THINNING WITH STOP WHEN A POROUS ZONE IS DETECTED - A method for producing a substrate including a step of thinning the thickness of the substrate is disclosed. The method is characterized in that it includes the following steps: the formation of a porous zone in an inner layer of the substrate; the progressive thinning of the thickness of the substrate towards the inner layer including a porous zone; the completion of the progressive thinning by polishing; and a controlled stoppage of polishing upon detection of the porous zone. | 10-06-2011 |
20110244602 | METHOD OF PRODUCING SEMICONDUCTOR - In a conventional SGT production method, during dry etching for forming a pillar-shaped silicon layer and a gate electrode, an etching amount cannot be controlled using an end-point detection process, which causes difficulty in producing an SGT while stabilizing a height dimension of the pillar-shaped silicon layer, and a gate length. In an SGT production method of the present invention, a hard mask for use in dry etching for forming a pillar-shaped silicon layer is formed in a layered structure comprising a first hard mask and a second hard mask, to allow the end-point detection process to be used during the dry etching for the pillar-shaped silicon layer. In addition, a gate conductive film for use in dry etching for forming a gate electrode is formed in a layered structure comprising a first gate conductive film and a second gate conductive film, to allow the end-point detection process to be used during the dry etching for the gate electrode. | 10-06-2011 |
20110250706 | METHOD OF FABRICATING MEMS, NEMS, PHOTONIC, MICRO- AND NANO-FABRICATED DEVICES AND SYSTEMS - An improved method for the fabrication of Micro-Electro-Mechanical Systems (MEMS), Nano-Electro-Mechanical Systems (NEMS), Photonics, Nanotechnology, 3-Dimensional Integration, Micro- and Nano-Fabricated Devices and Systems for both rapid prototyping development and manufacturing is disclosed. The method includes providing a plurality of different standardized and repeatable process modules usable in fabricating the devices and systems, defining a process sequence for fabricating a predefined one of the devices or systems, and identifying a series of the process modules that are usable in performing the defined process sequence and thus in fabricating the predefined device or system. | 10-13-2011 |
20110250707 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first group identifier allocated to a first group of semiconductor wafers is detected. The first group of semiconductor wafers includes a first semiconductor wafer to be processed first among the first group. A first processor of a plurality of processors, which process respective ones of the first group of semiconductor wafers, are determined based on the first group identifier. The first processor is used for processing the first semiconductor wafer. The first semiconductor wafer is supplied to the first processor. | 10-13-2011 |
20110275166 | SYSTEMS AND METHODS FOR THIN-FILM DEPOSITION OF METAL OXIDES USING EXCITED NITROGEN-OXYGEN SPECIES - The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD). | 11-10-2011 |
20110281376 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND STORAGE MEDIUM RECORDING PROGRAM - Disclosed is a substrate processing apparatus including: a substrate processing unit that performs substrate processing by supplying a processing liquid to a substrate to be processed; a positioning mechanism that contacts the sides of the substrate to determine the position of the substrate; a positioning driver that drives the positioning mechanism; a detector that detects the position of the positioning mechanism; a storage unit that stores the position of the positioning mechanism with respect to a reference substrate serving as a reference of the substrate as a reference position information; and an operator that calculates a difference between the reference position information and the position information of the positioning mechanism detected in the detector and calculates measurement information on the processed substrate based on the difference. | 11-17-2011 |
20110312106 | METHOD FOR PREPARING A LIGHT-EMITTING DEVICE USING GAS CLUSTER ION BEAM PROCESSING - A method of manufacturing semiconductor-based light-emitting devices, such as light-emitting diodes (LEDs), is described. The method comprises irradiating an interface region with a gas cluster ion beam (GCIB) to improve the interface region between a light-emitting device stack and the substrate, within the light-emitting device stack, and/or between the light-emitting device stack and a metal contact layer in an end-type contact. | 12-22-2011 |
20120015454 | METHOD OF MANUFACTURING EPITAXIAL SILICON WAFER AND APPARATUS THEREFOR - A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer. | 01-19-2012 |
20120021536 | METHOD AND SYSTEM FOR APPLICATION OF AN INSULATING DIELECTRIC MATERIAL TO PHOTOVOLTAIC MODULE SUBSTRATES - A method and related system are provided for depositing a dielectric material into voids in one or more of the semiconductor material layers of a photovoltaic (PV) module substrate. A first side of the substrate is exposed to a light source such that light is transmitted through the substrate and any voids in the semiconductor material layers on the opposite side of the substrate. The light transmitted through the voids is detected and a printer is registered to the pattern of detected light to print a dielectric material and fill the voids. | 01-26-2012 |
20120021537 | METHODS OF EVALUATING EPITAXIAL GROWTH AND METHODS OF FORMING AN EPITAXIAL LAYER - A method of evaluating an epitaxial growing process includes forming a mold layer on each of a plurality of substrates, forming a photoresist pattern on each mold layer, the photoresist pattern having opening portions, a total area of a bottom portion of the opening portions being different for each substrate, patterning each mold layer to expose a surface portion of the substrate to form an evaluation pattern on each substrate, evaluation patterns including opening portions corresponding to the opening portion in the photoresist pattern, determining substrate opening ratios for each substrate based on the opening portions in the evaluation pattern thereon, the substrate opening ratios being different for each substrate, performing a selective epitaxial process on each substrate to form an epitaxial layer, and evaluating characteristics of the epitaxial layer for each substrate to determine an optimal substrate opening ratio. | 01-26-2012 |
20120021538 | PLASMA PROCESSING METHOD AND STORAGE MEDIUM - There is provided a plasma processing method performing a plasma etching process on an oxide film of a target substrate through one or more steps by using a processing gas including a CF-based gas and a COS gas. The plasma processing method includes: performing a plasma etching process on the oxide film of the target substrate according to a processing recipe; measuring a concentration of sulfur (S) remaining on the target substrate (residual S concentration) after the plasma etching process is performed according to the processing recipe; adjusting a ratio of a COS gas flow rate with respect to a CF-based gas flow rate (COS/CF ratio) so as to allow the residual S concentration to become equal to or smaller than a predetermined value; and performing an actual plasma etching process according to a modified processing recipe storing the adjusted COS/CF ratio. | 01-26-2012 |
20120028376 | Method of Controlling Critical Dimensions of Trenches in a Metallization System of a Semiconductor Device During Etch of an Etch Stop Layer - When forming metal lines and vias in complex metallization systems of semiconductor devices, an additional control mechanism for adjusting the final critical dimension may be implemented in the last etch process for etching through the etch stop layer after having patterned the low-k dielectric material. To this end, the concentration of a polymerizing gas may be controlled in accordance with the initial critical dimension obtained after the lithography process, thereby efficiently re-adjusting the final critical dimension so as to be close to the desired target value. | 02-02-2012 |
20120034713 | PROCESS, VOLTAGE, TEMPERATURE SENSOR - An integrated circuit includes a process sensor, a temperature sensor, and a voltage sensor. The process sensor is configured to sense a process parameter indicative of a semiconductor process by which the integrated circuit is formed and, based upon the sensed process parameter, to provide a characterization of the semiconductor process to the output of the process sensor. The temperature sensor is configured to provide an indication of a temperature of the integrated circuit to an output of the temperature sensor and the voltage sensor is configured to provide an indication of a power supply voltage level of the integrated circuit to an output of the voltage sensor. The output of the process sensor is coupled to at least one of the temperature sensor and the voltage sensor to compensate at least one of the indication of the temperature and the indication of the power supply voltage level. | 02-09-2012 |
20120058576 | Deposition System - A pumping and valve control device can be used in an atomic layer deposition system. | 03-08-2012 |
20120070914 | TEMPERATURE CONTROL MODULE USING GAS PRESSURE TO CONTROL THERMAL CONDUCTANCE BETWEEN LIQUID COOLANT AND COMPONENT BODY - A temperature control module for a semiconductor processing chamber comprises a thermally conductive component body, one or more channels in the component body and one or more tubes concentric therewith, such that gas filled spaces surround the tubes. By flowing a heat transfer liquid in the tubes and adjusting the gas pressure in the spaces, localized temperature of the component body can be precisely controlled. One or more heating elements can be arranged in each zone and a heat transfer liquid can be passed through the tubes to effect heating or cooling of each zone by activating the heating elements and/or varying pressure of the gas in the spaces. | 03-22-2012 |
20120077289 | APPARATUS AND METHOD OF TEMPERATURE CONTROL DURING CLEAVING PROCESSES OF THICK MATERIALS - A method for temperature control during a process of cleaving a plurality of free-standing thick films from a bulk material includes clamping a bulk material using a mechanical clamp device adapted to engage the bottom region of the bulk material through a seal with a planar surface of a stage to form a cavity with a height between the bottom region and the planar surface. The planar surface includes a plurality of gas passageways allowing a gas filled in the cavity with adjustable pressure. The method also includes maintaining the temperature of the surface region by processing at least input data and executing a control scheme utilizing at least one or more of;
| 03-29-2012 |
20120083050 | DETECTING A DEPOSITION CONDITION - Apparatus and methods for detecting evaporation conditions in an evaporator for evaporating metal onto semiconductor wafers, such as GaAs wafers, are disclosed. One such apparatus can include a crystal monitor sensor configured to detect metal vapor associated with a metal source prior to metal deposition onto a semiconductor wafer. This apparatus can also include a shutter configured to remain in a closed position when the crystal monitor sensor detects an undesired condition, so as to prevent metal deposition onto the semiconductor wafer. In some implementations, the undesired condition can be indicative of a composition of a metal source, a deposition rate of a metal source, impurities of a metal source, position of a metal source, position of an electron beam, and/or intensity of an electron beam. | 04-05-2012 |
20120088316 | SYSTEM AND METHOD FOR WAFER BACK-GRINDING CONTROL - In a system or method for controlling wafer back-grinding, a chuck table has a surface for supporting a semiconductor wafer during a back-grinding process, one or more holes in the surface, and one or more sensors disposed in the one or more holes for monitoring a parameter during back-grinding. A computer-implemented process control tool is coupled to receive one or mote outputs from the one or more sensors and control the back-grinding process based on the received one or more outputs. | 04-12-2012 |
20120107968 | GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE, METHOD OF FABRICATING GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE, AND METHOD OF ESTIMATING DAMAGE FROM FORMATION OF SCRIBE GROOVE - A method of fabricating group-III nitride semiconductor laser device includes: preparing a substrate comprising a hexagonal group-III nitride semiconductor and having a semipolar principal surface; forming a substrate product having a laser structure, an anode electrode, and a cathode electrode, where the laser structure includes a semiconductor region and the substrate, where the semiconductor region is formed on the semipolar principal surface; scribing a first surface of the substrate product in a direction of an a-axis of the hexagonal group-III nitride semiconductor to form first and second scribed grooves; and carrying out breakup of the substrate product by press against a second surface of the substrate product, to form another substrate product and a laser bar. | 05-03-2012 |
20120115254 | HEATING PLATE WITH PLANAR HEATER ZONES FOR SEMICONDUCTOR PROCESSING - A heating plate for a substrate support assembly in a semiconductor plasma processing apparatus, comprises multiple independently controllable planar heater zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar heater zone includes one or more heater elements made of an insulator-conductor composite. A substrate support assembly in which the heating plate is incorporated includes an electrostatic clamping electrode and a temperature controlled base plate. Methods for manufacturing the heating plate include bonding together ceramic sheets having planar heater zones, power supply lines, power return lines and vias. | 05-10-2012 |
20120115255 | METHOD AND APPARATUS FOR DYNAMIC THIN-LAYER CHEMICAL PROCESSING OF SEMICONDUCTOR WAFERS - A semiconductor wafer processing and analysis apparatus ( | 05-10-2012 |
20120115256 | METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT - A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications. | 05-10-2012 |
20120129275 | DUAL-BULB LAMPHEAD CONTROL METHODOLOGY - The present invention generally relates to methods of controlling UV lamp output to increase irradiance uniformity. The methods generally include determining a baseline irradiance within a chamber, determining the relative irradiance on a substrate corresponding to a first lamp and a second lamp, and determining correction or compensation factors based on the relative irradiances and the baseline irradiance. The lamps are then adjusted via closed loop control using the correction or compensation factors to individually adjust the lamps to the desired output. The lamps may optionally be adjusted to equal irradiances prior to adjusting the lamps to the desired output. The closed loop control ensures process uniformity from substrate to substrate. The irradiance measurement and the correction or compensation factors allow for adjustment of lamp set points due to chamber component degradation, chamber component replacement, or chamber cleaning. | 05-24-2012 |
20120142122 | METHOD OF INSPECTING AND PROCESSING SEMICONDUCTOR WAFERS - A wafer inspection method comprises imaging a full surface of the wafer at an imaging resolution insufficient to resolve individual microstructures which are repetitively arranged on the wafer. A mask | 06-07-2012 |
20120149133 | MEMS PROCESS METHOD FOR HIGH ASPECT RATIO STRUCTURES - Methods for the controlled manufacture of high aspect ratio features. The method may include forming a layer stack on a top surface of a substrate and forming features in the layers of the layer stack. The high aspect ratio features may be defined using a resist layer that is patterned with a photolithographic condition. After removing at least one of the layers removed from the top of the layer stack, a feature dimension may be measured for features at different locations on the substrate. The method may further include changing the photolithographic condition based on the measured dimension and processing another substrate using the changed photolithographic condition. | 06-14-2012 |
20120156807 | METHOD OF UPDATING CALIBRATION DATA AND A DEVICE MANUFACTURING METHOD - A method of updating calibration data of a first position detection system adapted to determine the position of an object, is presented. The first position detection system includes a target and a plurality of sensors one of which is mounted on an object and the calibration data including coefficients relating an apparent measured position to an actual position and which can be used to convert an apparent measured position to an actual position thereby to correct for physical imperfections in the first position detection system and enable determination of the actual position from the apparent measured position. | 06-21-2012 |
20120156808 | METHOD FOR APPLYING LIQUID MATERIAL, AND APPARATUS AND PROGRAM FOR SAME - Provided are a method for filling a liquid material, and an apparatus and a program for the same, which make it possible, without changing a moving speed of an ejection device, to correct a change in ejection amount and to stabilize an application shape. Disclosed are: a method for filling a liquid material into a gap between a substrate and a work by using the capillary action; and an apparatus and a program for the same. The method comprises the steps of: generating an application pattern consisting of a plurality of application areas continuous to one another; assigning a plurality of ejection cycles, each obtained by combining the number of ejection pulses and the number of pause pulses at a predetermined ratio therebetween, to each of the application areas; and measuring an ejection amount at correction intervals and calculating a correction amount for the ejection amount. The method further comprises at least any one of the steps of: adjusting the numbers of ejection pulses and the numbers of pause pulses, which are included in the application pattern, based on the calculated correction amount; and adjusting the length of any application area continuous to at least one application area without changing ejection amounts per unit time in the respective application areas. | 06-21-2012 |
20120171786 | APPARATUS FOR MANUFACTURING SOLAR CELLS AND PROCESS FOR OPERATING SUCH APPARATUS - Apparatus ( | 07-05-2012 |
20120184054 | MANUFACTURING APPARATUS AND METHOD FOR SEMICONDUCTOR DEVICE - Provided is a semiconductor manufacturing apparatus including: a reaction chamber including a gas supply inlet and a gas exhaust outlet, and into which a wafer is to be introduced; a process gas supply mechanism that supplies process gas into the reaction chamber from the gas supply inlet of the reaction chamber; a wafer retaining member that is arranged in the reaction chamber and that retains the wafer; a heater that heats the wafer retained by the wafer retaining member to a predetermined temperature; a rotation drive control mechanism that rotates the wafer retaining member together with the wafer; a gas exhaustion mechanism that exhausts gas in the reaction chamber from the gas exhaust outlet of the reaction chamber; and a drain that is disposed at a bottom portion near a wall surface in the reaction chamber and that collects and discharges oily silane that drips from the wall surface. | 07-19-2012 |
20120202300 | DIE BONDER INCLUDING AUTOMATIC BOND LINE THICKNESS MEASUREMENT - A method for assembling integrated circuit (IC) devices includes dispensing a die attach adhesive onto a surface of a workpiece using a die bonding system, and placing an IC die on the die attach adhesive at surface of the workpiece to form an IC device. A pre-cure bond line thickness (pre-cure BLT) value is automatically optically measured for the die attach adhesive. The IC device is unloaded from the die bonding system after automatically optically measuring. The method can include comparing the pre-cure BLT value to a pre-cure BLT specification range, and if the pre-cure BLT value is outside the pre-cure BLT specification range, adjusting at least one die attach adhesive dispensing parameter based on the pre-cure BLT value for subsequent assembling. The adjusting can be automatic adjusting and the adjustment can be to the Z height parameter of the bond arm. | 08-09-2012 |
20120208300 | ETCH PROCESSING CHAMBER - A substrate etching method and apparatus are disclosed. In one embodiment, a method for etching is provided that includes, in a plasma processing chamber, etching a feature in a silicon layer using an etch recipe that includes cyclical etching and deposition substeps until an end point is reached, wherein an aspect ratio of the feature increases with a number of cyclical etching and deposition substeps performed over time until the end point is reached; and adjusting a recipe variable of the etch recipe in response to the current aspect ratio of the feature during etching to manage thickness of sidewall polymers when the feature becomes deeper to avoid closing the feature and preventing subsequent etching. | 08-16-2012 |
20120208301 | Methods and Systems for Creating or Performing a Dynamic Sampling Scheme for a Process During Which Measurements Are Performed on Wafers - Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one tot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process. | 08-16-2012 |
20120214258 | Die Bonder and Semiconductor Manufacturing Method - The present invention provides a reliable die bonder that can accurately bond a die and a semiconductor manufacturing method. The present invention is provided with a bonding head that adsorbs a die from a wafer and bonds it to a substrate, a positioning mechanism that is provided with a first adjustment mechanism that positions a position of the die at predetermined accuracy, and positions the bonding head, a positioning controller that controls the positioning mechanism and a second adjustment mechanism that is provided to the bonding head, and adjusts a position of the die at higher accuracy than the first adjustment mechanism. | 08-23-2012 |
20120231555 | ADAPTIVE ENDPOINT METHOD FOR PAD LIFE EFFECT ON CHEMICAL MECHANICAL POLISHING - The present disclosure provides a semiconductor manufacturing method. The method includes defining a plurality of time regions of pad life for a polishing pad in a chemical mechanical polishing (CMP) system; assigning a ladder coefficient to the polishing pad according to the plurality of time regions of pad life; defining a plurality of endpoint windows to the plurality of time regions, respectively, according to pad life effect; applying a CMP process to a wafer positioned on the polishing pad; determining a time region of a polishing signal of the wafer based on the ladder coefficient; associating one of the endpoint windows to the polishing signal according to the time region; and ending the CMP process at an endpoint determined by the endpoint window. | 09-13-2012 |
20120231556 | ETCH TOOL PROCESS INDICATOR METHOD AND APPARATUS - A method for providing a process indicator for an etching chamber is provided. A wafer with a blanket etch layer is provided into the etching chamber. A blanket etch is performed on the blanket etch layer. A blanket deposition layer is deposited over the blanket etch layer after performing the blanket etch has been completed. A thickness of the blanket etch layer and a thickness of the blanket deposition layer is measured. The measured thicknesses are used to determine a process indicator. | 09-13-2012 |
20120238040 | PLASMA ETCHING APPARATUS AND PLASMA ETCHING METHOD - Disclosed is a technology that can obtain high in-plane uniformity of etching while etching a substrate using plasma. A proper temperature of a focus ring capable of performing etching having high in-plane uniformity is identified in advance for each of the multilayers formed on a wafer, the temperature is reflected to a processing recipe as a set temperature, and a heating mechanism and a cooling mechanism are controlled such that the temperature of the focus ring is within an appropriate temperature range including the set temperature thereof for each of the layers to be successively etched. Heat of the focus ring is radiated using a laser and is discharged to a supporting table without using a heater, to independently separate the heating mechanism and the cooling mechanism from each other. | 09-20-2012 |
20120244644 | System and Method for Increasing Productivity of Organic Light Emitting Diode Material Screening - A system and method of increasing productivity of OLED material screening includes providing a substrate that includes an organic semiconductor, processing regions on the substrate by combinatorially varying parameters associated with the OLED device production on the substrate, performing a first characterization test on the processed regions on the substrate to generate first results, processing regions on the substrate in a combinatorial manner by varying parameters associated with the OLED device production on the substrate based on the first results of the first characterization test, performing a second characterization test on the processed regions on the substrate to generate second results, and determining whether the substrate meets a predetermined quality threshold based on the second results. | 09-27-2012 |
20120252141 | Adaptive Recipe Selector - The invention provides a method of processing a wafer using Ion Energy (IE)-related multilayer process sequences and Ion Energy Controlled Multi-Input/Multi-Output (IEC-MIMO) models and libraries that can include one or more measurement procedures, one or more IEC-etch sequences, and one or more Ion Energy Optimized (IEO) etch procedures. The IEC-MIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple IEC etch sequences. The multiple layers and/or the multiple IEC etch sequence can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using IEO etch procedures. | 10-04-2012 |
20120258555 | Multi-Frequency Hollow Cathode and Systems Implementing the Same - A hollow cathode system is provided for plasma generation in substrate plasma processing. The system includes an electrically conductive member shaped to circumscribe an interior cavity, and formed to have a process gas inlet in fluid communication with the interior cavity, and formed to have an opening that exposes the interior cavity to a substrate processing region. The system also includes a first radiofrequency (RF) power source in electrical communication with the electrically conductive member so as to enable transmission of a first RF power to the electrically conductive member. The system further includes a second RF power source in electrical communication with the electrically conductive member so as to enable transmission of a second RF power to the electrically conductive member. The first and second RF power sources are independently controllable with regard to frequency and amplitude. | 10-11-2012 |
20120270340 | MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED DEVICE - In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape. | 10-25-2012 |
20120276660 | SYSTEM FOR NON RADIAL TEMPERATURE CONTROL FOR ROTATING SUBSTRATES - Embodiments of the present invention provide apparatus and method for reducing non uniformity during thermal processing. One embodiment provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to rotate the substrate, a sensor assembly configured to measure temperature of the substrate at a plurality of locations, and one or more pulse heating elements configured to provide pulsed energy towards the processing volume. | 11-01-2012 |
20120309115 | APPARATUS AND METHODS FOR SUPPORTING AND CONTROLLING A SUBSTRATE - Embodiments of the present invention provide apparatus and methods for supporting and controlling a substrate during thermal processing. One embodiment of the present invention provides an apparatus for processing a substrate. The apparatus includes a chamber body defining an inner volume, a substrate support disposed in the inner volume, and an auxiliary force assembly configured to apply an auxiliary force to the substrate. Another embodiment provides a gas delivery assembly configured to adjust a thermal mass of a fluid flow delivered to position, control and/or rotate a substrate. | 12-06-2012 |
20120309116 | Substrate Analysis Using Surface Acoustic Wave Metrology - A system for imposing and analyzing surface acoustic waves in a substrate to determine characteristics of the substrate is disclosed. Optical elements and arrangements for imposing and analyzing surface acoustic waves in a substrate are also disclosed. NSOM's, gratings, and nanolight elements may be used to impose surface acoustic waves in a substrate and may also be used to measure transient changes in the substrate due to the passage of surface acoustic waves therethrough. | 12-06-2012 |
20120315708 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a source electrode and a drain electrode on a front face of a semiconductor substrate which is transparent to visible light, forming a front-side gate electrode between the source electrode and the drain electrode on the front face of the semiconductor substrate; forming an aligning mark on a region of the front face of the semiconductor substrate other than a region between the source electrode and the drain electrode, aligning the semiconductor substrate based on the aligning mark that is seen through the semiconductor substrate, and forming a back-side gate electrode on a back face of the semiconductor substrate in a location opposite the front-side gate electrode. | 12-13-2012 |
20120315709 | PROCESS AND APPARATUS FOR PRODUCING A SUBSTRATE - Process for producing a solar cell substrate, where metal particles are deposited on the surface of substrate. Metal particles are produced by liquid flame spraying method in such a way that the mean diameter of the particles to be between 30 nm and 150 nm and the deposition process is controlled in such a way that the average distance between particles is not more than four times the mean diameter of particles. Apparatus for carrying out such process. | 12-13-2012 |
20120315710 | METHOD FOR PRODUCING RECONSTITUTED WAFERS AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICES - In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S | 12-13-2012 |
20120322168 | CHEMICAL VAPOR DEPOSITION APPARATUS - System and method for forming one or more materials. The system includes a susceptor component configured to rotate around a central axis, and a showerhead component that is located above the susceptor component and not in direct contact with the susceptor component. Additionally, the system includes one or more substrate holders located on the susceptor component and configured to rotate around the central axis and also rotate around corresponding holder axes respectively, and a central component. Moreover, the system includes one or more first inlets formed within the central component, one or more second inlets, and one or more third inlets formed within the showerhead component and located farther away from the central component than the one or more second inlets. | 12-20-2012 |
20120329178 | NOVEL THERMAL PROCESSING APPARATUS - The present invention generally relates to an optical system that is able to reliably deliver a uniform amount of energy across an anneal region contained on a surface of a substrate. The optical system is adapted to deliver, or project, a uniform amount of energy having a desired two-dimensional shape on a desired region on the surface of the substrate. An energy source for the optical system is typically a plurality of lasers, which are combined to form the energy field. | 12-27-2012 |
20130005054 | Film Formation Apparatus and Film Formation Method - There is provided a film formation apparatus which is capable of forming an EL layer using an EL material with high purity. The EL material is purified by sublimation immediately before film formation in the film formation apparatus, to thereby remove oxygen, water, and another impurity, which are included in the EL material. Also, when film formation is performed using the EL material (high purity EL material) obtained by purifying with sublimation as an evaporation source, a high purity EL layer can be formed. | 01-03-2013 |
20130011936 | SELECTIVE ETCHING BATH METHODS - An etching method. The method includes etching a first plurality of silicon wafers in a first enchant, each silicon wafer having SiO | 01-10-2013 |
20130011937 | METHOD FOR WAFER BACK-GRINDING CONTROL - A method of reducing manufacturing defects of semiconductor wafers during a back-grinding process. The method includes receiving a semiconductor wafer on a chuck table, wherein said chuck table has a surface upon which a front side of the wafer is placed, and wherein said chuck table has one or more holes in surface and one or more sensors placed in said one or more holes. The method further includes grinding at least a portion of a back side of the semiconductor wafer. The method further includes monitoring a parameter, while grinding, measured by the one or more sensors and adjusting the grinding based at least on the monitored parameter. | 01-10-2013 |
20130023064 | Negative Ion Control for Dielectric Etch - Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer. | 01-24-2013 |
20130023065 | Apparatus and Methods for End Point Determination in Reactive Ion Etching - Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed. | 01-24-2013 |
20130023066 | SYSTEM AND METHOD FOR INCREASING PRODUCTIVITY OF ORGANIC LIGHT EMITTING DIODE MATERIAL SCREENING - A system and method of increasing productivity of OLED material screening includes providing a substrate that includes an organic semiconductor, processing regions on the substrate by combinatorially varying parameters associated with the OLED device production on the substrate, performing a first characterization test on the processed regions on the substrate to generate first results, processing regions on the substrate in a combinatorial manner by varying parameters associated with the OLED device production on the substrate based on the first results of the first characterization test, performing a second characterization test on the processed regions on the substrate to generate second results, and determining whether the substrate meets a predetermined quality threshold based on the second results. | 01-24-2013 |
20130029433 | PROCESS CONDITION MEASURING DEVICE - An instrument comprises a substrate, a plurality of sensors distributed at positions across the substrate's surface, at least one electronic processing component on the surface, electrical conductors extending across the surface and connected to the sensors and processing component, and a cover disposed over the sensors, processing component and conductors. The cover and substrate have similar material properties to a production substrate. The cover is configured to electromagnetically shield the sensors, conductors, or processing component. The instrument has approximately the same thickness and/or flatness as the production substrate. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 01-31-2013 |
20130045545 | TEST MAP CLASSIFICATION METHOD AND FABRICATION PROCESS CONDITION SETTING METHOD USING THE SAME - A test map classification method includes modifying test data by converting to a test map including a wafer identifier, a coordinate, and data on whether a predetermined failure item occurs; calculating similarities of wafer pairs in the test map; performing similarity filtering to reset all the similarities, except for at least one similarity, on the basis of a predetermined wafer; determining whether there are similar wafers by comparing the filtered similarities with a reference value; and classifying spatial patterns using a similar relationship between the wafer pairs when there are similar wafers. | 02-21-2013 |
20130078743 | Method and Apparatus For Depositing A Layer On A Semiconductor Wafer by Vapor Deposition In A Process Chamber - A layer is deposited onto a semiconductor wafer by CVD in a process chamber having upper and lower covers, wherein the wafer front side temperature is measured; the wafer is heated to deposition temperature; the temperature of the upper process chamber cover is controlled to a target temperature by measuring the temperature of the center of the outer surface of the upper cover as the value of a controlled variable of an upper cover temperature control loop; a gas flow rate of process gas for depositing the layer is set; and a layer is deposited on the heated wafer front side during control of the upper cover temperature to the target temperature. A process chamber suitable therefor has a sensor for measuring the upper cover outer surface center temperature and a controller for controlling this temperature to a predetermined value. | 03-28-2013 |
20130078744 | HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS OF THIN FILM - A semiconductor wafer, on the surface of which a silicon dioxide base material and an amorphous silicon thin film are formed in this order, is carried into a chamber. An insulated gate bipolar transistor (IGBT) is connected with a power supply circuit to a flash lamp, and the IGBT makes an energization period to the flash lamp to be 0.01 millisecond or more and 1 millisecond or less, consequently making a flash light irradiation time to be 0.01 millisecond or more and 1 millisecond or less. Since a flash heat treatment is performed with a remarkably short flash light irradiation time, the excessive heating of the thin film of amorphous silicon is suppressed and harmful influence such as the exfoliation of the film is prevented. | 03-28-2013 |
20130084654 | COMBINED SILICON OXIDE ETCH AND CONTAMINATION REMOVAL PROCESS - A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process. | 04-04-2013 |
20130089934 | Material Delivery System and Method - A system and method for controlling saturated vapor pressure of a precursor material is provided. An embodiment comprises generating a calibration curve and utilizing the calibration curve to control a temperature of the precursor material in order to control its saturated vapor pressure. Alternatively, the calibration curve may be substituted for a real time sensor which can take readings in real time and adjust the temperature and saturated vapor pressure based upon the real time readings. | 04-11-2013 |
20130089935 | OVERLAY AND SEMICONDUCTOR PROCESS CONTROL USING A WAFER GEOMETRY METRIC - The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region. | 04-11-2013 |
20130102091 | TEST SYSTEM SUPPORTING SIMPLIFIED CONFIGURATION FOR CONTROLLING TEST BLOCK CONCURRENCY - Techniques for configuring a test system that enable simple specification of a degree of concurrency in testing separate functional portions of a semiconductor device. For a test flow with multiple sub-flows; the pins accessed in connection with each sub-flow may define a flow domain. Site regions, each associated with a flow domain, may be defined. Tester sites may be associated with each of these flow domain specific site regions and independently operating resources may be assigned to these tester sites. A second portion of the defined site regions may be associated with tester sites, but resources assigned to these site regions may be accessed from multiple flow domains. Test blocks, even if not developed for concurrent execution, may be executed concurrently using resources in the flow domain specific site regions. Flexibility is provided to share resources through the use of the second portion of the site regions. | 04-25-2013 |
20130109109 | SUBSTRATE HEAT TREATING APPARATUS, TEMPERATURE CONTROL METHOD OF SUBSTRATE HEAT TREATING APPARATUS, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, TEMPERATURE CONTROL PROGRAM OF SUBSTRATE HEAT TREATING APPARATUS, AND RECORDING MEDIUM | 05-02-2013 |
20130130408 | MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED DEVICE - In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape. | 05-23-2013 |
20130137193 | SYSTEMS AND METHODS FOR PREPARATION OF SAMPLES FOR SUB-SURFACE DEFECT REVIEW - One embodiment relates to a method of preparation of a sample of a substrate for sub-surface review using a scanning electron microscope apparatus. A defect at a location indicated in a first results file is re-detected, and the location of the defect is marked with at least one discrete marking point having predetermined positioning relative to the location of the defect. The location of the defect may be determined relative to the design for the device, and a cut location and a cut angle may be determined in at least a partly-automated manner using that information. Another embodiment relates to a system for preparing a sample for sub-surface review. Another embodiment relates to a method for marking a defect for review on a target substrate. Other embodiments, aspects and feature are also disclosed. | 05-30-2013 |
20130149799 | WAFER TEMPERATURE CORRECTION SYSTEM FOR ION IMPLANTATION DEVICE - To provide an ion implantation device capable of correcting the temperature of the wafer. The ion implantation device of the present invention has: an irradiation means that radiates ions; a retention means that includes a disk | 06-13-2013 |
20130157387 | Multi-zone EPD Detectors - The present disclosure relates to a semiconductor body etching apparatus having a multi-zone end point detection system. In some embodiments, the multi-zone end point detection system has a processing chamber that houses a workpiece that is etched according to an etching process. A plurality of end point detector (EPD) probes are located within the processing chamber. Respective EPD probes are located within different zones in the processing chamber, thereby enabling the detection of end point signals from multiple zones within the processing chamber. The detected end point signals are provided from the plurality of EPD probes to an advanced process control (APC) unit. The APC unit is configured to make a tuning knob adjustment to etching process parameters based upon the detected end point signals and to thereby account for etching non-uniformities. | 06-20-2013 |
20130171745 | ENERGY METER CALIBRATION AND MONITORING - A method of controlling a thermal treatment process for semiconductor substrates is described. A substrate is disposed in a thermal process chamber. A plurality of test locations are identified on the substrate surface, and the test locations are processed with different combinations of energy fluence and exposure duration. A physical property such as reflectivity is measured for each test process, and the data compared to a standard data set. The performance of the process is thus compared to a known physical quantity, and an adjustment applied to correct performance of the thermal processing apparatus. | 07-04-2013 |
20130189800 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus is provided which includes an inert gas supply route connected to a process gas supply piping which supplies a process gas into a processing chamber in a vacuum vessel, a valve which opens or closes the inert gas supply route, and an adjuster which adjusts a flow rate of the inert gas. When processing of a sample is complete, an inert gas is supplied into the process gas supply piping so that a pressure in the process gas supply piping is maintained at a pressure higher than a pressure at which a compound of the process gas and a material of an inner wall of the process gas supply piping vaporizes. | 07-25-2013 |
20130196453 | PRESUMABLY DEFECTIVE PORTION DECISION APPARATUS, PRESUMABLY DEFECTIVE PORTION DECISION METHOD, FABRICATION METHOD FOR SEMICONDUCTOR DEVICE AND PROGRAM - Disclosed herein is a presumably defective portion decision apparatus, including: an arithmetic operation section configured to divide a level difference included in level difference data which indicate a level difference distribution on the surface of a semiconductor device into two or more unit level differences in the depthwise direction of the level difference and determine, for each of the unit level differences obtained by the division, a relationship between the height of a contour line at a level difference position of an upper face and an area of an opening surrounded by the contour line to decide presence or absence of a presumably defective portion. | 08-01-2013 |
20130196454 | VAPOR DEPOSITION METHOD, VAPOR DEPOSITION DEVICE AND ORGANIC EL DISPLAY DEVICE - A coating film ( | 08-01-2013 |
20130210171 | METHOD FOR MOLECULAR ADHESION BONDING WITH COMPENSATION FOR RADIAL MISALIGNMENT - A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment. | 08-15-2013 |
20130217152 | SYSTEMS AND METHODS FOR FLEXIBLE COMPONENTS FOR POWERED CARDS AND DEVICES - Die may be thinned using a thinning and/or a polishing process. Such thinned die may be flexible and may change operational characteristics when flexed. The flexible die may be applied to a mechanical carrier (e.g., a PCB) of a card or device. Detection circuitry may also be provided on the PCB and may be used to detect changed operational characteristics. Such detection circuitry may cause a reaction to the changed characteristics by controlling other components on the card or device based upon the flex-induced changed characteristics. The thinned die may be stacked, interconnected, and encapsulated between sheets of laminate material to form a flexible card or device. | 08-22-2013 |
20130236989 | SIDEWALL AND CHAMFER PROTECTION DURING HARD MASK REMOVAL FOR INTERCONNECT PATTERNING - A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process. | 09-12-2013 |
20130236990 | COATING APPARATUS AND MANUFACTURING METHOD OF COATED BODY - According to one embodiment, a coating apparatus includes a stage having a mounting surface on which a coating target is mounted, a rotating mechanism that rotates the stage, a coating nozzle that discharges a coating material, a moving mechanism that moves the coating nozzle, a supply device that supplies a material to the coating nozzle, an ejection device that ejects the material, a communication tube that allows the supply device, and a valve device. Further, the coating apparatus includes a control unit which rotates the stage by the rotating mechanism, switches the valve device to achieve the continuity of the supply unit and the coating nozzle, drives the moving mechanism to move the coating nozzle, and applies the coating material to the coating target on the stage. | 09-12-2013 |
20130267044 | SUPERIOR INTEGRITY OF HIGH-K METAL GATE STACKS BY PRESERVING A RESIST MATERIAL ABOVE END CAPS OF GATE ELECTRODE STRUCTURES - When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance. | 10-10-2013 |
20130273669 | Method for improving Uniformity of Chemical-Mechanical Planarization Process - The invention provides a method for improving uniformity of chemical-mechanical planarization process, comprising the steps of: forming features on a substrate; forming a first dielectric isolation layer between the features; planarizing the first dielectric isolation layer until the features are exposed, causing the first dielectric isolation layer between the features to have a recess depth; forming a second dielectric isolation layer on the features and the first dielectric isolation layer, whereby reducing the difference in height between the second dielectric isolation layer between the features and the second dielectric isolation layer on the top of the features; planarizing the second dielectric isolation layer until the features are exposed. According to the method for improving uniformity of chemical-mechanical planarization process of the invention, a dielectric isolation layer is formed again after grinding the dielectric isolation layer on the top of the features, such that the difference in height between the dielectric layer between the features and the dielectric layer on the top of the features is effectively reduced, and the recess of the features is compensated, the within-in-die uniformity is effectively improved. | 10-17-2013 |
20130273670 | Concentration Measuring Device used in Manufacturing Process - A semiconductor manufacturing system comprises a main body that exclusively flows a first fluid that is used in a manufacturing process and a second fluid whose concentration is known, and that outputs a state signal showing whether or not the fluid flowing in the flow channel is the second fluid and a concentration measuring device having a concentration measuring part that measures a concentration of a predetermined component in the fluid flowing in the flow channel, a state signal receiving part that receives the state signal from the main body, and a correcting part that obtains a reference measurement value as being a measurement value measured by the concentration measuring part during a period while it is judged that the second fluid flows in the flow channel by the state signal and that corrects the concentration measuring part based on the reference measurement value. | 10-17-2013 |
20130280823 | Apparatus for Monitoring Ion Implantation - An apparatus for monitoring an ion distribution of a wafer comprises a first sensor and a sensor. The first sensor, the second senor and the wafer are placed in an effective range of a uniform ion implantation current profile. A controller determines the ion dose of each region of the wafer based upon the detected signal from the first sensor and the second senor. In addition, the controller adjusts the scanning frequency of an ion beam or the movement speed of the wafer to achieve a uniform ion distribution on the wafer. | 10-24-2013 |
20130302916 | METHODS AND APPARATUSES FOR HIGH PRESSURE GAS ANNEALING - Novel methods and apparatuses for annealing semiconductor devices in a high pressure gas environment. According to an embodiment, the annealing vessel has a dual chamber structure, and potentially toxic, flammable, or otherwise reactive gas is confined in an inner chamber which is protected by pressures of inert gas contained in the outer chamber. The incoming gas delivery system and exhaust gas venting system are likewise protected by various methods. Embodiments of the present invention can be used, for example, for high-K gate dielectric anneal, post metallization sintering anneal, and forming gas anneal in the semiconductor manufacturing process. | 11-14-2013 |
20130330843 | METHOD OF MANUFACTURING SCALED EQUIVALENT OXIDE THICKNESS GATE STACKS IN SEMICONDUCTOR DEVICES AND RELATED DESIGN STRUCTURE - A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH | 12-12-2013 |
20130330844 | Laser annealing systems and methods with ultra-short dwell times - Laser annealing systems and methods for annealing a semiconductor wafer with ultra-short dwell times are disclosed. The laser annealing systems can include one or two laser beams that at least partially overlap. One of the laser beams is a pre-heat laser beam and the other laser beam is the annealing laser beam. The annealing laser beam scans sufficiently fast so that the dwell time is in the range from about 1 μs to about 100 μs. These ultra-short dwell times are useful for annealing product wafers formed from thin device wafers because they prevent the device side of the device wafer from being damaged by heating during the annealing process. Embodiments of single-laser-beam annealing systems and methods are also disclosed. | 12-12-2013 |
20130337584 | SHAPE SIMULATION APPARATUS, SHAPE SIMULATION PROGRAM, SEMICONDUCTOR PRODUCTION APPARATUS, AND SEMICONDUCTOR DEVICE PRODUCTION METHOD - Disclosed herein is a shape simulation apparatus including: a flux computation block configured to compute the flux of particles incident on the surface of a wafer covered with a mask; and a shape computation block configured to compute a surface shape of the wafer by allowing the coordinates of a plurality of calculation points established on the surface of the wafer to be time-evolved based on the incident flux computed. | 12-19-2013 |
20130344624 | SEMICONDUCTOR MANUFACTURING OPTIMIZATION BY COMBINING SMALL LOTS INTO INDIVIDUAL CARRIERS - An integrated circuit is formed by identifying process parameters of a plurality of process steps for the first partial lot containing the integrated circuit; confirming the number of wafers in the first partial lot is less than the wafer carrier capacity; examining lots upstream of the partial lot and identifying a second partial lot which can be combined with the first partial lot into a single wafer carrier and which can be processed with the first partial lot; combining the wafers of the partial lots into a single wafer carrier; processing the partial lots through the plurality of process steps; and performing a multi-lot verification process. The multi-lot verification process determines if all wafers in the partial lots have completed the process step; determines if any wafers in the partial lots are on hold; and determining if all wafers in the partial lots are in a same material carrier. | 12-26-2013 |
20140004626 | TEMPERATURE CONTROL OF CHEMICAL MECHANICAL POLISHING | 01-02-2014 |
20140011302 | SPACER FOR A GATE ELECTRODE HAVING TENSILE STRESS AND A METHOD OF FORMING THE SAME - By reducing a deposition rate and maintaining a low bias power in a plasma atmosphere, a spacer layer, for example a silicon nitride layer, may be deposited that exhibits tensile stress. The amount of tensile stress is controllable within a wide range, thereby providing the potential for forming sidewall spacer elements that modify the charge carrier mobility and thus the conductivity of the channel region of a field effect transistor. | 01-09-2014 |
20140024142 | SPECTRAL REFLECTOMETRY WINDOW HEATER - A plasma processing tool for fabricating a semiconductor device on a semiconductor wafer includes an optical window disposed on a plasma chamber, remotely from a plasma region. The window is thermally connected to an electrical heater element capable of maintaining the window at a temperature of at least 30° C. A heater controller provides electrical power to the heater element. During operation of the plasma processing tool, the heater controller provides power to the heater element so as to maintain the window at a temperature of at least 30° C. during at least a portion of a plasma process step in which by-products are produced in the plasma chamber. | 01-23-2014 |
20140030825 | APPARATUS FOR MANUFACTURING AN INORGANIC THIN-FILM SOLAR CELL, AND METHOD FOR CONTROLLING SAME - The present invention relates to an apparatus for manufacturing an inorganic thin-film solar cell, the apparatus including: a substrate stage which is mounted in a chamber and in which a solar cell substrate is disposed; and an inorganic powder supply unit including a nozzle configured to discharge an inorganic powder aerosol containing an inorganic powder onto the substrate stage in a supersonic flow so as to form a solar cell layer on the solar cell substrate, and an inorganic powder supply portion configured to supply the inorganic powder aerosol to the nozzle. | 01-30-2014 |
20140045278 | Method of Manufacturing Semiconductor Device, Method of Processing Substrate and Substrate Processing Apparatus - A method of manufacturing a semiconductor device includes: (a) supplying a first process gas from a first process gas supply unit into a process chamber via a flow rate control device to form a film on a substrate; (b) transmitting a signal representing an exhaust pressure detected by a pressure detector to a controller after the first process gas is supplied into the process chamber; (c) controlling a pressure adjustor and the flow rate control device once the signal is received by the controller such that the exhaust pressure reaches a predetermined pressure; (d) supplying a purge gas from a purge gas supply unit into the process chamber to purge an inside atmosphere after forming the first film; and (e) supplying a second process gas from a second process gas supply unit into the process chamber via the flow rate control device to form a second film. | 02-13-2014 |
20140045279 | Semiconductor Component and Method for Producing a Semiconductor Component - A method can be used to produce a semiconductor component. A semiconductor layer sequence has an active region that is provided for generating radiation and also has an indicator layer. Material of the semiconductor layer sequence that is arranged on that side of the indicator layer that is remote from the active region is removed in regions. The material is removed using a dry-chemical removal of the semiconductor layer sequence. A property of a process gas is monitored during the removal to determine that the indicator layer has been reached based on a change in the property of the process gas. | 02-13-2014 |
20140065730 | IMPLANT-INDUCED DAMAGE CONTROL IN ION IMPLANTATION - An ion implantation system is provided having an ion implantation apparatus configured to provide a spot ion beam having a beam density to a workpiece, wherein the workpiece has a crystalline structure associated therewith. A scanning system iteratively scans one or more of the spot ion beam and workpiece with respect to one another along one or more axes. A controller is also provided and configured to establish a predetermined localized temperature of the workpiece as a predetermined location on the workpiece is exposed to the spot ion beam. A predetermined localized disorder of the crystalline structure of the workpiece is thereby achieved at the predetermined location, wherein the controller is configured to control one or more of the beam density of the spot ion beam and a duty cycle associated with the scanning system to establish the localized temperature of the workpiece at the predetermined location on the workpiece. | 03-06-2014 |
20140073065 | MICROWAVE ANNEALING APPARATUS AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - According to one embodiment, a microwave annealing apparatus is provided, including a housing shielding electromagnetic waves, a first electromagnetic wave source configured to apply a first electromagnetic wave into the housing, a second electromagnetic wave source configured to apply, into the housing, a second electromagnetic wave having a higher frequency than the first electromagnetic wave, a susceptor configured to hold a semiconductor substrate, made of a material transparent to the first electromagnetic wave and provided in the housing, a temperature measuring device configured to measure the temperature of the semiconductor substrate, and a control unit configured to control the power of each of the first and second electromagnetic wave sources in accordance with the temperature measured by the temperature measuring device. | 03-13-2014 |
20140073066 | PLASMA ETCHING APPARATUS AND CONTROL METHOD - In a control method, a first processing is performed on an object to be processed by controlling a temperature of a base to a first temperature and controlling a temperature of an electrostatic chuck that is disposed on a mounting surface of the base so as to mount thereon the object to be processed and has a heater installed therein to a second temperature. A second processing is performed on the object by controlling a temperature of the base to a third temperature and controlling a temperature of the electrostatic chuck to a fourth temperature by a heater. In the control method, a difference between the first temperature and the second temperature and a difference between the third temperature and the fourth temperature are within a tolerable temperature of the junction layer for bonding the base and the electrostatic chuck. | 03-13-2014 |
20140073067 | WAFER PROCESSING METHOD - A wafer processing method divides a wafer along a plurality of crossing streets formed on the front side of the wafer to thereby partition a plurality of regions where a plurality of devices are respectively formed. The method includes a division groove forming step of cutting the back side of the wafer along each street by using a cutting blade to thereby form a division groove along each street with a predetermined thickness left between the bottom of the division groove and the front side of the wafer, a wafer supporting step of attaching the back side of the wafer to a dicing tape supported by an annular frame, and a wafer dividing step of applying an external force to the wafer attached to the dicing tape to thereby divide the wafer into the individual devices along the streets where the division grooves are respectively formed. | 03-13-2014 |
20140080229 | ADAPTIVE SEMICONDUCTOR PROCESSING USING FEEDBACK FROM MEASUREMENT DEVICES - A semiconductor processing device and a method of operating the same. The method may include measuring at least one property of a semiconductor wafer and determining a recipe for processing the semiconductor wafer based on the at least one property. The semiconductor wafer may be processed with a plurality of chemical mechanical polishing (CMP) modules based on the determined recipe, wherein the recipe comprises a value of at least one parameter for use by each of the plurality of CMP modules. The measurements may be made in situ or by an inline metrology device. The recipe and various parameters associated with the recipe may be determined by a controller of the semiconductor processing device. | 03-20-2014 |
20140087488 | SHOWERHEAD ELECTRODE ASSEMBLY IN A CAPACITIVELY COUPLED PLASMA PROCESSING APPARATUS - A showerhead electrode assembly for use in a capacitively coupled plasma processing apparatus comprising a heat transfer plate. The heat transfer plate having independently controllable gas volumes which may be pressurized to locally control thermal conductance between a heater member and a cooling member such that uniform temperatures may be established on a plasma exposed surface of the showerhead electrode assembly. | 03-27-2014 |
20140087489 | BOTTOM AND SIDE PLASMA TUNING HAVING CLOSED LOOP CONTROL - An apparatus for plasma processing a substrate is provided. The apparatus comprises a processing chamber, a substrate support disposed in the processing chamber, and a lid assembly coupled to the processing chamber. The lid assembly comprises a conductive gas distributor coupled to a power source. A tuning electrode may be disposed between the conductive gas distributor and the chamber body for adjusting a ground pathway of the plasma. A second tuning electrode may be coupled to the substrate support, and a bias electrode may also be coupled to the substrate support. | 03-27-2014 |
20140093984 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE TRANSFER METHOD AND STORAGE MEDIUM - In a substrate processing apparatus | 04-03-2014 |
20140106474 | SYSTEMS AND METHODS OF AUTOMATICALLY DETECTING FAILURE PATTERNS FOR SEMICONDUCTOR WAFER FABRICATION PROCESSES - A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process. | 04-17-2014 |
20140113389 | Multi-Wafer Reactor - A solution for manufacturing semiconductors is provided. An embodiment provides a chemical vapor deposition reactor, which includes a chemical vapor deposition chamber. A substrate holder located in the chemical vapor deposition chamber can be rotated about its own axis at a first angular speed, and a gas injection component located in the chemical vapor deposition chamber can be rotated about an axis of the gas injection component at a second angular speed. The angular speeds are independently selectable and can be configured to cause each point on a surface of a substrate wafer to travel in an epicyclical trajectory within a gas flow injected by the gas injection component. An angle between the substrate holder axis and the gas injection component axis and/or a distance between the substrate holder axis and the gas injection component axis can be controlled variables. | 04-24-2014 |
20140120636 | SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND THERMOCOUPLE SUPPORT - A substrate processing apparatus includes: a reaction tube configured to accommodate a substrate holder holding a plurality of substrates and process a substrate held on the substrate holder; a heating unit installed outside the reaction tube and configured to heat an inside of the reaction tube; a protection tube installed to extend in a vertical direction in contact with an outer wall of the reaction tube; an insulating tube disposed inside the protection tube and having through-holes extending in a vertical direction; a thermocouple having a thermocouple junction provided at an upper end thereof, and thermocouple wires joined at the thermocouple junction and inserted into the through-holes of the insulating tube; a gas supply unit configured to supply a gas, for processing a substrate accommodated in the reaction tube, into the reaction tube; and an exhaust unit configured to exhaust a gas from the reaction tube. | 05-01-2014 |
20140127833 | DEPOSITION AMOUNT MEASURING APPARATUS, DEPOSITING APPARATUS INCLUDING THE SAME, AND METHOD FOR MANUFACTURING LIGHT EMITTING DISPLAY - A deposition amount measuring apparatus includes a plate-shaped body having a rotating shaft, a plurality of deposition amount sensors along side surfaces of the body, the deposition amount sensors being configured to measure an amount of deposition material, and a housing surrounding the body, the housing including an inflow port that exposes one of the deposition amount sensors. | 05-08-2014 |
20140127834 | METHODS FOR LIQUID TRANSER COATING OF THREE-DIMENSIONAL SUBSTRATES - Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate. | 05-08-2014 |
20140141534 | dielectric doping using high productivity combinatorial methods - A combination of deposition processes can be used to evaluate layer properties using a combinatorial workflow. The processes can include a base ALD process and another process, such as a PVD process. The high productivity combinatorial technique can provide an evaluation of the material properties for given ALD base layer and PVD additional elements. An ALD process can then be developed to provide the desired layers, replacing the ALD and PVD combination. | 05-22-2014 |
20140141535 | METHOD FOR ALIGNING SUBSTRATE AND MASK AND METHOD FOR PREPARING SEMICONDUCTOR DEVICE - The invention relates to the technical field of an alignment method, and discloses a method for aligning substrate and mask, including: firstly forming at least one set of alignment marks on a mask plate; selecting a certain number of large-size substrates as sample substrates; forming a plurality of sets of alignment marks on each sample substrate using the mask plate and the at least one set of alignment marks formed thereon to divide the sample substrate into a plurality of sub-substrate areas; and then performing mask process on the respective sample substrates, accurate alignment for each sub-substrate area can be realized by means of the plurality of sets of alignment marks on the sample substrate, and one sub-substrate area can be accurately aligned by means of at least two sets of alignment marks formed on the sample substrate. In the alignment, positions of the plurality of sets of alignment marks formed on the sample substrate are recorded and stored, and mask process on a non-sample substrate is performed based on parameters relating to the stored positions of the plurality of sets of alignment marks, thus the seaming degree between patterns in the same layer and the coincidence degree between patterns in different layers on the non-sample substrate are guaranteed, so that mass production for large-size substrates with good quality can be realized. The invention also discloses a method for preparing semiconductor device. | 05-22-2014 |
20140141536 | Method and System for Providing a Target Design Displaying High Sensitivity to Scanner Focus Change - A segmented mask includes a set of cell structures, wherein each cell structure includes a set of features having an unresolvable segmentation pitch along a first direction, wherein the unresolvable segmentation pitch along the first direction is smaller than the illumination of the lithography printing tool, wherein the plurality of cell structures have a pitch along a second direction perpendicular to the first direction, wherein the unresolvable segmentation pitch is suitable for generating a printed pattern for shifting the best focus position of the lithography tool by a selected amount to achieve a selected level of focus sensitivity. | 05-22-2014 |
20140141537 | PRODUCTION OF HIGH PRECIPITATE DENSITY WAFERS BY ACTIVATION OF INACTIVE OXYGEN PRECIPITATE NUCLEI - Processes for the treatment of silicon wafers to form a high density non-uniform distribution of oxygen precipitate nuclei therein such that, upon being subjected to the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, the wafers form oxygen precipitates in the bulk and a precipitate-free zone near the surface are disclosed. The processes involve activation of inactive oxygen precipitate nuclei by performing heat treatments between about 400° C. and about 600° C. for at least about 1 hour. | 05-22-2014 |
20140170781 | DOUBLE SIDE POLISHER WITH PLATEN PARALLELISM CONTROL - A platen for polishing a surface of a wafer has a reaction plate, a polishing plate, and a bladder. The reaction plate has a top and bottom surface, and defines a longitudinal axis. The polishing plate is positioned coaxially with the reaction plate. The polishing plate has a second top surface and a second bottom surface. The second top surface is adjacent to the bottom surface of the reaction plate. The bladder is coaxially located along a radially outer portion of either the top or bottom surface of the reaction plate. The bladder is connected with the polishing plate and able to expand to deform the polishing plate with respect to the bottom surface of the reaction plate. | 06-19-2014 |
20140186974 | MEASUREMENT DEVICE AND METHOD FOR VAPOUR DEPOSITION APPLICATIONS - In vapour deposition applications, especially OLED mass production, where it is necessary to measure and/or control the deposition rate of evaporation sources within specific tolerances, a measurement system is adapted to use robust and accurate optical thickness measurement methods at high and low rate sources, so that the thickness of a layer deposited on a substrate can be measured and controlled. A first evaporation source ( | 07-03-2014 |
20140199785 | MULTIZONE CONTROL OF LAMPS IN A CONICAL LAMPHEAD USING PYROMETERS - A method and apparatus for processing a semiconductor substrate is described. The apparatus is a process chamber having an optically transparent upper dome and lower dome. Vacuum is maintained in the process chamber during processing. The upper dome is thermally controlled by flowing a thermal control fluid along the upper dome outside the processing region. Thermal lamps are positioned proximate the lower dome, and thermal sensors are disposed among the lamps. The lamps are powered in zones, and a controller adjusts power to the lamp zones based on data received from the thermal sensors. | 07-17-2014 |
20140199786 | RAPID CONDUCTIVE COOLING USING A SECONDARY PROCESS PLANE - In one embodiment, a substrate processing apparatus includes a chamber having an interior volume with an upper portion and a lower portion, a cooling source disposed in the upper portion of the interior volume, a heating source opposing the cooling source, a magnetically movable substrate support that moves between the upper portion and the lower the portion, and a plurality of sensors coupled to the chamber to detect the position of the substrate support relative to the heating source and the cooling source | 07-17-2014 |
20140199787 | Semiconductor Mask Blanks with a Compatible Stop Layer - Provided is a method for creating a mask blank that includes a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detection of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer. | 07-17-2014 |
20140199788 | Floating substrate monitoring and control device, and method for the same - Disclosed is a process tunnel ( | 07-17-2014 |
20140206108 | HEAT TREATMENT APPARATUS AND HEAT TREATMENT METHOD FOR HEATING SUBSTRATE BY IRRADIATING SUBSTRATE WITH FLASH OF LIGHT - A flash heating part in a heat treatment apparatus includes 30 built-in flash lamps, and irradiates a semiconductor wafer held by a holder in a chamber with a flash of light. Thirty switching elements are provided in a one-to-one correspondence with the 30 flash lamps. Each of the switching elements defines the waveform of current flowing through a corresponding one of the flash lamps by intermittently supplying electrical charge thereto. Radiation thermometers measure an in-plane temperature distribution of the semiconductor wafer during flash irradiation. Based on the results of measurement with the radiation thermometers, a controller individually controls the operations of the 30 switching elements to individually define the light emission patterns of the 30 flash lamps. | 07-24-2014 |
20140212994 | SELF ALIGNED DUAL PATTERNING TECHNIQUE ENHANCEMENT WITH MAGNETIC SHIELDING - Embodiments of the present disclosure generally provide apparatus and method for improving processing uniformity by reducing external magnetic noises. One embodiment of the present disclosure provides an apparatus for processing semiconductor substrates. The apparatus includes a chamber body defining a vacuum volume for processing one or more substrate therein, and a shield assembly for shielding magnetic flux from the chamber body disposed outside the chamber body, wherein the shield assembly comprises a bottom plate disposed between the chamber body and the ground to shield magnetic flux from the earth. | 07-31-2014 |
20140220709 | CONTROLLING CD AND CD UNIFORMITY WITH TRIM TIME AND TEMPERATURE ON A WAFER BY WAFER BASIS - Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile. | 08-07-2014 |
20140220710 | SYSTEM FOR NON RADIAL TEMPERATURE CONTROL FOR ROTATING SUBSTRATES - Embodiments of the present invention provide apparatus and method for reducing non uniformity during thermal processing. One embodiment provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to rotate the substrate, a sensor assembly configured to measure temperature of the substrate at a plurality of locations, and one or more pulse heating elements configured to provide pulsed energy towards the processing volume. | 08-07-2014 |
20140234991 | Thermal processing apparatus for thermal processing substrate and positioning method of positioning substrate transfer position - A substrate holder positioning method, capable of positioning a substrate holder without using any positioning jig, includes: measuring a first position of a substrate held on a substrate holder included in a substrate carrying mechanism; carrying the substrate held on the substrate holder to a substrate rotating unit for holding and rotating the substrate; turning the substrate held by the substrate rotating unit through a predetermined angle by the substrate rotating unit; transferring the substrate turned by the substrate rotating unit from the substrate rotating unit to the substrate holder; measuring a second position of the substrate transferred from the substrate rotating unit to the substrate holder; determining the position of the center of rotation of the substrate rotating unit on the basis of the first and the second position; and positioning the substrate holder on the basis of the position of the center of rotation. | 08-21-2014 |
20140256065 | ETCHING METHOD - There is provided an etching method. A temperature at a plurality of predetermined positions on an upper surface of an Si substrate is measured during the etching processing. The etching processing includes supplying an etching solution to the upper surface of the Si substrate. An exothermic reaction occurs in the etching processing. The upper surface is heated or cooled depending on the measured value. | 09-11-2014 |
20140273290 | SOLVENT ANNEAL PROCESSING FOR DIRECTED-SELF ASSEMBLY APPLICATIONS - A method and apparatus for solvent annealing a layered substrate including a layer of a block copolymer are provided. The method includes (a) introducing an annealing gas into a processing chamber; (b) maintaining the annealing gas in the processing chamber for a first time period; (c) removing the annealing gas from the processing chamber; and (d) repeating steps (a)-(c) a plurality of times in order induce the block copolymer to undergo cyclic self-assembly. The apparatus includes a processing chamber comprising a process space; a substrate support in the process space; an annealing gas supply and a purge gas supply, both in fluid communication with the process space; a heating element positioned within the processing chamber; an exhaust port in the processing chamber; and a sequencing device programmed to control the annealing gas supply, the heating element, the isolation valve of the exhaust port, and the purge gas supply. | 09-18-2014 |
20140273291 | Wafer Strength by Control of Uniformity of Edge Bulk Micro Defects - A method is provided for qualifying a semiconductor wafer for subsequent processing, such as thermal processing. A plurality of locations are defined about a periphery of the semiconductor wafer, and one or more properties, such as oxygen concentration and a density of bulk micro defects present, are measured at each of the plurality of locations. A statistical profile associated with the periphery of the semiconductor wafer is determined based on the one or more properties measured at the plurality of locations. The semiconductor wafer is subsequently thermally treated when the statistical profile falls within a predetermined range. The semiconductor wafer is rejected from subsequent processing when the statistical profile deviates from the predetermined range. As such, wafers prone to distortion, warpage, and breakage are rejected from subsequent thermal processing. | 09-18-2014 |
20140273292 | METHODS OF FORMING SILICON NITRIDE SPACERS - Embodiments of methods of forming silicon nitride spacers are provided herein. In some embodiments, a method of forming silicon nitride spacers atop a substrate includes: depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate; modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and removing the modified portion of the silicon nitride layer by performing a wet cleaning process to form the silicon nitride spacers, wherein the wet cleaning process removes the modified portion of the silicon nitride layer selectively to the silicon containing layer. | 09-18-2014 |
20140273293 | Portable Wireless Sensor - The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a portable device. The portable device includes first and second sensors that respectively measure first and second fabrication process parameters. The first fabrication process parameter is different from the second fabrication process parameter. The portable device also includes a wireless transceiver that is coupled to the first and second sensors. The wireless transceiver receives the first and second fabrication process parameters and transmits wireless signals containing the first and second fabrication process parameters. | 09-18-2014 |
20140287539 | FILM FORMATION APPARATUS AND FILM FORMATION METHOD - At the time of transporting a substrate into or from a space where a film formation process is performed, the space where the film formation process is performed, a space where a lower heater | 09-25-2014 |
20140302620 | METHOD FOR MANUFACTURING SOLAR CELL - A method for manufacturing a solar cell capable of significantly reducing the amount of wastewater generated during a wet-etching process and improving the efficiency of the solar cell. A method comprising: texturing to form an uneven structure on one semiconductor substrate surface by etching the semiconductor substrate surface with a texturing device; forming a temporary layer at an upper portion of the semiconductor substrate surface to surround a first byproduct layer formed at a predetermined region of the semiconductor substrate surface during the texturing; and doping the semiconductor substrate surface with a predetermined dopant using a doping device to form a first semiconductor layer and a second semiconductor layer disposed above the first semiconductor layer and having a different polarity than the first semiconductor layer. The first byproduct layer and the temporary layer are simultaneously removed. | 10-09-2014 |
20140308761 | Sidewall Image Transfer Process - A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed. | 10-16-2014 |
20140308762 | ADJUSTABLE DUMMY FILL - A method of placing a dummy fill layer on a substrate is disclosed (FIG. | 10-16-2014 |
20140335631 | SEMICONDUCTOR DEFECT CHARACTERIZATION - The defect-containing die identified from an inspection layer analysis subsequent to a manufacturing step for a wafer including a plurality of die and as well as the faulty die identified from a fault testing of the wafer are processed to identify a subset of the die that both contain a defect and are faulty. A probability analysis is performed to determine a confidence level of whether the die in the subset are faulty due to their defects. | 11-13-2014 |
20140342471 | Variable Doping Of Solar Cells - A system and method for determining the edge or region where a saw first enters a silicon brick, and using this information to process this region differently is disclosed. This region, referred to as the saw entry region, may be thinner, or have a rougher texture than the rest of the substrate. This difference may impact the substrate's ultimate performance. For example, if the substrate is processed as a solar cell, the performance of the saw entry region may be suboptimal. | 11-20-2014 |
20140349417 | System, Method and Apparatus for RF Power Compensation in Plasma Etch Chamber - A system and method of applying power to a target plasma chamber include, characterizing a no plasma performance slope of the target plasma chamber, applying a selected plasma recipe to a first wafer in the target chamber, the selected plasma recipe includes a selected power set point value and monitoring a recipe factor value on the RF electrode. A ratio of process efficiency is generated comparing the reference chamber and the target chamber, the generating using as inputs the no plasma performance slopes of the target chamber and the reference chamber and the monitored recipe factor value. An adjusted power set point value is calculated, the adjusted power set point configured to cause power delivered to a plasma formed in the target chamber to match power that would be delivered to a reference plasma formed in the reference chamber. | 11-27-2014 |
20140349418 | PLASMA PROCESSING METHOD - A plasma processing method in which a stable process region can be ensured in a wide range, from low microwave power to high microwave power. The plasma processing method includes making production of plasma easy in a region in which production of plasma by continuous discharge is difficult, and plasma-processing an object to be processed, with the generated plasma, wherein the plasma is produced by pulsed discharge in which ON and OFF are repeated, radio-frequency power for producing the pulsed discharge, during an ON period, is a power to facilitate production of plasma by continuous discharge, and a duty ratio of the pulsed discharge is controlled so that an average power of the radio-frequency power per cycle is power in the region in which production of plasma by continuous discharge is difficult. | 11-27-2014 |
20140356980 | METHOD AND PROCESS TO REDUCE STRESS BASED OVERLAY ERROR - Thermal processing and alignment methods and processes used during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device after at least one laser annealing process is completed, the device including a substrate surface and at least one layer over the substrate surface; applying a mask layer to the at least one layer; performing lithography on the mask layer to form a top layer; positioning a first contact-to-gate layer over the top layer; checking alignment of electrical connections between the substrate surface and the first contact-to-gate layer; and determining if an adjustment is needed to at least one parameter of at least one laser annealing beam used during the laser annealing process. In enhanced aspects, the at least one laser annealing process includes: performing three laser anneals; applying three mask layers; and performing lithography three times. | 12-04-2014 |
20140356981 | WAFER BONDING MISALIGNMENT REDUCTION - A method for wafer bonding includes measuring grid distortion for a mated pairing of wafers to be bonded to determine if misalignment exists between the wafers. During processing of subsequent wafers, magnification of one or more lithographic patterns is adjusted to account for the misalignment. The subsequent wafers are bonded with reduced misalignment. | 12-04-2014 |
20140356982 | METHODS FOR OVERLAY IMPROVEMENT THROUGH FEED FORWARD CORRECTION - Methods and processes for establishing a rework threshold for layers applied after thermal processing during fabrication of semiconductor devices are provided. One method includes, for instance: obtaining a device after at least one laser annealing process is completed, the device including a substrate surface and at least one layer over the substrate surface; performing lithography on the at least one layer; positioning a first contact-to-gate layer over the at least one layer; checking alignment of electrical connections between the substrate surface and the first contact-to-gate layer; determining if an overlay error is present; and adjusting at least one subsequent fabrication process pursuant to the overlay error. | 12-04-2014 |
20140363903 | SUBSTRATE TREATING APPARATUS AND METHOD OF TREATING SUBSTRATE - A substrate treating apparatus including: a chamber capable of accommodating a substrate; a treating part which conducts a predetermined treatment associated with forming a coating film containing a metal to the substrate accommodated in the chamber; and a detection part which detects a concentration of a predetermined gas containing a chalcogen element within a gas inside the chamber. | 12-11-2014 |
20140370623 | EVAPORATION APPARATUS AND METHOD - An evaporation apparatus comprises a chamber configured to contain at least one dispensing nozzle and at least one substrate to be coated. The chamber has at least one adjustable shielding member defining an adjustable aperture. The member is positioned between the at least one dispensing nozzle and the at least one substrate. The aperture is adjustable in at least one of the group consisting of area and shape. The at least one adjustable shielding member has a heater. | 12-18-2014 |
20140370624 | WAFER ALIGNMENT AND BONDING TOOL FOR 3D INTEGRATION - A bonding apparatus for 3D integration may include a plurality of infrared microscopes that emit and receive infrared light for imaging, a first bonding chuck that holds a first semiconductor structure, and a second bonding chuck that holds a second semiconductor structure, whereby the second bonding chuck has a plurality of openings that are transparent to the received infrared light. A force pin is coupled to the first bonding chuck for applying a predetermined force to the first semiconductor structure for bonding to the second semiconductor structure. A temperature controller is coupled to the second bonding chuck, whereby the temperature controller applies a predetermined temperature to the second semiconductor structure, such that, prior to the bonding, the first and the second semiconductor structure are de-aligned with respect to each other using the plurality of infrared microscopes and the plurality of openings. The de-alignment is based on the predetermined force and the application of the predetermined temperature. | 12-18-2014 |
20140377885 | PROCESS FLOW FOR REPLACEMENT METAL GATE TRANSISTORS - A replacement metal gate transistor and methods of forming replacement metal gate transistors are described. Various examples provide methods of manufacturing a replacement metal gate transistor that includes depositing a dielectric layer into a trench, wherein the dielectric layer is deposited onto the bottom of the trench and the sidewalls of the trench, depositing a first metal layer into the trench, wherein the first metal layer is deposited onto the bottom of the trench and the sidewalls of the trench over the dielectric layer, depositing a second metal layer into the trench, wherein the second metal layer is deposited onto the bottom of the trench and the sidewalls of the trench over the first metal layer, removing at least a portion of the second metal layer from the sidewalls of the trench, and depositing a conducting layer into the trench. Other embodiments are disclosed and claimed. | 12-25-2014 |
20140377886 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING GRINDING SEMICONDUCTOR WAFER - A method of manufacturing a semiconductor device according to one embodiment includes: preparing a semiconductor water which is partitioned into a plurality of first semiconductor chips, the plurality of first semiconductor chips including a first group of first semiconductor chips and a second group of first semiconductor chips; providing a second semiconductor chip over at least one of first semiconductor chips of the first group; providing a sealer on the first semiconductor chips of the second group; and grinding one face of the semiconductor wafer which is on the opposite side from a face on which the second semiconductor chip and the sealer are provided. | 12-25-2014 |
20150011022 | METHODS OF DIVIDING LAYOUTS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - Target pattern layouts that include lower and upper target patterns are designed. Each lower target pattern is combined with a upper target pattern that at least partially overlaps a top surface thereof to form combination structures. The combination structures are divided into first and second combination structures. A first target pattern is formed from the lower target pattern in the first combination structure and a third target pattern is formed from the upper target pattern in the first combination structure. The first and third target patterns are formed in first and third lithography processes, respectively. A second target pattern is formed from the lower target pattern in the second combination structure and a fourth target pattern is formed from the upper target pattern in the second combination structure. The second and fourth target patterns are formed in second and fourth lithography processes, respectively. | 01-08-2015 |
20150011023 | MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE - A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes a conductive layer. The conductive layer includes conductive tracks which may be defined by photomasks. The conductive tracks may have quality characteristics. Distinct quality characteristics of distinct conductive tracks may be compared. Based on the comparison, signals and supply voltage may be routed on particular conductive tracks. | 01-08-2015 |
20150011024 | ANALYSIS DEVICE, ANALYSIS METHOD, FILM FORMATION DEVICE, AND FILM FORMATION METHOD - An analysis device includes an X-ray generation part configured to generate four monochromatic X-rays with different energies to irradiate a sample, an electrically conductive sample stage configured to place the sample thereon and formed of an electrically conductive material, an electrode configured to detect an electric current carried by irradiating the sample with the four monochromatic X-rays with different energies, and an electric power source configured to apply a voltage between the electrically conductive sample stage and the electrode, wherein the four monochromatic X-rays with different energies are X-rays included within a range from an absorption edge of a compound semiconductor included in the sample to a higher energy side of 300 eV. | 01-08-2015 |
20150024515 | SYSTEMS, METHODS, AND APPARATUS FOR MINIMIZING CROSS COUPLED WAFER SURFACE POTENTIALS - This disclosure describes systems, methods, and apparatus for reducing a DC bias on a substrate surface in a plasma processing chamber due to cross coupling of RF power to an electrode coupled to the substrate. This is brought about via tuning of a resonant circuit coupled between the substrate and ground based on indirect measurements of harmonics of the RF field level at a surface of the substrate. The resulting reduction in DC bias allows a lower ion energy than possible without this resonant circuit and tuning thereof. | 01-22-2015 |
20150031147 | ORGANIC LIGHT EMITTING DIODE FABRICATION - A method of monitoring an OLED production process for making a production process OLED device, the production process OLED device having a layered structure comprising an anode layer and a cathode layer, said anode and cathode layers sandwiching a hole injection layer, a hole transport layer and at least one organic light emitting layer, the method comprising: fabricating at least one similar OLED device to said production process OLED device, wherein said at least one similar OLED device has a layered structure corresponding to said production process OLED device and a range of hole injection and/or transport layer thicknesses; characterising a spectral variation of a light output of said at least one similar OLED device with respect to variation in said hole injection and/or transport layer thickness; partially fabricating a said production process OLED device using said production process, wherein said partial fabrication comprises depositing one or more layers comprising at least said hole injection and/or transport layer; measuring a thickness of said one or more layers comprising at least said hole injection and/or transport layer; predicting a light output for said partially fabricated production process OLED device, in a target colour space, from said measuring, using said characterised spectral variation; and monitoring said production process using said predicted light output. | 01-29-2015 |
20150044783 | METHODS OF ALLEVIATING ADVERSE STRESS EFFECTS ON A WAFER, AND METHODS OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a forming a semiconductor device comprises forming at least one semiconductor device structure over a surface of a wafer. An opposing surface of the wafer is subjected to at least one chemical-mechanical polishing process to form a modified opposing surface of the wafer comprising at least one recessed region and at least one elevated region. Additional methods of forming a semiconductor device, and methods of reducing stress on a wafer are also described. | 02-12-2015 |
20150050751 | METHOD OF CONTROLLING THRESHOLD VOLTAGE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of controlling a threshold voltage is provided. The method of controlling a threshold voltage includes performing a film-thickness measuring step to measure the thickness of a film layer on a wafer to obtain a film-thickness value. Then, at least one parameter is decided, selected, or generated according to the film-thickness value. Next, an ion implantation process is performed on the wafer, wherein the ion implantation process is executed according to the parameter to form a threshold voltage adjustment region in the wafer below the film layer. | 02-19-2015 |
20150050752 | METHODS FOR CLEANING A WAFER EDGE INCLUDING A NOTCH - In a method for removing metal at the edge of a wafer, including from a notch in the edge of the wafer, water is dripped or otherwise supplied onto the up-facing metal-plated front side of the wafer, while rotating the wafer. A metal etchant, such as sulfuric acid, is provided onto the back side of the wafer, at a flow rate multiple times greater than the water flow rate. The etchant flows over the edge of the wafer and the notch, and onto an annular edge on the front side of the wafer. The metal plated in the notch is removed, even if the notch has a radial depth greater than the width of the exclusion zone. The flow rates of the water and the etchant, and the rotation speed may be adjusted to provide a static water film, with the etchant diffusing into the outer edge of the water film. | 02-19-2015 |
20150050753 | ACCELERATED RELAXATION OF STRAIN-RELAXED EPITAXIAL BUFFERS BY USE OF INTEGRATED OR STAND-ALONE THERMAL PROCESSING - Implementations of the present disclosure generally relate to methods and apparatus for forming a film on a substrate. More particularly, implementations of the present disclosure relate to methods and apparatus for heteroepitaxial growth of crystalline films. In one implementation, a method of heteroepitaxial deposition of a strain relaxed buffer (SRB) layer on a substrate is provided. The method comprises epitaxially depositing a buffer layer over a dissimilar substrate, rapidly heating the buffer layer to relax the buffer layer, rapidly cooling the buffer layer and determining whether the buffer layer has achieved a desired thickness. | 02-19-2015 |
20150056723 | Processing Substrates Using Site-Isolated Processing - Substrate processing systems and methods are described for processing substrates having two or more regions. The processing includes one or more of molecular self-assembly and combinatorial processing. At least one of materials, processes, processing conditions, material application sequences, and process sequences is different for the processing in at least one region of the substrate relative to at least one other region of the substrate. Processing systems are described that include numerous processing modules. The modules include a site-isolated reactor (SIR) configured for one or more of molecular self-assembly and combinatorial processing of a substrate. | 02-26-2015 |
20150064808 | LED THIN-FILM DEVICE PARTIAL SINGULATION PRIOR TO SUBSTRATE THINNING OR REMOVAL - LED dies are partially singulated while on an unthinned depth growth substrate. Slots are made through the streets separating the LED dies, but not through the growth substrate, leaving the now separated LED dies on the growth substrate. A secondary support is attached to the LED dies on the opposite surface from the growth substrate, and the growth substrate is thinned or removed, leaving the LED dies on the secondary support. Because the LED dies are separated while on the unthinned growth substrate, the likelihood of distortion before slicing is virtually eliminated, and the width of the streets between the LED dies may be correspondingly reduced. | 03-05-2015 |
20150064809 | SUBSTRATE SUPPORT SYSTEM - A method and apparatus for a substrate support system for a substrate process chamber, the chamber comprising a chamber body enclosing a processing region, a primary substrate support and a secondary substrate support at least partially disposed in the processing region, the secondary substrate support circumscribing the primary substrate support, wherein one or both of the primary substrate support and the secondary substrate support are movable relative to each other, and the primary substrate support is rotatable relative to the secondary substrate support. | 03-05-2015 |
20150072444 | Reducing Wafer Bonding Misalignment By Varying Thermal Treatment Prior To Bonding - A bonding layer of the first wafer article is thermally treated and a bonding layer of a second wafer article is thermally treated in accordance with first and second process parameters, respectively prior to bonding the first wafer article with the second wafer article. First and second grid distortion in the first and second wafer articles is measured and a difference is determined between the first and second grid distortions. A prediction is made for maintaining the difference within a prescribed tolerance. At least one of the first process parameters and the second process parameters can be conditionally varied in accordance with the prediction. The thermally treating of the first wafer article and the thermally treating of the second wafer article can then be performed with respect to another pair of the first and second wafer articles prior to bonding the another pair of wafer articles to one another through their respective bonding layers. | 03-12-2015 |
20150079700 | SYSTEMS AND METHODS FOR SIMILARITY-BASED SEMICONDUCTOR PROCESS CONTROL - The present disclosure provides methods and systems for providing a similarity index in semiconductor process control. One of the methods disclosed herein is a method for semiconductor fabrication process control. The method includes steps of receiving a first semiconductor device wafer and receiving a second semiconductor device wafer. The method also includes a step of collecting metrology data from the first and second semiconductor device wafers. The metrology data includes a first set of vectors associated with the first semiconductor device wafer and a second set of vectors associated with the second semiconductor device wafer. The method includes determining a similarity index based in part on a similarity index value between a first vector from the first set of vectors and a second vector from the second set of vectors and continuing to process additional wafers under current parameters when the similarity index is above a threshold value. | 03-19-2015 |
20150079701 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND MANUFACTURING APPARATUS - A manufacturing apparatus includes a chuck for contacting a peripheral portion of a workpiece. The apparatus includes a nozzle to eject a process fluid (liquid or gas) toward a first surface while the workpiece is in contact with the chuck. The apparatus also includes a plate having an opening configured such that a support fluid (liquid or gas) can be ejected toward a second surface of the workpiece while the workpiece is in contact with the chuck. In an example, the support fluid can be used to counteract a displacement of the interior portion in the direction perpendicular to the plane of the workpiece due to, for example, gravity and/or hydrostatic pressure of the process fluid. | 03-19-2015 |
20150087082 | SELECTIVE HEATING DURING SEMICONDUCTOR DEVICE PROCESSING TO COMPENSATE FOR SUBSTRATE UNIFORMITY VARIATIONS - In some embodiments, a system includes (1) a controller configured to receive information regarding substrate uniformity; (2) a processing tool configured to perform a semiconductor device manufacturing process on a substrate; and (3) a laser delivery mechanism coupled to the controller, the laser delivery mechanism configured to selectively deliver laser energy to the substrate during processing within the processing tool so as to selectively heat the substrate during processing. The controller is configured to employ the substrate uniformity information to determine a temperature profile to apply to the substrate during processing within the processing tool and to employ the laser delivery mechanism to selectively heat the substrate during processing within the processing tool based on the temperature profile. Numerous other embodiments are provided. | 03-26-2015 |
20150087083 | BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a flip-chip bonding apparatus ( | 03-26-2015 |
20150104885 | MOVEABLE CURRENT SENSOR FOR INCREASING ION BEAM UTILIZATION DURING ION IMPLANTATION - An ion implant apparatus and moveable ion beam current sensor are described. Various examples provide moving the ion beam current sensor during an ion implant process such that a distance between the ion beam current sensor and a substrate is maintained during scanning of the ion beam toward the substrate. The ion beam current sensor is disposed on a moveable support configured to move the ion beam current sensor in a first direction corresponding to the scanning of the ion beam while the substrate is moved in a second direction. | 04-16-2015 |
20150111311 | METHOD OF SELECTIVELY REMOVING SILICON NITRIDE AND ETCHING APPARATUS THEREOF - A method of selectively removing silicon nitride is provided. The method includes: providing a wafer having silicon nitride on a surface of the wafer; supplying a mixture of phosphoric acid and a silicon-containing material into a process tank, in which the mixture has a predetermined silicon concentration; and submerging the wafer into the mixture within the process tank to remove the silicon nitride. An etching apparatus of selectively removing silicon nitride is also provided. | 04-23-2015 |
20150118764 | PROCESS FOR TREATING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE FOR IMPROVING THICKNESS UNIFORMITY OF THE SEMICONDUCTOR LAYER - The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising: measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thickness identified as being an overthickness at the end of the measurement step. | 04-30-2015 |
20150125967 | Controlling the Device Performance by Forming a Stressed Backside Dielectric Layer - A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device. | 05-07-2015 |
20150132863 | PLASMA PROCESSING APPARATUS AND HEATER TEMPERATURE CONTROL METHOD - A plasma processing apparatus is provided that converts a gas into plasma using a high frequency power and performs a plasma process on a workpiece using an action of the plasma. The plasma processing apparatus includes a processing chamber that can be depressurized, a mounting table that is arranged within the processing chamber and holds the workpiece, an electrostatic chuck that is arranged on the mounting table and electrostatically attracts the workpiece by applying a voltage to a chuck electrode, a heater arranged within or near the electrostatic chuck, and a temperature control unit. The heater is divided into a circular center zone, at least two middle zones arranged concentrically at an outer periphery side of the center zone, and an edge zone arranged concentrically at an outermost periphery. The temperature control unit adjusts a control temperature of the heater with respect to each of the zones. | 05-14-2015 |
20150140688 | SETUP FOR MULTIPLE CROSS-SECTION SAMPLE PREPARATION - A multiple-sample-holder polishing setup for cross-section sample preparation and a method of making a device using the same are presented. The multiple-sample-holder polishing setup includes a frame. The frame has a hollow center, one or more long and short rods and a recess for accommodating a polishing head. The setup includes one or more sample holders. The sample holder is to be attached to the one or more long and short rods of the frame. A paddle is affixed to each sample holder. A sample is attached to the paddle. The sample is coated with a thin epoxy layer prior to polishing thereby allowing for easy inspection for site of interests as well as quick material removal. | 05-21-2015 |
20150140689 | SUBSTRATE BONDING METHOD AND SUBSTRATE BONDING APPARATUS - According to one embodiment, there is provided a substrate bonding method. The substrate bonding method includes disposing a first substrate and a second substrate to face each other. The substrate bonding method includes controlling the first substrate and the second substrate to have a temperature difference. The substrate bonding method includes, in a state where the first substrate and the second substrate are controlled to have the temperature difference, bonding the first substrate to the second substrate by bringing the first substrate into contact with the second substrate while deforming the first substrate so that a central portion of the first substrate is projected toward the second substrate. The central portion of the first substrate is on an inner side of a peripheral portion of the first substrate. | 05-21-2015 |
20150140690 | ETCHING METHOD FOR SEMICONDUCTOR PRODUCT - There is provided an etching method for a semiconductor product. The semiconductor product having, on a substrate, an SiO | 05-21-2015 |
20150292082 | SUBSTRATE PROCESSING APPARATUS, NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM THEREOF AND SEMICONDUCTOR MANUFACTURING METHOD BY EMPLOYING THEREOF - Embodiments of the invention relate to a substrate processing apparatus. In one embodiment, a substrate processing apparatus includes a plurality of process units. The process unit includes a process chamber for processing a substrate, an exhaust conduit connected to the process chamber and an exhaust pump arranged in the path of the exhaust conduit. The substrate processing apparatus further includes a connecting conduit connected to the exhaust conduits of the process units in the upstream of the exhaust pump and a switching unit which switches an exhaust path of the process chamber to the other exhaust pump in the other process unit via the connecting conduit. | 10-15-2015 |
20150311077 | ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - An ion implantation apparatus includes a beam scanner, a beam measurement unit that is able to measure an ion irradiation amount distribution in a beam scanning direction at a wafer position, and a control unit that outputs a control waveform to the beam scanner for scanning an ion beam. The control unit includes an output unit that outputs a reference control waveform to the beam scanner, an acquisition unit that acquires the ion irradiation amount distribution measured for the ion beam scanned based on the reference control waveform from a beam measurement unit, and a generation unit that generates a correction control waveform by using the acquired ion irradiation amount distribution. The control unit outputs the correction control waveform so that the ion irradiation amount distribution becomes a target distribution and the ion irradiation amount distribution per unit time becomes a target value. | 10-29-2015 |
20150311128 | DISPLAY ELEMENT MANUFACTURING METHOD AND MANUFACTURING APPARATUS - The display element manufacturing apparatus has a transporting part, which transports a substrate in a first direction, a first alignment system, which detects fiducial marks, a second alignment system, which is arranged at a prescribed distance from the first alignment system in the first direction and detects fiducial marks, calculating parts, which detect the fiducial marks and calculate the expansion/contraction of the substrate in the first direction or the transport speed of the substrate, and a processing part, which processes a prescribed position of the substrate based on at least one of the expansion/contraction of the substrate in the first direction or the transport speed of the substrate and the fiducial marks. | 10-29-2015 |
20150318145 | LITHOGRAPHY APPARATUS, AND METHOD OF MANUFACTURING AN ARTICLE - The present invention provides a lithography apparatus that forms a pattern on a substrate, the apparatus comprising a base, a stage configured to hold the substrate and be movable above the base with the stage supported by the base, a patterning device configured to perform patterning on the substrate held by the stage, a chamber housing the base and the stage, and supporting the patterning device, a detector configured to obtain information of relative positions between the patterning device and the base, a driving device configured to move the base, and a controller configured to control the driving device based on the information obtained by the detector such that the relative positions satisfy a predetermined condition. | 11-05-2015 |
20150318224 | CORRELATION BETWEEN CONDUCTIVITY AND PH MEASUREMENTS FOR KOH TEXTURING SOLUTIONS AND ADDITIVES - The variability of an etchant concentration in an immersion processes for treatment of semiconductor devices can be significantly lowered by continuously measuring the conductivity of an etchant solution and comparing against predetermined thresholds. The etchant concentration can be maintained by a feed and bleed process based on conductivity measurements of the etchant solution and the conductivity measurements being correlated with premeasured pH values of an etchant solution. | 11-05-2015 |
20150325457 | Method of Packaging Semiconductor Devices and Apparatus for Performing the Same - Provided are an apparatus and method of packaging semiconductor devices mounted on a flexible substrate having a longitudinally extending tape shape and on which packaging areas are defined along the extending direction thereof. The flexible substrate is transferred through a packaging module. An empty area, on which a semiconductor device is not mounted, is detected by a camera from among the packaging areas. Heat dissipation paint composition is applied on at least one semiconductor device located in a processing region of the packaging module by a screen printing process. Thus, a heat dissipation layer configured to package the semiconductor device is formed. Here, operations of the packaging module are controlled by a control unit so that the packaging process is omitted with respect to the empty area. | 11-12-2015 |
20150325488 | VAPOR PHASE GROWTH METHOD AND VAPOR PHASE GROWTH APPARATUS - A vapor phase growth method of growing a film on a substrate by supplying material gases to the substrate while heating the substrate with a heating unit according to an embodiment, the method includes: measuring a temperature of the substrate with a radiation thermometer; executing a temperature feedback control to control an output of the heating unit to cause a measurement value of the radiation thermometer to have a set value when a film is not grown on the substrate; and executing a constant output control to maintain an output of the heating unit constant when a film causing thin-film interference in a wavelength measured by the radiation thermometer is grown on the substrate. | 11-12-2015 |
20150332981 | METHOD FOR WAFER ETCHING IN DEEP SILICON TRENCH ETCHING PROCESS - A method for wafer etching in a deep silicon trench etching process includes the following steps: a. electrostatically absorbing a wafer using an electrostatic chuck, and stabilizing the atmosphere required by the process (S | 11-19-2015 |
20150340281 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures. | 11-26-2015 |
20150341991 | Apparatus and Method for Heating Semiconductor Wafers via Microwaves - An apparatus for heating a semiconductor wafer includes: a microwave source; an applicator cavity; and, a fixture for supporting a wafer in the cavity. The fixture comprises a dielectric mechanical support for the wafer and a grounded metallic ring movably positioned parallel to and concentric with the wafer at some distance from the wafer, to adjust the microwave power distribution to compensate for edge effects. A closed-loop feedback system adjusts the distance based on wafer edge and center temperatures. A method for heating a semiconductor wafer comprises: a. placing the wafer in a microwave cavity; b. supporting the wafer on a fixture comprising a dielectric wafer support and a grounded metallic ring movably positioned at some distance from the wafer; c. introducing microwave power into the cavity to heat the wafer; and d. adjusting the distance between wafer and ring to modify the power distribution near the wafer edge. | 11-26-2015 |
20150348852 | Etching Apparatus and Method - An etchant is supplied to a workpiece. Furthermore, the workpiece is irradiated with spatially modulated light to adjust a temperature profile of the workpiece while etchant is supplied. | 12-03-2015 |
20150356233 | COMPUTATIONAL WAFER INSPECTION - Disclosed herein is a computer-implemented defect prediction method for a device manufacturing process involving processing a portion of a design layout onto a substrate, the method comprising: identifying a hot spot from the portion of the design layout; determining a range of values of a processing parameter of the device manufacturing process for the hot spot, wherein when the processing parameter has a value outside the range, a defect is produced from the hot spot with the device manufacturing process; determining an actual value of the processing parameter; determining or predicting, using the actual value, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the hot spot with the device manufacturing process. | 12-10-2015 |
20150357188 | FILM FORMING METHOD, COMPUTER STORAGE MEDIUM, AND FILM FORMING SYSTEM - The present invention is to form an organic film on a substrate having a pattern formed on a front surface thereof and configured to: apply an organic material onto the substrate; then thermally treat the organic material to form an organic film on the substrate; and then perform ultraviolet irradiation processing on the organic film to remove a surface of the organic film down to a predetermined depth, thereby appropriately and efficiently form the organic film on the substrate. | 12-10-2015 |
20150357198 | METHOD OF ETCHING AND CLEANING WAFERS - A method of operating a wafer processing system includes etching a batch of wafers. The method also includes transferring at least a portion of the batch of wafers to a first front opening universal pod (FOUP). The method further includes purging an interior of the first FOUP with an inert gas. The method additionally includes transporting the first FOUP from a first loading port to a second loading port. The method also includes monitoring an elapsed time from the purging. The method further includes performing a second purging of the interior of the first FOUP if the elapsed time exceeds a threshold time. The method additionally includes cleaning the batch of wafers. | 12-10-2015 |
20150357209 | NEGATIVE ION CONTROL FOR DIELECTRIC ETCH - Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer. | 12-10-2015 |
20150357252 | METHOD AND SYSTEM FOR REAL-TIME POLISHING RECIPE CONTROL - Systems and methods are provided for controlling a polishing process in real-time. First and second characteristics are identified in first and second data sets, respectively, with each data set corresponding to a real-time wafer polishing data. A time delta is computed between the times at which the first and second characteristics occur within their respective data sets, and polishing parameters are then updated in real-time based on the computed time delta. | 12-10-2015 |
20150360343 | CHEMICAL MECHANICAL POLISHING RETAINING RING WITH INTEGRATED SENSOR - A retaining ring for a chemical mechanical polishing carrier head having a mounting surface for a substrate is provided herein. In some embodiments, the retaining ring may include an annular body have a central opening, a channel formed in the body, wherein a first end of the channel is proximate the central opening, and a sensor disposed within the channel and proximate the first end, wherein the sensor is configured to detect acoustic and/or vibration emissions from processes performed on the substrate. | 12-17-2015 |
20150364385 | IN SITU ETCH COMPENSATE PROCESS - A method includes performing an etching on a mask layer to form an opening in the mask layer. The mask layer is a part of a wafer. The method further includes measuring a lateral size of the opening, comparing the lateral size of the opening with a specified range, and performing a compensation etch to compensate for a difference between the lateral size and the specified range. After the compensation etch, a target layer of the wafer is etched to extend the opening into the target layer. | 12-17-2015 |
20150364388 | AUTO-CORRECTION OF MALFUNCTIONING THERMAL CONTROL ELEMENT IN A TEMPERATURE CONTROL PLATE OF A SEMICONDUCTOR SUBSTRATE SUPPORT ASSEMBLY - A method for auto-correction of at least one malfunctioning thermal control element among an array of thermal control elements that are independently controllable and located in a temperature control plate of a substrate support assembly which supports a semiconductor substrate during processing thereof, the method including: detecting, by a control unit including a processor, that at least one thermal control element of the array of thermal control elements is malfunctioning; deactivating, by the control unit, the at least one malfunctioning thermal control element; and modifying, by the control unit, a power level of at least one functioning thermal control element in the temperature control plate to minimize impact of the malfunctioning thermal control element on the desired temperature output at the location of the at least one malfunctioning thermal control element. | 12-17-2015 |
20150364389 | POLISH APPARATUS, POLISH METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A polish apparatus including a rotatable table configured to receive a polish pad having a polish surface; a polish head configured to hold a polish object and configured to be capable of placing the polish object in contact with the polish surface while holding the polish object; at least one contact portion being provided with a contact surface and configured to be capable of contacting the polish surface when the table is in rotation; and a measurement portion configured to measure a state of the contact surface of the contact portion being configured to contact the polish surface of the polish pad. | 12-17-2015 |
20150364391 | POLISHING APPARATUS AND WEAR DETECTION METHOD - There is provided a polishing apparatus capable of detecting uneven wear occurring on a polishing pad and detecting an appropriate replacement timing of the polishing pad. The polishing apparatus detects, every predetermined time, a value of rotation speed or a value of rotation torque of a table drive shaft for rotationally driving a polishing table or a dresser drive shaft for driving a dresser, or a value of swing torque of a dresser swing shaft for driving the dresser; calculates a change quantity thereof based on the value of the detected rotation speed, the value of the detected rotation torque, or the value of the detected swing torque; determines whether or not the change quantity exceeds a predetermined value; and notifies a user of a warning when a determination is made that the change quantity exceeds the predetermined value. | 12-17-2015 |
20150364444 | SEMICONDUCTOR DEVICE AND METHOD OF ADAPTIVE PATTERNING FOR PANELIZED PACKAGING WITH DYNAMIC VIA CLIPPING - A semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping is described. A panel comprising an encapsulating material disposed around a plurality of semiconductor die can be formed. An actual position for each of the plurality of semiconductor die within the panel can be measured. A conductive redistribution layer (RDL) comprising first capture pads aligned with the actual positions of each of the plurality of semiconductor die can be formed. A plurality of second capture pads at least partially disposed over the first capture pads and aligned with a package outline for each of the plurality of semiconductor packages can be formed. A nominal footprint of a plurality of conductive vias can be adjusted to account for a misalignment between each semiconductor die and its corresponding package outline. | 12-17-2015 |
20150371883 | SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - In the present invention, a substrate is placed at a predetermined position on a substrate support even though the substrate is deviated on a substrate transfer unit. | 12-24-2015 |
20150371909 | METHODS FOR POST-EPITAXIAL WARP PREDICTION AND CONTROL - In one aspect, a method of predicting warp in a plurality of wafers after an epitaxial layer deposition process is provided. The method includes receiving, by a processor, a measured resistivity of a first wafer of the plurality of wafers, receiving, by the processor, a measured shape of the first wafer after at least one of a grinding process and an etching process, and calculating, using the processor, a change in wafer shape during the epitaxial layer deposition process. The method further includes superposing, using the processor, the calculated shape change onto the measured shape of the first wafer to determine a post-epitaxial wafer shape and calculating, using the processor, a post-epitaxial warp value based on the determined post-epitaxial wafer shape. | 12-24-2015 |
20150371912 | METHODS AND SYSTEMS FOR CHEMICAL MECHANICAL PLANARIZATION ENDPOINT DETECTION USING AN ALTERNATING CURRENT REFERENCE SIGNAL - Methods, non-transitory computer readable media, and systems are provided for detecting an endpoint of a chemical mechanical planarization (CMP) process on a semiconductor substrate. The method comprises generating a reference signal, generating a first signal with which to control a CMP system, generating a second signal using a combination of the first signal and the reference signal, commanding the CMP system with the second signal, generating a response signal that indicates an operational characteristic of the CMP system that is responsive to the second signal and a friction property of the semiconductor substrate, and filtering the response signal using the reference signal to determine the endpoint of the CMP process. | 12-24-2015 |
20150371914 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A substrate processing apparatus for executing a predetermined process on a substrate loaded into a process chamber by running a recipe containing a plurality of steps is provided. The recipe includes a processing step of processing the substrate, and a leak check step executed before the processing step to check whether a leak occurs inside the process chamber, and the substrate processing apparatus includes a main control unit configured to execute the processing step while keeping an error that occurs in the leak check step. | 12-24-2015 |
20160005630 | SUBSTRATE TREATING APPARATUS AND METHOD OF TREATING SUBSTRATE - A substrate treating apparatus includes a rotating and holding unit that rotates a substrate, a first supply source that supplies first pure water having a first temperature, a second supply source that supplies second pure water having a second temperature higher than the first temperature, a treatment solution supply unit that supplies a treatment solution to a central section of an upper surface of the substrate, a first supply unit that supplies a first liquid containing the first pure water to a central section of a lower surface of the substrate, a second supply unit that supplies a second liquid containing the second pure water to a peripheral section and an intermediate section of the lower surface, and a heat amount control unit that independently controls an amount of heat to be supplied by the first supply unit and an amount of heat to be supplied by the second supply unit. | 01-07-2016 |
20160005632 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - According to one embodiment, there is provided a substrate processing apparatus including a processing chamber, a substrate processing unit, and a monitoring unit. A stage is placed in the processing chamber. A substrate is able to be put on the stage. The substrate processing unit is configured to process the substrate inside the processing chamber. The monitoring unit is configured to monitor a mass of the substrate via the stage with performing a correction according to a pressure, in a period when the substrate is being processed by the substrate processing unit. | 01-07-2016 |
20160013065 | PLASMA ETCHING APPARATUS AND PLASMA ETCHING METHOD | 01-14-2016 |
20160013085 | In-Situ Acoustic Monitoring of Chemical Mechanical Polishing | 01-14-2016 |
20160013109 | OVERLAY MEASURING METHOD AND SYSTEM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME | 01-14-2016 |
20160013338 | REACTION APPARATUS AND METHOD FOR MANUFACTURING A CIGS ABSORBER OF A THIN FILM SOLAR CELL | 01-14-2016 |
20160027670 | HEAT RESERVOIR CHAMBER, AND METHOD FOR THERMAL TREATMENT - The present disclosure provides a thermal treatment chamber. The thermal treatment chamber includes a wafer holder to hold a to-be-processed wafer; a heat reservoir located under the wafer holder, but being separated from the wafer holder, for adjusting a temperature of the wafer holder based on the to-be-processed wafer; and a first driving unit connected to the heat reservoir for adjusting a distance between the wafer holder and the heat reservoir to adjust the temperature of the wafer holder. | 01-28-2016 |
20160027708 | Real-Time Calibration for Wafer Processing Chamber Lamp Modules - An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer processing chamber. The apparatus further includes radiant heating elements disposed in different zones and operable to heat different portions of a wafer located within the wafer processing chamber. The apparatus further includes sensors disposed outside the wafer processing chamber and operable to monitor energy from the radiant heating elements disposed in the different zones. The apparatus further includes a computer configured to utilize the sensors to characterize the radiant heating elements disposed in the different zones and to provide a calibration for the radiant heating elements disposed in the different zones such that a substantially uniform temperature profile is maintained across a surface of the wafer. | 01-28-2016 |
20160043008 | OPTICAL ACOUSTIC SUBSTRATE ASSESSMENT SYSTEM AND METHOD - A system and method for identifying one or more characteristics of a structure formed into a substrate is herein disclosed. Surface and bulk acoustic waves are induced in the substrate and travel past a structure of interest where the acoustic waves are sensed. Information concerning one or more characteristics of the structure is encoded in the wave. The encoded information is assessed to determine the characteristic of interest. | 02-11-2016 |
20160064285 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - On a peripheral circuit area upon a semiconductor substrate, an NMOS gate stack, comprising a first high-dielectric film, an NMOS gate metal, and a first semiconductor film, is formed, and a PMOS gate stack, comprising a second high-dielectric film, a PMOS gate metal, and a second semiconductor film, is formed so that a predetermined step is formed between the NMOS gate stack and the PMOS gate stack. A third semiconductor film is formed over the entire surface of the semiconductor substrate so as to fill in the step. The third semiconductor film is planarized by way of CMP so as to form a fourth semiconductor film that is thinner than the third semiconductor film. | 03-03-2016 |
20160079039 | Dual Plasma Volume Processing Apparatus for Neutral/Ion Flux Control - A semiconductor wafer processing apparatus includes a first electrode exposed to a first plasma generation volume, a second electrode exposed to a second plasma generation volume, and a gas distribution unit disposed between the first and second plasma generation volumes. The first electrode is defined to transmit radiofrequency (RF) power to the first plasma generation volume, and distribute a first plasma process gas to the first plasma generation volume. The second electrode is defined to transmit RF power to the second plasma generation volume, and hold a substrate in exposure to the second plasma generation volume. The gas distribution unit includes an arrangement of through-holes defined to fluidly connect the first plasma generation volume to the second plasma generation volume. The gas distribution unit also includes an arrangement of gas supply ports defined to distribute a second plasma process gas to the second plasma generation volume. | 03-17-2016 |
20160079041 | HEAT TRANSFER PLATE FOR A SHOWERHEAD ELECTRODE ASSEMBLY OF A CAPACITIVELY COUPLED PLASMA PROCESSING APPARATUS - A heat transfer plate useful in a showerhead electrode assembly of a capacitively coupled plasma processing apparatus. The heat transfer plate includes independently controllable gas volumes which may be pressurized to locally control thermal conductance between a heater member and a cooling member such that uniform temperatures may be established on a plasma exposed surface of the showerhead electrode assembly. | 03-17-2016 |
20160079074 | ETCHING METHOD AND ETCHING APPARATUS - An etching method for performing a plasma etching on an object to be processed by using a supplied gas is provided. In the etching method, a temperature of a focus ring is adjusted by using a first temperature adjustment mechanism controllable independently of a temperature control of the object to be processed while measuring a time variation until the temperature of the focus ring reaches a target value. A degree of consumption of the focus ring is estimated from the measured time variation based on a preliminarily set correlation between the time variation and the degree of consumption of the focus ring. The target value of the temperature of the focus ring is corrected based on the estimated degree of consumption of the focus ring. | 03-17-2016 |
20160079075 | DETERMINATION OF ETCHING PARAMETERS FOR PULSED XENON DIFLUORIDE (XEF2) ETCHING OF SILICON USING CHAMBER PRESSURE DATA - A method for determining depletion of an etchant, an etch depth, and an etch rate during an etch of a material such as Si using an etchant such as xenon difluoride (XeF | 03-17-2016 |
20160093542 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS - A method of manufacturing a semiconductor device includes forming a film along a surface of a semiconductor substrate in a first state having a first surface area by supplying a reaction gas at a first flow rate. The method further includes detecting a transition from the first state to a second state having a second surface area different from the first surface area. The method still further includes forming a film by changing the flow rate of the reaction gas from the first flow rate to a second flow rate different form the first flow rate after detecting the transition from the first state to the second state. | 03-31-2016 |
20160099185 | METHOD OF CONTROLLING AN ETCHING PROCESS FOR FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method of controlling an etching process for forming fine patterns of a semiconductor device includes forming a lower pattern having a plurality of openings on a substrate, obtaining a width value of the lower pattern, and controlling a process recipe of an etching process for forming the lower pattern by using the width value. | 04-07-2016 |
20160111344 | METHOD AND APPARATUS FOR CHARACTERIZING METAL OXIDE REDUCTION - Method and apparatus for characterizing metal oxide reduction using metal oxide films formed in an anneal chamber are disclosed. Oxygen is provided into an anneal chamber. A substrate including a metal seed layer is exposed to the oxygen and exposed to a heated substrate support in the anneal chamber to form a metal oxide of the metal seed layer. The oxidized substrate can be stored for later use or transferred to a processing chamber for reducing the metal oxide to metal. The oxidized substrates formed in this manner provide metal oxides that are repeatable, uniform, and stable. The oxidized substrate is exposed to a reducing treatment under conditions that reduce the metal oxide to metal in the form of a film integrated with the metal seed layer. | 04-21-2016 |
20160118250 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide semiconductor device includes the following steps. There is prepared a first silicon carbide layer having a first main surface and a second main surface. A first recess including a side portion and a bottom portion is formed in the first main surface of the first silicon carbide layer. A second silicon carbide layer is formed in contact with the first main surface, the side portion, and the bottom portion. An image of a second recess formed at a position facing the first recess of the fourth main surface is obtained. Alignment is performed based on the image of the second recess. The first main surface corresponds to a plane angled off relative to a {0001} plane. A ratio obtained by dividing a depth of the first recess by a thickness of the second silicon carbide layer is more than 0.2. | 04-28-2016 |
20160118309 | Minimal Contact Wet Processing Systems and Methods - Embodiments provided herein describe systems and methods for processing substrates. A substrate having a first region and a second region is provided. A container is positioned proximate to the first region of the substrate. The container has an opening on an end thereof adjacent to the substrate. A processing liquid is dispensed into the container such that the processing liquid contacts the first region of the substrate through the opening. The gaseous pressure in a portion of the container devoid of the processing liquid is reduced. The reduction of the gaseous pressure prevents the processing liquid from flowing from the first region of the substrate to the second region of the substrate. | 04-28-2016 |
20160126148 | SYSTEM AND METHOD FOR PERFORMING A WET ETCHING PROCESS - A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device, including a measuring station to optically measure the thickness of a wafer before and after each etching steps in the process. The system also includes a controller to analyze the thickness measurements in view of a target wafer profile and generate an etch recipe, dynamically and in real time, for each etching step. In addition, the process controller can cause a single wafer wet etching station to etch the wafer according to the generated etching recipes. In addition, the system can, based on the pre and post-etch thickness measurements and target etch profile, generate and/or refine the etch recipes. | 05-05-2016 |
20160133485 | SYSTEMS AND METHODS FOR IN-LINE MEASUREMENT OF PRE-UNDERFILL WETTING ANGLE - Systems and method for determining whether to apply a liquid adhesive to a chip substrate based on a measured wetting angle are disclosed. According to the disclosed systems and methods, the chip substrate is treated, for example, by cleaning and activating the chip substrate surface with energetic plasma. One or more liquid adhesive drops are dispensed on the treated chip substrate surface. A camera captures a top-down image of the one or more liquid adhesive drops. The wetting angle between the liquid adhesive drops is calculated based on the image and volume data of the liquid adhesive drops. A layer of the liquid adhesive is applied to the chip substrate based on the calculated wetting angle and predetermined parameters. | 05-12-2016 |
20160138188 | MULTIZONE CONTROL OF LAMPS IN A CONICAL LAMPHEAD USING PYROMETERS - A method and apparatus for processing a semiconductor substrate is described. The apparatus is a process chamber having an optically transparent upper dome and lower dome. Vacuum is maintained in the process chamber during processing. The upper dome is thermally controlled by flowing a thermal control fluid along the upper dome outside the processing region. Thermal lamps are positioned proximate the lower dome, and thermal sensors are disposed among the lamps. The lamps are powered in zones, and a controller adjusts power to the lamp zones based on data received from the thermal sensors. | 05-19-2016 |
20160148822 | SUBSTRATE CARRIER USING A PROPORTIONAL THERMAL FLUID DELIVERY SYSTEM - A substrate carrier is described that uses a proportional thermal fluid delivery system In one example the apparatus includes a heat exchanger to provide a thermal fluid to a fluid channel of a substrate carrier and to receive the thermal fluid from the fluid channel, the thermal fluid in the fluid channel to control the temperature of the carrier during substrate processing. A proportional valve controls the rate of flow of thermal fluid from the heat exchanger to the fluid channel, A temperature controller receives a measured temperature from a thermal sensor of the carrier and controls the proportional valve in response to the measured temperature to adjust the rate of flow. | 05-26-2016 |
20160148850 | PROCESS CONTROL TECHNIQUES FOR SEMICONDUCTOR MANUFACTURING PROCESSES - Techniques for measuring and/or compensating for process variations in a semiconductor manufacturing processes. Machine learning algorithms are used on extensive sets of input data, including upstream data, to organize and pre-process the input data, and to correlate the input data to specific features of interest. The correlations can then be used to make process adjustments. The techniques may be applied to any feature or step of the semiconductor manufacturing process, such as overlay, critical dimension, and yield prediction. | 05-26-2016 |
20160155631 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD | 06-02-2016 |
20160155676 | METHODS FOR DEPOSITING FILMS ON SENSITIVE SUBSTRATES | 06-02-2016 |
20160155721 | Bonding Method, Storage Medium, Bonding Apparatus and Bonding System | 06-02-2016 |
20160158890 | SYSTEMS AND METHODS FOR SCRIBING PHOTOVOLTAIC STRUCTURES - A system for scribing a photovoltaic structure is provided. During operation, a conveyor can move a photovoltaic structure along a path, and a scribing apparatus is directed toward that path to scribe a groove of a predetermined depth. In one embodiment, the groove does not penetrate an interface between a base layer and an emitter layer of the photovoltaic structure. | 06-09-2016 |
20160172252 | ALIGNMENT OF THREE DIMENSIONAL INTEGRATED CIRCUIT COMPONENTS | 06-16-2016 |
20160172592 | METHOD FOR MANUFACTURING ORGANIC EL DISPLAY PANEL AND SYSTEM FOR MANUFACTURING ORGANIC EL DISPLAY PANEL | 06-16-2016 |
20160181166 | METHOD OF FINE-TUNING PROCESS CONTROLS DURING INTEGRATED CIRCUIT CHIP MANUFACTURING BASED ON SUBSTRATE BACKSIDE ROUGHNESS | 06-23-2016 |
20160196966 | METHOD AND DEVICE FOR POLISHING SEMICONDUCTOR WAFER | 07-07-2016 |
20160196967 | REMOVAL OF METAL | 07-07-2016 |
20160196995 | SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD | 07-07-2016 |
20160197230 | LIGHTING EMITTING DEVICE WITH ALIGNED-BONDING AND THE MANUFACTURING METHOD THEREOF | 07-07-2016 |
20160204044 | PROCESSING METHODS AND APPARATUS WITH TEMPERATURE DISTRIBUTION CONTROL | 07-14-2016 |
20160254166 | Chemical Circulation System and Methods of Cleaning Chemicals | 09-01-2016 |
20160377991 | METHOD OF LAYER MANAGEMENT WITH DOUBLE-LAYER OVERLAY ACCURACY CONTROL, CALIBRATION MARK AND MEASUREMENT SYSTEM - The present invention provides a method for solving the need for layer management with double-layer overlay accuracy control, a calibration mark structure which realizes the method and a measurement system with the calibration mark structure. The method modifies the layout of the overlay calibration marks such that overlay information of two layers is contained in one combined calibration mark, has realized the overlay accuracy data collection for the two previous layers in the current layer by one-time measurement, and can treat the overlay accuracies of the two layers as different control accuracies. Thus, the method can complete the automatic feedback optimization of the overlay accuracy compensation, is simple and easy, and can better help the enterprises for production quality assurance and cost control. | 12-29-2016 |
20160379902 | MEASUREMENT APPARATUS, MEASUREMENT METHOD, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A measurement apparatus according to an embodiment includes an electron emission unit and a detection unit that detects a reflection electron reflected by a recessed shape pattern. In addition, the measurement apparatus includes a time measurement unit that measures a response time from when the electron beam is emitted to when the reflection electron is detected. Further, the measurement apparatus includes a bent amount calculation unit that calculates the amount of bent, i.e., a position deviation amount, between an upper surface portion and a bottom surface portion of the recessed shape pattern. The bent amount calculation unit calculates the amount of bent on the basis of a condition for determining the incidence path of the electron beam to the recessed shape pattern, and the response time. | 12-29-2016 |
20160379903 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes etching a stack of first-material layers and second-material layers alternately disposed one on another on a substrate. An upper portion of the stack is etched using an end point detection (EPD) signal of an etching reaction gas, and a function of an injection time of an etchant with respect to a depth of an opening is obtained while the upper portion of the stack is etched. A lower portion of the stack is etched using the obtained function. | 12-29-2016 |
20170233866 | Film Forming Apparatus, Film Forming Method, and Computer-Readable Storage Medium | 08-17-2017 |
20190143474 | SYSTEM AND METHOD FOR MONITORING CHEMICAL MECHANICAL POLISHING | 05-16-2019 |
20190148192 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS | 05-16-2019 |
20190148193 | CORRELATION BETWEEN CONDUCTIVITY AND PH MEASUREMENTS FOR KOH TEXTURING SOLUTIONS AND ADDITIVES | 05-16-2019 |
20220136772 | RTP SUBSTRATE TEMPERATURE ONE FOR ALL CONTROL ALGORITHM - Embodiments disclosed herein include a method of processing a substrate. In an embodiment, the method comprises detecting one or more substrate parameters of a substrate in a processing chamber, and heating the substrate to a first temperature with an open loop tuning (OLT) heating process based on the one or more substrate parameters. In an embodiment, the method may further comprise placing the substrate on an edge ring, and heating the substrate to a second temperature with a low temperature closed loop controller. In an embodiment, the method further comprises heating the substrate to a third temperature with a high temperature closed loop controller. | 05-05-2022 |
20220139698 | Using Cumulative Heat Amount Data To Qualify Hot Plate Used For Postexposure Baking - A test wafer is placed inside a baking module and is baked. Via one or more temperature sensors, a cumulative heat amount delivered to the test wafer during the baking is measured. The measured cumulative heat amount is compared with a predefined cumulative heat amount threshold. In response to the comparing indicating that the measured cumulative heat amount is within the predefined cumulative heat amount threshold, it is determined that the baking module is qualified for actual semiconductor fabrication. In response to the comparing indicating that the measured cumulative heat amount is outside of the predefined cumulative heat amount threshold, it is determined that the baking module is not qualified for actual semiconductor fabrication. | 05-05-2022 |