Entries |
Document | Title | Date |
20080199975 | METHODS OF FORMING A METAL OXIDE LAYER PATTERN HAVING A DECREASED LINE WIDTH OF A PORTION THEREOF AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - Provided herein are methods of forming a metal oxide layer pattern on a substrate including providing a preliminary metal oxide layer on a substrate; etching the preliminary metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increases in a vertically downward direction; and etching the preliminary metal oxide layer pattern to form a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer. The present invention also provides methods of manufacturing a semiconductor device including forming a metal oxide layer and a first conductive layer on a substrate; etching the metal oxide layer to provide a preliminary metal oxide layer pattern, wherein the line width of the preliminary metal oxide layer pattern gradually increase in a vertically downward direction; etching the first conductive layer to provide a first conductive layer pattern; and etching the preliminary metal oxide layer pattern to provide a metal oxide layer pattern in a manner so as to decrease the line width of a lower portion of the preliminary metal oxide layer pattern. | 08-21-2008 |
20080199976 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC CAPACITOR - A semiconductor device manufacturing method has a step forming a transistor layer portion on a semiconductor substrate, and a step forming a ferroelectric capacitor portion including a lower electrode, a ferroelectric substance and an upper electrode above the transistor layer portion, wherein the step forming the ferroelectric capacitor portion includes adjusting an area of the upper electrode on the basis of manufacturing parameters of the ferroelectric capacitor portion. | 08-21-2008 |
20080206895 | MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape as the lower electrode, and is formed by one of sputtering, plasma CVD, and ALD. | 08-28-2008 |
20080213924 | Ferroelectric memory device and method of manufacturing the same - A method of manufacturing a ferroelectric memory device includes: forming a hydrogen barrier film which covers a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, wherein a thickness of an area of the hydrogen barrier film provided on the upper electrode is made greater than a thickness of an area of the hydrogen barrier film provided on a sidewall of the ferroelectric capacitor by forming the area of the hydrogen barrier film provided on the upper electrode in a plurality of layers. | 09-04-2008 |
20080220542 | LOW-FIRE FERROELECTRIC MATERIAL - A low-fire ferroelectric composition, includes a lead bismuth titanate compound having a formula represented by: (Bi | 09-11-2008 |
20080248595 | Method for Manufacturing Semiconductor Device and Computer Storage Medium - A method for fabricating a semiconductor device includes the steps of forming a PbTiOx film having a predominantly (111) orientation on a lower electrode as a nucleation layer by an MOCVD process with a film thickness exceeding 2 nm, and forming a PZT film having a predominantly (111) orientation on the nucleation layer, wherein the step of forming the PbTiOx film is conducted under an oxygen partial pressure of less than 340 Pa. | 10-09-2008 |
20080248596 | Method of making a circuitized substrate having at least one capacitor therein - A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art. In still another embodiment, at least two spaced-apart conductors may be formed within a metal layer deposited on a dielectric layer, these conductors defining a channel there-between. The capacitive dielectric material may then be deposited (e.g., using lamination) within the channels. | 10-09-2008 |
20080261331 | MRAM AND METHOD OF MANUFACTURING THE SAME - A magnetic memory device comprising, a magneto-resistance effect element that is provided at an intersection between a first write line and a second write line. And the magneto-resistance effect element having, an easy axis that extends in a direction of extension of the first write line, and a first conductive layer for electrical connection to the magneto-resistance effect element, the first conductive layer having sides which are in flush with sides of the magneto-resistance effect element. | 10-23-2008 |
20080261332 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a ferroelectric film on a first conductive film by a sol-gel method; forming a first conductive metal oxide film on the ferroelectric film; carrying out a first annealing on the first conductive metal oxide film; forming a second conductive metal oxide film on the first conductive metal oxide film, so that the first and second conductive films serve as a second conductive film; and forming a capacitor by patterning the first conductive film, the ferroelectric film and the second conductive film. In the step of forming the first conductive metal oxide film, ferroelectric characteristics are adjusted with a flow rate ratio of oxygen by utilizing the fact that the ferroelectric characteristics of the ferroelectric film improve as the flow rate ratio of oxygen in a sputtering gas increases. | 10-23-2008 |
20080261333 | Methods of forming a material film, methods of forming a capacitor, and methods of forming a semiconductor memory device using the same - A method of forming a material (e.g., ferroelectric) film, a method of manufacturing a capacitor, and a method of forming a semiconductor memory device using the method of forming the (e.g., ferroelectric) film are provided. Pursuant to an example embodiment of the present invention, a method of forming a ferroelectric film includes preparing a substrate, depositing an amorphous ferroelectric film on the substrate, and crystallizing the amorphous ferroelectric film by irradiating it with a laser beam. According to still another example embodiment of the present invention, a method of forming a ferroelectric film may reduce the thermal damage to other elements because the ferroelectric film may be formed at a temperature lower than about 500° C. to about 550° C. | 10-23-2008 |
20080274567 | METHOD OF FORMING INTEGRATED CIRCUIT HAVING A MAGNETIC TUNNEL JUNCTION DEVICE - A method for manufacturing an integrated circuit having a magnetic tunnel junction device is disclosed. The method includes depositing a bottom pinning structure above the bottom conductive structure. A first ferromagnetic structure is deposited above the bottom pinning structure in a chamber. A tunnel barrier structure is deposited above the first ferromagnetic layer structure in the chamber, and a second ferromagnetic structure is deposited above the tunnel barrier structure of the magnetic tunnel junction device in another chamber. | 11-06-2008 |
20080286883 | Dry etching method and production method of magnetic memory device - Provision of a process capable of preferably etching particularly PtMn used for a pin layer of an MRAM is an object: a dry etching method for performing dry etching on a layer including platinum and/or manganese by using pulse plasma and a production method of an MRAM, wherein the dry etching method is applied to processing of the pin layer. The MRAM is configured to have a memory portion comprising a magnetic memory element composed of tunnel magnetoresistive effect element formed by stacking a magnetic fixed layer having a fixed magnetization direction, a tunnel barrier layer and a magnetic layer capable of changing the magnetization direction. | 11-20-2008 |
20080293165 | METHOD FOR MANUFACTURING NON-VOLATILE MAGNETIC MEMORY - In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured. | 11-27-2008 |
20080299679 | Low resistance tunneling magnetoresistive sensor with composite inner pinned layer - A high performance TMR sensor is fabricated by employing a composite inner pinned (AP | 12-04-2008 |
20080299680 | METHODS OF FORMING MAGNETIC MEMORY DEVICES - Methods for creating a memory device can include depositing a sense layer, patterning the sense layer to form a plurality of magnetic data cells, depositing a separation layer over the plurality of data cells, depositing a reference layer over the separation layer, and patterning the reference layer to form an elongated magnetic reference cell wherein the elongated magnetic reference cell extends uninterrupted along more than one of the plurality of magnetic data cells. | 12-04-2008 |
20080311682 | MICROWAVE INTEGRATED CIRCUIT PACKAGE AND METHOD FOR FORMING SUCH PACKAGE - A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects. | 12-18-2008 |
20080311683 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method of manufacturing a semiconductor device including forming a lower electrode over a substrate, increasing the temperature of the substrate with the lower electrode to a predetermined temperature under mixture gas atmosphere of inert gas and oxygen gas, forming a dielectric film on the lower electrode by using an organic metal raw material after the temperature reaches the predetermined temperature, and forming an upper electrode on the dielectric film. | 12-18-2008 |
20090004759 | Cobalt-doped indium-tin oxide films and methods - Methods of forming cobalt-doped indium-tin oxide structures are shown. Properties of structures include transparency, conductivity, and ferromagnetism. Monolayers that contain indium, monolayers that contain tin, and monolayers that contain cobalt are deposited onto a substrate and subsequently processed to form cobalt-doped indium-tin oxide. Devices that include oxide structures formed with these methods should have better step coverage over substrate topography and more robust film mechanical properties. | 01-01-2009 |
20090029485 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A capacitor in which a ferroelectric film ( | 01-29-2009 |
20090035877 | METHODS OF FORMING A FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A FERROELECTRIC CAPACITOR INCLUDING THE SAME - A method of forming a ferroelectric layer is provided. A metal-organic source gas is provided into a chamber into which an oxidation gas is provided for a first time period to form ferroelectric grains on a substrate. A ferroelectric layer is formed by performing at least twice a step of providing a metal-organic source gas into the chamber during the first time period using a pulse method to grow the ferroelectric grains. | 02-05-2009 |
20090047747 | Method of forming an amorphous ferroelectric memory device - This disclosure relates to amorphous ferroelectric memory devices and methods for forming them. | 02-19-2009 |
20090053833 | Method of Manufacturing Magnetic Multi-layered Film - A method of manufacturing a magnetic multi-layered film including: a first magnetic layer forming step of forming a first magnetic layer on a substrate; a non-magnetic layer forming step of forming a non-magnetic layer on the first magnetic layer; and a second magnetic layer forming step of forming a second magnetic layer on the non-magnetic layer, the method further including, before the non-magnetic layer forming step, a plasma treatment step of introducing the substrate into a plasma treatment apparatus and treating the substrate with inductive coupling-type plasma, with the substrate being electrically insulated from the plasma treatment apparatus. | 02-26-2009 |
20090061537 | METHOD OF MANUFACTURING OSCILLATOR DEVICE - A method of manufacturing oscillator devices each having an oscillator and a resilient supporting member for supporting the oscillator for oscillatory motion, includes a step of processing one and the same substrate to form oscillators and resilient supporting members of oscillator devices so that oscillators of adjacent oscillator devices are connected to each other, a step of forming or placing a magnetic material so that it extends across the connected oscillators of the adjacent oscillator devices, and a step of simultaneously cutting and separating the connected oscillators and the magnetic material formed or placed to extend across the connected oscillators, whereby oscillator devices such as oscillatory type actuators having good reliability and performance evenness can be manufactured with a good productivity. | 03-05-2009 |
20090061538 | Methods of forming ferroelectric capacitors and methods of manufacturing semiconductor devices using the same - In a method of forming a ferroelectric capacitor, a lower electrode layer is formed on a substrate. A first crystalline layer is formed on the lower electrode layer. A ferroelectric layer is formed on the first crystalline layer. The first crystalline layer one of prevents a component of the ferroelectric layer from diffusing into the lower electrode layer and mitigates fatigue of the ferroelectric layer. An upper electrode layer is formed on the ferroelectric layer. | 03-05-2009 |
20090068761 | Method of Forming a Micromagnetic Device - A method of forming a micromagnetic device on a substrate including forming a first insulating layer above the substrate, a first seed layer above the first insulating layer, a first conductive winding layer above the first seed layer, and a second insulating layer above the first conductive winding layer. The method also includes forming a first magnetic core layer above the second insulating layer, a third insulating layer above the first magnetic core layer, and a second magnetic core layer above the third insulating layer. The method still further includes forming a fourth insulating layer above the second magnetic core layer, a second seed layer above the fourth insulating layer, and a second conductive winding layer above the second seed layer and in vias to the first conductive winding layer. The first and second conductive winding layers form a winding for the micromagnetic device. | 03-12-2009 |
20090068762 | Methods of Processing a Substrate and Forming a Micromagnetic Device - A method of processing a substrate with a conductive film formed thereover and method of forming a micromagnetic device. In one embodiment, the method of processing the substrate includes reducing a temperature of the substrate to a stress-compensating temperature, and maintaining the temperature of the substrate at the stress-compensating temperature for a period of time. The method also includes increasing the temperature of the substrate above the stress-compensating temperature. | 03-12-2009 |
20090068763 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A method for manufacturing a semiconductor device includes the steps of: forming a ferroelectric capacitor having a first electrode, a ferroelectric film and a second electrode successively laminated on a base substrate; forming a first interlayer dielectric film that covers the ferroelectric capacitor and the base substrate; forming a material film for a second interlayer dielectric film covering the first interlayer dielectric film; exposing the first interlayer dielectric film located on the ferroelectric capacitor by polishing an upper surface side of the material film for the second interlayer dielectric film by a CMP method; forming a contact hole that penetrates the first interlayer dielectric film and exposes the second electrode, after the step of exposing the first interlayer dielectric film; and forming in the contact hole a plug conductive section that conductively connects to the second electrode, wherein the first interlayer dielectric film has a lower polishing rate in the CMP method compared to the second interlayer dielectric film. | 03-12-2009 |
20090068764 | Semiconductor device and method of manufacturing the same - According to the present invention, contact plugs are formed by a CVD method without deteriorating the properties of the ferroelectric capacitor in a semiconductor device having a fine ferroelectric capacitor. Adhesive film is formed in a contact hole, which exposes an upper electrode of the ferroelectric capacitor after conducting heat treatment in an oxidizing atmosphere, and a W layer is deposited by the CVD method using such TiN adhesive film as a hydrogen barrier and the contact hole is filled. | 03-12-2009 |
20090075399 | METHOD FOR MANUFACTURING FERROELECTRIC MEMORY DEVICE - A method for manufacturing a ferroelectric memory device includes the steps of: forming a ferroelectric capacitor on a substrate; forming a hydrogen barrier film that covers the ferroelectric capacitor; forming a dielectric film that covers the hydrogen barrier film; and forming a through hole that penetrates the dielectric film and the hydrogen barrier film by etching that uses a mixed gas containing perfluorocarbon gas and oxygen gas, wherein the flow quantity of the perfluorocarbon gas is 0.77 times or more but 3.8 times or less the flow quantity of the oxygen gas. | 03-19-2009 |
20090075400 | METHOD FOR MANUFACTURING FERROELECTRIC MEMORY - A method for manufacturing a ferroelectric memory includes the steps of: forming an iridium film above a substrate; forming an iridium oxide layer on the iridium film; changing the iridium oxide layer into an amorphous iridium layer; oxidizing the amorphous iridium layer to form an iridium oxide portion; forming a ferroelectric film on the iridium oxide portion by a MOCVD method; and forming an electrode on the ferroelectric film. | 03-19-2009 |
20090075401 | METHOD FOR MANUFACTURING FERROELECTRIC CAPACITOR AND METHOD FOR MANUFACTURING FERROELECTRIC MEMORY DEVICE - A method for manufacturing a ferroelectric capacitor having a ferroelectric film interposed between a first electrode and a second electrode is provided. The method includes the steps of: forming an electrode film above a substrate; thermally oxidizing a surface layer of the electrode film to form an oxidized electrode layer in an atmosphere of atmospheric-pressure with an oxygen partial pressure being 2% or grater; forming a ferroelectric film on the electrode layer by a MOCVD method thereby forming a first electrode composed of the electrode film including the oxidized electrode layer that serves as a base for the ferroelectric film; and forming a second electrode on the ferroelectric film. | 03-19-2009 |
20090093070 | CAPACITOR, METHOD OF MANUFACTURING THE SAME, METHOD OF MANUFACTURING FERROELECTRIC MEMORY DEVICE, METHOD OF MANUFACTURING ACTUATOR, AND METHOD OF MANUFACTURING LIQUID JET HEAD - A method of manufacturing a capacitor, including: forming a lower electrode on a substrate; forming a dielectric film of a ferroelectric or a piezoelectric on the lower electrode; forming an upper electrode on the dielectric film; and forming a silicon oxide film so that at least the dielectric film is covered with the silicon oxide film, the silicon oxide film being formed by using trimethoxysilane. | 04-09-2009 |
20090098664 | FERROELECTRIC THIN FILM DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of manufacturing a ferroelectric thin film device, and, more particularly, to a method of manufacturing a ferroelectric thin film device having high crystallinity, good surface roughness and high deposition efficiency through on-axis type sputtering, and to a ferroelectric thin film device manufactured using the method. The method of manufacturing a ferroelectric thin film device includes: depositing an SrRuO | 04-16-2009 |
20090104718 | Method of magnetic tunneling layer processes for spin-transfer torque MRAM - A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers by a third etch process. Optionally, the third etch may stop on the tunnel barrier or in the free layer. A second embodiment involves forming a first parallel line pattern on a hard mask layer and transferring the line pattern through the MTJ stack with a first etch step. A planar insulation layer is formed adjacent to the sidewalls in the line pattern and then a second parallel line pattern is formed which is transferred by a second etch through the MTJ stack to form a post pattern. Etch end point may be controlled independently for hard-axis and easy-axis dimensions. | 04-23-2009 |
20090117671 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING FERREOELECTRIC CAPACITOR - A method for manufacturing a semiconductor device includes the step of conducting an acceptance/rejection judgment about the semiconductor device. The acceptance/rejection judgment is conducted by using a hysteresis loop that indicates the relationship between the applied voltage and the polarization quantity of the ferroelectric capacitor. | 05-07-2009 |
20090130779 | Method of Forming a Magnetic Tunnel Junction Structure - In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) structure including a conductive layer on a substrate. The method also includes depositing a sacrificial layer on the conductive layer before depositing a patterning film layer. | 05-21-2009 |
20090137065 | METHOD FOR MANUFACTURING MEMORY DEVICE - A method for manufacturing a memory device including a ferroelectric memory array region and a logic circuit region is provided. The method includes the steps of: forming, above a base substrate, a plurality of ferroelectric capacitors in the ferroelectric memory array region; forming a wiring layer above the base substrate in the logic circuit region; forming an interlayer dielectric layer that covers the ferroelectric capacitors and the wiring layer; etching the interlayer dielectric layer formed at least in the ferroelectric memory array region to form a concave section; polishing the interlayer dielectric layer by a CMP (chemical mechanical polishing) method; etching the interlayer dielectric layer above the ferroelectric capacitors and the wiring layer to form contact holes; and forming contact sections in the contact holes. | 05-28-2009 |
20090137066 | Sensor for a magnetic memory device and method of manufacturing the same - The invention encompasses fabrication methods including the steps of preparing a silicon substrate, forming an amorphous III-V material layer on the silicon substrate, heating the amorphous III-V material layer, and epitaxially growing III-V material on the amorphous III-V material layer. | 05-28-2009 |
20090137067 | METHOD FOR FORMING AN INDUCTOR - A spiral inductor fabricated above a semiconductor substrate provides a large inductance while occupying only a small surface area. Including a layer of magnetic material above and below the inductor increases the inductance of the inductor. The magnetic material also acts as barrier that confines electronic noise generated in the spiral inductor to the area occupied by the spiral inductor. Inductance in a pair of stacked spiral inductors is increased by including a layer of magnetic material between the stacked spiral inductors. | 05-28-2009 |
20090142857 | Package design of small diameter sensor - A small sensor assembly is produced by encapsulating an inner package within an outer package. The inner assembly can have electrical components and sensors attached to a lead frame. The electrical components can be protected within inner packages that have alignment indentations. The alignment indentations are positioned over the outside edges of the lead frame and, preferably, no electrical components directly underlie the alignment indentations. The inner assembly is held in alignment by movable pins within a mold into which plastic is flowed. The mold is configured to cause some of the plastic to set earlier than the rest of the plastic and to hold the inner assembly in alignment within the mold. The movable pins can be retracted once enough plastic has set to hold the inner assembly. Unset plastic can then flow into the alignment indentations. A sealed sensor assembly is formed once all the plastic has set. | 06-04-2009 |
20090148962 | SUBSTRATE STRUCTURE AND METHOD FOR WIDEBAND POWER DECOUPLING - A substrate structure and method of wideband power decoupling comprising one or more embedded capacitors each comprising a ferroelectric material. | 06-11-2009 |
20090155931 | FERROELECTRIC LAYER WITH DOMAINS STABILIZED BY STRAIN - The present invention describes a method including: providing a substrate; forming an underlying layer over the substrate; heating the substrate; forming a ferroelectric layer over the underlying layer, the ferroelectric layer having a thickness below a critical thickness, the underlying layer having a smaller lattice constant than the ferroelectric layer; cooling the substrate to room temperature; and inducing a compressive strain in the ferroelectric layer. | 06-18-2009 |
20090155932 | METHOD OF MANUFACTURING MAGNETIC FIELD DETECTOR - Disclosed is a method of manufacturing a magnetic field detector having various structures that can be used as a high-density magnetic biosensor. An embodiment of the invention provides a method of manufacturing a magnetic field detector including a magnetoresistive element using a magnetic bead detecting thin film. The method includes: preparing a substrate; depositing the thin film on an upper surface of the substrate; and etching the thin film to form a ring-shaped magnetoresistive element. | 06-18-2009 |
20090162947 | AERODYNAMIC SHAPES FOR WAFER STRUCTURES TO REDUCE DAMAGE CAUSED BY CLEANING PROCESSES - Wafer structures and associated methods of fabrication are described. The wafer structures are fabricated to have aerodynamic shapes. Even if the structures on the wafer are fragile, the aerodynamic shapes of the structures create less resistance to a fluid flow of a cleaning process, and are less likely to be damaged by the cleaning process. Also, the aerodynamic shape of the structures allows a fluid flow to be directed toward the wafer from a single angle to effectively clean the wafer. | 06-25-2009 |
20090162948 | METHOD FOR ELIMINATING DEFECTS FROM SEMICONDUCTOR MATERIALS - Using a helium cryostat, the temperature for a substrate wafer(s) is reduced to 2.2 Kelvin over a period of twenty-four hours. Next, a soak segment will hold the temperature of the substrate wafer at 2.2 Kelvins for a period of ninety-six hours. At these low temperatures, alloys such as GaAs, InP, and GaP will form dipole molecular moments, which will re-align along lines of internal magnetic force as molecular bonds condense. Next the substrate wafer's temperature is ramped up to room temperature over a period of twenty-four hours. Next, the temperature of the substrate wafer is ramped up to assure that the temperature gradients made to occur within the wafer are kept low. Typically, a temper ramp up temperature will range between 300° F. to 1100° F. and depends upon the single crystal material used to construct the substrate wafer. Next, the substrate wafer undergoes a temper hold segment, which assures that the entire substrate wafer has had the benefit of the tempering temperature. A typical temper hold segment is around 3 hours and depends upon the material, thickness, and diameter size of the substrate wafer. | 06-25-2009 |
20090197350 | MAGNETIC MEMORY DEVICE AND METHOD - An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode via a connection that covers less than half of the first portion of the first electrode. Another exemplary embodiment of an MRAM device includes a magnetic tunnel junction, first and second electrodes (first and second magnetic field generating means) directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, and an electric power source having one pole connected to the first electrode via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second electrodes and the magnetic tunnel junction. Methods of operating and manufacturing these magnetic random access memories are also disclosed. | 08-06-2009 |
20090209050 | In-Situ Formed Capping Layer in MTJ Devices - A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers. | 08-20-2009 |
20090209051 | NONVOLATILE FERROELECTRIC PERPENDICULAR ELECTRODE CELL, FeRAM HAVING THE CELL AND METHOD FOR MANUFACTURING THE CELL - A nonvolatile ferroelectric perpendicular electrode cell comprises a ferroelectric capacitor and a serial PN diode switch. The ferroelectric capacitor includes a word line perpendicular electrode as a first electrode and a storage perpendicular electrode as a second electrode apart at a predetermined interval from the word line perpendicular electrode to have a column type, where a ferroelectric material is filled in a space where the first electrode are separated from the second electrode. The serial PN diode switch, which is connected between a bit line and the ferroelectric capacitor, selectively switches a current direction between the bit line and the ferroelectric capacitor depending on voltage change between the bit line and the ferroelectric capacitor. | 08-20-2009 |
20090233381 | Interconnect For a GMR Memory Cells And An Underlying Conductive Layer - A conductive plug located in a planar dielectric layer, under GMR memory cells, are used to directly connect the lower ferromagnetic layer of one of the GMR memory cell and a conductive layer under the planar dielectric layer. | 09-17-2009 |
20090233382 | High Polarization Ferroelectric Capacitors for Integrated Circuits - One aspect of the invention relates to a method of manufacturing an integrated circuit comprising forming an array of ferroelectric memory cells on a semiconductor substrate, heating the substrate to a temperature near a Curie temperature of the ferroelectric cores, and subjecting the substrate to a temperature program, whereby thermally induced stresses on the ferroelectric cores cause a switched polarization of the cores to increase by at least about 25% as the cores cool to about room temperature. Embodiments of the invention include metal filled vias of expanded cross-section above and below the ferroelectric cores, which increase the thermal stresses on the ferroelectric cores during cooling. | 09-17-2009 |
20090246890 | METHOD FOR MANUFACTURING A TUNNEL JUNCTION MAGNETORESISTIVE SENSOR WITH IMPROVED PERFORMANCE AND HAVING A CoFeB FREE LAYER - A method for manufacturing a magnetoresistive sensor that provides increased magnetoresistive performance. The method includes forming a series of sensor layers with at least one layer containing CoFeB, and having a first capping layer thereover. A high temperature annealing is performed to optimize the grains structure of the sensor layers. The first capping layer is then removed, such as by reactive ion etching (RIE). An antiferromagnetic layer is then deposited followed by a second capping layer. A second annealing is performed to set the magnetization of the pinned layer, the second annealing being performed at a lower temperature than the first annealing. | 10-01-2009 |
20090258443 | Nonvolatile memory devices and methods of fabricating the same - Nonvolatile memory devices and methods of fabricating the same are provided. In some embodiments, a nonvolatile memory device includes a lower conductive member formed on an upper part of or inside a substrate, a ferroelectric organic layer formed on the lower conductive member, a protective layer formed on the ferroelectric organic layer, and an upper conductive member formed on the protective layer to cross the lower conductive member. | 10-15-2009 |
20090263918 | METHODS AND APPARATUSES FOR DETERMINING THICKNESS OF A CONDUCTIVE LAYER - Methods and apparatuses are provided for calibrating eddy current sensors. A calibration curve is formed relating thickness of a conductive layer in a magnetic field to a value measured by the eddy current sensors or a value derived from such measurement, such as argument of impedance. The calibration curve may be an analytic function having infinite number terms, such as trigonometric, hyperbolic, and logarithmic, or a continuous plurality of functions, such as lines. Such curves can reduce the number of wafers used in the calibration of the sensors while providing higher accuracy over a larger thickness range. High accuracy allows the omission of optical sensors, and use of eddy current sensors for endpoint detection, transition call detection, and closed loop control in which a process parameter is changed based on the measured magnetic flux density change in one or more processing zones. | 10-22-2009 |
20090269860 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NH | 10-29-2009 |
20090275146 | METHOD AND APPARATUS FOR MANUFACTURING DEVICE - A method for manufacturing a device, includes: (A) forming a first electrode layer on a substrate; (B) forming a ferroelectric layer on the first electrode layer; (C) forming a second electrode layer on the ferroelectric layer; (D) forming a mask having a predetermined pattern on the second electrode layer; (E) forming a memory element by selectively removing the first electrode layer, the ferroelectric layer, and the second electrode layer using the mask; and (F) removing the mask, where at least, the processes (D) and (E), or the processes (E) and (F) are continuously performed under a reduced pressure. | 11-05-2009 |
20090275147 | MITIGATION OF EDGE DEGRADATION IN FERROELECTRIC MEMORY DEVICES THROUGH PLASMA ETCH CLEAN - A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed. | 11-05-2009 |
20090275148 | MITIGATION OF EDGE DEGRADATION IN FERROELECTRIC MEMORY DEVICES THROUGH PLASMA ETCH CLEAN - A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed. | 11-05-2009 |
20090280577 | Manufacturing method of a semiconductor device - There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode. | 11-12-2009 |
20090280578 | FERROELECTRIC MEMORY DEVICE AND FABRICATION PROCESS THEREOF, FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE - A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode. | 11-12-2009 |
20090298200 | Spin Transfer MRAM Device with Separated CPP Assisted Writing - A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in each bit cell have different resistance states and the MTJ cell and CPP cell in each sub-cell have different resistance states. The MTJ free layer rotates in response to switching in the CPP free layer because of a large demagnetization field exerted by the CPP free layer. An improved circuit design is disclosed that enables a faster and more reliable read process since the reference is a second MTJ within the same bit cell. When R | 12-03-2009 |
20090298201 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a manufacturing method of a semiconductor device, a first insulating film covering a ferroelectric capacitor is formed, and a first opening that has a relatively large diameter and reaches an electrode of the ferroelectric capacitor is formed in the first insulating film, and then recovery annealing of the ferroelectric capacitor is performed, and thereby, a path for oxygen can be secured in performing the recovery annealing, and the sufficient recovery annealing can be performed without causing problems during a manufacturing process. | 12-03-2009 |
20090298202 | Techniques for Coupling in Semiconductor Devices - Techniques for exchange coupling of magnetic layers in semiconductor devices are provided. In one aspect, a semiconductor device is provided. The device comprises at least two magnetic layers, and a spacer layer formed between the magnetic layers, the spacer layer being configured to provide ferromagnetic exchange coupling between the layers, the magnetic layers experiencing anti-ferromagnetic dipole coupling, such that a net coupling of the magnetic layers is anti-ferromagnetic in a zero applied magnetic field. The semiconductor device may comprise magnetic random access memory (MRAM). In another aspect, a method for coupling magnetic layers in a semiconductor device comprising at least two magnetic layers and a spacer layer therebetween, the method comprises the following step. Ferromagnetic exchange coupling is provided of the magnetic layers, the magnetic layers experiencing anti-ferromagnetic dipole coupling, such that a net coupling of the magnetic layers is anti-ferromagnetic in a zero applied magnetic field. | 12-03-2009 |
20090298203 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An aluminum oxide film covering a ferroelectric capacitor is formed. Next, an opening ( | 12-03-2009 |
20090298204 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film | 12-03-2009 |
20090317923 | SPIN-CURRENT SWITCHED MAGNETIC MEMORY ELEMENT SUITABLE FOR CIRCUIT INTEGRATION AND METHOD OF FABRICATING THE MEMORY ELEMENT - A magnetic memory element switchable by current injection includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers (e.g., between two of the magnetic layers). The memory element has the switching threshold current and device impedance suitable for integration with complementary metal oxide semiconductor (CMOS) integrated circuits. | 12-24-2009 |
20090325319 | Novel capping layer for a magnetic tunnel junction device to enhance dR/R and a method of making the same - An MTJ in an MRAM array or TMR read head is disclosed in which a low magnetization capping layer is a composite having a NiFeHf inner layer formed on a NiFe or CoFeB/NiFe free layer, a Ta middle layer, and a Ru outer layer on the Ta layer. For example, a low magnetization NiFeHf layer is achieved by co-sputtering NiFe and Hf targets with a forward power of 400 W and 200 W, respectively. A higher Hf content increases the oxygen gettering power of the NiFeHf layer and the thickness is modified to change dR/R, RA, and magnetostriction values. A so-called dead layer between the free layer and capping layer is restored by incorporating a NiFeHf layer on the free layer to improve lattice matching. The Fe content in the NiFe target used to make the NiFeHf layer is preferably the same as in the NiFe free layer. | 12-31-2009 |
20100003767 | MAGNETIC TUNNEL JUNCTION DEVICE, MEMORY CELL HAVING THE SAME, AND METHOD FOR FABRICATING THE SAME - A method for fabricating a magnetic tunnel junction device includes forming an insulation layer having a plurality of openings, forming a first electrode over the bottom and the sidewall of an opening of the plurality of openings, forming a magnetic tunnel junction layer over the first electrode, and forming a second electrode over the magnetic tunnel junction layer to fill the remaining openings. | 01-07-2010 |
20100009466 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An interlayer insulating film ( | 01-14-2010 |
20100009467 | Novel magnetic tunnel junction (MTJ) to reduce spin transfer magnetization switching current - A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×10 | 01-14-2010 |
20100015729 | METHODS OF FORMING A THIN FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME - In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved. | 01-21-2010 |
20100015730 | Magnetic self-assembly for integrated circuit packages - An integrated circuit package may include a substrate and an integrated circuit. The substrate may include at least one region, and a first magnetic material associated with the at least one region. The integrated circuit may have a second magnetic material associated therewith. The second magnetic material may be attracted to the first magnetic material to coupled the integrated circuit to the at least one region of the substrate. The IC package may be utilized in an RFID tag of an RFID system. An associated method for assembling an integrated circuit to a substrate is also provided. | 01-21-2010 |
20100022030 | DRY ETCH STOP PROCESS FOR ELIMINATING ELECTRICAL SHORTING IN MRAM DEVICE STRUCTURES - The present invention relates generally to semiconductor fabrication and particularly to fabricating magnetic tunnel junction devices. In particular, this invention relates to a method for using the dielectric layer in tunnel junctions as an etch stop layer to eliminate electrical shorting that can result from the patterning process. | 01-28-2010 |
20100022031 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film. | 01-28-2010 |
20100022032 | METHOD OF FORMING ORGANIC FERROELECTRIC FILM, METHOD OF MANUFACTURING MEMORY ELEMENT, MEMORY DEVICE, AND ELECTRONIC APPARATUS - A method of forming an organic ferroelectric film configured to include an organic ferroelectric material with a crystalline property as a principal material includes (a) forming a low crystallinity film having a crystallinity lower than a crystallinity of the organic ferroelectric film on one surface of a substrate, and (b) forming the organic ferroelectric film from the low crystallinity film. The step (a) includes applying a liquid material containing the organic ferroelectric material on the one surface of the substrate and then drying the liquid material, and the step (b) includes heating and pressurizing the low crystallinity film to enhancing the crystallinity in the low crystallinity film while fairing the low crystallinity film. | 01-28-2010 |
20100041168 | METHODS OF FABRICATING MAGNETIC MEMORY DEVICES WITH THIN CONDUCTIVE BRIDGES - A magnetic memory device includes a free layer and a guide layer on a substrate. An insulating layer is interposed between the free layer and the guide layer. At least one conductive bridge passes through the insulating layer and electrically connects the free layer and the guide layer. A diffusion barrier may be interposed between the guide layer and the insulating layer. The device may further include a reference layer having a fixed magnetization direction on a side of the free layer opposite the insulating layer and a tunnel barrier between the reference layer and the free layer. Related fabrication methods are also described. | 02-18-2010 |
20100047929 | Novel underlayer for high performance magnetic tunneling junction MRAM - An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to avoid shunting of a sense current caused by redeposition of the capping layer on the sidewalls of the tunnel barrier layer. Alternatively, the α-TaN layer is the seed layer in the MTJ. Furthermore, the seed layer may be a composite layer comprised of a NiCr, NiFe, or NiFeCr layer on the α-TaN layer. An α-TaN capping layer or seed layer can also be used in a TMR read head. An MTJ formed on an α-TaN capping layer has a high MR ratio, high Vb, and a RA similar to results obtained from MTJs based on an optimized Ta capping layer. | 02-25-2010 |
20100047930 | MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact. | 02-25-2010 |
20100047931 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - When adopting a stack-type capacitor structure for a ferroelectric capacitor structure ( | 02-25-2010 |
20100055804 | METHOD FOR PATTERNING SEMICONDUCTOR DEVICE HAVING MAGNETIC TUNNELING JUNCTION STRUCTURE - A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier. | 03-04-2010 |
20100055805 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes forming a first film made of a first metal to an upper portion of a substrate, forming a second film made of an amorphous metal oxide or an microcrystalline metal oxide on the first film, subjecting the second film to a heat treatment, subjecting the second film after the heat treatment to a reduction treatment, forming a third film made of a ferroelectric material on the second film, and forming a fourth film made of a second metal on the third film. | 03-04-2010 |
20100055806 | Piezoelectrically Actuated Ultrananocrystalline Diamond Tip Array Integrated With Ferroelectric Or Phase Change Media For High-Density Memory - A compact large density memory piezoactuated storage device and process for its fabrication provides an integrated microelectromechanical (MEMS) and/or nanoelectromechanical (NEMS) system and structure that features an integrated large density array of nanotips made of wear-resistant conductive ultrananocrystalline diamond (UNCD) in which the tips are actuated via a piezoelectric thin film integrated with the UNCD tips. The tips of the special piezoactuated storage device effectively contact an underlying metal layer (top electrode) deposited on a polarizable ferroelectric layer that is grown on top of another metal layer (bottom electrode) to form a ferroelectric capacitor. Information is imprinted in the ferroelectric layer by the polarization induced by the application of a voltage pulse between the top and bottom electrodes through the conductive UNCD tips. This integrated microelectromechanical (MEMS) and/or nanoelectromechanical (NEMS) system and structure can be efficiently used to imprint data in the ferroelectric layer for memory storage with high density in the gigabit (Gb) to terabit (Tb) range. An alternative memory media to the ferroelectric layer can be a phase change material that exhibits two orders of magnitude difference in electrical resistance between amorphous and crystalline phases. | 03-04-2010 |
20100068828 | METHOD OF FORMING A STRUCTURE HAVING A GIANT RESISTANCE ANISOTROPY OR LOW-K DIELECTRIC - A method is provided involving the growth of carbon nanotubes to provide giant resistance anisotropy or a low-k dielectric. The method comprises growing a plurality of one-dimensional nanostructures ( | 03-18-2010 |
20100068829 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM - A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma. | 03-18-2010 |
20100087014 | HEAT TREATMENT APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a heat treatment apparatus including a treatment chamber housing a silicon substrate, a heater being provided in the treatment chamber and heating the silicon substrate, and an atmosphere adjustment mechanism reducing a concentration of oxygen contained in an atmosphere inside the treatment chamber to less than an oxygen concentration in the air. The atmosphere adjustment mechanism is provided with an oxygen trap, for example. | 04-08-2010 |
20100093110 | Ferroelectric passive memory cell, device and method of manufacture thereof - A first passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer; wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out or data-input purposes only, a plurality of conducting pins isolated from one another. | 04-15-2010 |
20100105152 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A lower electrode film is formed above a semiconductor substrate first, and then a ferroelectric film is formed on the lower electrode film. After that, an upper electrode film is formed on the ferroelectric film. When forming the upper electrode, an IrO | 04-29-2010 |
20100112728 | METHODS FOR STRIPPING MATERIAL FOR WAFER RECLAMATION - Removal compositions and processes for removing at least one material layer from a rejected microelectronic device structure having same thereon. The removal composition includes hydrofluoric acid. The composition achieves substantial removal of the material(s) to be removed while not damaging the layers to be retained, for reclaiming, reworking, recycling and/or reuse of said structure. | 05-06-2010 |
20100120175 | SENSOR DOUBLE PATTERNING METHODS - A method of making a memory cell or magnetic element by double patterning. The method includes providing a starting stack having a first area, masking a portion of the first area of the starting stack resulting in a first masked portion and a first unmasked portion. Then, removing the first unmasked portion of the starting stack to provide a second area. A portion of this second area is masked, resulting in a second masked portion and a second unmasked portion. The method also includes removing the second unmasked portion to provide a third area, with the finished cell or element being the third area. | 05-13-2010 |
20100120176 | METHOD FOR MANUFACTURING MAGNETIC MEMORY CHIP DEVICE - A method for manufacturing a magnetic memory chip device is provided with a step of writing information on a plurality of magnetic memory chips formed on a silicon wafer; a step of adhering a high permeability plate, which is composed of a material having permeability higher than that of silicon and has a thickness of 50 μm or more, on the rear surface of a silicon wafer after writing the information; and a step of dicing the silicon wafer into magnetic memory chips after adhering the high permeability plate. | 05-13-2010 |
20100129938 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a semiconductor substrate and a transistor formed on the semiconductor substrate. The semiconductor device also includes: a first interlayer insulation film formed on the semiconductor substrate including the upper portion of the transistor, a first contact formed to be connected through the first interlayer insulation film to the transistor, a ferroelectric capacitor formed to be connected to the first contact, a second interlayer insulation film formed on the first interlayer insulation film, and a second contact formed to connect the ferroelectric capacitor to a wiring through the second interlayer insulation film. The contact surfaces between the second contact and the ferroelectric capacitor have the same planar shape. | 05-27-2010 |
20100136712 | COMPOUND AND METHOD FOR PRODUCING THE SAME - The invention provides a Ti doped lead barium zirconate dielectric material which could be applied to high frequency devices. The material comprises a compound with the chemical formula (Pb | 06-03-2010 |
20100136713 | Hafnium doped cap and free layer for mram device - A high performance MTJ, and a process for manufacturing it, are described. A capping layer of NiFeHf is used to getter oxygen out of the free layer, thereby increasing the sharpness of the free layer-tunneling layer interface. The free layer comprises two NiFe layers whose magnetostriction constants are of opposite sign, thereby largely canceling one another. | 06-03-2010 |
20100144062 | FABRICATING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS - A first electrode film, a ferroelectric film, and a second electrode film are accumulated above a semiconductor in this order, a hard mask is accumulated above the second electrode, scrub cleaning is performed on the surface of the hard mask with an surfactant, the hard mask on which the scrub cleaning is performed has been patterned according to a planar shape of a ferroelectric capacitor, and etching is performed by using as a hard mask the hard mask that has been patterned. | 06-10-2010 |
20100144063 | Seminconductor device - The present invention provides a signal transmitting/receiving method comprising: disposing a ferromagnetic film between a semiconductor device having an inductor and an external device which includes an external inductor provided in a position corresponding to the inductor of the semiconductor device; disposing the inductor and the external inductor so as to face each other via the ferromagnetic film therebetween; and in a state in which the inductor and the external inductor face each other, transmitting and receiving the signals between the inductor and the external inductor by electromagnetic induction. | 06-10-2010 |
20100144064 | SEMICONDUCTOR DEVICE HAVING A FERROELECTRIC CAPACITOR - An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at a value in a range of 90 weight % to 93 weight % to produce a package structure. | 06-10-2010 |
20100151595 | MAGNETIC RAM - A memory element for a magnetic RAM, having a first magnetic portion in a first recess of a first insulating layer; and a non-magnetic portion and a second magnetic portion in a second recess of a second insulating layer covering the first insulating layer, the second recess exposing the first magnetic portion and a portion of the first insulating layer around the first magnetic portion, the non-magnetic portion being interposed between the first and second magnetic portions. | 06-17-2010 |
20100167423 | Semiconductor package and methods of manufacturing the same - A semiconductor package includes a semiconductor chip having first and second pads, a first insulation layer pattern formed on the semiconductor chip and having first and second openings that expose the first and the second pads, respectively, a first conductive layer pattern elongated along the first insulation layer pattern from the first pad, a first external terminal formed on the first conductive layer pattern, a second insulation layer pattern formed on the first conductive layer pattern and the first insulation layer pattern to expose the first external terminal and having a third opening in communication with the second opening, a second conductive layer pattern elongated along the second insulation layer pattern from the second pad, and a second external terminal formed on the second conductive layer pattern. | 07-01-2010 |
20100178714 | Method of forming magnetic memory device - There are provided a magnetic memory device and a method of forming the magnetic memory device. The method of forming the magnetic memory device includes sequentially forming a first magnetic conductor, a tunnel barrier layer, and a second magnetic conductor on a substrate, forming a mask pattern on the second magnetic conductor, performing a primary etching of the second magnetic conductor by using the mask pattern as an etching mask, forming at least one spacer on sidewalls of the second magnetic conductor formed by the primary etching, and performing a secondary etching of the first magnetic conductor by using the mask pattern and the at least one spacers as an etching mask. | 07-15-2010 |
20100178715 | MRAM with storage layer and super-paramagnetic sensing layer - An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external field, and in which magnetization is roughly proportional to an external field until reaching a saturation value. In one embodiment, a separate storage layer is formed above, below, or adjacent to the MTJ and has uniaxial anisotropy with a magnetization direction along its easy axis which parallels the first axis. In a second embodiment, the storage layer is formed on a non-magnetic conducting spacer layer within the MTJ and is patterned simultaneously with the MTJ. The SP free layer may be multiple layers or laminated layers of CoFeB. The storage layer may have a SyAP configuration and a laminated structure. | 07-15-2010 |
20100184239 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING MAGNETIC MEMORY - In the case where a laminated structure formed by laminating tunneling magnetoresistive films are processed by ion milling or the like, scattered substances of a material constituting the tunneling magnetoresistive film are deposited onto side walls of the laminated structure, or contaminate the inside of a device for processing. Accordingly, it has been difficult to manufacture a magnetic memory or a semiconductor device on which the magnetic memory is mounted, with stable characteristics. | 07-22-2010 |
20100184240 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a method of manufacturing a semiconductor device, which comprises the steps of: forming a hydrogen diffusion preventing insulating film covering capacitors; forming a capacitor protecting insulating film on the hydrogen diffusion preventing insulating film; and forming a first insulating film on the capacitor protecting insulating film by a plasma CVD method where, while a high-frequency bias electric power is applied toward the semiconductor substrate, a plasma-generating high frequency electric power is applied to first deposition gas containing oxygen and silicon compound gas. In the method, a condition by which moisture content in the capacitor protecting insulating film becomes less than that in the first insulating film is adopted as a film deposition condition for the capacitor protecting insulating film. | 07-22-2010 |
20100197043 | STRUCTURE AND METHOD FOR FABRICATING CLADDED CONDUCTIVE LINES IN MAGNETIC MEMORIES - A method of forming a magnetoelectronic device includes forming a dielectric material ( | 08-05-2010 |
20100197044 | METHOD OF MANUFACTURING A MAGNETIC RANDOM ACCESS MEMORY, METHOD OF MANUFACTURING AN EMBEDDED MEMORY, AND TEMPLATE - A magnetic material of a magnetoresistive element is formed on a lower electrode. An upper electrode is formed on the magnetic material. A resist for nano-imprint lithography is formed on the upper electrode. A first pattern or a second pattern is formed in the resist by setting a first template or a second template into contact with the resist and curing the resist. The first template has the first pattern that corresponds to the magnetoresistive element and the lower electrode. The second template has the second pattern that corresponds to the magnetoresistive element and the upper electrode. The magnetic material and the lower electrode are patterned at the same time by using the resist having the first pattern, or the magnetic material and the upper electrode are patterned at the same time by using the resist having the second pattern. | 08-05-2010 |
20100197045 | Power Semiconductor Devices Having Integrated Inductor - An electronic device ( | 08-05-2010 |
20100197046 | SEMICONDUCTOR DEVICE - A silicide film is formed between a ferroelectric capacitor structure, which is formed by sandwiching a ferroelectric film between a lower electrode and an upper electrode, and a conductive plug (the conductive material constituting the plug is tungsten (W) for example). Here, an example is shown in which a base film of the conductive plug is the silicide film. | 08-05-2010 |
20100221848 | Embedded Magnetic Random Access Memory (MRAM) - A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ. | 09-02-2010 |
20100240151 | Method of double patterning and etching magnetic tunnel junction structures for spin-transfer torque MRAM devices - A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps each followed by two plasma etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers. The hard mask has an upper Ta layer with a thickness of 300 to 400 Angstroms and a lower NiCr layer less than 50 Angstroms thick. The upper Ta layer is etched with a fluorocarbon etch while lower NiCr layer and underlying MTJ layers are etched with a CH | 09-23-2010 |
20100240152 | Current-Confined Effect of Magnetic Nano-Current-Channel (NCC) for Magnetic Random Access Memory (MRAM) - One embodiment of the present invention includes a memory element having a composite free layer including a first free sub-layer formed on top of the bottom electrode, a nano-current-channel (NCC) layer formed on top of the first free sub-layer, and a second free sub-layer formed on top of the NCC layer, wherein when switching current is applied to the memory element, in a direction that is substantially perpendicular to the layers of the memory element, local magnetic moments of the NCC layer switch the state of the memory element. | 09-23-2010 |
20100248395 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A ferroelectric capacitor provided with a ferroelectric film ( | 09-30-2010 |
20100261294 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - After a first via hole leading to a ferroelectric capacitor structure are formed in an interlayer insulating film by dry etching, a second via hole to expose part of the ferroelectric capacitor structure is formed in a hydrogen diffusion preventing film so as to be aligned with the first via hole by wet etching, and a via hole constructed by the first via hole and the second via hole communicating with each other is formed. | 10-14-2010 |
20100261295 | High performance MTJ element for STT-RAM and method for making the same - A method of forming a STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co | 10-14-2010 |
20100261296 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is disclosed. The semiconductor device includes a ferroelectric capacitor formed on a substrate and a wiring structure formed on the ferroelectric capacitor. The wiring structure includes a dielectric inter layer and a Cu wiring section formed in the dielectric inter layer. In addition, an etching stopper layer including a hydrogen diffusion preventing layer is formed so as to face the dielectric inter layer. | 10-14-2010 |
20100267171 | MAGNETIC STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - In an MRAM, a curved region ( | 10-21-2010 |
20100285613 | IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND FABRICATION METHOD THEREOF - An in-plane switching mode liquid crystal display device includes a first substrate including a pixel electrode in a pixel region, a second substrate facing the first substrate and including a common electrode, a first alignment layer on the pixel electrode, a second alignment layer on the common electrode, a first ferroelectric liquid crystal layer on the first alignment layer and including a first spontaneous polarization, a second ferroelectric liquid crystal layer on the second alignment layer and including a second spontaneous polarization, a rotational direction of the first ferroelectric liquid crystal layer with respect to the first alignment layer being different from a rotational direction of the second ferroelectric liquid crystal layer with respect to the second alignment layer, and a twisted nematic liquid crystal layer between the first and second ferroelectric liquid crystal layers. | 11-11-2010 |
20100304504 | PROCESS AND APPARATUS FOR FABRICATING MAGNETIC DEVICE - Process and apparatus for fabricating a magnetic device is provided. Magnetic and/or nonmagnetic layers i n the device are etched by a mixed gas of a hydrogen gas and an inert gas such as N | 12-02-2010 |
20100323458 | METHOD FOR MAKING P(VDF/TrFE) COPOLYMER LAYER SENSORS, AND CORRESPONDING SENSOR - The invention relates to the manufacture of a matrix sensor using a sensitive layer of a ferroelectric P(VDF/TrFE) copolymer, deposited on an integrated circuit. In order to simplify the manufacture and improve the yields, deposited first on the integrated circuit is a first layer of titanium and it is etched in order to form a matrix array of electrodes electrically connected to the integrated circuit; next, a P(VDF/TrFE) copolymer comprising a small proportion of around 1 to 10% of a second polymer that favors the adhesion of the P(VDF/TrFE) copolymer is deposited on the integrated circuit; the polymer is either underneath the P(VDF/TrFE) or blended therewith. The copolymer and its adhesion promoter are etched in a single step, and finally a second conductive layer is deposited and it is etched in order to form a counter electrode for the whole of the matrix array. For use in ultrasonic image sensors. | 12-23-2010 |
20100330707 | Robust Self-Aligned Process for Sub-65nm Current-Perpendicular Junction Pillars - A method for fabricating a device includes forming a first insulation layer to cover a removable mask and a device structure that has been defined by the mask. The device structure is below the mask. The mask is lifted off to expose a top portion of the device structure. A conductive island structure is formed over the first insulation layer and the exposed top portion of the device structure. The first insulation layer and the conductive island structure are covered with a second insulation layer. A contact is formed through the second insulation layer to the conductive island structure. | 12-30-2010 |
20100330708 | METHODS FOR MULTI-STAGE MOLDING OF INTEGRATED CIRCUIT PACKAGE - Methods for providing an integrated circuit using a multi-stage molding process to protect wirebonds. In one embodiment, a method includes attaching a die to a leadframe having a lead finger, attaching a wirebond between the die and the leadfinger, applying a first mold material over at least a portion of the wirebond and the die and the leadfinger to form an assembly, waiting for the first mold material to at least partially cure, and applying a second mold material over the assembly. | 12-30-2010 |
20110008915 | METHOD FOR USE IN MAKING ELECTRONIC DEVICES HAVING THIN-FILM MAGNETIC COMPONENTS - Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness. | 01-13-2011 |
20110033955 | NONVOLATILE FERROELECTRIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile ferroelectric memory device includes a plurality of unit cells. Each of the unit cells includes a cell capacitor and a cell transistor. The cell capacitor includes a storage node, a ferroelectric layer, and a plate line. The cell capacitors of more than one of the plurality of unit cells are provided in a trench. | 02-10-2011 |
20110045609 | METHOD FOR DETACHING LAYERS WITH LOW MAGNETIC PERMEABILITY - A method for detaching a first material layer from a second material layer includes following steps. Firstly, a high-magnetic-permeability material layer is formed on a first material layer. Secondly, a second material layer is formed on the high-magnetic-permeability material layer. Thirdly, the first and second material layers are cooled such that the first and second material layers shrink, wherein the first and second material layers are low-magnetic-permeability materials. Finally, the high-magnetic-permeability material layer is heated by applying a high-frequency radiofrequency electromagnetic wave thereto such that the high-magnetic-permeability material layer expands, thus detaching the first material layer from the second material layer. | 02-24-2011 |
20110053293 | MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively. | 03-03-2011 |
20110059557 | METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE - A method of manufacturing a nonvolatile memory device having a laminated structure in which a first magnetic material layer, a tunnel insulator film, and a second magnetic material layer are sequentially laminated, in which information is stored when an electric resistance value changes depending on a magnetization reversal state is disclosed. The method includes the steps of: sequentially forming the first magnetic material layer, the tunnel insulator film, and the second magnetic material layer; forming a mask layer on the second magnetic material layer; oxidizing a part uncovered by the mask layer of the second magnetic material layer; and reducing the oxidized part of the second magnetic material layer. | 03-10-2011 |
20110076784 | Fabrication of Magnetic Element Arrays - Techniques for fabricating an array of magnetic elements to form memory and other devices with a high areal density. | 03-31-2011 |
20110076785 | Process to fabricate bottom electrode for MRAM device - Formation of a bottom electrode for an MTJ device on a silicon nitride substrate is facilitated by including a protective coating that is partly consumed during etching of the alpha tantalum portion of said bottom electrode. Adhesion to SiN is enhanced by using a TaN/NiCr bilayer as “glue”. | 03-31-2011 |
20110081732 | Method of Manufacturing Magnetic Tunnel Junction Device and Apparatus for Manufacturing the Same - A method of manufacturing a magnetic tunnel junction device includes a barrier layer forming step of forming a tunnel barrier layer. The barrier layer forming step comprises a step of depositing a first metal layer, an oxygen surfactant layer forming step of forming an oxygen surfactant layer on the first metal layer, a step of deposing a second metal layer above the first oxygen surfactant layer, and an oxidation step of oxidizing the first metal layer and the second metal layer to form a metal oxide layer. | 04-07-2011 |
20110081733 | Thin film photovoltaic device - The present invention provides a thin film photovoltaic device and a method of forming a thin film photovoltaic device. The thin film photovoltaic device has a substrate, a thin film layer formed on the substrate and first and second electrodes formed on one side of the thin film layer. By applying an electric field over the first and second electrodes, the thin film layer is polarized in a direction parallel to the surface plane of the film. Upon exposure to light, the thin film layer converts light energy into electricity. According to the method, a thin film layer is formed on a substrate. A first electrode and a second electrode are formed on one side of the thin film layer. By applying an electric field over the first and second electrodes, the thin film layer is polarized in a direction parallel to the surface plane of the film. | 04-07-2011 |
20110086439 | METHOD AND APPARATUS FOR MANUFACTURING MAGNETORESISTIVE ELEMENT - A method of manufacturing a magnetoresistive element includes a tunnel barrier forming step. The tunnel barrier forming step comprises a metal layer forming step of forming a metal layer to have a first thickness, a plasma processing step of performing a plasma treatment which exposes the metal layer to a plasma of an inert gas to etch the metal layer to have a second thickness smaller than the first thickness, and an oxidation step of oxidizing the metal layer having undergone the plasma treatment to form a metal oxide which forms a tunnel barrier. | 04-14-2011 |
20110086440 | METHOD FOR MANUFACTURING AN EXTRAORDINARY MAGNETORESISTIVE (EMR) DEVICE WITH NOVEL LEAD STRUCTURE - A method for manufacturing an extraordinary magnetoresistive sensor (EMR sensor) having reduced size and increased resolution is described. The sensor includes a plurality of electrically conductive leads contacting a magnetically active layer and also includes an electrically conductive shunt structure. The electrically conductive leads of the sensor and the shunt structure can be formed in a common photolithographic masking and etching process so that they are self aligned with one another. This avoids the need to align multiple photolithographic processing steps, thereby allowing greatly increased resolution and reduced lead spacing. The EMR sensor can be formed with a magnetically active layer that can be close to or at the air bearing surface (ABS) for improved magnetic spacing with an adjacent magnetic medium of a data recording system. | 04-14-2011 |
20110091998 | SEMICONDUCTOR DEVICE INCLUDING FERROELECTRIC CAPACITOR - A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AO | 04-21-2011 |
20110104827 | Template-Registered DiBlock Copolymer Mask for MRAM Device Formation - A method for fabricating a magnetoresistive random access memory (MRAM) includes forming a mask over a magnetic layer; forming a template on the mask; applying a diblock copolymer to the template; curing the diblock copolymer to form a first plurality of uniform shapes registered to the template; etching the mask to form a second plurality of uniform shapes; and etching the magnetic layer to form a third plurality of uniform shapes, the third plurality of uniform shapes comprising a plurality of magnetic tunnel junctions (MTJs). A diblock copolymer mask for fabricating a magnetoresistive random access memory (MRAM) includes a magnetic layer; a mask formed on the magnetic layer; a template formed on the mask; and a diblock copolymer mask comprising a plurality of uniform shapes formed on and registered to the template. | 05-05-2011 |
20110104828 | METHOD FOR MAKING MICROSTRUCTURES BY CONVERTING POROUS SILICON INTO POROUS METAL OR CERAMICS - A method for making a micro structure ( | 05-05-2011 |
20110104829 | METHOD OF TRANSFER BY MEANS OF A FERROELECTRIC SUBSTRATE - A method of carrying out a transfer of one or more first components or of a first layer onto a second substrate including: a) application and maintaining, by electrostatic effect, of the one or more first components or of the first layer, on a first substrate, made of a ferroelectric material, electrically charged, b) placing in contact, direct or by molecular adhesion, and transfer of the components or the layer onto a second substrate, and c) dismantling of the first substrate, leaving at least one part of the components or the layer on the second substrate. | 05-05-2011 |
20110111532 | METHODS OF FORMING PATTERN STRUCTURES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - Methods of forming pattern structures and methods of manufacturing memory devices using the same are provided, the methods of forming pattern structures include forming an etching object layer on a substrate and performing a plasma reactive etching process on the etching object layer using an etching gas including at least ammonia (NH | 05-12-2011 |
20110117677 | Spacer structure in MRAM cell and method of its fabrication - Methods are presented for fabricating an MTJ element having a uniform vertical distance between its free layer and a bit line and, in addition, having a protective spacer layer formed abutting the lateral sides of the MTJ element to eliminate leakage currents between MTJ layers and the bit line. Each method forms a dielectric spacer layer on the lateral sides of the MTJ element and, depending on the method, includes an additional layer that protects the spacer layer during etching processes used to form a Cu damascene bit line. At various stages in the process, a dielectric layer is also formed to act as a CMP stop layer so that the capping layer on the MTJ element is not thinned by the CMP process that planarizes the surrounding insulation. Subsequent to planarization, the stop layer is removed by an anisotropic etch of such precision that the MTJ element capping layer is not reduced in thickness and serves to maintain uniform vertical distance between the bit line and the MTJ free layer. | 05-19-2011 |
20110124133 | SPIN-CURRENT SWITCHABLE MAGNETIC MEMORY ELEMENT AND METHOD OF FABRICATING THE MEMORY ELEMENT - A method of fabricating a magnetic memory element includes forming a plurality of magnetic layers having a perpendicular magnetic anisotropy component, in which the plurality of magnetic layers includes a first magnetic layer having an alloy of a rare-earth metal and a transition metal, and a second magnetic layer. | 05-26-2011 |
20110129946 | High density spin-transfer torque MRAM process - A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden. | 06-02-2011 |
20110143459 | SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure. | 06-16-2011 |
20110143460 | METHOD OF MANUFACTURING MAGNETORESISTANCE ELEMENT AND STORAGE MEDIUM USED IN THE MANUFACTURING METHOD - An embodiment of the invention provides a method of manufacturing a magnetoresistance element with an MR ratio higher than that of the related art. | 06-16-2011 |
20110151587 | METHOD OF PRODUCING AN INTEGRATED MICROMAGNET SENSOR ASSEMBLY - A method of integrating a permanent bias magnet within a magnetoresistance sensor comprising depositing an alternating pattern of a metal material and a semiconductor material on or within a surface of an insulating substrate; depositing a mask on the surface of the insulating substrate to create an opening above the alternating pattern of metal material and semiconductor material; applying a magnetic paste within the opening above the alternating pattern of metal material and semiconductor material; curing the magnetic paste to form a hardened bias magnet; removing the mask; and magnetizing the hardened bias magnet by applying a strong magnetic field to the hardened bias magnet at a desired orientation. | 06-23-2011 |
20110151588 | METHOD AND MAGNETIC TRANSFER STAMP FOR TRANSFERRING SEMICONDUCTOR DICE USING MAGNETIC TRANSFER PRINTING TECHNIQUES - Releasable semiconductor dice are deposited with a magnetic layer and held by magnetic forces to a magnetic or electromagnetic transfer stamp for the transfer of the dice from a host substrate directly or indirectly to a target substrate. | 06-23-2011 |
20110151589 | PRODUCTION OF A DEVICE COMPRISING MAGNETIC STRUCTURES FORMED ON ONE AND THE SAME SUBSTRATE AND HAVING RESPECTIVE DIFFERENT MAGNETIZATION ORIENTATIONS - The invention relates to a method for producing a device comprising magnetic blocks magnetized in different directions, comprising steps of:
| 06-23-2011 |
20110159609 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming first conductive layer on semiconductor substrate; forming a magnetic film on the first conductive layer; forming second conductive layer on the magnetic film; forming a first mask layer on the second conductive layer; patterning the second conductive layer; patterning the magnetic film; forming a first insulating film on the first conductive layer to cover side surfaces of the patterned second conductive layer and the patterned magnetic film; forming a second mask layer on the first insulating film to cover the patterned second conductive layer, the patterned magnetic film, and the first insulating film; patterning the first insulating film; patterning the first conductive layer; forming a second insulating film on the semiconductor substrate to cover the patterned second conductive layer, the patterned magnetic film, and the patterned first conductive layer; and forming a third insulating film on the second insulating film. | 06-30-2011 |
20110165702 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A ferroelectric capacitor is formed over a semiconductor substrate ( | 07-07-2011 |
20110171755 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE HAVING MEMORY ELEMENT WITH PROTECTIVE FILM - To provide a manufacturing method of a semiconductor device capable of forming, as a protective film of an MTJ element, a silicon nitride film having good insulation properties without deteriorating the properties of the MTJ element. The method of the invention includes steps of forming a silicon nitride film over the entire surface including an MTJ element portion (MTJ element and an upper electrode) while using a parallel plate plasma CVD apparatus as a film forming apparatus and a film forming gas not containing NH | 07-14-2011 |
20110177621 | MAGNETIC MEMORY CELL CONSTRUCTION - A magnetic tunnel junction cell having a free layer, a ferromagnetic pinned layer, and a barrier layer therebetween. The free layer has a central ferromagnetic portion and a stabilizing portion radially proximate the central ferromagnetic portion. The construction can be used for both in-plane magnetic memory cells where the magnetization orientation of the magnetic layer is in the stack film plane and out-of-plane magnetic memory cells where the magnetization orientation of the magnetic layer is out of the stack film plane, e.g., perpendicular to the stack plane. | 07-21-2011 |
20110183440 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, AND THIN FILM DEVICE - A manufacturing method of a semiconductor device is disclosed. The manufacturing method includes the steps of forming a contact plug in an insulation film so as to be connected to an element on a semiconductor substrate, applying PLA pretreatment to the insulation film in an NH | 07-28-2011 |
20110183441 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device and a method of fabricating a semiconductor device that includes forming an interlayer insulating film on a semiconductor substrate; depositing a first soft magnetic thin film on the interlayer insulating film through sputtering using a target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N | 07-28-2011 |
20110189796 | Uniformity in the Performance of MTJ Cells - A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode. | 08-04-2011 |
20110201133 | Method for forming polarization reversal - A method for forming a ferroelectric spontaneous polarization reversal, including the steps of forming a concave portion on a top face of a ferroelectric substrate or a bottom face of a ferroelectric substrate, and applying an electric field into the substrate, wherein a ferroelectric spontaneous polarization reversal is formed at least in one portion of a region of the substrate with the concave portion, and wherein the shape of the concave portion is configured such that the width of the concave portion gets narrower gradually toward the inside of the substrate. The method may further include the steps of, after the reversal, making into almost a flat-plane the top or bottom face having the concave portion, and then, forming a new concave portion in another region and applying an electric field to form another reversal in one portion of the region of the substrate having the new concave portion. | 08-18-2011 |
20110207240 | Information storage devices using movement of magnetic domain walls and methods of manufacturing the same - An information storage device using movement of magnetic domain walls includes a writing magnetic layer having a magnetic domain wall. A stack structure is formed on the writing magnetic layer. The stack structure includes a connecting magnetic layer and an information storing magnetic layer stacked sequentially. The information storage device also includes a reader for reading information stored in the information storing magnetic layer. | 08-25-2011 |
20110212545 | Ferroelectric passive memory cell, device and method of manufacture thereof - A first passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer; wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out or data-input purposes only, a plurality of conducting pins isolated from one another. | 09-01-2011 |
20110217792 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An FeRAM is produced by a method including the steps of forming a lower electrode layer ( | 09-08-2011 |
20110217793 | Methods of Processing a Substrate and Forming a Micromagnetic Device - A method of processing a substrate with a conductive film formed thereover and method of forming a micromagnetic device. In one embodiment, the method of processing the substrate includes reducing a temperature of the substrate to a stress-compensating temperature, and maintaining the temperature of the substrate at the stress-compensating temperature for a period of time. The method also includes increasing the temperature of the substrate above the stress-compensating temperature. | 09-08-2011 |
20110223692 | MICROWAVE INTEGRATED CIRCUIT PACKAGE AND METHOD FOR FORMING SUCH PACKAGE - A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects. | 09-15-2011 |
20110229985 | Fabrication of Magnetic Tunnel Junction (MTJ) Devices with Reduced Surface Roughness for Magnetic Random Access Memory (MRAM) - Reliability and yield of MTJ devices is improved by reducing surface roughness in the MTJ layers of the MTJ devices. Surface roughness is reduced by reducing surface roughness of layers below the MTJ layers such as the bottom electrode layer. Planarizing the bottom electrode layer through chemical mechanical polishing or etch back of spin-on material before depositing the MTJ layers decreases surface roughness of the bottom electrode layer and the MTJ layers. Alternatively, a capping layer may be planarized before deposition of the bottom electrode layer and MTJ layers to reduce surface roughness in the capping layer, the bottom electrode layer, and the MTJ layers. | 09-22-2011 |
20110229986 | Magnetic Memory Devices and Methods of Forming the Same - Provided are a magnetic memory device and a method of forming the same. The method may include forming a pinning pattern on a substrate; forming a first interlayer insulating layer that exposes the pinning pattern on the substrate; forming a pinned layer, a tunneling barrier layer and a second magnetic conductive layer on the pinning pattern; and forming a pinned pattern, a tunnel barrier pattern and a second magnetic conductive pattern by performing a patterning process on the pinned layer, the tunnel barrier layer and the second magnetic conductive layer. | 09-22-2011 |
20110244599 | PROCESS INTEGRATION OF A SINGLE CHIP THREE AXIS MAGNETIC FIELD SENSOR - A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane. | 10-06-2011 |
20110256642 | MANUFACTURING METHOD OF MAGNETO-RESISTANCE EFFECT ELEMENT - The present invention provides a manufacturing method of a magneto-resistance effect element, in which the step coverage of a formed film can be enlarged and also the film can be deposited in a low temperature range. In an embodiment of the present invention, an insulating protective layer is formed on a multilayered structure by a plasma CVD apparatus in which a plasma source and a film deposition chamber are separated from each other by a partition wall plate. According to the present method, it is possible to deposit the protective layer without inviting the degradation of a magnetic characteristic and also to perform low temperature film deposition even at a temperature lower than 150° C. Hence, it is possible to deposit the protective layer while leaving resist and also to reduce the number of steps in the manufacturing of the magneto-resistance effect element having a multilayered structure. | 10-20-2011 |
20110256643 | METHOD FOR DETACHING LAYERS WITH LOW MAGNETIC PERMEABILITY - A method for detaching a first material layer from a second material layer includes following steps: forming a high-magnetic-permeability material layer on a first material layer comprised of low-magnetic-permeability material; removing a portion of the high-magnetic-permeability material layer to expose a portion of the first material layer; epitaxially growing a second material layer comprised of low-magnetic-permeability material on the exposed portion of the first material layer and the high-magnetic-permeability material layer; cooling the first and second material layers; heating the high-magnetic-permeability material layer, thus detaching the first material layer from the second material layer. | 10-20-2011 |
20110269250 | GROWTH METHOD OF FE3N MATERIAL - A kind of growth method of Fe | 11-03-2011 |
20110269251 | Spin Transfer Torque Memory Device Having Common Source Line and Method for Manufacturing the Same - A spin transfer torque memory device and a method for manufacturing the same. The spin transfer torque memory device comprises a MRAM cell using a MTJ and a vertical transistor. A common source line is formed in the bottom of the vertical transistor, thereby obtaining the high-integrated and simplified memory device. | 11-03-2011 |
20110275163 | Zr-SUBSTITUTED BaTiO3 FILMS - The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition (ALD), to form a zirconium substituted layer of barium titanium oxide (BaTiO | 11-10-2011 |
20110281375 | MAGNETIC MICROELECTRONIC DEVICE ATTACHMENT - The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic devices of the microelectronic packages may have magnetic attachment structures comprising a magnetic material formed on an attachment structure. The microelectronic device may be aligned on a substrate with a magnetic field and then held in place therewith while being attached to the substrate. The microelectronic device may also be aligned with an alignment plate which magnetically aligns and holds the component in place while being packaged. | 11-17-2011 |
20110318848 | FERROMAGNETIC PREFERRED GRAIN GROWTH PROMOTION SEED LAYER FOR AMORPHOUS OR MICROCRYSTALLINE MgO TUNNEL BARRIER - MgO-based magnetic tunnel junction (MTJ) device includes in essence a ferromagnetic reference layer, a MgO tunnel barrier and a ferromagnetic free layer. The microstructure of MgO tunnel barrier, which is prepared by the metallic Mg deposition followed by the oxidation process or reactive sputtering, is amorphous or microcrystalline with poor (001) out-of-plane texture. In the present invention at least only the ferromagnetic reference layer or both of the ferromagnetic reference and free layer is proposed to be bi-layer structure having a crystalline preferred grain growth promotion (PGGP) seed layer adjacent to the tunnel barrier. This crystalline PGGP seed layer induces the crystallization and the preferred grain growth of the MgO tunnel barrier upon post-deposition annealing. | 12-29-2011 |
20120003757 | HIGH CAPACITY LOW COST MULTI-STATE MAGNETIC MEMORY - A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states. | 01-05-2012 |
20120009689 | Method of Forming a MEMS Power Inductor - A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace. | 01-12-2012 |
20120015452 | Information storage devices using magnetic domain wall movement and methods of manufacturing the same - In an information storage device, a writing magnetic layer is formed on a substrate and has a magnetic domain wall. A connecting magnetic layer is formed on the writing magnetic layer, and an information storing magnetic layer is formed on an upper portion of side surfaces of the connecting magnetic layer. A reader reads information stored in the information storing magnetic layer. | 01-19-2012 |
20120021535 | MAGNETIC STACK WITH OXIDE TO REDUCE SWITCHING CURRENT - A magnetic stack having a ferromagnetic free layer, a metal oxide layer that is antiferromagnetic at a first temperature and non-magnetic at a second temperature higher than the first temperature, a ferromagnetic pinned reference layer, and a non-magnetic spacer layer between the free layer and the reference layer. During a writing process, the metal oxide layer is non-magnetic. For magnetic memory cells, such as magnetic tunnel junction cells, the metal oxide layer provides reduced switching currents. | 01-26-2012 |
20120028373 | Bi-layer hard mask for the patterning and etching of nanometer size MRAM devices - A composite hard mask is disclosed that prevents build up of metal etch residue in a MRAM device during etch processes that define an MTJ shape. As a result, MTJ shape integrity is substantially improved. The hard mask has a lower non-magnetic spacer, a middle conductive layer, and an upper sacrificial dielectric layer. The non-magnetic spacer serves as an etch stop during a pattern transfer with fluorocarbon plasma through the conductive layer. A photoresist pattern is transferred through the dielectric layer with a first fluorocarbon etch. Then the photoresist is removed and a second fluorocarbon etch transfers the pattern through the conductive layer. The dielectric layer protects the top surface of the conductive layer during the second fluorocarbon etch and during a substantial portion of a third RIE step with a gas comprised of C, H, and O that transfers the pattern through the underlying MTJ layers. | 02-02-2012 |
20120028374 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A ferroelectric capacitor provided with a ferroelectric film ( | 02-02-2012 |
20120034712 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a semiconductor device including a ferroelectric capacitor formed over a semiconductor substrate, wherein the ferroelectric capacitor including a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film, and the upper electrode including a first conductive film formed of a first conductive noble metal oxide, and a second conductive film formed of a metal nitride compound formed on the first conductive film. | 02-09-2012 |
20120058574 | MRAM with storage layer and super-paramagnetic sensing layer - An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external field, and in which magnetization is roughly proportional to an external field until reaching a saturation value. In one embodiment, a separate storage layer is formed above, below, or adjacent to the MTJ and has uniaxial anisotropy with a magnetization direction along its easy axis which parallels the first axis. In a second embodiment, the storage layer is formed on a non-magnetic conducting spacer layer within the MTJ and is patterned simultaneously with the MTJ. The SP free layer may be multiple layers or laminated layers of CoFeB. The storage layer may have a SyAP configuration and a laminated structure. | 03-08-2012 |
20120058575 | Low switching current dual spin filter (DSF) element for STT-RAM and a method for making the same - A dual spin filter that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R in STT-RAM devices is disclosed. The bottom spin valve has a MgO tunnel barrier layer formed with a natural oxidation process to achieve low RA, a CoFe/Ru/CoFeB—CoFe pinned layer, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel (NCC) layer to minimize Jc | 03-08-2012 |
20120064640 | Spin transfer MRAM device with novel magnetic synthetic free layer - A method of forming a CPP MTJ MRAM element that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes a tunneling barrier layer of MgO and a non-magnetic CPP layer of Cu or Cr and utilizes a novel synthetic free layer having three ferromagnetic layers mutually exchange coupled in pairwise configurations. The free layer comprises an inner ferromagnetic and two outer ferromagnetic layers, with the inner layer being ferromagnetically exchange coupled to one outer layer and anti-ferromagnetically exchange coupled to the other outer layer. The ferromagnetic coupling is very strong across an ultra-thin layer of Ta, Hf or Zr of thickness preferably less than 0.4 nm. | 03-15-2012 |
20120077287 | DRAWN DUMMY FeCAP, VIA AND METAL STRUCTURES - A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components. | 03-29-2012 |
20120077288 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film | 03-29-2012 |
20120094398 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - In a semiconductor device manufacturing method, an amorphous or microcrystalline metal oxide film is formed over a first metal film which is preferentially oriented along a predetermined crystal plane. After that, a ferroelectric film is formed by a MOCVD method. When the ferroelectric film is formed, the metal oxide film formed over the first metal film is reduced to a second metal film and the ferroelectric film is formed over the second metal film. When the ferroelectric film is formed, the amorphous or microcrystalline metal oxide film is apt to be reduced uniformly. As a result, the second metal film the orientation of which is good is obtained and the ferroelectric film the orientation of which is good is formed over the second metal film. After the ferroelectric film is formed, an upper electrode is formed over the ferroelectric film. | 04-19-2012 |
20120107962 | METHOD OF FABRICATING EPITAXIAL SEMICONDUCTOR DEVICES - A method of fabricating epitaxial semiconductor devices includes: (a) forming an etch limiting film that includes a sacrificial layer on an epitaxial substrate; (b) growing epitaxially layers of a semiconductor structure on the sacrificial layer; (c) forming on the semiconductor structure a layer of a device substrate that can be magnetized, and a patterned passage unit that extends from the device substrate to a depth as deep as the sacrificial layer such that a plurality of semiconductor units are defined in the semiconductor structure and the device substrate; and (d) separating the semiconductor units from the epitaxial substrate by etching laterally the sacrificial layer through the patterned passage unit while a magnetic attraction force is applied to the device substrate. | 05-03-2012 |
20120107963 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor device which is characterized as follows. The semiconductor device includes: an interlayer insulating film formed above a semiconductor substrate and provided with a hole above an impurity diffusion region; a conductive plug formed in the hole and electrically connected to the impurity diffusion region; a conductive oxygen barrier film formed on the conductive plug and the interlayer insulating film around the conductive plug; a conductive anti-diffusion film formed on the conductive oxygen barrier film; and a capacitor that has a lower electrode which is formed on the conductive anti-diffusion film and which exposes platinum or palladium on the upper surface, a capacitor dielectric film made of a ferroelectric material, and an upper electrode. The conductive anti-diffusion film is made of a non-oxide conductive material for preventing the diffusion of the constituent element of the capacitor dielectric film. | 05-03-2012 |
20120107964 | LOW-COST NON-VOLATILE FLASH-RAM MEMORY - A method of flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs. | 05-03-2012 |
20120107965 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an insulating film provided over a semiconductor substrate, a conductive plug buried in the insulating film, an underlying conductive film which is provided on the conductive plug and on the insulating film and which has a flat upper surface, and a ferroelectric capacitor provided on the underlying conductive film. At least in a region on the conductive plug, the concentration of nitrogen in the underlying conductive film gradually decreases from the upper surface to the inside. | 05-03-2012 |
20120107966 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material on a free layer of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of the capping material to form a layer of oxidized material. | 05-03-2012 |
20120115250 | CONCAVE-CONVEX PATTERN FORMING METHOD AND MAGNETIC TUNNEL JUNCTION ELEMENT FORMING METHOD - A method of forming a concave-convex pattern according to an embodiment includes: forming a guide pattern on a base material, the guide pattern having a convex portion; forming a formative layer on the guide pattern, the formative layer including a stacked structure formed by stacking a first layer and a second layer, the first layer including at least one element selected from a first metal element and a metalloid element, the second layer including a second metal element different from the first metal element; selectively leaving the formative layer only at side faces of the convex portions by performing etching on the formative layer; removing the guide pattern; and forming the concave-convex pattern in the base material by performing etching on the base material, with the remaining formative layer being used as a mask. | 05-10-2012 |
20120115251 | PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE - Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer. | 05-10-2012 |
20120115252 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device, including a silicon substrate, a first insulating film formed on the silicon substrate, a first conductive plug formed in an inside of a first contact hole of the first insulating film, an underlying conductive film having a flat surface formed on the first conductive plug and in the circumference thereof, a crystalline conductive film formed on the underlying conductive film, and a capacitor in which a lower electrode, a dielectric film made of a ferroelectric material, and an upper electrode are laminated in this order on the crystalline conductive film. | 05-10-2012 |
20120115253 | Semiconductor apparatus - A method for manufacturing a semiconductor apparatus includes forming a semiconductor device on a principal surface of a substrate, in which the semiconductor device includes an interconnect layer, forming a buffer film which covers the semiconductor device and prevents diffusion of a magnetic material, and forming a magnetic shielding film which covers the buffer film and includes the magnetic material. | 05-10-2012 |
20120122246 | METHOD FOR MANUFACTURING MAGNETIC MEMORY CHIP DEVICE - A method for manufacturing a magnetic memory chip device comprises the steps of: writing information in each of a plurality of magnetic memory chips formed on a silicon wafer; adhering a high magnetic permeability plate on a back face of the silicon wafer after writing information, the high magnetic permeability plate having a higher magnetic permeability than silicon and having a thickness of 50 um or more; dicing the silicon wafer into respective magnetic memory chips after adhering the high magnetic permeability plate. | 05-17-2012 |
20120122247 | ELECTRONIC DEVICE INCLUDING A MAGNETO-RESISTIVE MEMORY DEVICE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE - A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer. | 05-17-2012 |
20120135543 | Method For Forming Magnetic Tunnel Junction Structure And Method For Forming Magnetic Random Access Memory Using The Same - A method of fabricating a magnetic tunnel junction structure includes forming a magnetic tunnel junction layer on a substrate. A mask pattern is formed on a region of the second magnetic layer. A magnetic tunnel junction layer pattern and a sidewall dielectric layer pattern on at least one sidewall of the magnetic tunnel junction layer pattern are formed by performing at least one etch process and at least one oxidation process multiple times. The at least one etch process may include a first etch process to etch a portion of the magnetic tunnel junction layer using an inert gas and the mask pattern to form a first etch product. The at least one oxidation process may include a first oxidation process to oxidize the first etch product attached on an etched side of the magnetic tunnel junction layer. | 05-31-2012 |
20120135544 | Method of Fabricating Semiconductor Device and Apparatus for Fabricating the Same - Provided is a method of fabricating a semiconductor device. The method of fabricating a semiconductor device includes forming a plurality of magnetic memory patterns spaced apart from each other on a substrate, with each of the magnetic memory patterns including a free pattern, a tunnel barrier pattern, and a reference pattern which are stacked on the substrate, performing a magnetic thermal treatment process on the magnetic memory patterns, and forming a passivation layer on the magnetic memory patterns. The magnetic thermal treatment process and the forming of the passivation layer are simultaneously performed in one reactor. | 05-31-2012 |
20120156806 | MAGNETIC RANDOM ACCESS MEMORY INTEGRATION HAVING IMPROVED SCALING - A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F | 06-21-2012 |
20120164757 | Method for Junction Isolation to Reduce Junction Damage for a TMR Sensor - The present invention provides a method for manufacturing a TMR sensor that reduces damage to a sensor stack during intermediate stages of the manufacturing process. In an embodiment of the invention, after formation of a sensor stack, a protective layer is deposited on the sensor stack that provides protection from materials that may be used in subsequent steps of the manufacturing process. The protective layer is subsequently converted to an insulating layer and the thickness of the insulating layer is extended to an appropriate thickness. In converting the protective layer to an insulating layer, the sensor stack is not directly exposed to materials that may damage it. For example, in an embodiment of the invention, Mg is used as the protective layer that is subsequently converted to MgO with the introduction of oxygen. Although direct contact of oxygen with the sensor stack may cause damage to the sensor stack, direct contact is avoided by the present invention. Subsequently, the thickness of the insulating layer, in this example can be extended to an appropriate thickness without exposing the sensor stack to damage causing oxygen and inter-diffusion. | 06-28-2012 |
20120171783 | FERROELECTRIC MEMORY AND MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF FERROELECTRIC CAPACITOR - Provided is a ferroelectric memory including a silicon substrate, a transistor formed on the silicon substrate, and a ferroelectric capacitor formed above the transistor. The ferroelectric capacitor includes a lower electrode, a ferroelectric film formed on the lower electrode, an upper electrode formed on the ferroelectric film, and a metal film formed on the upper electrode. | 07-05-2012 |
20120171784 | MAGNETRON-SPUTTERING FILM-FORMING APPARATUS AND MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE - A magnetron-sputtering film-forming apparatus includes: a vacuum film-forming chamber ( | 07-05-2012 |
20120171785 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE - There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode. | 07-05-2012 |
20120184053 | METHOD OF MANUFACTURING A MAGNETIC READ SENSOR HAVING A LOW RESISTANCE CAP STRUCTURE - A method for manufacturing a magnetic sensor that decreases area resistance and decreases MR ratio of the sensor by eliminating any oxide formation in the capping layer of the sensor. The method includes forming a sensor stack having a multi-layer capping structure formed there-over. The multi-layer capping structure can include first, second, third and fourth layers. The second layer is constructed of a material that is not easily oxidized and which is different from the first layer. The sensor can be formed using a mask that includes a carbon hard mask. After the sensor stack has been formed by ion milling, the hard mask can be removed by reactive ion etching. Then, a cleaning process is performed to remove the second, third and fourth layers of the capping layer structure using an end point detection method such as secondary ion mass spectrometry to detect the presence of the second layer. | 07-19-2012 |
20120220056 | MECHANICAL COUPLING IN A MULTI-CHIP MODULE USING MAGNETIC COMPONENTS - A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features mate with each other. In particular, a positive feature may mate with a given pair of negative features, which includes negative features on each of the substrates. Furthermore, at least one of the negative features in the given pair may include a hard magnetic material, and the positive feature and the other negative feature in the given pair may include a soft magnetic material that provide a flux-return path to the hard magnetic material. In this way, the hard magnetic material may facilitate the remateable mechanical coupling of the substrates. | 08-30-2012 |
20120220057 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Ferroelectric capacitors ( | 08-30-2012 |
20120225498 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a manufacturing method of semiconductor device includes forming plural elements on a substrate, forming a silicon compound film so as to bury between a plurality of elements, and modifying the silicon compound film to a silicon dioxide film by radiating microwaves. | 09-06-2012 |
20120225499 | Method for Use in Making Electronic Devices Having Thin-Film Magnetic Components - Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness. | 09-06-2012 |
20120225500 | TRANSPARENT NONVOLATILE MEMORY THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided are a transparent nonvolatile memory thin film transistor (TFT) and a method of manufacturing the same. The memory TFT includes source and drain electrodes disposed on a transparent substrate. A transparent semiconductor thin layer is disposed on the source and drain electrodes and the transparent substrate interposed between the source and drain electrodes. An organic ferroelectric thin layer is disposed on the transparent semiconductor thin layer. A gate electrode is disposed on the organic ferroelectric thin layer in alignment with the transparent semiconductor thin layer. Thus, the transparent nonvolatile memory TFT employs the organic ferroelectric thin layer, the oxide semiconductor thin layer, and auxiliary insulating layers disposed above and below the organic ferroelectric thin layer, thereby enabling low-cost manufacture of a transparent nonvolatile memory device capable of a low-temperature process. | 09-06-2012 |
20120231553 | SUBSTRATE PROCESSING APPARATUS AND FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE - A substrate processing apparatus includes a processing vessel evacuated by an evacuation system and including therein a stage for holding thereon a substrate to be processed, the processing vessel defining therein a processing space, a processing gas supply path that introduces an etching gas into the processing vessel, a plasma source that forms plasma in the processing space, and a high-frequency source connected to the stage. The processing vessel includes therein a shielding plate dividing the processing space into a first processing space part including a surface of the substrate to be processed and a second processing space part corresponding to a remaining part of the processing space, wherein the shielding plate is formed with an opening having a size larger than a size of the substrate to be processed. | 09-13-2012 |
20120244639 | METHOD OF MANUFACTURING MAGNETIC MEMORY - According to one embodiment, a method of manufacturing a magnetic memory, the method includes forming a first magnetic layer having a variable magnetization, forming a tunnel barrier layer on the first magnetic layer, forming a second magnetic layer on the tunnel barrier layer, the second magnetic layer having an invariable magnetization, forming a hard mask layer as a mask on the second magnetic layer, patterning the second magnetic layer by using the mask of the hard mask layer, and executing a GCIB-irradiation by using the mask of the hard mask layer, after the patterning. | 09-27-2012 |
20120244640 | METHOD OF MANUFACTURING MULTILAYER FILM - According to one embodiment, a method of manufacturing a multilayer film, the method includes forming a first layer, forming a second layer on the first layer, and transcribing a crystal information of one of the first and second layers to the other one of the first and second layers by executing a GCIB-irradiation to the second layer. | 09-27-2012 |
20120244641 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The device includes a magnetoresistance effect element using magnetic material containing at least one of cobalt, iron, and nickel. Forming the element includes forming a stacked body above a semiconductor substrate. The stacked body includes layers. The layers includes the magnetic material. Forming the element further includes processing the stacked body in a vacuum atmosphere by plasma etching using a first gas containing chlorine. Forming the element further includes subjecting the stacked body to a gas treatment using a second gas containing an amino group while holding the stacked body in the vacuum atmosphere. | 09-27-2012 |
20120244642 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring. | 09-27-2012 |
20120264234 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B). Annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer. Cooling down of the STTMRAM element to a second temperature that is lower than the first temperature is performed and a third free sub-layer is directly deposited on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer. | 10-18-2012 |
20120276657 | METHOD OF PATTERNING OF MAGNETIC TUNNEL JUNCTIONS - Embodiments of the invention generally relate to methods for fabricating devices on semiconductor substrates. More specifically, embodiments of the invention relate to methods of patterning magnetic materials. Certain embodiments described herein use a reducing chemistry containing a hydrogen gas or hydrogen containing gas with an optional dilution gas at temperatures ranging from 20 to 300 degrees Celsius at a substrate bias less than 1,000 DC voltage to reduce the amount of sputtering and redeposition. Exemplary hydrogen containing gases which may be used with the embodiments described herein include NH | 11-01-2012 |
20120276658 | METHOD OF ETCHING A WORKPIECE - A workpiece is implanted to a first depth to form a first amorphized region. This amorphized region is then etched to the first depth. After etching, the workpiece is implanted to a second depth to form a second amorphized region below a location of the first amorphized region. The second amorphized region is then etched to the second depth. The implant and etch steps may be repeated until structure is formed to the desired depth. The workpiece may be, for example, a compound semiconductor, such as GaN, a magnetic material, silicon, or other materials. | 11-01-2012 |
20120276659 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An impurity-doped PZT film in an amorphous state doped with La, Ca, Sr, Si, Nb and/or the like is formed on a Pt film composing a bottom electrode film. Next, crystallization annealing for the impurity-doped PZT film is performed. Next, a PZT film is formed on the impurity-doped PZT film by an MOCVD method. Thereafter, an IrO | 11-01-2012 |
20120282711 | MAGNETIC TUNNEL JUNCTION (MTJ) FORMATION USING MULTIPLE ETCHING PROCESSES - A method of manufacturing a magnetic memory element includes the steps of forming a permanent magnetic layer on top a bottom electrode, forming a pinning layer on top the permanent magnetic layer, forming a magnetic tunnel junction (MTJ) including a barrier layer on top of the pinning layer, forming a top electrode on top of the MTJ, forming a hard mask on top of the top electrode, and using the hard mask to perform a series of etching processes to reduce the width of the MTJ and the top electrode to substantially a desired width, where one of these etching processes is stopped when a predetermined material in the pinning layer is detected thereby avoiding deposition of metal onto the barrier layer of the etching process thereby preventing shorting. | 11-08-2012 |
20120288963 | MANUFACTURING METHOD OF MAGNETO-RESISTIVE ELEMENT - The present invention provides a manufacturing method of a magneto-resistive element capable of obtaining a higher MR ratio, in a method of forming a metal oxide layer (e.g., MgO layer) by oxidation treatment of a metal layer (e.g., Mg layer). An embodiment of the present invention includes the steps of; providing a substrate having a first ferromagnetic layer; fabricating a tunnel barrier layer on the first ferromagnetic layer; and forming a second ferromagnetic layer on the tunnel barrier layer. The step of fabricating the tunnel barrier layer includes; the steps of; depositing a first metal layer on the first ferromagnetic layer; | 11-15-2012 |
20120288964 | SPIN-TORQUE BASED MEMORY DEVICE WITH READ AND WRITE CURRENT PATHS MODULATED WITH A NON-LINEAR SHUNT RESISTOR - A fabrication method includes forming a spin-polarizing layer, a spin transport layer on the spin polarizing layer on a substrate, a free layer magnet on the spin transport layer, a non-magnetic layer on the spin polarizing layer, a reference layer on the non-magnetic layer, and a hard mask layer on the reference layer, etching the hard mask layer and forming a read portion including the reference layer, the nonmagnetic layer and the free layer magnet, forming a nonlinear resistor layer on surfaces of the spin transport layer, the spacers, and the hard mask layer, etching the nonlinear resistor layer, the spin transport layer, and the spin polarizing layer and forming a write portion including the spin transport layer and the spin polarizing layer, forming an interlevel dielectric layer, forming a trench, exposing an upper surface of the reference layer of the read and write portions. | 11-15-2012 |
20120288965 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Stable contact hole forming is attained even when an aluminum oxide film is present between layers provided with contact holes. The process comprises the steps of forming a first element layer on a semiconductor substrate; forming a first interlayer insulating film on the first element layer; forming a second element layer on the first interlayer insulating film; forming a second interlayer insulating film on the second element layer; forming a hole resist pattern on the second interlayer insulating film; conducting a first etching for forming of holes by etching the second interlayer insulating film; and conducting a second etching for extending of holes to the first element layer by etching the first interlayer insulating film. | 11-15-2012 |
20120295370 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A STTMRAM element has a free sub-layer with enhanced internal stiffness. A first free sub-layer is made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, with an amount greater than the amount of B in the first free sub-layer. The STTMRAM element is cooled to a second temperature that is lower than the first temperature and a third free sub-layer is deposited directly on top of the second free layer, with the third free sub-layer being made partially of boron B. The amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer. | 11-22-2012 |
20120301975 | SEMICONDUCTOR DEVICE INCLUDING A MAGNETIC TUNNEL JUNCTION DEVICE INCLUDING A LAMINATED STRUCTURE AND MANUFACTURING METHOD THEREFOR - A semiconductor device having a MTJ device excellent in operating characteristics and a manufacturing method therefor are provided. The MTJ device is formed of a laminated structure which is obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower and upper magnetic films contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlO | 11-29-2012 |
20120309112 | FERROELECTRIC MEMORY DEVICE AND FABRICATION PROCESS THEREOF, FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE - A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode. | 12-06-2012 |
20120309113 | Quantum Tunneling Devices and Circuits with Lattice-Mismatched Semiconductor Structures - Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials. | 12-06-2012 |
20120315707 | MAGNETIC PATTERNS AND METHODS OF FORMING MAGNETIC PATTERNS - In a method of forming a magnetic pattern, a lower electrode layer is formed on a substrate. An insulating interlayer is formed on the lower electrode layer. The insulating interlayer is partially removed to form an opening. A first pinned layer pattern filling the opening is formed. A second pinned layer, a tunnel barrier layer, a free layer and an upper electrode layer are formed on the insulating interlayer and the first pinned layer pattern. The upper electrode layer, the free layer, the tunnel barrier layer and the second pinned layer are patterned to form a second pinned layer pattern, a tunnel barrier pattern, a free layer pattern and an upper electrode. The second pinned layer pattern covers an upper surface of the first pinned layer pattern. | 12-13-2012 |
20120329177 | SPIN-TORQUE MAGNETORESISTIVE STRUCTURES WITH BILAYER FREE LAYER - Magnetoresistive structures, devices, memories, and methods for forming the same are presented. For example, a magnetoresistive structure includes a ferromagnetic layer, a ferrimagnetic layer coupled to the ferromagnetic layer, a pinned layer and a nonmagnetic spacer layer. A free side of the magnetoresistive structure comprises the ferromagnetic layer and the ferrimagnetic layer. The nonmagnetic spacer layer is at least partly between the free side and the pinned layer. A saturation magnetization of the ferromagnetic layer opposes a saturation magnetization of the ferrimagnetic layer. The nonmagnetic spacer layer may include a tunnel barrier layer, such as one composed of magnesium oxide (MgO), or a nonmagnetic metal layer. | 12-27-2012 |
20130005051 | MAGNETIC STACKS WITH PERPENDICULAR MAGNETIC ANISOTROPY FOR SPIN MOMENTUM TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY - A magnetic tunnel junction (MTJ) includes a magnetic free layer, having a variable magnetization direction; an insulating tunnel barrier located adjacent to the free layer; a magnetic fixed layer having an invariable magnetization direction, the fixed layer disposed adjacent the tunnel barrier such that the tunnel barrier is located between the free layer and the fixed layer, wherein the free layer and the fixed layer have perpendicular magnetic anisotropy; and one or more of: a composite fixed layer, the composite fixed layer comprising a dusting layer, a spacer layer, and a reference layer; a synthetic antiferromagnetic (SAF) fixed layer structure, the SAF fixed layer structure comprising a SAF spacer located between the fixed layer and a second fixed magnetic layer; and a dipole layer, wherein the free layer is located between the dipole layer and the tunnel barrier. | 01-03-2013 |
20130005052 | MAGNETIC TUNNEL JUNCTION WITH IRON DUSTING LAYER BETWEEN FREE LAYER AND TUNNEL BARRIER - A magnetic tunnel junction (MTJ) for a magnetic random access memory (MRAM) includes a magnetic free layer having a variable magnetization direction; an iron (Fe) dusting layer formed on the free layer; an insulating tunnel barrier formed on the dusting layer; and a magnetic fixed layer having an invariable magnetization direction, disposed adjacent the tunnel barrier such that the tunnel barrier is located between the free layer and the fixed layer; wherein the free layer and the fixed layer have perpendicular magnetic anisotropy and are magnetically coupled through the tunnel barrier. | 01-03-2013 |
20130005053 | Magnetic Spin Shift Register Memory - A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material. | 01-03-2013 |
20130017625 | SEMICONDUCTOR FABRICATING DEVICE AND METHOD FOR DRIVING THE SAME, AND METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION USING THE SAMEAANM CHOI; Won JoonAACI SeoulAACO KRAAGP CHOI; Won Joon Seoul KR - In a method for fabricating a magnetic tunnel junction, a first magnetic layer is formed on a substrate, and a tunnel insulating layer is formed on the first magnetic layer. Subsequently, a second magnetic layer is formed on the tunnel insulating layer. In the method, the first magnetic layer is formed by periodically sputtering a magnetic target while a metal target is continuously sputtered. | 01-17-2013 |
20130017626 | ETCHING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEAANM TOMIOKA; KazuhiroAACI Yokohama-shiAACO JPAAGP TOMIOKA; Kazuhiro Yokohama-shi JP - According to one embodiment, an etching apparatus includes a stage having an upper surface and a lower surface, and being capable of mounting a substrate on the upper surface, a chamber covering above the upper surface, a lower electrode having an opening portion, and provided under the lower surface, a gas supplying portion supplying an etching gas in the chamber, a high-frequency power source portion executing a plasma gasification of the etching gas by applying a high-frequency to the lower electrode, a micro wave generating portion setting a temperature of the substrate within an optimum range by applying a micro wave to the substrate through the opening portion, and a control portion controlling the gas supplying portion, the high-frequency power source portion and the micro wave generating portion. | 01-17-2013 |
20130017627 | Embedded Magnetic Random Access Memory (MRAM) - A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed therethrough and are formed on top of the access transistor. An magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ. | 01-17-2013 |
20130023062 | THIN FILM MANUFACTURING APPARATUS, THIN FILM MANUFACTURING METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In an apparatus for manufacturing a ceramic thin film by employing a thermal CVD method, an internal jig, which is provided with a heat radiation material film on the surface, is provided at a position that faces a substrate (S) on which the film is to be formed. The thin film and a semiconductor device are manufactured using such apparatus. | 01-24-2013 |
20130023063 | METHOD FOR MANUFACTURING FERROELECTRIC DEVICE - A seed layer having a predetermined pattern is formed on a side of one surface of a second substrate, and a ferroelectric layer is formed on the side of the one surface of the second substrate. A lower electrode is formed on the ferroelectric layer, and the lower electrode and a first substrate are bonded via a bonding layer. A laser beam with a predetermined wavelength is irradiated from a side of other surface of the second substrate to transfer a ferroelectric film, which overlaps with the seed layer, of the ferroelectric layer and the seed layer onto the side of said one surface of the first substrate. The laser beam passes through the second substrate, is reflected by the seed layer, and is absorbed by a second portion of the ferroelectric layer. The second portion does not overlap with the seed layer. | 01-24-2013 |
20130029431 | METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE - According to one embodiment, a method for manufacturing a nonvolatile memory device including a plurality of memory cells is disclosed. Each of the plurality of memory cells includes a base layer including a first electrode, a magnetic tunnel junction device provided on the base layer, and a second electrode provided on the magnetic tunnel junction device. The magnetic tunnel junction device includes a first magnetic layer, a tunneling barrier layer provided on the first magnetic layer, and a second magnetic layer provided on the tunneling barrier layer. The method can include etching a portion of the second magnetic layer and a portion of the first magnetic layer by irradiating gas clusters onto a portion of a surface of the second magnetic layer or a portion of a surface of the first magnetic layer. | 01-31-2013 |
20130029432 | THIN-WAFER CURRENT SENSORS - Embodiments relate to IC current sensors fabricated using thin-wafer manufacturing technologies. Such technologies can include processing in which dicing before grinding (DBG) is utilized, which can improve reliability and minimize stress effects. While embodiments utilize face-up mounting, face-down mounting is made possible in other embodiments by via through-contacts. IC current sensor embodiments can present many advantages while minimizing drawbacks often associated with conventional IC current sensors. | 01-31-2013 |
20130034917 | METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION DEVICE - A method for fabricating a semiconductor device includes forming a plurality of layers which are stacked as a bottom layer, an MTJ layer, and a top layer, patterning the top layer and the MTJ layer using an etch mask pattern to form a top layer pattern and an MTJ pattern, forming a carbon spacer on the sidewalls of the MTJ pattern and the top layer pattern to protect the MTJ pattern and the top layer pattern, and patterning the bottom layer using the carbon spacer and the etch mask pattern as an etch mask to form a bottom layer pattern. | 02-07-2013 |
20130040408 | METHOD OF FABRICATING RESISTANCE VARIABLE MEMORY DEVICE AND DEVICES AND SYSTEMS FORMED THEREBY - An exemplary method of forming a variable resistance memory may include forming first source/drain regions in a substrate, forming gate line structures and conductive isolation patterns buried in the substrate with the first source/drain regions interposed therebetween, and forming lower contact plugs on the first source/drain regions. The forming of lower contact plugs may include forming a first interlayer insulating layer, including a first recess region exposing the first source/drain regions adjacent to each other in a first direction, forming a conductive layer in the first recess region, patterning the conductive layer to form preliminary conductive patterns spaced apart from each other in the first direction, and patterning the preliminary conductive patterns to form conductive patterns spaced apart from each other in a second direction substantially orthogonal to the first direction. | 02-14-2013 |
20130059401 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a depression in an upper portion of a semiconductor substrate, placing a sacrificial material in the depression, forming a plurality of fins extending in one direction and arranged periodically by selectively removing the semiconductor substrate and the sacrificial material, forming a device isolation insulating film in a lower portion of space between the fins, removing the sacrificial material, forming a gate insulating film on an exposed surface of the fin, and forming a gate electrode. The gate electrode extends in a direction crossing the one direction so as to straddle the fin on the device isolation insulating film. | 03-07-2013 |
20130065326 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a mask film on a partial region of a semiconductor substrate; forming a mask member above the semiconductor substrate in both the region where the mask film is formed and a region where the mask film is not formed; patterning the mask film and an upper portion of the semiconductor substrate by performing etching using the mask member as a mask. The method further includes removing part of the patterned upper portion of the semiconductor substrate by performing etching using the patterned mask film as a mask. | 03-14-2013 |
20130071954 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B). Annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer. Cooling down of the STTMRAM element to a second temperature that is lower than the first temperature is performed and a third free sub-layer is directly deposited on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer. | 03-21-2013 |
20130078742 | ENHANCEMENT OF PROPERTIES OF THIN FILM FERROELECTRIC MATERIALS - Methods are provided for enhancing properties, including polarization, of thin-film ferroelectric materials in electronic devices. According to one embodiment, a process for enhancing properties of ferroelectric material in a device having completed wafer processing includes applying mechanical stress to the device, independently controlling the temperature of the device to cycle the temperature from room temperature to at or near the Curie temperature of the ferroelectric material and back to room temperature while the device is applied with the mechanical stress, and then removing the mechanical stress. Certain of the subject methods can be performed as part of a back end of line (BEOL) process, and may be performed during the testing phase at wafer or die level. | 03-28-2013 |
20130084653 | MEDIUM PATTERNING METHOD AND ASSOCIATED APPARATUS - According to one embodiment, a method for patterning a medium having a patterned hard mask applied thereon is disclosed herein. The patterned hard mark includes a plurality of apertures exposing portions of the medium. The method includes directing ions toward the medium, implanting a portion of the ions into the exposed portions of the medium, removing a layer of the patterned hard mask with another portion of the ions, and depositing hard mask material onto the patterned hard mask. Depositing hard mask material onto the exposed portions of the medium may follow implantation of the portion of the ions into the exposed portions of the medium. | 04-04-2013 |
20130095576 | TRANSFORMER SIGNAL COUPLING FOR FLIP-CHIP INTEGRATION - Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor. | 04-18-2013 |
20130115719 | METHOD FOR MANUFACTURING INTEGRATED CIRCUIT STRUCTURE WITH MAGNETORESISTANCE COMPONENT - A method or manufacturing an integrated circuit structure with a magnetoresistance component is provided. A substrate is provided. A circuit structure layer including a metal pad is formed on the substrate. A dielectric layer is formed on the circuit structure. A metal damascene structure is formed in the dielectric layer. An opening is formed in the dielectric layer so as to form a step-drop. A magnetoresistance material layer is formed on the dielectric layer after forming the metal damascene structure and the opening A photolithography process is applied to pattern the magnetoresistance material layer to form a magnetoresistance component electrically connected to the metal damascene structure. | 05-09-2013 |
20130122609 | Zr-SUBSTITUTED BaTiO3 FILMS - The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition (ALD), to form a zirconium substituted layer of barium titanium oxide, produces a reliable ferroelectric structure for use in a variety of electronic devices such as a dielectric in nonvolatile random access memories (NVRAM), tunable dielectrics for multi layer ceramic capacitors (MLCC), infrared sensors and electro-optic modulators. In various embodiments, structures can be formed by depositing alternating layers of barium titanate and barium zirconate by ALD on a substrate surface using precursor chemicals, and repeating to form a sequentially deposited interleaved structure of desired thickness and composition. The properties of the dielectric may be tuned by adjusting the percentage of zirconium to titanium to optimize properties such as a dielectric constant, Curie point, film polarization, ferroelectric property and a desired relaxor response. | 05-16-2013 |
20130130405 | APPARATUS AND METHODS FOR SILICON OXIDE CVD RESIST PLANARIZATION - Embodiments of the present invention provide methods and apparatus for forming a patterned magnetic layer for use in magnetic media. According to embodiments of the present application, a silicon oxide layer formed by low temperature chemical vapor deposition is used to form a pattern in a hard mask layer, and the patterned hard mask is used to form a patterned magnetic layer by plasma ion implantation. | 05-23-2013 |
20130130406 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer. | 05-23-2013 |
20130130407 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a capacitor, the capacitor includes a lower electrode, which includes platinum, provided above a semiconductor substrate; a first ferroelectric film, which includes lead zirconate titanate added with La, provided on the lower electrode; a second ferroelectric film, which includes lead zirconate titanate added with La, Ca, and Sr, provided directly on the first ferroelectric film, the second ferroelectric film having a thickness smaller than that of the first ferroelectric film and includes amounts of Ca and Sr greater than amounts of Ca and Sr that may be present in the first ferroelectric film; and an upper electrode, which includes a conductive oxide, provided on the second ferroelectric film. | 05-23-2013 |
20130143333 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a substrate and a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode. The upper electrode includes a first layer formed of an oxide whose stoichiometric composition is expressed as AOx | 06-06-2013 |
20130149794 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a conductive film over a semiconductor substrate; forming a first ferroelectric film over the conductive film; forming an amorphous second ferroelectric film over the first ferroelectric film; forming a transition metal oxide material film containing ruthenium over the second ferroelectric film; forming a first conductive metal oxide film over the transition metal oxide material film without exposing the transition metal oxide material film to the air; annealing and crystallizing the second ferroelectric film; and patterning the first conductive metal oxide film, the first ferroelectric film, the second ferroelectric film, and the conductive film to form a ferroelectric capacitor. | 06-13-2013 |
20130149795 | ETCHING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In an etching method of an embodiment, a film to be etched, which includes a first metallic element, is formed on a semiconductor substrate. A carbide layer, which includes a second metallic element, is formed on the film to be etched. The carbide layer is etched. The film to be etched is etched by using the carbide layer as a mask. | 06-13-2013 |
20130149796 | SEMICONDUCTOR DEVICE WITH FERRO-ELECTRIC CAPACITOR - A semiconductor device has a ferro-electric capacitor with small leak current and less process deterioration even upon miniaturization. The semiconductor device includes: a semiconductor element formed in a semiconductor substrate; lamination of an interlayer insulating film and a lower insulating shielding film having a hydrogen/moisture shielding function, the lamination being formed covering the semiconductor element; a conductive adhesion enhancing film formed above the lower insulating shielding film; and a ferro-electric capacitor including a lower electrode formed above the conductive adhesion enhancing film, a ferro-electric film formed on the lower electrode and being disposed within the lower electrode as viewed in plan, and an upper electrode formed on the ferro-electric film and being disposed within the ferro-electric film as viewed in plan, wherein the conductive adhesion enhancing film has a function of improving adhesion of the lower electrode and reducing leak current of the ferro-electric capacitor. | 06-13-2013 |
20130149797 | Magnetic Random Access Memory (MRAM) Manufacturing Process for a Small Magnetic Tunnel Junction (MTJ) Design with a Low Programming Current Requirement - A method of making a magnetic random access memory cell includes forming a magnetic tunnel junction (MTJ) on top of a wafer, depositing oxide on top of the MTJ, depositing a photo-resist layer on top of the oxide layer, forming a trench in the photo-resist layer and oxide layer where the trench has a width that is substantially the same as that of the MTJ. Then, the photo-resist layer is removed and a hard mask layer is deposited on top of the oxide layer in the trench and the wafer is planarized to remove the portion of the hard mask layer that is not in the trench to substantially level the top of oxide layer and the hard layer on the wafer. The remaining oxide layer is etched and the MTJ is etched to remove the portion of the MTJ which is not covered by the hard mask layer. | 06-13-2013 |
20130157382 | PROFILE METHOD IN MAGNETIC WRITE HEAD FABRICATION - A method according to one embodiment includes depositing a dielectric hard mask layer above a polymer mask under-layer; forming a photoresist mask above the hard mask layer; transferring the image of the photoresist mask onto the hard mask layer using reactive ion etching, thereby defining a hard mask; determining that a critical dimension bias of the hard mask is within or outside a specification; and changing a level of an input source power used during a subsequent reactive ion etching step to move the critical dimension bias towards a target critical dimension bias when the critical dimension bias of the hard mask is outside the specification. Additional embodiments are also disclosed. | 06-20-2013 |
20130157383 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask. | 06-20-2013 |
20130157384 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a first insulation layer over a bottom layer, selectively removing a portion the first insulation layer to form a first trench that exposes the bottom layer, forming spacers on inner sidewalls of the first trench; forming a pillar-shaped second insulation layer in the first trench between the spacers, removing the spacers to form a second trench between the pillar-shaped second insulation layer and the first insulation layer, and burying a conductive layer in the second trench. | 06-20-2013 |
20130157385 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a bottom-electrode metal layer over a substrate, planarizing the bottom-electrode metal layer by a first thickness through a chemical mechanical polishing (CMP) process, etching the bottom-electrode metal layer by a second thickness through a wet etching process, forming a plurality of layers of a magnetic tunneling junction (MTJ) element over the bottom-electrode metal layer, forming a top electrode over the plurality of layers, and forming the MTJ element and a bottom electrode by etching the plurality of layers and the bottom-electrode metal layer using the top electrode as an etch mask. | 06-20-2013 |
20130171741 | METHOD FOR FABRICATING VARIABLE RESISTANCE MEMORY DEVICE - A method for fabricating a variable resistance memory device in accordance with an embodiment of the present invention includes: sequentially forming a first conductive layer and a variable resistance layer on a substrate; forming stacked structures in which first conductive lines and variable resistance lines are sequentially stacked by selectively etching the variable resistance layer and the first conductive layer; forming an insulating layer to fill a space between the stacked structures; forming a second conductive layer on the insulating layer and the stacked structures; and forming a second conductive line and a variable resistance pattern by etching the second conductive layer and the variable resistance line using mask patterns in a line type extending in a direction intersecting the stacked structures. | 07-04-2013 |
20130171742 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a miniaturized semiconductor device so as to form MTJ elements therein include the steps of depositing a magnetic tunnel junction (MTJ) precursor layer on a substrate and planarizing the precursor layer; forming a sacrificial and patternable dielectric layer on the MTJ precursor layer; patterning the sacrificial dielectric layer in accordance with predetermined placements and shapes of a to-be-formed hard mask, the patterning forming corresponding openings in the sacrificial dielectric layer; depositing an etch-resistant conductive material such as Cu in the openings for example by way of plating, and selectively removing the sacrificial dielectric layer so as to leave behind the etch-resistant conductive material in the form of a desired hard mask. Using the hard mask to etch and thus pattern the MTJ precursor layer so as to form MTJ elements having desired locations, sizes and shapes. | 07-04-2013 |
20130171743 | MAGNETIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A magnetic device and a method of manufacturing the same. In the method, a lower magnetic layer, an insulation layer, and an upper magnetic layer are sequentially formed on a substrate. An upper magnetic layer pattern is formed by patterning the upper magnetic layer until an upper surface of the insulation layer is exposed. An isolation layer pattern is formed from portions of the insulation layer and the lower magnetic layer by performing an oxidation process on the exposed upper surface of the insulation layer, and an insulation layer pattern and a lower magnetic layer pattern are formed from portions of the insulation layer and the lower magnetic layer, where the isolation layer pattern is not formed. | 07-04-2013 |
20130177997 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - An upper electrode of a ferroelectric capacitor has a first layer formed of a first oxide expressed by a chemical formula AO | 07-11-2013 |
20130189799 | METHOD OF FABRICATING DUAL TRENCH ISOLATED EPITAXIAL DIODE ARRAY - The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory. | 07-25-2013 |
20130196451 | MANUFACTURING METHOD OF MAGNETIC TUNNELING JUNCTION DEVICE - A method of manufacturing a magnetic tunneling junction device, includes: forming a magnetic pinned layer over a substrate; forming an insulating film over the magnetic pinned layer; forming a recess in the insulating film, the recess reaching a bottom of the insulating film; forming a tunneling insulating film over a bottom and side walls of the recess and over the insulating film; forming a magnetic free layer over the tunneling insulating film; forming an upper electrode conductive film on the magnetic free layer; and oxidizing a portion of the magnetic free layer along the side walls of the recess. | 08-01-2013 |
20130203186 | HEAT TREATMENT APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a heat treatment apparatus including a treatment chamber housing a silicon substrate, a heater being provided in the treatment chamber and heating the silicon substrate, and an atmosphere adjustment mechanism reducing a concentration of oxygen contained in an atmosphere inside the treatment chamber to less than an oxygen concentration in the air. The atmosphere adjustment mechanism is provided with an oxygen trap, for example. | 08-08-2013 |
20130203187 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The semiconductor device of this invention includes a semiconductor substrate having a main surface, and a magnetoresistive element located over the main surface of the semiconductor substrate. Further, it includes a protective layer, a wiring, a first upper electrode, and a second upper electrode. The protective layer is disposed so as to cover the side surface of the magnetoresistive element. The wiring is located over the top of the magnetoresistive element. The first upper electrode substantially the same in dimensions in plan view as the magnetoresistive element is disposed over the magnetoresistive element. The second upper electrode is electrically coupled with the first upper electrode over the first upper electrode, and larger in dimensions in plan view than the first upper electrode. | 08-08-2013 |
20130210169 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM - A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma. | 08-15-2013 |
20130217151 | METHOD FOR PRODUCING SPIN INJECTION ELECTRODE - A production method of the present disclosure includes: a first step of preparing a multi-layer graphene, and an iron oxide that is a ferromagnetic material contacting the graphene and containing Fe | 08-22-2013 |
20130224887 | Method of Forming a Laminated Magnetic Core with Sputter Deposited and Electroplated Layers - A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between each vertically adjacent pair of magnetic layers, is formed in a method that forms the magnetic layers with an electroplating process, and the insulation layers with a sputter depositing process. | 08-29-2013 |
20130224888 | SYSTEMS AND METHODS FOR FABRICATING SELF-ALIGNED RESISTIVE/MAGNETIC MEMORY CELL - Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr | 08-29-2013 |
20130236987 | SYSTEM, METHOD AND APPARATUS FOR MASK STRUCTURE FOR PATTERNING A WORKPIECE BY IONS - A method of fabricating workpieces includes one or more layers on a substrate that are masked with an ion implantation mask comprising two or more layers. The mask layers include a first mask layer closer to the substrate, and a second mask layer on the first mask layer. The method also comprises ion implanting one or more of the layers on the substrate. Ion implantation may form portions with altered physical properties from the layers under the mask. The portions may form a plurality of non-magnetic regions corresponding to apertures in the mask. | 09-12-2013 |
20130236988 | METHODS AND STRUCTURES OF INTEGRATED MEMS-CMOS DEVICES - A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched. | 09-12-2013 |
20130244342 | Reverse Partial Etching Scheme for Magnetic Device Applications - A magnetic tunnel junction (MTJ) structure is provided over a device wherein the MTJ comprises a tunnel barrier layer between a free layer and a pinned layer; and a top and bottom electrode inside the MTJ structure. A hard mask layer is formed on the top electrode. The hard mask layer, top electrode, free layer, tunnel barrier layer, and pinned layer are patterned to define the magnetic tunnel junction (MTJ) structures. A first dielectric layer is deposited over the MTJ structures and planarized to expose the top electrode. Thereafter, the top electrode and free layer are patterned. A second dielectric layer is deposited over the MTJ structures and planarized to expose the top electrode. A third dielectric layer is deposited over the MTJ structures and a metal line contact is formed through the third dielectric layer to the top electrode to complete fabrication of the magnetic device. | 09-19-2013 |
20130244343 | METHOD FOR PREPARING A THIN FILM DEVICE AND METHOD FOR PREPARING A COMMON MODE FILTER USING THE SAME - One aspect of the present invention provides a method for preparing a thin film device with an insulation layer from a dry polyimide film and a method for preparing a common mode filter using the same. A method for preparing a thin film device according to this aspect of the present invention includes the steps of forming at least one first conductive pattern on a substrate; placing a dry polyimide film on the first conductive pattern; applying a force to the dry polyimide film such that the dry polyimide film fills spaces in the first conductive pattern; and forming at least one second conductive pattern on the dry polyimide film. | 09-19-2013 |
20130244344 | METHOD FOR MANUFACTURING HIGH DENSITY NON-VOLATILE MAGNETIC MEMORY - Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited. | 09-19-2013 |
20130244345 | FABRICATION AND INTEGRATION OF DEVICES WITH TOP AND BOTTOM ELECTRODES INCLUDING MAGNETIC TUNNEL JUNCTIONS - An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs). | 09-19-2013 |
20130252348 | MAGNETORESISTIVE RANDOM ACCESS MEMORY ELEMENT AND FABRICATION METHOD THEREOF - A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer. | 09-26-2013 |
20130260482 | METHOD OF MANUFACTURING FERROELECTRIC THIN FILM - A method of manufacturing a ferroelectric thin film on a lower electrode by electrostatically spraying a ferroelectric thin film-forming electrostatic spray solution so as to coat the electrostatic spray solution on the lower electrode and form a coated film, drying, calcining, and then firing the coated film so as to crystallize the coated film. In this method, the electrostatic spray solution is a mixed solution in which a ferroelectric thin film-forming sol-gel solution and powder having the same composition as the solid content of the sol-gel solution and having a particle diameter that can be ejected from the spout are uniformly mixed, and, when the metallic compound-converted mass of a metallic compound dissolved in the sol-gel solution is represented by A and the mass of the powder is represented by B, a ratio of B with respect to (A+B) is in a range of 5% to 40%. | 10-03-2013 |
20130260483 | Integrated Circuits With Magnetic Core Inductors And Methods of Fabrications Thereof - In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil. | 10-03-2013 |
20130267042 | MRAM Fabrication Method with Sidewall Cleaning - Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described. | 10-10-2013 |
20130267043 | Magnetic Field Sensors and Methods for Fabricating the Magnetic Field Sensors - Magnetic field sensors and associated methods of manufacturing the magnetic field sensors include molded structures to encapsulate a magnetic field sensing element and an associated die attach pad of a lead frame and to also encapsulate or form a magnet or a flux concentrator. | 10-10-2013 |
20130288391 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A variable resistance memory device includes vertical electrodes vertically projecting from a substrate, first horizontal electrodes stacked along the vertical electrodes, second horizontal electrodes stacked along the vertical electrodes, and a variable resistance layer interposed between the vertical electrodes and the first and second horizontal electrodes, wherein the first and second horizontal electrodes are arranged in directions crossing with each other. | 10-31-2013 |
20130288392 | Method for Use in Making Electronic Devices Having Thin-Film Magnetic Components - Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness. | 10-31-2013 |
20130288393 | TECHNIQUES FOR PATTERNING MULTILAYER MAGNETIC MEMORY DEVICES USING ION IMPLANTATION - A method of patterning a substrate includes providing a layer stack comprising a plurality of layers on a base portion of the substrate, where the layer stack includes an electrically conductive layer and a magnetic layer. The method further includes forming a first mask feature on an outer surface of the layer stack above a first protected region and a second mask feature on the outer surface of the layer stack above a second protected region, and directing ions towards the layer stack to magnetically isolate and electrically isolate the first protected region from the second protected region. | 10-31-2013 |
20130288394 | MAGNETIC MEMORY AND METHOD OF FABRICATION - A method of forming a magnetic memory includes providing a layer stack comprising a plurality of magnetic layers and a plurality of electrically conducting layers on a base portion of a substrate; forming a first mask feature on an outer surface of the layer stack above a first protected region and a second mask feature on the outer surface of the layer stack above a second protected region, the first mask feature and second mask feature defining an exposed region of the layer stack in portions of the layer stack therebetween; and directing ions towards exposed the region of the layer stack in an ion exposure that is effective to magnetically isolate the first protected region from the second protected region and to electrically isolate the first protected region from the second protected region without removal of the exposed region of the layer stack. | 10-31-2013 |
20130288395 | MAGNETIC TUNNEL JUNCTION DEVICE FABRICATION - In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer coupled to the MTJ cap layer. The top electrode layer includes at least two layers and one layer of the two layers includes a nitrified metal. | 10-31-2013 |
20130288396 | Embedded Magnetic Random Access Memory (MRAM) - A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ. | 10-31-2013 |
20130288397 | MAGNETORESISTIVE EFFECT ELEMENT, MAGNETIC MEMORY, AND METHOD OF MANUFACTURING MAGENTORESISTIVE EFFECT ELEMENT - According to one embodiment, a magnetoresistive effect element includes a first magnetic layer including perpendicular anisotropy to a film surface and an invariable magnetization direction, the first magnetic layer having a magnetic film including an element selected from a first group including Tb, Gd, and Dy and an element selected from a second group including Co and Fe, a second magnetic layer including perpendicular magnetic anisotropy to the film surface and a variable magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer. The magnetic film includes amorphous phases and crystals whose particle sizes are 0.5 nm or more. | 10-31-2013 |
20130288398 | METHOD OF MANUFACTURING TUNNELING MAGNETORESISTIVE ELEMENT - [Object] To provide a method of manufacturing a perpendicular magnetization-type magnetic element, which does not need a step of depositing MgO. | 10-31-2013 |
20130295693 | SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SEMICONDUCTOR DEVICE - A semiconductor device with a functional element including an upper electrode composed of an electrically conductive metal oxide and being configured to store information; an interlayer insulating film covering the functional element; a contact hole formed in the interlayer insulating film, the contact hole including a side wall surface and a bottom and exposing an upper surface of the upper electrode at the bottom; an electrically conductive barrier film covering the bottom and the side wall surface of the contact hole; and a tungsten film formed on the electrically conductive barrier film, the tungsten film filling at least part of the contact hole, wherein a layer in which silicon atoms are concentrated is formed at the interface between the tungsten film and the electrically conductive barrier film. | 11-07-2013 |
20130295694 | CIRCUIT PROTECTION DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a circuit protection device and a method of manufacturing the same. The circuit protection device includes a common mode noise filter having a plurality of sheets, each of the sheets being formed to optionally include a coil pattern, an internal electrode, a hole filled with a conductive material, and a hole filled with a magnetic material; and an electrostatic discharge (ESD) protection device having a plurality of sheets, each of the sheets being formed to optionally include an internal electrode and a hole filled with an ESD protection material. | 11-07-2013 |
20130302912 | Method to Reduce Magnetic Film Stress for Better Yield - A method of forming a thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate so that the thin-film deposition is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer is formed on the CMOS substrate and is patterned by either forming undercut trenches extending into its upper surface or by fabricating T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage. | 11-14-2013 |
20130302913 | STORAGE ELEMENT, METHOD FOR MANUFACTURING STORAGE ELEMENT, AND MEMORY - A method of manufacturing a storage element by forming a magnetic layer; and forming a tunnel barrier layer on the magnetic layer, wherein, n the forming a tunnel barrier layer, the tunnel barrier layer is formed to a predetermined thickness in at least two steps in a divided manner. | 11-14-2013 |
20130302914 | Embedded Magnetic Random Access Memory (MRAM) - A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ. | 11-14-2013 |
20130309782 | PHASE CHANGE MATERIAL CELL WITH PIEZOELECTRIC OR FERROELECTRIC STRESS INDUCER LINER - An example embodiment disclosed is a process for fabricating a phase change memory cell. The method includes forming a bottom electrode, creating a pore in an insulating layer above the bottom electrode, depositing piezoelectric material in the pore, depositing phase change material in the pore proximate the piezoelectric material, and forming a top electrode over the phase change material. Depositing the piezoelectric material in the pore may include conforming the piezoelectric material to at least one wall defining the pore such that the piezoelectric material is deposited between the phase change material and the wall. The conformal deposition may be achieved by chemical vapor deposition (CVD) or by atomic layer deposition (ALD). | 11-21-2013 |
20130309783 | HYDROGEN-BLOCKING FILM FOR FERROELECTRIC CAPACITORS - An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH | 11-21-2013 |
20130309784 | Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications - A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X) | 11-21-2013 |
20130337582 | MRAM ETCHING PROCESSES - Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes. | 12-19-2013 |
20140004625 | MAGNETIC TUNNEL JUNCTION SELF-ALIGNMENT IN MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICES | 01-02-2014 |
20140011296 | HIGH CAPACITY LOW COST MULTI-STACKED CROSS-LINE MAGNETIC MEMORY - One embodiment of the present invention includes a diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ. | 01-09-2014 |
20140011297 | NONVOLATILE MEMORY CELL AND METHOD OF MANUFACTURING THE SAME - Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region. | 01-09-2014 |
20140011298 | MAGNETIC TUNNEL JUNCTION STRUCTURE - A method comprises forming a trench in a substrate. The method also comprises depositing a magnetic tunnel junction (MTJ) structure within the trench. The method further comprises planarizing the MTJ. | 01-09-2014 |
20140017817 | TECHNIQUES FOR TREATING SIDEWALLS OF PATTERNED STRUCTURES USING ANGLED ION TREATMENT - In one embodiment a method of method of treating a sidewall layer of a patterned feature includes providing the patterned feature as an etched structure comprising one or more layers disposed on a substrate and generally parallel to a plane of the substrate defined by a front surface of the substrate. The sidewall layer comprises material from the one or more etched layers. The method further includes arranging the substrate proximate a sheath modifier that is adjacent a plasma, and providing ions in an ion dose to the substrate by extracting the ions from the plasma through the sheath modifier, the ions impinging upon the substrate at an angle with respect to a perpendicular to the plane of the substrate. | 01-16-2014 |
20140017818 | METHOD FOR MANUFACTURING NON-VOLATILE MAGNETIC MEMORY CELL IN TWO FACILITIES - In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured. | 01-16-2014 |
20140017819 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A ferroelectric capacitor is formed above a semiconductor substrate ( | 01-16-2014 |
20140017820 | Co/Ni Multilayers with Improved Out-of-Plane Anisotropy for Magnetic Device Applications - A method for forming a MTJ in a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/Ni) | 01-16-2014 |
20140024138 | METHOD FOR ETCHING METAL LAYER AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - The inventive concepts disclosed herein include, for instance, methods for etching a metal layer and methods for manufacturing a semiconductor device using the etched metal layer. A wafer including a metal layer and a mask layer on the metal layer may be loaded into a process chamber. An etching gas may be supplied into the process chamber to etch the metal layer exposed by the mask layer. After the etching process, the mask layer may be removed. The etching gas can include phosphorus (P) and fluorine (F). An RF power may be constantly or selectively supplied to the process chamber, or different levels of RF power can be selectively supplied. An etching gas can be supplied to the process chamber when the RF power is off or at a lower level. A surface activation gas can be supplied when the RF power is on or at a higher level. | 01-23-2014 |
20140024139 | Hole First Hardmask Definition - A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack. | 01-23-2014 |
20140024140 | MAGNETORESISTANCE EFFECT DEVICE AND METHOD OF PRODUCTION OF THE SAME - A magnetoresistance effect device including a multilayer structure having a pair of ferromagnetic layers and a barrier layer positioned between them, wherein at least one ferromagnetic layer has at least the part contacting the barrier layer made amorphous and the barrier layer is an MgO layer having a highly oriented texture structure. | 01-23-2014 |
20140024141 | STT-MRAM CELL STRUCTURES - A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 01-23-2014 |
20140030824 | SEMICONDUCTOR DEVICE HAVING CAPACITOR WITH CAPACITOR FILM HELD BETWEEN LOWER ELECTRODE AND UPPER ELECTRODE - A ferroelectric memory is constituted to comprise a capacitor being formed above a semiconductor substrate ( | 01-30-2014 |
20140038309 | MAGNETIC RANDOM ACCESS MEMORY WITH SYNTHETIC ANTIFERROMAGNETIC STORAGE LAYERS AND NON-PINNED REFERENCE LAYERS - A method for fabricating a synthetic antiferromagnetic device, includes depositing a magnesium oxide spacer layer on a reference layer having a first and second ruthenium layer, depositing a cobalt iron boron layer on the magnesium oxide spacer layer; and depositing a third ruthenium layer on the cobalt iron boron layer, the third ruthenium layer having a thickness of approximately 0-18 angstroms. | 02-06-2014 |
20140038310 | MAGNETIC RANDOM ACCESS MEMORY WITH SYNTHETIC ANTIFERROMAGNETIC STORAGE LAYERS - A synthetic antiferromagnetic device includes a reference layer, a magnesium oxide spacer layer disposed on the reference layer, a cobalt iron boron layer disposed on the magnesium oxide spacer layer, and a first ruthenium layer disposed on cobalt iron boron layer, the first ruthenium layer having a thickness of approximately 0 Å to 32 Å. | 02-06-2014 |
20140038311 | METHODS FOR ETCHING MATERIALS USED IN MRAM APPLICATIONS - Embodiments of the invention provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in magnetoresistive random access memory applications. In one embodiment, a method of forming a MTJ structure on a substrate includes providing a substrate having a insulating tunneling layer disposed between a first and a second ferromagnetic layer disposed on the substrate, wherein the first ferromagnetic layer is disposed on the substrate followed by the insulating tunneling layer and the second ferromagnetic layer sequentially, supplying an ion implantation gas mixture to implant ions into the first ferromagnetic layer exposed by openings defined by the second ferromagnetic layer, and etching the implanted first ferromagnetic layer | 02-06-2014 |
20140038312 | FABRICATION OF A MAGNETIC TUNNEL JUNCTION DEVICE - A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material. | 02-06-2014 |
20140038313 | SEMICONDUCTOR FABRICATING DEVICE AND METHOD FOR DRIVING THE SAME, AND METHOD FOR FABRICATING MAGNETIC TUNNEL JUNCTION USING THE SAME - In a method for fabricating a magnetic tunnel junction, a first magnetic layer is formed on a substrate, and a tunnel insulating layer is formed on the first magnetic layer. Subsequently, a second magnetic layer is formed on the tunnel insulating layer. In the method, the first magnetic layer is formed by periodically sputtering a magnetic target while a metal target is continuously sputtered. | 02-06-2014 |
20140038314 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH ENHANCED MAGNETIC STIFFNESS AND METHOD OF MAKING SAME - A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, the amount of B of the second free sub-layer being greater than the amount of B in the first free sub-layer. Cooling down the STTMRAM element to a second temperature that is lower than the first temperature and depositing a third free sub-layer directly on top of the second free layer, with the third free sub-layer being made partially of boron (B), wherein the amount of B in the third sub-free layer is less than the amount of B in the second free sub-layer. | 02-06-2014 |
20140057369 | METHODS FOR FORMING INTERCONNECTION LINE USING SCREEN PRINTING TECHNIQUE - Methods of forming an interconnection line pattern using a screen printing technique. The method includes preparing a substrate having unevenness, aligning a stencil mask on the substrate, and printing a paste including materials for forming the interconnection line pattern on a convex portion of the unevenness formed on the substrate. | 02-27-2014 |
20140073064 | MAGNETIC TUNNEL JUNCTION (MTJ) ON PLANARIZED ELECTRODE - A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ. | 03-13-2014 |
20140080227 | Method of Manufacturing Semiconductor Device - According to one embodiment, a method of manufacturing a semiconductor device includes forming a silicon nitride layer on a metal layer, forming a plasma of a gas mixture of carbon oxide and oxygen, and selectively etching the silicon nitride layer with respect to the metal layer by using the plasma of the gas mixture. | 03-20-2014 |
20140080228 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer. | 03-20-2014 |
20140087483 | MANUFACTURING METHOD OF MAGNETORESISTIVE EFFECT ELEMENT AND MANUFACTURING APPARATUS OF MAGNETORESISTIVE EFFECT ELEMENT - According to one embodiment, a manufacturing method of a magnetoresistive effect element includes forming a laminated structure on a substrate, the laminated structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having an invariable magnetization direction, and a non-magnetic layer between the first and second magnetic layers, forming a first mask layer having a predetermined plane shape on the laminated structure, and processing the laminated structure based on the first mask layer by using an ion beam whose solid angle in a center of the substrate is 10° or more. | 03-27-2014 |
20140087484 | METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERRORELECTRIC RANDOM ACCESS MEMORY (F-RAM) WITH SIMULTANEOUS FORMATION OF SIDEWALL FERROELECTRIC CAPACITORS - A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate, and forming bottom electrode spacers proximal to sidewalls of the opening. Next, a ferroelectric dielectric layer is formed in the opening over the surface of the substrate and between the bottom electrode spacers, and a pair of top electrodes is formed within the opening comprising first and second side portions displaced laterally from respective ones of the bottom electrode spacers by the ferroelectric dielectric layer. | 03-27-2014 |
20140087485 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a first magnetic film containing boron, forming a second magnetic film free from boron, above the first magnetic film. The method further includes selectively etching the second magnetic film with respect to the first magnetic film using plasma of etching gas which contains oxygen and hydrogen and which is free from halogen. | 03-27-2014 |
20140093983 | METHOD FOR FABRICATING A DAMASCENE SELF-ALIGNED FERRORELECTRIC RANDOM ACCESS MEMORY (F-RAM) HAVING A FERROELECTRIC CAPACITOR ALIGNED WITH A THREE DIMENSIONAL TRANSISTOR STRUCTURE - A method for a non-volatile, ferroelectric random access memory (F-RAM) device that includes a ferroelectric capacitor aligned with a preexisting structure is described. In one embodiment, the method includes forming an opening in an insulating layer over a contact in a planar surface of a substrate to expose at least a portion of the contact. Next a self-aligned contact (SAC) is formed electrically coupling to the contact, the SAC medially located in the opening and proximal to a sidewall thereof. A ferroelectric spacer is then formed in the opening medially of the SAC, and a top electrode spacer formed in the opening over the insulating cap and medially of the ferroelectric spacer. | 04-03-2014 |
20140099734 | DEPOSITION METHOD AND DEPOSITION APPARATUS - Disclosed is a method for depositing an insulating film with a high coverage through a low temperature process. The deposition method deposits an insulating film on a substrate using a deposition apparatus which includes a processing container that defines a processing space in which plasma is generated, a gas supply unit configured to supply a gas into the processing space, and a plasma generating unit configured to generate plasma by supplying microwave into the processing container. The deposition method includes depositing an insulating film that includes SiN on the substrate by supplying into a gas formed by adding H | 04-10-2014 |
20140099735 | Structure and Method to Fabricate High Performance MTJ Devices for Spin-Transfer Torque (STT)-RAM Application - A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by natural oxidation and containing an oxygen surfactant layer to form a more uniform MgO layer and lower breakdown distribution percent. A CoFeB/NCC/CoFeB composite free layer with a middle nanocurrent channel layer minimizes Jc | 04-10-2014 |
20140120634 | METHOD OF MANUFACTURING TOUCH SENSING PANEL - A method of manufacturing a touch sensing panel includes providing a substrate, forming a plurality of first electrodes arranged on the substrate, the first electrodes being separated from each other, forming a photoresist layer on the plurality of first electrodes, forming a plurality of photoresist removing regions positioned to intersect the first electrodes and to be separated from each other on the photoresist layer, and forming a tunneling magnetoresistance (TMR) element layer and a second electrode layer comprising a plurality of second electrodes on the photoresist layer. The method provides a touch sensing panel capable of being driven at high speed and reduces manufacturing cost and time. | 05-01-2014 |
20140120635 | ETCHING METHOD AND SUBSTRATE PROCESSING APPARATUS - A gas for an etching process and a treatment process of a metal stacked film in which an insulating layer is interposed between two layers of magnetic materials can be optimized. An etching method of etching a multilayered film including a metal stacked film in which an insulating layer is interposed between a first magnetic layer and a second magnetic layer includes etching the metal stacked film with plasma generated by supplying a gas containing at least C, O, and H into a processing chamber; and treating the metal stacked film with plasma generated by supplying a gas containing at least a CF | 05-01-2014 |
20140127830 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A method of forming a magnetoresistive random access memory (MRAM) apparatus includes forming a first conductive line on a first insulating layer, forming a second insulating layer on the first conductive line and forming a magnetic tunnel junction through the second insulating layer to contact the first conductive line. The method also includes forming a cavity adjacent to the magnetic tunnel junction in the second insulating layer and forming a second conductive line on the second insulating layer to contact the magnetic tunnel junction. | 05-08-2014 |
20140127831 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A method of forming a magnetic random access memory (MRAM) device includes forming at least one write line, forming a first insulating layer over the at least one write line and forming a heating line on the first insulating layer. The method includes forming at least one tunnel junction above the at least one write line, the at least one tunnel junction connected to the heating line, forming a second insulating layer on the heating line and forming heat current supply vias at each end of the current line. The method further includes forming heat current supply lines connected to each heat current supply via and forming at least one read line above the at least one tunnel junction and physically connected to the at least one tunnel junction. | 05-08-2014 |
20140127832 | FORMING METHOD OF AN ANNULAR STORAGE UNIT OF A MAGNETO-RESISTIVE MEMORY - The present invention discloses a method of forming an annular storage structure of a magneto-resistive memory. It relates to the manufacturing process of the semiconductor devices. The method includes the following steps: a silicon oxide layer and a silicon nitride layer is formed on the thin-film layer of a magnetic channel junction; a circular silicon nitride trench is formed; a poly-silicon thin film is deposited to cover the silicon nitride trench, the annular poly-silicon structure is formed by plasma etching back; the remaining silicon nitride thin film is removed to form the annular poly-silicon hard mask; the poly-silicon hard mask is used when the magnetic channel junction thin film layer is etched by plasma etching. At last, the unit structure of magnetic channel junction is formed. The advantages of the above technical solutions are: the diameter of the round photo-resist pattern is larger; it is possible to use the photo-etching with normal resolution, thus the method reduces the cost of production enhances market competitiveness and obtains significant economic benefits. | 05-08-2014 |
20140134754 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM - A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma. | 05-15-2014 |
20140141530 | MAGNETIC DOMAIN WALL SHIFT REGISTER MEMORY DEVICE READOUT - A memory device includes a first nanowire, a second nanowire and a magnetic tunnel junction device coupling the first and second nanowires. | 05-22-2014 |
20140141531 | METHOD FOR PRODUCING FERROELECTRIC THIN FILM - It is possible to produce a ferroelectric thin film controlled to have the preferential crystal orientation in the (100) plane with a simple process without providing a seed layer or a buffer layer. A ferroelectric thin film is produced on a lower electrode by irradiating a surface of the lower electrode of a substrate having the lower electrode where the crystal plane is oriented in a (111) axis direction, with an atmospheric pressure plasma, coating a composition for forming a ferroelectric thin film on the lower electrode, and heating and crystallizing the coated composition. | 05-22-2014 |
20140141532 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A plasma processing method is used to etch a multilayered material having a stacked structure, in which a first magnetic layer, an insulating layer, a second magnetic layer, and a mask material are stacked in sequence, in a plasma processing apparatus including a processing chamber that partitions a processing space where plasma is generated and a gas supply unit that supplies a processing gas into the processing space. The plasma processing method includes a mask forming process of forming a mask on the second magnetic layer by etching the mask material; an etching process of supplying the processing gas into the processing chamber to generate plasma, etching the second magnetic layer by the mask, and stopping the etching on a surface of the insulating layer. Further, the second magnetic layer contains CoFeB, the insulating layer contains MgO, and the processing gas contains H | 05-22-2014 |
20140141533 | METHOD OF FABRICATING A MAGNETORESISTIVE RANDOM ACCESS STRUCTURE - One method includes forming an anti-ferromagnetic layer on a substrate. A ferromagnetic layer may be formed on the anti-ferromagnetic layer. The ferromagnetic layer includes a first, second and third portions where the second portion is located between the first and third portions. A first ion irradiation is performed to only one portion of the ferromagnetic layer. A second ion irradiation is performed to another portion of the ferromagnetic layer. | 05-22-2014 |
20140147940 | PROCESS-COMPATIBLE SPUTTERING TARGET FOR FORMING FERROELECTRIC MEMORY CAPACITOR PLATES - A sputtering target for a conductive oxide, such as SrRuO | 05-29-2014 |
20140147941 | MRAM DEVICE AND INTEGRATION TECHNIQUES COMPATIBLE WITH LOGIC INTEGRATION - A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps. | 05-29-2014 |
20140170774 | METHOD FOR MANUFACTURING A MAGNETORESISTIVE SENSOR - A method for manufacturing a magnetic sensor that allows the sensor to be constructed with a very narrow track width and with smooth, well defined side walls. A tri-layer mask structure is deposited over a series of sensor layers. The tri-layer mask structure includes an under-layer, a Si containing hard mask deposited over the under-layer and a photoresist layer deposited over the Si containing hard mask. The photoresist layer is photolithographically patterned to define a photoresist mask. A first reactive ion etching is performed to transfer the image of the photoresist mask onto the Si containing hard mask. The first reactive ion etching is performed in a chemistry that includes CF | 06-19-2014 |
20140170775 | HPC Workflow for Rapid Screening of Materials and Stacks for STT-RAM - In some embodiments, HPC techniques are applied to the screening and evaluating the materials, process parameters, process sequences, and post deposition treatment processes for the development of STT-RAM stacks. Simple test structures are employed for initial screening of basic materials properties of candidate materials for each layer within the stack. The use of multiple site-isolated regions on a single substrate allows many material and/or process conditions to be evaluated in a timely and cost effective manner. Interactions between the layers as well as interactions with the substrate can be investigated in a straightforward manner. | 06-19-2014 |
20140170776 | MTJ STACK AND BOTTOM ELECTRODE PATTERNING PROCESS WITH ION BEAM ETCHING USING A SINGLE MASK - Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step. | 06-19-2014 |
20140170777 | Vertically Oriented Semiconductor Device and Shielding Structure Thereof - The present disclosure involves a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an electronic device positioned over the substrate. The electronic device includes an opening. The semiconductor device includes a shielding device positioned over the substrate and surrounding the electronic device. The shielding device includes a plurality of elongate members. A subset of the plurality of elongate members extend through the opening of the electronic device. At least one of the electronic device and the shielding device is formed in an interconnect structure positioned over the substrate. | 06-19-2014 |
20140170778 | METHOD OF MANUFACTURING MAGNETORESISTIVE ELEMENT AND METHOD OF PROCESSING MAGNETORESISTIVE FILM - In a case where reactive ion etching using a gas containing an oxygen atom is used for etching or a magnetoresistive element, a magnetic film becomes damaged due to oxidation. Such damage to the element by the oxidation becomes a factor which causes deterioration in element properties. In the etching of the magnetoresistive element according to one embodiment of the present invention, a magnetoresistive film is subjected to ion beam etching and thereafter to reactive ion etching. A side deposition formed by the ion beam etching coats a sidewall of the magnetoresistive film and reduces damage by the oxygen atom during the later reactive ion etching. Also, a time during which the element is exposed to plasma of the gas containing the oxygen atom can be reduced. | 06-19-2014 |
20140170779 | COHERENT SPIN FIELD EFFECT TRANSISTOR - A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000° K to provide a few monolayer thick layer. Where the gate is cobalt, the resulting magnetic oxide is Co | 06-19-2014 |
20140179026 | METHOD FOR GENERATING QUANTIZED ANOMALOUS HALL EFFECT - A method for generating quantum anomalous Hall effect is provided. A topological insulator quantum well film in 3QL to 5QL is formed on an insulating substrate. The topological insulator quantum well film is doped with a first element and a second element to form the magnetically doped topological insulator quantum well film. The doping of the first element and the second element respectively introduce hole type charge carriers and electron type charge carriers in the magnetically doped topological insulator quantum well film, to decrease the carrier density of the magnetically doped topological insulator quantum well film to be smaller than or equal to 1×10 | 06-26-2014 |
20140206104 | STRAIN INDUCED REDUCTION OF SWITCHING CURRENT IN SPIN-TRANSFER TORQUE SWITCHING DEVICES - Partial perpendicular magnetic anisotropy (PPMA) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an MTJ to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the MTJ results. The directed static strain/stress on the MTJ is induced in a controlled direction and/or with a controlled magnitude during fabrication. The MTJ is permanently subject to a predetermined directed stress and permanently includes the directed static strain/strain that provides reduced switching current. | 07-24-2014 |
20140206105 | TRANSFORMER SIGNAL COUPLING FOR FLIP-CHIP INTEGRATION - Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer. In another embodiment, a method for matching impedance in an RF circuit fabricated using flip-chip techniques may include passing an RF input signal through a first inductor formed using a passive process, inducing a time varying magnetic flux in proximity to a second inductor formed using an active process, and passing an RF signal induced by the time varying magnetic flux through the second inductor. | 07-24-2014 |
20140206106 | MAGNETIC MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane. The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region. The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region. | 07-24-2014 |
20140206107 | SEMICONDUCTOR FERROELECTRIC DEVICE, MANUFACTURING METHOD FOR THE SAME, AND ELECTRONIC DEVICE - A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode. | 07-24-2014 |
20140212993 | METHOD OF MANUFACTURING A MAGNETORESISTIVE DEVICE - A method of manufacturing a magnetoresistive-based device includes etching a hard mask layer, the etching having a selectivity greater than 2:1 and preferably less than 5:1 of the hard mask layer to a photo resist thereover. Optionally, the photo resist is trimmed prior to the etch, and oxygen may be applied during or just subsequent to the trim of the photo resist to increase side shrinkage. An additional step includes an oxygen treatment during the etch to remove polymer from the structure and etch chamber. | 07-31-2014 |
20140220707 | METHOD FOR MANUFACTURING AND MAGNETIC DEVICES HAVING DOUBLE TUNNEL BARRIERS - A dual tunnel barrier magnetic element has a free magnetic layer positioned between first and second tunnel barriers and an electrode over the second tunnel barrier. A two step etch process allows for forming an encapsulation material on a side wall of the electrode and the second tunnel barrier subsequent to the first etch for preventing damage to the first tunnel barrier when performing the second etch to remove a portion of the free layer. | 08-07-2014 |
20140220708 | MR Enhancing Layer (MREL) For Spintronic Devices - The performance of an MR device has been improved by inserting one or more Magneto-Resistance Enhancing Layers (MRELs) into approximately the center of one or more of the magnetic layers such as an inner pinned (AP1) layer, spin injection layer (SIL), field generation layer (FGL), and a free layer. An MREL is a layer of a low band gap, high electron mobility semiconductor such as ZnO or a semimetal such as Bi. The MREL may further comprise a first conductive layer that contacts a bottom surface of the semiconductor or semimetal layer, and a second conductive layer that contacts a top surface of the semiconductor or semimetal layer. | 08-07-2014 |
20140242728 | METHOD OF ETCHING A MAGNESIUM OXIDE FILM - A magnetoresistive device includes an MR element including a metal layer, and an insulating portion made of magnesium oxide and in contact with the MR element. A method of manufacturing the magnetoresistive device includes the step of removing an unwanted magnesium oxide film that is formed by the magnesium oxide in the process of forming the insulating portion. In this step, the unwanted magnesium oxide film is wet etched by using an etchant containing an aqueous ammonia solution. | 08-28-2014 |
20140248718 | PATTERNING OF MAGNETIC TUNNEL JUNCTION (MTJ) FILM STACKS - Chemical modification of non-volatile magnetic random access memory (MRAM) magnetic tunnel junctions (MTJs) for film stack etching is described. In an example, a method of etching a MTJ film stack includes modifying one or more layers of the MTJ film stack with a phosphorous trifluoride (PF | 09-04-2014 |
20140248719 | MTJ MANUFACTURING METHOD UTILIZING IN-SITU ANNEALING AND ETCH BACK - The present invention is directed to a method for manufacturing spin transfer torque magnetic random access memory (STTMRAM) devices. The method, which utilizes in-situ annealing and etch-back of the magnetic tunnel junction (MTJ) film stack, comprises the steps of depositing a barrier layer on top of a bottom magnetic layer and then depositing an interface magnetic layer on top of the barrier layer to form an MTJ film stack; annealing the MTJ film stack at a first temperature and then cool the MTJ film stack to a second temperature lower than the first temperature; etching away a top portion of the interface magnetic layer; and depositing at least one top layer on top of the etched interface magnetic layer. The method may further include the step of annealing the MTJ film stack at a third temperature between the first and second temperature after the step of depositing at least one top layer. | 09-04-2014 |
20140256061 | Method of Etching MTJ Using CO Process Chemistries - A method for fabricating a magnetic film structure is provided. The method comprises forming a magnetic structure on a bottom electrode layer, the magnetic structure comprising at least one pinned bottom magnetic film layer having a fixed magnetic orientation; at least one top magnetic film layer whose magnetic orientation can be manipulated by a current; and a tunneling layer between the bottom magnetic film layer and the top magnetic film layer; forming a metallic hard mask atop the magnetic structure; patterning and etching the metallic hard mask to define exposed areas of the magnetic structure; selectively etching the exposed areas of the magnetic structure by a chemical etch process based on a CO etch chemistry to form discrete magnetic bits. | 09-11-2014 |
20140256062 | METHOD FOR FABRICATING NONVOLATILE MEMORY DEVICE - A method for fabricating a nonvolatile memory device is provided. The method includes forming a transistor including an impurity region formed in a substrate, forming a first interlayer insulation layer covering the transistor, the first interlayer insulation layer including a protrusion overlapping the impurity region, and forming an information storage unit on the protrusion, the information storage unit exposing side surfaces of the protrusion using point cusp magnetron-physical vapor deposition (PCM-PVD) and electrically connected to the impurity region. | 09-11-2014 |
20140256063 | CONTACTLESS COMMUNICATIONS USING FERROMAGNETIC MATERIAL - A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils. | 09-11-2014 |
20140273282 | PARALLEL SHUNT PATHS IN THERMALLY ASSISTED MAGNETIC MEMORY CELLS - A thermally assisted magnetic memory cell device includes a substrate, a first electrode disposed on the substrate, a magnetic tunnel junction disposed on the first electrode, a second electrode disposed on the magnetic tunnel junction, a conductive hard mask disposed on the second electrode and a parallel shunt path coupled to the magnetic tunnel junction, thereby electrically coupling the first and second electrodes. | 09-18-2014 |
20140273283 | FORMING MAGNETIC MICROELECTROMECHANICAL INDUCTIVE COMPONENTS - A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space. | 09-18-2014 |
20140273284 | THERMALLY ASSISTED MRAM WITH MULTILAYER STRAP AND TOP CONTACT FOR LOW THERMAL CONDUCTIVITY - A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). The device includes a magnetic tunnel junction configured to store data, a first multilayer contact structure positioned on one end of the magnetic tunnel junction, and a second multilayer contact structure positioned on an opposite end of the magnetic tunnel junction. The first multilayer contact structure and the second multilayer contact structure each include multiple layers of metals. The multiple layers of metals are structured to inhibit thermal conductivity between the magnetic tunnel junction and surrounding structures, and the multiple layers of metals are structured to electrically conduct electrical current. | 09-18-2014 |
20140273285 | MEMORY ARRAY WITH SELF-ALIGNED EPITAXIALLY GROWN MEMORY ELEMENTS AND ANNULAR FET - A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element. | 09-18-2014 |
20140273286 | STRUCTURE AND FABRICATION OF MEMORY ARRAY WITH EPITAXIALLY GROWN MEMORY ELEMENTS AND LINE-SPACE PATTERNS - A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. | 09-18-2014 |
20140273287 | METHOD OF MANUFACTURING THE SAME - A method of manufacturing magnetoresistive random access memory (MRAM) device includes foaming first and second patterns on a substrate in an alternating and repeating arrangement, forming a first capping layer on top surfaces of the first and second patterns, and removing first portions of the first capping layer and a portion of the second patterns thereunder to form first openings exposing the substrate. The method further includes forming source lines filling lower portions of the first openings, respectively, forming second capping layer patterns filling upper portions of the first openings, respectively, and removing second portions of the first capping layer and a portion of the second patterns thereunder to form second openings exposing the substrate. Then, contact plugs and pad layers are integrally formed and sequentially stacked on the substrate to fill the second openings. | 09-18-2014 |
20140273288 | METHOD OF FORMING A MAGNETIC TUNNEL JUNCTION DEVICE - A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure. | 09-18-2014 |
20140287534 | HIGHLY SENSITIVE MAGNETIC TUNABLE HETEROJUNCTION DEVICE FOR RESISTIVE SWITCHING - The present invention discloses highly sensitive magnetic heterojunction device consisting of a composite comprising ferromagnetic (La | 09-25-2014 |
20140287535 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity. | 09-25-2014 |
20140287536 | METHOD OF MANUFACTURING A MAGNETORESISTIVE-BASED DEVICE WITH VIA INTEGRATION - A method is provided for forming a first via with an electrically conductive material, for example, copper, that is formed over and coupled to a conductive landing pad of an MRAM array. A sputter step is performed to lower the surface of the first via below that of a surrounding dielectric material. This recess is repeated in subsequent processing steps, providing alignment marks for the formation of a magnetic tunnel junction. The magnetic tunnel junction may be offset from the first via, and a second via being formed above the magnetic tunnel junction and to a conductive layer. | 09-25-2014 |
20140287537 | Method of Fabricating a Magnetoresistive Element - A method of fabricating a magnetoresistive element, the method comprising: forming a first plurality of layers without breaking a vacuum, the first plurality of layers sequentially comprising: a first nonmagnetic conductive layer; a first ferromagnetic layer comprising an amorphous structure and a first magnetization direction; a nonmagnetic tunnel barrier layer; a second ferromagnetic layer comprising an amorphous structure and a second magnetization direction, and a getter layer having a direct contact with the second ferromagnetic layer; annealing the first plurality of layers; removing the getter layer and a portion of the second ferromagnetic layer adjacent to the getter layer; forming above the second ferromagnetic layer a second plurality of layers such that interface between the second ferromagnetic layer and the second plurality of layers is formed without breaking a vacuum after removing the getter layer and the portion of the second ferromagnetic layer, the second plurality of layers sequentially comprising: a third magnetic layer comprising a third fixed magnetization direction directed substantially perpendicular to a substrate surface, and a second nonmagnetic conductive layer; wherein the first ferromagnetic layer, the tunnel barrier layer, and the second ferromagnetic layer crystallize during annealing into a coherent body-centered cubic (bcc) structure with (001) plane oriented, the first magnetization direction and the second magnetization direction are directed substantially perpendicular to the substrate surface, the second magnetization direction is fixed and is directed antiparallel to the third magnetization direction, and the first magnetization direction is reversible. | 09-25-2014 |
20140295579 | METHOD OF PATTERNING MTJ STACK - This invention comprises methods to form isolated magnetic tunneling junction (MTJ) memory element with small footprint using oxygen-ion implantation. After patterned resist is form on an MTJ film, the substrate is subject to a series of ion implantations outside the mask areas to subsequently implant Mg and oxygen ions into the exposed MTJ junction region, followed by high temperature rapid thermal annealing. Using such a process, implanted oxygen ions, Mg ions and non-oxidized Mg atoms in MTJ stack form highly resistive MgO crystalline and the ion implanted area is converted into electrically insulated metal oxide, creating a shape well-defined MTJ memory element with ultra-small dimensions and vertical edges. | 10-02-2014 |
20140295580 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND MANUFACTURING APPARATUS - A method for manufacturing a semiconductor device includes accommodating in a processing chamber a semiconductor structural body having a semiconductor substrate and a laminated structure formed on the semiconductor substrate and having multiple metal films including a noble-metal film, and generating a bias voltage on the semiconductor substrate while generating an oxygen plasma in the processing chamber such that a plasma treatment removes at least part of the noble-metal film in the laminated structure of the semiconductor structural body. | 10-02-2014 |
20140308757 | MEMS DEVICE AND A METHOD OF MAKING THE SAME - A MEMS gyro is provided, having a movable portion, a non-movable portion, and a magnetic sensing structure that comprises a magnetic source disposed at the movable portion, a magnetic sensing element positioned at the non-movable portion. The movable portion is capable of moving in response to external angular velocity or an external accelerator such that the magnetic field sensed by the magnetic sensing element is in relation to the movement of the movable portion, therefore, the angular velocity or the accelerator. A method of making the MEMS gyro device is disclosed herein. | 10-16-2014 |
20140308758 | PATTERNING MAGNETIC MEMORY - Methods of forming material junctions for magnetic memory devices are described. The methods involve providing a material stack including a bottom magnetic tunneling junction layer, a tunneling barrier layer, and a top magnetic tunneling junction layer (from bottom to top) on a substrate. The top magnetic tunneling junction layer is patterned to form a top magnetic tunneling junction and then a dielectric spacer layer may be formed over the top magnetic tunneling junction. The dielectric spacer is etched to leave a vertical dielectric spacer to maintain electrical separation between the top magnetic tunneling junction and the bottom magnetic tunneling junction during and following subsequent etching/processing. In an alternative embodiment the spacer layer is lithographically defined. | 10-16-2014 |
20140308759 | METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING MAGNETIC TUNNEL JUNCTION AND RELATED DEVICE - A method of forming a semiconductor device includes forming a perpendicular magnetized magnetic device, annealing the perpendicular magnetized magnetic device, and applying a magnetic field to the perpendicular magnetized magnetic device. The semiconductor device may be a magnetoresistance data storage device. The magnetic field is applied in a direction that is substantially perpendicular to a substrate coupled to the perpendicular magnetized magnetic device. | 10-16-2014 |
20140308760 | PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE WITH ENHANCED STABILITY AND METHOD TO FORM SAME - Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer. | 10-16-2014 |
20140315329 | METHOD OF MANUFACTURING A MAGNETORESISTIVE-BASED DEVICE - A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode. | 10-23-2014 |
20140322827 | METHOD FOR PACKAGING DISPLAY DEVICE AND APPARATUS THEREFOR - The present application provides a method for packaging a display device and an apparatus therefor. The method includes: providing a display device, a platform, a laser beam and a magnetic mechanism; wherein the display device includes a light emitting element, the light emitting element includes at least one effective light emitting region thereon and is prepared on an upper surface of a glass substrate, the glass substrate is bonded to a glass cover plate via a sealing adhesive layer; the display device is placed on the platform; the laser beam penetrates the glass cover plate and focuses on the sealing adhesive layer to sinter the sealing adhesive layer; and the magnetic mechanism clamps the glass cover plate and the glass substrate from top to bottom and applies a uniform pressing force on the effective light emitting region of the display device. | 10-30-2014 |
20140322828 | Method for Manufacturing Magnetoresistance Component - A method for manufacturing a magnetoresistance component is provided. A substrate is provided. A circuit structure layer including an interconnect structure is formed on the substrate, wherein the interconnect structure comprises a metal pad. A dielectric layer is formed on the circuit structure. A metal damascene structure is formed in the dielectric layer. A patterned magnetoresistance component is formed above the metal damascene structure to electrically connect to the metal damascene structure. | 10-30-2014 |
20140322829 | SEMICONDCUTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a pinned layer having a magnetic direction permanently set to a first direction, a tunnel insulating layer arranged on the pinned layer, a free layer arranged on the tunnel insulating layer and having a changeable magnetic direction, and a magnetic induction layer formed to surround the pinned layer and have a magnetic direction permanently set to a second direction different from the first direction. | 10-30-2014 |
20140329337 | PERPENDICULAR SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE HAVING OFFSET CELLS AND METHOD TO FORM SAME - Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device. | 11-06-2014 |
20140349413 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device may include forming a material layer on a substrate, performing a selective oxidation process to form a capping oxide layer on a first surface of the material layer, wherein a second surface of the material layer is not oxidized, and etching the material layer through the second surface to form a material pattern. An etch rate of the capping oxide layer is less than an etch rate of the material layer. A semiconductor device may include a lower electrode on a substrate, a data storage part on a top surface of the lower electrode, an upper electrode on the data storage part, and a capping oxide layer arranged on at least a portion of a top surface of the upper electrode. The capping oxide layer may include an oxide formed by oxidation of an upper surface of the upper electrode. | 11-27-2014 |
20140349414 | METHOD TO REDUCE MAGNETIC FILM STRESS FOR BETTER YIELD - A thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate, is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer on the CMOS substrate is patterned by either undercut trenches extending into its upper surface or by T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage. | 11-27-2014 |
20140349415 | PERPENDICULAR MTJ STACKS WITH MAGNETIC ANISOTROPY ENHANCING LAYER AND CRYSTALLIZATION BARRIER LAYER - Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer. | 11-27-2014 |
20140349416 | METHOD FOR MANUFACTURING A MAGNETIC TUNNEL JUNCTION - The present invention relates to a magnetic tunnel junction device and a manufacturing method thereof. The magnetic tunnel junction device includes: i) a first magnetic layer including a compound having a chemical formula of (A | 11-27-2014 |
20140356979 | THERMALLY ASSISTED MRAM WITH A MULTILAYER ENCAPSULANT FOR LOW THERMAL CONDUCTIVITY - A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction. | 12-04-2014 |
20140363902 | MAGNETIC MATERIALS WITH ENHANCED PERPENDICULAR ANISOTROPY ENERGY DENSITY FOR STT-RAM - A mechanism is provided for a spin torque transfer random access memory device. A reference layer is disposed on a seed layer. A tunnel barrier is disposed on the reference layer. A free layer is disposed on the tunnel barrier. A cap layer is disposed on the free layer. The free layer includes a magnetic layer and a metal oxide layer, in which the magnetic layer is disposed on the tunnel barrier and the metal oxide layer is disposed on the magnetic layer. A metal material used in the metal oxide layer includes at least one of Ti, Ta, Ru, Hf, Al, La, and any combination thereof. | 12-11-2014 |
20140370621 | FERROELECTRIC CAPACITOR ENCAPSULATED WITH A HYDROGEN BARRIER - An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. | 12-18-2014 |
20140377884 | METHOD OF FABRICATING A MAGNETIC TUNNEL JUNCTION DEVICE - The present disclosure relates to a magnetic tunnel junction (MTJ) device and its fabricating method. Through forming MTJ through a damascene process, device damage due to the etching process and may be avoided. In some embodiments, a spacer is formed between a first portion and a second portion of the MTJ to prevent the tunnel insulating layer of the MTJ from being damaged in subsequent processes, greatly increasing product yield thereby. In other embodiments, signal quality may be improved and magnetic flux leakage may be reduced through the improved cup-shaped MTJ structure of this invention. | 12-25-2014 |
20150017741 | PLASMA ETCHING METHOD - In a plasma etching method of plasma-etching a sample which has a first magnetic film, a second magnetic film disposed above the first magnetic film, a metal oxide film disposed between the first magnetic film and the second magnetic film, a second metal film disposed over the second magnetic film and forming an upper electrode, and a first metal film disposed below the first magnetic film and forming a lower electrode, the plasma etching method includes the steps of: a first process for etching the first magnetic film, the metal oxide film, and the second magnetic film by using carbon monoxide gas; and a second process for etching the sample by using mixed gas of hydrogen gas and inactive gas after the first process. In this case, the first metal film is a film containing therein tantalum. | 01-15-2015 |
20150017742 | METHODS FOR MANUFACTURING A DATA STORAGE DEVICE - Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches. | 01-15-2015 |
20150017743 | MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages. | 01-15-2015 |
20150031146 | TOOL FOR ANNEALING OF MAGNETIC STACKS - In one embodiment of the invention, there is provided a tool for annealing a magnetic stack. The tool includes a housing defining a heating chamber; a holding mechanism to hold at least one wafer in a single line within the heating chamber, a heating mechanism to heat the at least one wafer; and a magnetic field generator to generate a magnetic field whose field lines pass through the single line of wafers during a magnetic annealing process; wherein the holding mechanism comprises a wafer support of holding the single line of wafers between the heating mechanism and the magnetic field generator. The tool may be a rapid thermal processor retrofitted with the magnetic field generator. | 01-29-2015 |
20150044781 | METHOD OF FORMING MAGNETIC MEMORY DEVICES - Provided is a method of forming a magnetic memory device. A first magnetic layer, a tunnel barrier, and a second magnetic layer are deposited on a substrate. The second magnetic layer, the tunnel barrier, and the first magnetic layer are etched to form magnetic tunnel junction structures. An ion beam etching process is performed using an oxygen-containing source gas to remove etching by-products on sidewalls of the magnetic tunnel junction structure and to oxidize the sidewalls of the magnetic tunnel junction structures. | 02-12-2015 |
20150044782 | FABRICATION PROCESS AND LAYOUT FOR MAGNETIC SENSOR ARRAYS - A magnetic sensor includes a plurality of groups, each group comprising a plurality of magnetic tunnel junction (MTJ) devices having a plurality of conductors configured to couple the MTJ devices within one group in parallel and the groups in series enabling independent optimization of the material resistance area (RA) of the MTJ and setting total device resistance so that the total bridge resistance is not so high that Johnson noise becomes a signal limiting concern, and yet not so low that CMOS elements may diminish the read signal. Alternatively, the magnetic tunnel junction devices within each of at least two groups in series and the at least two groups in parallel resulting in the individual configuration of the electrical connection path and the magnetic reference direction of the reference layer, leading to independent optimization of both functions, and more freedom in device design and layout. The X and Y pitch of the sense elements are arranged such that the line segment that stabilizes, for example, the right side of one sense element; also stabilizes the left side of the adjacent sense element. | 02-12-2015 |
20150050750 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A plasma processing method of etching a multilayered material having a structure where a first magnetic layer | 02-19-2015 |
20150056722 | MTJ STRUCTURE AND INTEGRATION SCHEME - A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack. | 02-26-2015 |
20150064804 | METHOD FOR MANUFACTURING NIOBATE-SYSTEM FERROELECTRIC THIN FILM DEVICE - There is provided a method for manufacturing a niobate-system ferroelectric thin film device, including: a lower electrode film formation step of forming a lower electrode film on a substrate; a niobate-system ferroelectric thin film formation step of forming a niobate-system ferroelectric thin film on the lower electrode film; an etch mask formation step of forming a desired etch mask pattern on the niobate-system ferroelectric thin film; and a ferroelectric thin film etching step of forming a desired fine pattern of the niobate-system ferroelectric thin film by wet etching using an etchant including an aqueous alkaline solution of a chelating agent. | 03-05-2015 |
20150064805 | METHOD FOR FABRICATING MAGNETORESISTIVE RANDOM ACCESS MEMORY ELEMENT - A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer. | 03-05-2015 |
20150064806 | MAGNETIC TRAP FOR CYLINDRICAL DIAMAGNETIC MATERIALS - A system for self-aligning diamagnetic materials includes first and second magnets contacting each other along a contact line and having a diametric magnetization perpendicular to the contact line and a diamagnetic rod positioned to levitate above the contact line of the first and second magnets. | 03-05-2015 |
20150072439 | METHOD OF MANUFACTURING MAGNETORESISTIVE ELEMENT - According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the first non-magnetic layer, forming a second non-magnetic layer on the second magnetic layer, forming a third magnetic layer on the second non-magnetic layer, patterning the third magnetic layer by a RIE using an etching gas including a noble gas and a nitrogen gas until a surface of the second non-magnetic layer is exposed, and patterning the second non-magnetic layer and the second magnetic layer after patterning of the third magnetic layer. | 03-12-2015 |
20150072440 | METHOD OF MANUFACTURING MAGNETORESISTIVE ELEMENT - According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the non-magnetic layer, and patterning the second magnetic layer by a RIE using an etching gas including a noble gas and a hydrocarbon gas. | 03-12-2015 |
20150072441 | METHOD OF FABRICATING A FERROELECTRIC CAPACITOR - Ferroelectric capacitors used in ferroelectric random access memories (F-RAM) and methods for fabricating the same to reduce sidewall leakage are described. In one embodiment, the method includes depositing over a surface of a substrate, a ferro stack including a bottom electrode layer electrically coupled to a bottom electrode contact extending through the substrate, a top electrode layer and ferroelectric layer there between. A hard-mask is formed over the ferro stack, and a top electrode formed by etching through the top electrode layer and at least partially through the ferroelectric layer. A non-conductive barrier is formed on sidewalls formed by etching through the top electrode layer and at least partially through the ferroelectric layer, and then a bottom electrode is formed by etching the bottom electrode layer so that conductive residues generated by the etching are electrically isolated from the top electrode by the non-conductive barrier. | 03-12-2015 |
20150072442 | SPIN INJECTOR DEVICE COMPRISING A PROTECTION LAYER AT THE CENTRE THEREOF - A method for manufacturing a spin injector device, comprising the following steps of:
| 03-12-2015 |
20150072443 | Method of Etching Ferroelectric Capacitor Stack - A method of etching a ferroelectric capacitor stack structure including conductive upper and lower plates with a ferroelectric material, such as lead-zirconium-titanate (PZT), therebetween, with each of these layers defined by the same hard mask element. The stack etch process involves a plasma etch with a fluorine-bearing species as an active species in the etch of the conductive plates, and a non-fluorine-bearing chemistry for etching the PZT ferroelectric material. An example of the fluorine-bearing species is CF | 03-12-2015 |
20150079698 | Thermal Treatment for Reducing Transistor Performance Variation in Ferroelectric Memories - Thermal treatment of a semiconductor wafer in the fabrication of integrated circuits including MOS transistors and ferroelectric capacitors, including those using lead-zirconium-titanate (PZT) ferroelectric material, to reduce variation in the electrical characteristics of the transistors. Thermal treatment of the wafer in a nitrogen-bearing atmosphere in which hydrogen is essentially absent is performed after formation of the transistors and capacitor. An optional thermal treatment of the wafer in a hydrogen-bearing atmosphere prior to deposition of the ferroelectric treatment may be performed. | 03-19-2015 |
20150079699 | METHOD OF MANUFACTURING A MAGNETORESISTIVE DEVICE - A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask. | 03-19-2015 |
20150087080 | SPIN TRANSFER TORQUE CELL FOR MAGNETIC RANDOM ACCESS MEMORY - Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via. | 03-26-2015 |
20150093841 | PROCESS FOR PRODUCTION OF FUNCTIONAL DEVICE, PROCESS FOR PRODUCTION OF FERROELECTRIC MATERIAL LAYER, PROCESS FOR PRODUCTION OF FIELD EFFECT TRANSISTOR, THIN FILM TRANSISTOR, FIELD EFFECT TRANSISTOR, AND PIEZOELECTRIC INK JET HEAD - A method of producing a functional device according to the present invention includes, in this order: the functional solid material precursor layer formation step of applying a functional liquid material onto a base material to form a precursor layer of a functional solid material; the drying step of heating the precursor layer to a first temperature in a range from 80° C. to 250° C. to preliminarily decrease fluidity of the precursor layer; the imprinting step of imprinting the precursor layer that is heated to a second temperature in a range from 80° C. to 300° C. to form an imprinted structure on the precursor layer; and the functional solid material layer formation step of heat treating the precursor layer at a third temperature higher than the second temperature to transform the precursor layer into a functional solid material layer. | 04-02-2015 |
20150104882 | FABRICATION METHOD FOR HIGH-DENSITY MRAM USING THIN HARD MASK - Embodiments of the invention are described that use a thin metallic hard mask, which can be a bi-layer film, to increase the incident IBE angle for MTJ sidewall cleaning without losing the process margin for the subsequent interconnection process. The patterned metallic hard mask pads also serve as the top electrode for the MTJ cells. Using a thin metallic hard mask is possible when the hard mask material acts as a CMP stopper without substantial loss of thickness. In the first embodiment, the single layer hard mask is preferably ruthenium. In the second embodiment, the lower layer of the bi-layer hard mask is preferably ruthenium. The wafer is preferably rotated during the IBE process for uniform etching. A capping layer under the hard mask is preferably used as the etch stopper during hard mask etch process in order not to damage or etch through the upper magnetic layer. | 04-16-2015 |
20150104883 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A method of fabricating a semiconductor device includes providing a wafer in a chamber of a point-cusp magnetron physical vapor deposition (PCM-PVD) apparatus, the chamber including a metal target. The method further includes providing an inert gas and a reactive gas in the chamber and forming an amorphous conductive layer on the wafer by reacting the reactive gas with a metal atom separated from the metal target by the inert gas. | 04-16-2015 |
20150104884 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask. | 04-16-2015 |
20150111309 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas. | 04-23-2015 |
20150111310 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A lower electrode film, a ferroelectric film, and an upper electrode film are formed on an insulation film covering a transistor formed on a semiconductor substrate. Furthermore, a Pt film is formed as a cap layer on the upper electrode film. Then, a hard mask (a TiN film and an SiO | 04-23-2015 |
20150125966 | STT-MRAM CELL STRUCTURES - A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 05-07-2015 |
20150140685 | MANUFACTURING METHOD FOR PATTERN MULTILAYER BODY AND MASK SET - A method for manufacturing a pattern multilayer body that has a plurality of pattern layers, and where a pattern is formed in each pattern layer, includes a step of forming an overlay pattern within an overlay pattern formation region, and in the step of forming the overlay pattern, a photoresist film is formed, and after a photoresist film is exposed via a main mask, a resist pattern is formed by exposing a sub mask(s). The main mask has a pattern light-shielding part that is commonly used for forming a pattern in each pattern layer, and each main light-shielding part for forming each overlay patter; and a sub mask has an opening part that is exposable to an unexposed region(s) within an overlay pattern formation region other than an unexposed region(s) on the photoresist film, which has been light-shielded by the main light-shielding part for forming a corresponding overlay pattern. This enables forming an overlay pattern that is high in position gap measurement accuracy in a direction orthogonal to the lamination direction when manufacturing a pattern multilayer body. | 05-21-2015 |
20150140686 | FORMING MAGNETIC MICROELECTROMECHANICAL INDUCTIVE COMPONENTS - A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space. | 05-21-2015 |
20150140687 | FORMING MAGNETIC MICROELECTROMECHANICAL INDUCTIVE COMPONENTS - A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space. | 05-21-2015 |
20150147824 | SILICON PRECURSORS FOR LOW TEMPERATURE ALD OF SILICON-BASED THIN-FILMS - A silicon precursor composition is described, including a silylene compound selected from among: silylene compounds of the formula: wherein each of R and R | 05-28-2015 |
20150147825 | MRAM Device and Fabrication Method Thereof - According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack. | 05-28-2015 |
20150295170 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a magnetoresistive element formed on a semiconductor substrate, a first contact plug which extends through an interlayer dielectric film formed on the semiconductor substrate and immediately below the magnetoresistive element, has a bottom surface in contact with an upper surface of the semiconductor substrate, and is adjacent to the magnetoresistive element, and an insulating film formed between the magnetoresistive element and the first contact plug and on the interlayer dielectric film, wherein the insulating film includes a first region positioned on a side of the interlayer dielectric film, and a second region positioned in the insulating film and on an upper surface of the first region, the insulating film is made of SiN, and the first region is a nitrogen rich film compared to the second region. | 10-15-2015 |
20150303206 | Methods Of Forming Ferroelectric Capacitors - A method of forming a ferroelectric capacitor includes forming inner conductive capacitor electrode material over a substrate. After forming the inner electrode material, an outermost region of the inner electrode material is treated to increase carbon content in the outermost region from what it was prior to the treating. After the treating, ferroelectric capacitor dielectric material is formed over the treated outermost region of the inner electrode material. Outer conductive capacitor electrode material is formed over the ferroelectric capacitor dielectric material. | 10-22-2015 |
20150311432 | PROCESS FOR PRODUCING MAGNETORESISTIVE EFFECT ELEMENT - This invention provides a production process in which in a process for producing a magnetoresistive effect element, noble metal atoms in a re-deposited film adhered to a side wall after element isolation are efficiently removed to prevent short-circuiting due to the re-deposited film. | 10-29-2015 |
20150311433 | SEMICONDUCTOR DEVICE, MAGNETIC MEMORY DEVICE, AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming conductive pillars on a substrate, sequentially forming a sacrificial layer and a molding structure between the conductive pillars, forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars, removing the sacrificial layer to form an air gap, removing the molding structure to form an expanded air gap, and patterning the conductive layer to open the expanded air gap. | 10-29-2015 |
20150325517 | Structure And Method For A High-K Transformer With Capacitive Coupling - The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer. | 11-12-2015 |
20150325785 | MAGNETORESISTIVE ELEMENT AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element. | 11-12-2015 |
20150333254 | Reduction of Barrier Resistance X Area (RA) Product and Protection of Perpendicular Magnetic Anisotropy (PMA) for Magnetic Device Applications - A method of forming a MTJ with a tunnel barrier having a high tunneling magnetoresistance ratio, and low resistance x area value is disclosed. The method preserves perpendicular magnetic anisotropy in bottom and top magnetic layers that adjoin bottom and top surfaces of the tunnel barrier. A key feature is a passive oxidation step of a first Mg layer that is deposited on the bottom magnetic layer wherein a maximum oxygen pressure is 10 | 11-19-2015 |
20150349086 | VERTICAL BJT FOR HIGH DENSITY MEMORY - Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively. | 12-03-2015 |
20150349245 | PLASMA PROCESSING METHOD - In a plasma processing method for plasma-etching magnetic layer by using a plasma processing device including a processing chamber in which a sample is plasma-processed, a dielectric window to seal an upper part of the processing chamber hermetically, an inductive coupling antenna disposed above the dielectric window, a radio-frequency power source to supply radio-frequency electric power to the inductive coupling antenna and a Faraday shield disposed between the inductive coupling antenna and the dielectric window, a deposit layer is formed on the plasma-etched magnetic layer by plasma processing while applying radio-frequency voltage to the Faraday shield after the magnetic layer is plasma-etched. | 12-03-2015 |
20150349246 | METHOD FOR ETCHING MTJ USING CO PROCESS CHEMISTIRES - A method for fabricating a magnetic film structure is provided. The method comprises forming a magnetic structure on a bottom electrode layer, the magnetic structure comprising at least one pinned bottom magnetic film layer having a fixed magnetic orientation; at least one top magnetic film layer whose magnetic orientation can be manipulated by a current; and a tunneling layer between the bottom magnetic film layer and the top magnetic film layer; forming a metallic hard mask atop the magnetic structure; patterning and etching the metallic hard mask to define exposed areas of the magnetic structure; selectively etching the exposed areas of the magnetic structure by a chemical etch process based on a CO etch chemistry to form discrete magnetic bits. | 12-03-2015 |
20150355295 | XMR SENSORS WITH HIGH SHAPE ANISOTROPY - Embodiments relate to xMR sensors having very high shape anisotropy. Embodiments also relate to novel structuring processes of xMR stacks to achieve very high shape anisotropies without chemically affecting the performance relevant magnetic field sensitive layer system while also providing comparatively uniform structure widths over a wafer, down to about 100 nm in embodiments. Embodiments can also provide xMR stacks having side walls of the performance relevant free layer system that are smooth and/or of a defined lateral geometry which is important for achieving a homogeneous magnetic behavior over the wafer. | 12-10-2015 |
20150357526 | ELECTROPHOTOGRAPHIC DEPOSITION OF UNPACKAGED SEMICONDUCTOR DEVICE - Described herein are techniques related a precision deposition of unpackaged semiconductor devices (“dies”) onto a substrate. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 12-10-2015 |
20150357560 | REDUCING SWITCHING VARIATION IN MAGNETORESISTIVE DEVICES - The magnetic characteristics of a magnetoresistive device are improved by rendering magnetic debris non-magnetic during processing operations. Further improvement is realized by annealing the partially- or fully-formed device in the presence of a magnetic field in order to eliminate or stabilize magnetic micro-pinning sites or other magnetic abnormalities within the magnetoresistive stack for the device. Such improvement in magnetic characteristics decreases deviation in switching characteristics in arrays of such magnetoresistive devices such as those present in MRAMs. | 12-10-2015 |
20150372222 | ELECTROSTATICALLY CONTROLLED MAGNETIC LOGIC DEVICE - A magnetic logic cell includes a first electrode portion, a magnetic portion arranged on the first electrode, the magnetic portion including an anti-ferromagnetic material or a ferrimagnetic material, a dielectric portion arranged on the magnetic portion, and a second electrode portion arranged on the dielectric portion. | 12-24-2015 |
20150380639 | MEMORY CIRCUIT AND METHOD OF FORMING THE SAME USING REDUCED MASK STEPS - Disclosed is a memory circuit and method of forming the same. The memory circuit comprises a lower metallization layer defining first conducting lines. A continuous magnetic storage element stack is atop the lower metallization layer wherein a bottom electrode of the stack is in direct contact with the first conducting lines. An upper metallization layer is atop the continuous magnetic storage element stack, the upper metallization layer defining second conducting lines, which are in direct contact with said continuous magnetic storage element stack. Localized areas of the continuous magnetic storage element stack define discrete magnetic bits, each energizable through a selected pair of the first and second conducting lines. In a second aspect and a third aspect, the continuous magnetic storage element stack is respectively partially and fully etched through a single mask, to define the discrete magnetic bits. | 12-31-2015 |
20150380640 | Method of Manufacturing a Magnetoresistive-Based Device - A method of manufacturing a magnetoresistive-based device using a plurality of hard masks. The magnetoresistive-based device includes magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer. In one embodiment, the method may include removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively, and removing the tunnel barrier layer and the second magnetic materials layer unprotected by a second hard mask to form a tunnel barrier and second magnetic materials, and the second electrically conductive layer unprotected by the second hard mask to form, and a second electrode. | 12-31-2015 |
20160005646 | MAGNETIC TRAP FOR CYLINDRICAL DIAMAGNETIC MATERIALS - A method for self-aligning diamagnetic materials includes contacting first and second magnets together other along a contact line so as to generate a diametric magnetization that is perpendicular to the contact line. A diamagnetic rod is positioned with respect to the first and second magnets to levitate above the contact line of the first and second magnets. | 01-07-2016 |
20160005728 | Integrated System and Method of Making the Integrated System - A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads. | 01-07-2016 |
20160005957 | PROCESS FOR PRODUCING MAGNETORESISTIVE EFFECT ELEMENT AND DEVICE PRODUCING METHOD - A production process in which in an element isolation process for a magnetoresistive effect element, a re-deposited film adhered to a side wall of the element is efficiently removed by ion beam etching. Ion beam etching is performed while a substrate located being inclined relative to the grid is rotated. In the ion beam etching, an energy amount of an ion beam entering from a direction in which a pattern groove formed on the substrate extends is increased larger than the energy amount of the ion beam entering from another direction by controlling a rotation speed of the substrate, and the re-deposited film adhered to the side wall of the magnetoresistive effect element formed on the substrate is efficiently removed by etching. | 01-07-2016 |
20160005958 | METHOD FOR MANUFACTURING MAGNETORESISTIVE ELEMENT - Provided is a method for manufacturing a magnetoresistive element, including a step of forming a tunnel barrier layer, wherein the step of forming the tunnel barrier layer includes a deposition step of depositing a metal film on top of a substrate, and an oxidation step of subjecting the metal film to an oxidation process. The oxidation step includes holding the substrate having Mg formed thereon, on a substrate holder in a processing container in which the oxidation process is performed, supplying an oxygen gas to the substrate by introducing the oxygen gas into the processing container, at a temperature at which Mg does not sublime, and heating the substrate after the introduction of the oxygen gas. | 01-07-2016 |
20160013262 | FABRICATION OF MULTILAYER CIRCUIT ELEMENTS | 01-14-2016 |
20160020387 | HYBRIDIZED OXIDE CAPPING LAYER FOR PERPENDICULAR MAGNETIC ANISOTROPY - A method of forming a hybrid oxide capping layer (HOCL) is disclosed and used in a magnetic tunnel junction to enhance thermal stability and perpendicular magnetic anisotropy in an adjoining free layer. The HOCL has a lower interface oxide layer and one or more transition metal oxide layers wherein each of the metal layers selected to form a transition metal oxide has an absolute value of free energy of oxide formation less than that of the metal used to make the interface oxide layer. One or more of the HOCL layers is under oxidized. Oxygen from one or more transition metal oxide layers preferably migrates into the interface oxide layer during annealing to further oxidize the interface oxide. As a result, a less strenuous oxidation step is required to initially oxidize the lower HOCL layer and minimizes oxidative damage to the free layer. | 01-21-2016 |
20160027999 | METHOD FOR MANUFACTURING MTJ MEMORY DEVICE - A method for manufacturing MTJ pillars for a MTJ memory device. The method includes depositing multiple MTJ layers on a substrate, depositing a hard mask on the substrate and coating a photoresist on the hard mask. Further, alternating steps of reactive ion etching and ion beam etching are performed to isolate MTJ pillars and expose side surfaces of the MTJ layers. An insulating layer is the applied to protect the side surfaces of the MTJ layers. A second insulating layer is deposited before the device is planarized using chemical mechanical polishing. | 01-28-2016 |
20160028000 | MRAM Device and Fabrication Method Thereof - A method of forming and a magnetoresistive random access memory (MRAM) device. In an embodiment, the MRAM device includes a magnetic tunnel junction (MTJ) disposed over a bottom electrode, the magnetic tunnel junction having a first sidewall, a top electrode disposed over the magnetic tunnel junction, and a dielectric spacer supported by the magnetic tunnel junction and extending along sidewalls of the top electrode, the dielectric spacer having a second sidewall substantially co-planar with the first sidewall of the magnetic tunnel junction. | 01-28-2016 |
20160028001 | PACKAGING FOR AN ELECTRONIC DEVICE - In one aspect, a method includes processing a metal substrate, performing a first etch on a first surface of the metal substrate to form, for an integrated circuit package, secondary leads and a curved component having two primary leads and performing a second etch, on a second surface of the substrate opposite the first surface, at locations on the secondary leads and locations on the curved component to provide a locking mechanism. Each primary lead located at a respective end of the curved component. | 01-28-2016 |
20160035788 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Active patterns spaced apart from each other by an isolation layer are formed in a substrate. Gate structures extending in the isolation layer through the active patterns are formed. Each active pattern is divided into a central portion and a peripheral portion facing the central portion by the gate structures. A protrusion of at least one of active pattern is formed. The protrusion is exposed from a top surface of the isolation layer, and transformed into silicide such that a first silicide ohmic pad is formed at the central portion of the active pattern and a second silicide ohmic pad is formed at the peripheral portion of the active pattern. A conductive line structure electrically connected to the first silicide ohmic pad is formed. A conductive contact electrically connected to the second silicide ohmic pad is formed. A data storage unit electrically connected to the conductive contact is formed. | 02-04-2016 |
20160035958 | MANUFACTURING PROCESS OF THE THERMOELECTRIC CONVERSION ELEMENT - A manufacturing process of the thermoelectric conversion element is provided, wherein the system using semiconductor process technology to the construction of the thermoelectric conversion element nanoscale thermoelectric effect to increase, and the use of different type and surface state of the sample to increase the thermoelectric conversion element thermoelectric figure of merit. Through the use of a specific thickness of deposition of nanostructures on a nanoscale roughening of the substrate cannot affect the conductivity of thermoelectric materials under, and also can improve the Seebeck coefficient and lower thermal conductivity in order o significantly enhance the thermoelectric figure of merit. | 02-04-2016 |
20160035972 | ELECTRONIC DEVICE COMPRISING SEMICONDUCTOR MEMORY USING METAL ELECTRODE AND METAL COMPOUND LAYER SURROUNDING SIDEWALL OF THE METAL ELECTRODE - This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode. The metal compound layer includes a compound of the metal of the upper electrode. | 02-04-2016 |
20160043308 | SELF CONTACTING BIT LINE TO MRAM CELL - Embodiments of the invention disclose magnetic memory cell configurations in which a magnetic storage structure is coupled to an upper metal layer with minimal overlay margin. This greatly reduces a size of the memory cell. | 02-11-2016 |
20160043309 | MULTIBIT SELF-REFERENCE THERMALLY ASSISTED MRAM - A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier. | 02-11-2016 |
20160054398 | DIE-SIZED ATOMIC MAGNETOMETER AND METHOD OF FORMING THE MAGNETOMETER - The cost and size of an atomic magnetometer are reduced by attaching together a first die which integrates together a vapor cell, top and side photo detectors, and processing electronics, a second die which integrates together an optics package and a heater for the vapor cell, and a third die which integrates together a VCSEL, a heater for the VCSEL, and control electronics. | 02-25-2016 |
20160056368 | DOMAIN WALL INJECTOR DEVICE USING FRINGING FIELDS AIDED BY SPIN TRANSFER TORQUE - A domain wall injector device uses electrical current passed across an interface between two magnetic regions whose magnetizations are aligned non-collinearly to create a domain wall or a series of domain walls in one of the magnetic regions. The method relies on a combination of innate fringing fields from the magnetic regions and the spin-transfer torque derived from the charge current. The device may be used to store data that are subsequently read out. | 02-25-2016 |
20160056371 | SINGLE-CHIP BRIDGE-TYPE MAGNETIC FIELD SENSOR AND PREPARATION METHOD THEREOF - The present invention discloses a design and manufacturing method for a single-chip magnetic sensor bridge. The sensor bridge comprises four magnetoresistive elements. The magnetization of the pinned layer of each of the four magnetoresistive elements is set in the same direction, but the magnetization directions of the free layers of the magnetoresistive elements on adjacent arms of the bridge are set at different angles with respect to the pinned layer magnetization direction. The absolute values of the angles of the magnetization directions of the free layers of all four magnetoresistive elements are the same with respect with their pinning layers. The disclosed magnetic biasing scheme enables the integration of a push-pull Wheatstone bridge magnetic field sensor on a single chip with better performance, lower cost, and easier manufacturability than conventional magnetoresistive sensor designs. | 02-25-2016 |
20160056372 | INTEGRATED CIRCUIT SHIELDING TECHNIQUE UTILIZING STACKED DIE TECHNOLOGY INCORPORATING TOP AND BOTTOM NICKEL-IRON ALLOY SHIELDS HAVING A LOW COEFFICIENT OF THERMAL EXPANSION - An integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion of especial utility in conjunction with magnetoresistive random access memory (MRAM) and other devices requiring magnetic shielding. | 02-25-2016 |
20160061525 | MAGNETIC ANNEALING APPARATUS AND MAGNETIC ANNEALING METHOD - Disclosed is a magnetic annealing apparatus including a processing container that performs a magnetic annealing processing on a plurality of substrates accommodated therein in a magnetic field; a substrate holder that holds the plurality of substrates substantially horizontally in the processing container; a division heater including a plurality of sub-division heaters and covering a substantially entire circumferential surface of an outer periphery of a predetermined region of the processing container along a longitudinal direction; a magnet installed to cover an outside of the division heater; and a controller configured to feedback-control a temperature of a predetermined control target heater among the plurality of sub-division heaters, and to control temperatures of the plurality of sub-division heaters other than the predetermined control target heater based on a control output obtained by multiplying a control output of the predetermined control target heater and a predetermined ratio. | 03-03-2016 |
20160071776 | MANUFACTURING METHOD OF MAGNETIC MEMORY DEVICE - According to one embodiment, a manufacturing method of a magnetic memory device, includes obtaining first and second magnetic fields for each of magnetoresistive effect elements, defining a group of the elements, for the first and second magnetic fields of the elements in the group, a highest first magnetic field being lower than a lowest second magnetic field, and a difference between the highest first magnetic field and the lowest second magnetic field being greater than a predetermined difference, determining a maximum applied magnetic field higher than the highest first magnetic field and lower than the lowest second magnetic field, and obtaining magnetic characteristics for each of the elements in the group by applying a magnetic field decreasing from the maximum applied magnetic field after the magnetic field is increased up to the maximum applied magnetic field. | 03-10-2016 |
20160072055 | MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a manufacturing method of a semiconductor memory device includes the following steps. The method includes forming a first magnetic layer, a second magnetic layer, and an insulating layer therebetween, forming a mask layer on the second magnetic layer, etching the second magnetic layer, the insulating layer, and the first magnetic layer using the mask layer as a mask and forming a magnetic tunnel junction (MTJ) element, and performing oxidation a sidewall of the MTJ element with H | 03-10-2016 |
20160072057 | INTEGRATED MAGNETORESISTIVE SENSOR, IN PARTICULAR THREE-AXIS MAGNETORESISTIVE SENSOR AND MANUFACTURING METHOD THEREOF - An integrated magnetoresistive device includes a substrate of semiconductor material that is covered, on a first surface, by an insulating layer. A magnetoresistor of ferromagnetic material extends within the insulating layer and defines a sensitivity plane of the sensor. A concentrator of ferromagnetic material includes at least one arm that extends in a transversal direction to the sensitivity plane and is vertically offset from the magnetoresistor. The concentrator concentrates deflects magnetic flux lines perpendicular to the sensitivity plane so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane. | 03-10-2016 |
20160079165 | PREPARATION METHOD OF THREE-DIMENSIONAL INTEGRATED INDUCTOR-CAPACITOR STRUCTURE - The invention relates to a field of semiconductor manufacturing Technology, more particularly, to a method for preparing three-dimensional integrated inductor-capacitor structure, which can realize the inductor-capacitor of three-dimensional structure, and form three-dimensional spiral inductor centering on the magnetic cores of single direction around through the preparation of the interconnected top metal conducting wires and bottom metal conducting wires, which can gain capacitance and inductance at the same time in a relatively small space, and reduce the production costs, and also greatly improves the inductance magnetic flux in order to increase the inductance value and reduce eddy current, and improve the quality factor Q value and the performance of inductance coil. | 03-17-2016 |
20160079341 | INDUCTOR STRUCTURE WITH MAGNETIC MATERIAL AND METHOD FOR FORMING THE SAME - The methods for forming an inductor structure are provided. The method includes forming an oxide layer over a substrate, and the layer includes an opening. The method includes forming a magnetic material over the oxide layer and in the opening and forming a patterned photoresist layer over the magnetic material, wherein the patterned photoresist layer overlaps the opening. The method further includes performing an etching process on the magnetic material using the patterned photoresist as a mask. | 03-17-2016 |
20160079521 | DIELECTRIC REPAIR FOR EMERGING MEMORY DEVICES - Systems and method include providing a non-volatile random access memory (NVRAM) stack including a plurality of layers. The plurality of layers includes a dielectric layer and a metal layer. The metal layer of the NVRAM stack is patterned. The patterning causes damage to lateral side portions of the dielectric layer. The lateral portions of the dielectric layer are repaired by depositing dielectric material on the lateral side portions of the dielectric layer. | 03-17-2016 |
20160087195 | ETCHING APPARATUS AND ETCHING METHOD - According to one embodiment, an etching apparatus includes an etching chamber, a stage in the etching chamber, a plasma generator in the etching chamber, the plasma generator being opposite to the stage and irradiating an ion beam toward the stage, a supporter supporting the stage, the supporter having a rotational axis in a direction in which the ion beam is irradiated, a first driver changing a beam angle between a direction which is perpendicular to an upper surface of the stage and the direction in which the ion beam is irradiated, and a second driver which rotates the stage on the rotational axis. | 03-24-2016 |
20160099408 | MANUFACTURING METHOD FOR INSULATING FILM AND MANUFACTURING APPARATUS FOR THE SAME - According to one embodiment, a method of manufacturing an insulating film, includes forming an insulating film on a substrate by sputtering, measuring a thickness of the insulating film at a plurality of locations, and irradiating a surface portion of the insulating film with X rays or ions, based on the measured thickness. | 04-07-2016 |
20160104835 | PROCESS INTEGRATION OF A SINGLE CHIP THREE AXIS MAGNETIC FIELD SENSOR - A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane. | 04-14-2016 |
20160111635 | DURABLE MINIATURE GAS COMPOSITION DETECTOR HAVING FAST RESPONSE TIME - A miniature oxygen sensor makes use of paramagnetic properties of oxygen gas to provide a fast response time, low power consumption, improved accuracy and sensitivity, and superior durability. The miniature oxygen sensor disclosed maintains a sample of ambient air within a micro-channel formed in a semiconductor substrate. O | 04-21-2016 |
20160118578 | MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a magnetic memory device includes forming a lower magnetic layer, a tunnel barrier layer, and an upper magnetic layer on a substrate, forming a magnetic tunnel junction (MTJ) pattern by patterning the lower magnetic layer, the tunnel barrier layer, and the upper magnetic layer, and irradiating a side wall of the MTJ pattern using a beam including an oxygen ion, wherein, in the forming of the MTJ pattern, a metal redeposition material covering the side wall of the MTJ pattern is formed and the beam is radiated to the metal redeposition material. | 04-28-2016 |
20160126454 | ISOLATION OF MAGNETIC LAYERS DURING ETCH IN A MAGNETORESISTIVE DEVICE - Methods for manufacturing magnetoresistive devices are presented in which isolation of magnetic layers in the magnetoresistive stack is achieved by oxidizing exposed sidewalls of the magnetic layers prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls. | 05-05-2016 |
20160133618 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric. The integrated circuit is below a passivation, which is over a metal structure. The metal structure includes a metal pad and an under bumper metallurgy, which is over and aligned with the metal pad. The metal pad is electrically connected to the integrated circuit, and the under bumper metallurgy is configured to electrically connect to a conductive component of another semiconductor device. The integrated circuit further includes a conductive trace, which is below and aligned with the metal structure. The conductive trace is connected to a power source such that an electromagnetic field is generated at the conductive trace when an electric current from the power source passes through the conductive trace. | 05-12-2016 |
20160133832 | METHOD OF MANUFACTURING MAGNETORESISTIVE ELEMENT(S) - A planar STT-MRAM includes apparatus, made by a method of operating and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a ferromagnetic recording layer forming a flux closure with a self-aligned ferromagnetic soft adjacent layer which has an electric field enhanced perpendicular anisotropy through an interface interaction with a dielectric functional layer. The energy switch barrier of the soft adjacent layer is reduced under an electric field along a perpendicular direction with a proper voltage on a digital line from a control circuitry; accordingly, the in-plane magnetization of the recording layer is readily reversible in a low spin-transfer switching current. | 05-12-2016 |
20160133833 | REPLACEMENT CONDUCTIVE HARD MASK FOR MULTI-STEP MAGNETIC TUNNEL JUNCTION (MTJ) ETCH - A multi-step etch technique for fabricating a magnetic tunnel junction (MTJ) apparatus includes forming a first conductive hard mask on a first electrode of the MTJ apparatus for etching the first electrode during a first etching step. The method also includes forming a second conductive hard mask on the first conductive hard mask for etching magnetic layers of the MTJ apparatus during a second etching step. A spacer layer is conformally deposited on sidewalls of the first conductive hard mask. The second conductive hard mask is deposited on the first conductive hard mask and aligned with the spacer layer on the sidewalls of the first conductive hard mask. | 05-12-2016 |
20160133834 | PLASMA ETCHING METHOD - In a plasma etching method of plasma-etching a sample which has a first magnetic film, a second magnetic film disposed above the first magnetic film, a metal oxide film disposed between the first magnetic film and the second magnetic film, a second metal film disposed over the second magnetic film and forming an upper electrode, and a first metal film disposed below the first magnetic film and forming a lower electrode, the plasma etching method includes the steps of: a first process for etching the first magnetic film, the metal oxide film, and the second magnetic film by using carbon monoxide gas; and a second process for etching the sample by using mixed gas of hydrogen gas and inactive gas after the first process. In this case, the first metal film is a film containing therein tantalum. | 05-12-2016 |
20160141496 | METHOD AND PROCESSING APPARATUS FOR FABRICATING A MAGNETIC RESISTIVE RANDOM ACCESS MEMORY DEVICE - Methods of fabricating MRAM devices are provided along with a processing apparatus for fabricating the MRAM devices. The methods may include forming a ferromagnetic layer, cooling the ferromagnetic layer to a temperature within a range of between about 50° K to about 300° K, forming and oxidizing one or more Mg layers on the cooled ferromagnetic layer to form an MgO structure, forming a free layer on the MgO structure, and forming a capping layer on the free layer. | 05-19-2016 |
20160149122 | Methods For Fabricating Magnetic Devices And Associated Systems And Devices - A method for exposing a photoresist material to light includes the following steps: (1) optically coupling the light to an optical mask via a prism and a first liquid layer joining the prism and the optical mask, (2) masking the light using the optical mask, and (3) optically coupling the masked light to the photoresist material. The method is used, for example, to fabricate a magnetic device on a semiconductor substrate. A hybrid semiconductor and magnetic device includes a semiconductor substrate and a top insulating structure deposited on an outer surface of the semiconductor substrate. The top insulating structure has opposing first and second sloping sidewalls, where each sloping sidewall forms an acute angle of at least 30 degrees, relative to an axis normal to the outer surface of the semiconductor substrate. The hybrid semiconductor and magnetic device further includes a magnetic core surrounding the top insulating structure. | 05-26-2016 |
20160149123 | METHOD OF FORMING A PATTERN USING ION BEAMS OF BILATERAL SYMMETRY, A METHOD OF FORMING A MAGNETIC MEMORY DEVICE USING THE SAME, AND AN ION BEAM APPARATUS GENERATING ION BEAMS OF BILATERAL SYMMETRY - A pattern-forming method includes providing a first ion beam at a first incidence angle and a second ion beam at a second incidence angle to a surface of an etch target layer formed on a substrate. Patterns are formed by patterning the etch target layer using the first and second ion beams. The first ion beam and the second ion beam are substantially symmetrical to each other with respect to a normal line that is perpendicular to a top surface of the substrate. Each of the first and second incidence angles is greater than 0 degrees and smaller than an angle obtained by subtracting a predetermined angle from 90 degrees. | 05-26-2016 |
20160149124 | MRAM HAVING SPIN HALL EFFECT WRITING AND METHOD OF MAKING THE SAME - Present invention includes an apparatus of and method of making a spin-transfer-torque magnetoresistive memory with three terminal magnetoresistive memory element(s) having highly conductive bottom electrodes overlaid on top of a SHE-metal layer in the regions outside of an MTJ stack. The memory cell has a bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two highly conductive bottom electrodes overlaid and electrically contacting on top of a SHE-metal layer in the outside of an MTJ region and to supply a bi-directional spin Hall effect recording current, and accordingly to switch the magnetization of the recording layer. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current along the SHE-metal layer by applying a low write current. | 05-26-2016 |
20160163821 | SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR AND METHOD FOR THE FORMATION THEREOF - A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region. | 06-09-2016 |
20160163970 | METHOD FOR MAKINGA MAGNETIC RANDOM ACCESS MEMORY ELEMENT WITH SMALL DIMENSION AND HIGH QULITY - This invention is about a method to make an MRAM element with small dimension, by building an MTJ as close as possible to an associated via connecting an associated circuitry in a semiconductor wafer. The invention provides a process scheme to flatten the interface of bottom electrode during film deposition, which ensures a good deposition of atomically smooth MTJ multilayer as close as possible to an associated via which otherwise might be atomically rough. The flattening scheme is first to deposit a thin amorphous conducting layer in the middle of BE deposition and immediately to bombard the amorphous layer by low energy ions to provide kinetic energy for surface atom diffusion to move from high point to low kinks. With such surface flattening scheme, not only the MRAM element can be made extremely small, but its device performance and magnetic stability can also be greatly improved. | 06-09-2016 |
20160163971 | METHOD OF MANUFACTURING A MAGNETIC MEMORY DEVICE - A method of manufacturing a magnetic memory device may include forming a lower magnetic layer, a tunnel barrier layer, and an upper magnetic layer on a substrate, forming a magnetic tunnel junction pattern by etching a stacked structure including the lower magnetic layer, the tunnel barrier layer, and the upper magnetic layer, forming a boron-absorption layer covering the magnetic tunnel junction pattern, and performing a heat treatment process so that boron included in the upper and lower magnetic layers may be absorbed by the boron-absorption layer. The heat treatment process may be undertaken in a gaseous atmosphere including at least one of hydrogen, oxygen, and nitrogen. | 06-09-2016 |
20160163973 | METHOD FOR MANUFACTURING MTJ MEMORY DEVICE - A method for manufacturing MTJ pillars for a MTJ memory device. The method includes depositing multiple MTJ layers on a substrate, depositing a hard mask on the substrate and coating a photoresist on the hard mask. Further, alternating steps of reactive ion etching and ion beam etching are performed to isolate MTJ pillars and expose side surfaces of the MTJ layers. An insulating layer is the applied to protect the side surfaces of the MTJ layers. A second insulating layer is deposited before the device is planarized using chemical mechanical polishing. | 06-09-2016 |
20160163974 | ELECTRIC FIELD ASSISTED PERPENDICULAR STT-MRAM - Present invention discloses a perpendicular STT-MRAM, a method of operating, and a method of manufacturing the same and a plurality of magnetoresistive memory elements having a recording layer which has an interface interaction with an underneath dielectric functional layer. The energy switch barrier of the recording layer is reduced under an electric field applying along a perpendicular direction of the functional with a proper voltage on a digital line from a control circuitry; accordingly, the perpendicular magnetization of the recording layer is readily reversible in a low spin-transfer switching current. | 06-09-2016 |
20160172085 | NANOCOMPOSITE MAGNETIC MATERIALS FOR MAGNETIC DEVICES AND SYSTEMS | 06-16-2016 |
20160172585 | AN IMPROVED METHOD TO MAKE OF FABRICATING IC/MRAM USING OXYGEN ION IMPLANTATION | 06-16-2016 |
20160181509 | METHODS OF MANUFACTURING MAGNETIC MEMORY DEVICE | 06-23-2016 |
20160181510 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | 06-23-2016 |
20160190436 | DOUBLE SYNTHETIC ANTIFERROMAGNET USING RARE EARTH METALS AND TRANSITION METALS - A mechanism relates to magnetic random access memory (MRAM). A free magnetic layer is provided and first fixed layers are disposed above the free magnetic layer. Second fixed layers are disposed below the free magnetic layer. The first fixed layers and the second fixed layers both comprise a rare earth element. | 06-30-2016 |
20160190437 | IN-SITU ANNEALING TO IMPROVE THE TUNNELING MAGNETO-RESISTANCE OF MAGNETIC TUNNEL JUNCTIONS - Embodiments are directed to a magnetic tunnel junction (MTJ) memory cell that includes a reference layer formed from a perpendicular magnetic anisotropy (PMA) reference layer and an interfacial reference layer. The MTJ further includes a free layer and a tunnel barrier positioned between the interfacial reference layer and the free layer. The tunnel barrier is configured to enable electrons to tunnel through the tunnel barrier between the interfacial reference layer and the free layer. A first in-situ alignment is provided between a tunnel barrier lattice structure of the tunnel barrier and an interfacial reference layer lattice structure of the interfacial reference layer. A second in-situ alignment is provided between the tunnel barrier lattice structure of the tunnel barrier and a free layer lattice structure of the free layer. The PMA reference layer lattice structure is not aligned with the interfacial reference layer lattice structure. | 06-30-2016 |
20160194761 | SELECTIVE DEPOSITION AND CO-DEPOSITION PROCESSES FOR FERROMAGNETIC THIN FILMS | 07-07-2016 |
20160197066 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 07-07-2016 |
20160197270 | METHOD AND SYSTEM FOR REMOVING BORON FROM MAGNETIC JUNCTIONS USABLE IN SPIN TRANSFER TORQUE MEMORY APPLICATIONS | 07-07-2016 |
20160204342 | METHOD OF MANUFACTURING MAGNETORESISTIVE ELEMENT AND MANUFACTURING SYSTEM FOR THE SAME | 07-14-2016 |
20160254444 | MAGNETIC MEMORY WITH HIGH THERMAL BUDGET | 09-01-2016 |
20160254445 | MAGNETIC MEMORY WITH HIGH THERMAL BUDGET | 09-01-2016 |
20160254446 | SUB-LITHOGRAPHIC PATTERNING OF MAGNETIC TUNNELING JUNCTION DEVICES | 09-01-2016 |
20160380188 | PERPENDICULAR MAGNETIC ANISOTROPY FREE LAYERS WITH IRON INSERTION AND OXIDE INTERFACES FOR SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY - A method of making a spin-torque transfer magnetic random access memory device (STT MRAM) device includes forming a tunnel barrier layer on a reference layer; forming a free layer on the tunnel barrier layer, the free layer comprising a cobalt iron boron (CoFeB) alloy layer and an iron (Fe) layer; and performing a sputtering process to form a metal oxide layer on the Fe layer. | 12-29-2016 |
20170236999 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE | 08-17-2017 |
20190148126 | PVDF-TrFE Co-Polymer Having Improved Ferroelectric Properties, Methods of Making a PVDF-TrFE Co-Polymer Having Improved Ferroelectric Properties and Methods of Changing the End Group of a PVDF-TrFE Co-Polymer | 05-16-2019 |
20190148632 | METHOD OF MANUFACTURING A VARIABLE RESISTANCE MEMORY DEVICE | 05-16-2019 |
20190148634 | RUTHENIUM REMOVAL COMPOSITION AND METHOD OF PRODUCING MAGNETORESISTIVE RANDOM ACCESS MEMORY | 05-16-2019 |