Entries |
Document | Title | Date |
20080198682 | SEMICONDUCTOR DEVICE AND METHOD FOR SELECTION AND DE-SELECTION OF MEMORY DEVICES INTERCONNECTED IN SERIES - A system includes a plurality of memory devices connected in-series that communicate with a memory controller. When a memory device receives a command strobe signal indicating the start of a command having an ID number, the memory device is placed in a de-selected state and the ID number is compared to the memory device's device address. Delayed versions of the command strobe signal and the command are forwarded while the memory device is in the de-selected state. If the ID number matches the device address with reference to the ID number, the memory device is placed in a selected state. In the selected state, the memory device may refrain from forwarding the delayed versions of the command strobe signal and the command, such that if there is a match, a truncated part of the command is forwarded before the memory device is placed in the selected state. | 08-21-2008 |
20080198683 | Semiconductor memory apparatus - A semiconductor memory that includes a row decoder part, a first cell array placed on either side of the row decoder part, a second cell array placed on the other side of the row decoder part, and a wiring layer that short-circuits word lines corresponding to a specified row address on the first cell array with word lines corresponding to a specified row address on the second cell array. | 08-21-2008 |
20080205186 | Semiconductor memory device and method for driving the same - A semiconductor memory device includes a pulse signal generator configured to combine a plurality of external command signals to generate a normal register control signal and an extended register control signal in response to a clock signal; a reset signal generator configured to receive operating information of a delay locked loop (DLL) circuit from an outside to generate a reset signal for a reset operation of the DLL circuit in response to the normal register control signal or the extended register control signal; and the DLL circuit configured to perform a reset operation in response to the reset signal | 08-28-2008 |
20080212393 | Semiconductor memory device - A semiconductor memory device can effectively select a word line. The semiconductor memory device includes a word line driver unit for including N unit driving circuits for driving N word lines of a cell block, the N unit driving circuits being divided into M group driving circuits; a common address latch unit for latching a first address for selecting one of the M group driving circuits of the word line driver unit, and outputting the latched first address to the word line driver unit; and an address latch unit for latching a second address for selecting a unit driving circuit of the selected group driving circuit in the word line driver unit, and outputting a latched second address to the word line driver unit. | 09-04-2008 |
20080212394 | WRITE DRIVING CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A write driving circuit includes a plurality of driving units that write data corresponding to detection signals on memory banks, and at least one detecting unit that detects data input from the outside, and outputs the detection signals to two or more driving units among the plurality of driving units. | 09-04-2008 |
20080212395 | Driver, and a semiconductor, memory device having the same - A driver may include a driving unit and/or a boosting unit. The driving unit may be configured to provide a driving signal to at least one load. The boosting unit may be configured to boost the driving signal based on transition time points of the driving signal to reduce a distortion of the driving signal. The transition time points may be time points during a transition of the driving signal from a first level to a second level. | 09-04-2008 |
20080212396 | Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays - A memory system, e.g., a domino static random access memory (SRAM), includes a plurality of memory cells and a wordline decoder coupled to the memory cells through wordlines. The wordline decoder provides a wordline signal to one or more memory cells over the wordlines to allow access to the memory cell(s) for a read operation or a write operation. Read_w | 09-04-2008 |
20080225624 | High speed array pipeline architecture - A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline. | 09-18-2008 |
20080225625 | Page mode access for non-volatile memory arrays - An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh. | 09-18-2008 |
20080225626 | CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE - Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal. | 09-18-2008 |
20080225627 | APPARATUS FOR MEMORY DEVICE WORDLINE - A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a main wordline signal and a plurality of wordlines selectively coupled to the main wordline. Each of the wordlines is selectively coupled to a lower resistivity shared interconnection line by way of a selected one of a plurality of switching elements each commonly coupled on one end to the shared interconnection line and individually coupled on an opposing end to the plurality of wordlines. Each of the plurality of switching elements is selectively activated to couple one of the plurality of wordlines to the shared interconnection line when the main wordline signal is selectively coupled to one of the plurality of wordlines. | 09-18-2008 |
20080225628 | Semiconductor memory device for driving a word line - A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable signal for controlling a driving of a sub word line and a main word line driving enable signal for controlling a driving of a main word line are controlled by the block information signal that contains only mat information but does not contain the redundancy information. Accordingly, the word line control signal may be activated earlier than the sub word line driving enable signal and the main word line driving enable signal, thereby advancing the enable timing of the word line. | 09-18-2008 |
20080239863 | MEMORY CIRCUIT ARRANGEMENT AND METHOD FOR THE PRODUCTION THEREOF - In a memory circuit arrangement and fabrication method, the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line. | 10-02-2008 |
20080253217 | Method for accessing a memory cell in an integrated circuit, method of determining a set of word line voltage identifiers in an integrated circuit, method for classifying memory cells in an integrated circuit, method for determining a word line voltage for accessing a memory cell in an integrated circuit and integrated circuits - Embodiments of the invention relate to a method for accessing a memory cell in an integrated circuit, a method of determining a set of word line voltage identifiers in an integrated circuit, a method for classifying memory cells in an integrated circuit, a method for determining a word line voltage for accessing a memory cell in an integrated circuit and integrated circuits. In an embodiment, a method of accessing a memory cell in an integrated circuit, wherein the integrated circuit has a memory cell field including a plurality of memory cells. The method includes selecting a word line voltage identifier from a pre-stored set of word line voltage identifiers, each one of the pre-stored set of word line voltage identifiers being assigned to at least one of the memory cells in the memory cell field and accessing the memory cell using a word line voltage being dependent on the selected word line voltage identifier. | 10-16-2008 |
20080253218 | Column decoder and semiconductor memory apparatus using the same - A column decoder according includes: a plurality of main decoding units coupled to different memory banks that decode a pre-decoding signal and output column selection signals to the corresponding memory banks; and one or more pre-decoders, having a lesser number than the main decoders, which generates and outputs the pre-decoding signal by decoding the column address and the bank information signal. | 10-16-2008 |
20080253219 | ACTIVE DRIVER CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - An active driver control circuit for a semiconductor memory apparatus includes an asynchronous decoding unit that can be activated in response to a bank selection signal, when an external command is a read or write command, can generate an enabled read/write enable signal, and when a precharge signal is enabled, disable the enabled read/write enable signal, a synchronous decoding unit that can be activated in response to the bank selection signal, can generate an enabled active enable signal when the external command is an active command, when the external command is a precharge command, can generate the precharge signal, and output the active enable signal and the precharge signal in synchronization with a clock, and an active driver control signal generating unit that can generate an active driver control signal in response to the active enable signal and the read/write enable signal. | 10-16-2008 |
20080279032 | Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control - An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal. | 11-13-2008 |
20080279033 | Semiconductor integrated circuit device - A semiconductor integrated circuit device provided with a memory circuit having a word line selection circuit with reduced leakage current is provided. The memory circuit includes: second word lines with which memory cells are connected; multiple bit lines that are extended in a direction orthogonal thereto and electrically connected with memory cells corresponding to selected second word lines of a plurality of the second word lines; and word drivers, constructed of CMOS inverter circuits, that select or deselect the second word lines. The sources of p-channel MOSFETs that constitute a plurality of word drivers including second word lines corresponding to selected bit lines are supplied with a voltage at a level at which second word lines are selected. The sources of the p-channel MOSFETs of the other word drivers are supplied with a voltage corresponding to a level at which second word lines are deselected. | 11-13-2008 |
20080298158 | TWO TRANSISTOR WORDLINE DECODER OUTPUT DRIVER - A wordline decoder scheme for a memory device is generally described. In one example, a memory device includes a distributed logical NOR gate to decode addressing signals to generate wordline selection signals within a block of memory wherein the distributed logical NOR gate comprises a wordline decoder output driver, the wordline decoder output driver comprising two transistors coupled with a wordline signal. | 12-04-2008 |
20080310246 | PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS - A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches. | 12-18-2008 |
20080316852 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises an array of memory cells each including an antifuse to store information based on a variation in resistance in accordance with destruction of the insulator in the antifuse. The antifuse includes a semiconductor substrate, a first conduction layer formed in the surface of the semiconductor substrate, a first electrode provided on the first conduction layer to be given a first voltage, a second conduction layer provided on the semiconductor substrate with the insulator interposed therebetween, and a second electrode provided on the second conduction layer to be given a second voltage different from the first voltage. The first electrode or the second electrode is formed of a metal silicide. | 12-25-2008 |
20090003120 | POWER-SAVING SEMICONDUCTOR MEMORY - A semiconductor memory, such as an SRAM, is described that accommodates smaller read/write accesses in one mode of operation and larger read/write accesses in a second mode of operation, wherein power is conserved during the smaller accesses. Methods of using such a semiconductor memory are also described. | 01-01-2009 |
20090010090 | BUCKET BRIGADE ADDRESS DECODING ARCHITECTURE FOR CLASSICAL AND QUANTUM RANDOM ACCESS MEMORIES - In an address signal decoder for a RAM memory, address signals are decoded in a “bucket brigade” address decoding architecture in which the address signals or bits are sequentially sent along the same address decoding path. The inventive architecture comprises a set of node switches linked into a binary tree. The address signals enter at the root node of the binary tree. As each address signal reaches a node switch at the end the path, it sets the path direction for that switch node so that subsequent address signals that follow the path will use that path direction. The decoder can be used with classical or quantum RAM memories. | 01-08-2009 |
20090016144 | SEMICONDUCTOR MEMORY DEVICE - In a memory cell having a first and a second load transistor, a first and a second drive transistor, and a first and a second access transistor, a third access transistor provided between a first bit line and a first memory node and having a gate terminal connected to a first column line and a fourth access transistor provided between a second bit line and a second memory node and having a gate terminal connected to a second column line, are additionally provided. | 01-15-2009 |
20090022006 | INTEGRATED LOGIC CIRCUIT AND METHOD FOR PRODUCING AN INTEGRATED LOGIC CIRCUIT - An integrated logic circuit comprises a memory area, wherein the memory area comprises a plurality of groups of memory cells, each group of memory cells assigned an address. The memory area further comprises an address decoder having a plurality of address inputs for receiving an address and for selecting a group of memory cells to which the received address is assigned and a plurality of data outputs for outputting information stored in a group of memory cells which is selected by the address decoder. The integrated logic circuit further comprises a coupling device which couples at least one portion of the data outputs of the memory area to at least one portion of the address inputs of the address decoder. | 01-22-2009 |
20090052270 | METHOD OF FLEXIBLE MEMORY SEGMENT ASSIGNMENT USING A SINGLE CHIP SELECT - Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a multi-bit device ID, which corresponds to a memory segment to which that device is mapped, is loaded for each memory device. Higher order address bits are then compared to the device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID. | 02-26-2009 |
20090059712 | OUTPUT DRIVER - An output driver is applicable to two or more interface standards. The output driver includes a pre-driver configured to generate pull-up control signals and pull-down control signals according to a logic value of data to be output and a target resistance, and adjust slew rates of the pull-up control signals and the pull-down control signals according to operation modes, and a driver configured to output the data in response to the pull-up and pull-down control signals. | 03-05-2009 |
20090067277 | Memory device command decoding system and memory device and processor-based system using same - Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode. | 03-12-2009 |
20090067278 | DATA OUTPUT CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver units being two or more times as much as the number of driver units in the first driver. A voltage level on the output node is the voltage level of an output signal. | 03-12-2009 |
20090080281 | NEGATIVE VOLTAGE DETECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A negative voltage detection circuit including first and second MOS transistor circuits configured to change a dimension size of a transistor based on a control signal, a first comparator circuit, a gate electrode of the second MOS transistor circuit commonly coupled to the gate electrode of the first MOS transistor circuit forming a current mirror circuit, a resistive divider supplied with a negative voltage to be detected, and coupled to the end of the current path of the second MOS transistor circuit to generate a second voltage, a second voltage comparator circuit to compare the second voltage with a reference voltage and to generate a detection signal corresponding to the value of the negative voltage, and a detection circuit for detecting a temperature or power supply voltage, generate the control signal corresponding to the detection result, and supply the control signal to the first and second MOS transistor circuits. | 03-26-2009 |
20090086562 | DEVICES, SYSTEMS, AND METHODS FOR INDEPENDENT OUTPUT DRIVE STRENGTHS - Methods, apparatuses and systems are disclosed for independently configurable data and strobe drivers within a memory device. A memory device may include at least one data driver, at least one strobe driver, and an extended mode register operably coupled to the at least one data driver and the at least one strobe driver. The extended mode register may be configured to independently set drive strengths for the at least one data driver and the at least one strobe driver. In another embodiment, a memory device may include one extended mode register configured to set drive strengths for the at least one data driver and another extended mode register configured to set drive strengths for the at least one strobe driver. | 04-02-2009 |
20090086563 | Memory Word Line Driver Featuring Reduced Power Consumption - Embodiments of a random access memory word line driver circuit that reduces consumption of standby power are described. The word line driver is based on NOR-gate logic in which, for memory array consisting of a plurality of memory cells and word line drivers, given two inputs selected one word line goes high and the rest remain zero. The decoder circuit comprises two PMOS transistors in series with an NMOS-based inverter circuit. This arrangement reduces the leakage current through the NMOS transistor when the word line is not selected. An array of word line drivers incorporating a NOR-based decoder includes a shared pull up PMOS transistor for one of two address lines. The shared pull-up PMOS transistor is manufactured to a size on the order of at least two times the width of the remaining transistors of each word line stage. | 04-02-2009 |
20090092000 | SEMICONDUCTOR MEMORY DEVICE WITH REDUCED CURRENT CONSUMPTION - A semiconductor memory device includes memory blocks, a main word decoder to set a main word line to a first potential for activation, a second potential, or a third potential, a circuit to generate a cyclic signal that indicates timing at intervals, a block selecting circuit to select a memory block to be accessed, a successive-selection circuit to select the memory blocks one after another, and a circuit configured to control the main word decoder such that unselected ones of the main word lines of a memory block selected by the block selecting circuit are set to the third potential, such that the main word lines of the selected memory block are maintained at the third potential after access, and such that the main word lines of a memory block selected by the successive-selection circuit are set to the second potential at the timing indicated by the cyclic signal. | 04-09-2009 |
20090097349 | Row active time control circuit and a semiconductor memory device having the same - A row active time control circuit is described that includes a master signal generating circuit and a row active control signal generating circuit. The master signal generating circuit generates one or more row active master signals based on an active command signal, a pre-charge command signal, and one or more row active control signals. The row active control signal generating circuit generates a pulse signal that oscillates based on the one or more row active master signals. The row active control signal also generates the one or more row active control signals by dividing a frequency of the generated pulse signal. | 04-16-2009 |
20090109789 | DECODER WITH MEMORY - In one embodiment, a decoder for decoding an address having a plurality of bits ranging from a first address bit a | 04-30-2009 |
20090129195 | BALANCED AND BI-DIRECTIONAL BIT LINE PATHS FOR MEMORY ARRAYS WITH PROGRAMMABLE MEMORY CELLS - Disclosed is a design structure of an improved large scale memory system and, more particularly, an improved memory system that incorporates an array of memory cells that are subjected to minimal location dependent power variations and that, optionally, allows for bi-directional random access of millions of bits. Specifically, the system architecture provides a consistent amount of bit line resistance in the write and read paths to each memory cell in the array, independent of position, in order to minimize variations in power delivery to the cells and, thereby, allow for optimal cell distributions. The system architecture further allows current to pass in either direction through the cells in order to minimize element electro-migration and, thereby, extend memory cell life. | 05-21-2009 |
20090141580 | Reduced Leakage Driver Circuit and Memory Device Employing Same - A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit. | 06-04-2009 |
20090161474 | REVERSIBLE-POLARITY DECODER CIRCUIT AND METHOD - Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks. | 06-25-2009 |
20090196118 | Design Structure Of Implementing Power Savings During Addressing Of DRAM Architectures - A design structure embodied in a machine readable medium used in a design process includes random access memory device having an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Logic in signal communication with the array receives a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated. | 08-06-2009 |
20090219778 | BACK-GATE DECODE PERSONALIZATION - A novel methodology for the construction and operation of logical circuits and gates that makes use of and contact to a fourth (4 | 09-03-2009 |
20090231946 | SEMICONDUCTOR MEMORY DEVICE HAVING COLUMN DECODER - A semiconductor memory device includes a cell matrix having a number of cells, a multiplicity of column decoders for selectively activating the cells in response to code signals containing column address information for the cells, wherein each column decoder contains a pre-driving unit for providing a state output signal transiting between a power supply voltage and a source voltage in response to the code signals and a driving unit for outputting a column selection signal to activate a corresponding cell in response to the state output signal, wherein the pre-driving unit and the driving unit include at least one PMOS transistor and at least one NMOS transistor receiving a pumping voltage and a back-bias voltage, respectively, through their bulk, the pumping voltage having a voltage level higher than that of the power supply voltage and the back-bias voltage having a voltage level lower than that of a ground voltage. | 09-17-2009 |
20090238024 | SEMICONDUCTOR MEMORY DEVICE REMOVING PARASITIC COUPLING CAPACITANCE BETWEEN WORD LINES - A semiconductor memory device includes a main word line shared by a plurality of mats. Each of the mats includes a plurality of sub word lines. A decoding unit is configured to decode a row address bit and output a word line driving signal. A plurality of sub word line driving units are each configured to activate one of the sub word lines according to the word line driving signal. In the semiconductor memory device each neighboring sub word line driving units is connected to a different main word line to remove parasitic coupling capacitance. | 09-24-2009 |
20090245010 | Data Driver Circuit for a Dynamic Random Access Memory (DRAM) Controller or the Like and Method Therefor - A data driver includes a first latch ( | 10-01-2009 |
20090245011 | WORDLINE DRIVER FOR DRAM AND DRIVING METHOD THEREOF - A wordline driver for DRAM comprises a multiplexer, an inverter and a transistor switch. One end of the multiplexer is connected to a wordline charging voltage, and the other end is connected to an external voltage, wherein the external voltage is less than the wordline charging voltage, and initially the external voltage is outputted. The output end of the inverter is connected to the select line of the multiplexer, and the input end thereof is electrically connected to the output end of the multiplexer. One end of the transistor switch is connected to the input end of the inverter, and the other end thereof is connected to the word line. | 10-01-2009 |
20090262595 | METHOD AND APPARATUS FOR OPERATING MASKABLE MEMORY CELLS - A plurality of masked memory cells organized in at least two groups, each group using an individual mask signal, is operated by providing a logically valid mask signal only for a selected group comprising the memory cell to be accessed while a logically invalid mask signal are used for all groups other than the selected group. | 10-22-2009 |
20090262596 | Address decoder and/or access line driver and method for memory devices - Address decoders and access line drivers are provided. One such row decoder and access line driver receives power supply voltages in a manner that prevents CHC damage and avoids GIDL currents in transistors in the decoder and driver. The row decoder and a latch in the driver are powered by a first supply voltage, and an output stage in the access line driver is powered by a second supply voltage. The first and second supply voltages are maintained at a relatively low level during standby before an address is decoded. Only after an address is decoded to set the latch are the supply voltages increased to levels needed to drive the access line. Further, before resetting the latch, the first and power supply voltages are decreased to their standby levels. By maintaining the first and second voltages relatively low until after the latch is set and reset, GIDL currents may be avoided and CHC damage may be prevented. | 10-22-2009 |
20090279377 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array including a plurality of mutually intersecting word lines and bit lines, and a plurality of memory cells connected at intersections thereof and each having a read port and a write port provided independently; and a plurality of word line drivers operative to drive the word lines. The elements contained in the memory cell have respective sizes in common with the elements contained in the word line driver. | 11-12-2009 |
20090285047 | ROW DECODE DRIVER GRADIENT DESIGN IN A MEMORY DEVICE - A memory device using a plurality of enhanced row decode drivers for activating wordlines in a memory array is disclosed. Circuit design attributes of the enhanced row decode drivers are varied as a function of proximity to a source of a row address signal applied to each decode driver. The circuit variations are operable to reduce the leakage power of the driver by degrading performance thereof while maintaining required worst case timing. The worst case timing being defined by the timing and performance requirements for the most distant of the row decode driver circuits relative to the source of the applied row address signals. | 11-19-2009 |
20090303826 | STATIC RANDOM-ACCESS MEMORY WITH BOOSTED VOLTAGES - Dual port memory elements and memory array circuitry that utilizes elevated and non-elevated power supply voltages for performing reliable reading and writing operations are provided. The memory array circuitry may contain circuitry to switch a power supply line of a column of memory elements in the array to an appropriate power supply voltage during reading and writing operations. Each memory element may contain circuitry to select between power supply voltages during reading and writing operations. During reading operations, an elevated voltage may power cross-coupled inverters that store data in the memory elements while a non-elevated voltage may be used to turn on associated address transistors. During writing operations, the non-elevated voltage may power the cross-coupled inverters while the elevated voltage may be used to turn on the associated address transistors. | 12-10-2009 |
20090316513 | SEMICONDUCTOR MEMORY APPARATUS HAVING A SUB-WORD LINE DRIVER FOR INCREASING AN AREA MARGIN IN THE MEMORY CORE AREA - A semiconductor memory apparatus with a sub-word line driver is presented which has an increased area margin in the memory core area. The sub-word line driver is configured to operate in response to activation of a main word line and in response to positive and negative sub-word line enable signals. The sub-word line driver includes a pull-up driver and a pull-down driver. The pull-up driver is configured to pull-up drive a first sub-word line to the potential level of the positive sub-word line enable signal in response to the activation of the main word line. The pull-down driver is configured to pull-down drive the first sub-word line in response to the negative sub-word line enable signal. | 12-24-2009 |
20090323455 | WORD LINE DRIVER, METHOD FOR DRIVING THE WORD LINE DRIVER, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE WORD LINE DRIVER - A word line driver, a method for driving the word line driver, and a semiconductor memory device having the word line driver. The word line driver receives a main word line driving signal and a sub word line driving signal, to drive a word line with a word line driving signal, wherein the word line is driven concurrently with an activation of the main word line driving signal. The word line driver can reduce the unnecessary current consumption. | 12-31-2009 |
20100014376 | DECODING CIRCUIT WITHSTANDING HIGH VOLTAGE VIA LOW-VOLTAGE MOS TRANSISTOR AND THE IMPLEMENTING METHOD THEREOF - The present invention discloses a decoding circuit withstanding high voltage via a low-voltage MOS transistor, where negative high voltage that can be withstood can be as high as double what the transistor itself can withstand via two-stage CMOS inverters connected serially. When the negative high voltage is withstood, the source of a PMOS transistor in the CMOS inverter is switched to high resistance, and the substrate to the ground; the source of an NMOS transistor in the first CMOS inverter is connected with a half negative high voltage, and the source of an NMOS transistor in the second CMOS inverter with a negative high voltage; the first CMOS inverter, whose output is the half negative high voltage, is grounded at its input terminal, and output of the second CMOS inverter is the negative high voltage. The present invention further discloses a method of implementing the decoding circuit and a memory circuit using the decoding circuit. The present invention can effectively reduce area the device occupies; it is applicable to the non-volatile memory field, realizing high-voltage output during a high-voltage operation and fast decoding output during a normal-voltage operation. | 01-21-2010 |
20100020629 | WORD LINE DRIVER CIRCUIT - A sector of a word line driver circuit is provided, comprising a local reset signal generator module and m word line clusters. The m word line clusters are coupled to the local reset signal generator module. The local reset signal generator module is used to generate j reset signals. The x-th reset signal is determined according to an x-th pre-decoding signal, a bank selectable signal and a sector selectable signal, wherein j is a nature number, and x is an integer from 1 to j. Each of the m word line clusters comprises j row drivers. The x-th row driver of the y-th word line cluster determines a [x+j*(y−1)]-th word line signal according to the x-th reset signal, the x-th pre-decoding signal, the sector selectable signal, and a y-th cluster select signal, wherein m is a nature number, and y is an integer from 1 to m. | 01-28-2010 |
20100027367 | ROW MASK ADDRESSING - Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed. | 02-04-2010 |
20100046313 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level. | 02-25-2010 |
20100085830 | Sequencing Decoder Circuit - A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits includes first and second decoder stages. The first decoder stage selects one or more first rows by decoding a first subset of the address bits, and the second decoder stage selects one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows. | 04-08-2010 |
20100091600 | CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE - Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal. | 04-15-2010 |
20100149901 | WORD LINE DECODER CIRCUIT - A word line decoder circuit is provided in the present invention. The word line decoder circuit comprises at least one local pre-decoder, at least one 3-transistors row driver, a controllable power supply, and a controllable pull-down circuit. The controllable power supply is controlled by an inversed sector select signal to provide a first voltage to the row driver and local pre-decoder. The local pre-decoder uses 5-transistors architecture, in which there are 2 PMOS transistors and 3 NOS transistors. The controllable pull-down circuit pulls down the local pre-decoder and is controlled by a sector select signal and pre-decoding signal. The local pre-decoder receives a local pre-decoding signal to select the row driver. When the row driver is selected, the row driver determines a word line according to a row driver pull-down signal and a row driver pull-up signal. | 06-17-2010 |
20100157716 | Sub word line driving circuit - A sub word line driving circuit includes a FX driver which buffers an inverted FX signal to generate a FX signal in response to a control signal, and a sub word line driver which is supplied with the FX signal and receives a main word line signal to drive a sub word line signal. | 06-24-2010 |
20100165778 | Word Line Driver Circuit with Reduced Leakage - A word line driver circuit for use in a memory array including multiple memory cells and multiple word lines coupled to the memory cells for selectively accessing the memory cells includes a driver adapted to generate a word line signal as a function of a first set of address signals received by the word line driver circuit. The circuit further includes a switching circuit having a plurality of output nodes, the output nodes connected to respective ones of the plurality of word lines, and having an input node connected to an output of the driver and adapted to receive the word line signal. The switching circuit is operative to direct the word line signal to a selected one of the word lines during a memory access as a function of at least one control signal. Between a given pair of memory accesses, the output nodes and the input node of the switching circuit are held to a same prescribed voltage level to thereby substantially eliminate a leakage current path in the switching circuit. | 07-01-2010 |
20100165779 | ROW DECODER FOR A MEMORY DEVICE - A semiconductor memory device including an array of memory cells arranged in a plurality of rows and in a plurality of columns. The memory device further includes a plurality of word lines each associated with a respective row of the array and identified by a respective row address, and a row decoder configured to receive a current row address and select a word line according to said current row address. The row decoder includes a plurality of row selection units each associated with a respective word line and configured to receive the current row address; each row selection unit is configured to be enabled for biasing the respective word line to a selection voltage if the current row address identifies said word line. Each row selection unit includes a corresponding enabling device for enabling the row selection unit after a predetermined time from the reception of the current row address. | 07-01-2010 |
20100177586 | MEMORY ARCHITECTURE HAVING MULTIPLE PARTIAL WORDLINE DRIVERS AND CONTACTED AND FEED-THROUGH BITLINES - Various embodiments are disclosed relating to a memory circuit architecture. In an example embodiment, which may accommodate a change to a new memory size or cell aspect ratio, while migrating between different process nodes or the same process generation, while retaining at least a portion of the periphery circuitry, a memory circuit architecture may be employed in which the memory array is divided into an upper half and a lower half, thereby splitting the cache Ways among the two halves. The wordline may be split among the two array halves, with each half driven by a half wordline driver. Also, in another embodiment, two sets of bitlines may be provided for each column, including a contacted set of bitlines and a feed-through set of bitlines. | 07-15-2010 |
20100188924 | DATA TRANSFER SYSTEM - The invention is directed to decreasing a circuit size of a system in which a plurality of devices or circuit blocks share and use one memory. A system is configured so that a memory block serves as a master and each of circuit blocks serves as a slave, and thus the slave side (the circuit blocks) receives necessary data from the memory block by only having decoders corresponding to addresses assigned thereto in advance and registers. In this case, since the registers have been also needed in a conventional system in order to hold data read out from a memory, the circuit size decreases in the whole system. Since this effect is enhanced in proportion to the number of the circuit blocks sharing the memory block, the effect is enhanced as the system size increases. | 07-29-2010 |
20100195431 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed. | 08-05-2010 |
20100202241 | WORD LINE DRIVING CIRCUIT AND METHOD - A word line driving circuit includes an address decoding signal generating unit and a word line voltage supply unit. The address decoding signal generating unit includes inverter chain receiving and delaying a first address decoding signal and outputting the delayed first address decoding signal. The word line voltage supply unit includes a pull-up driver that supplies the delayed first address signal to a selected word line in response to a second address decoding signal. The inverter chain includes an NMOS transistor outputting the delayed first address signal and a source terminal of the NMOS transistor receives a set voltage that is higher than a ground voltage and lower than a high voltage. | 08-12-2010 |
20100208541 | CACHE MEMORY - Disclosed is a cache memory, and more particularly to a cache memory, in which a word-line voltage control logic unit and a word-line driver are added as a logic circuit between a row decoder and a word line, so that a reinforcement voltage signal having a higher level than a basic voltage signal can be applied when accessing the word line corresponding to an access time failure, thereby decreasing an access time delay in the word line in order to minimize an access failure to the cache memory due to process variation. The cache memory including: a row decoder which decodes and outputs an input address signal; a plurality of word-line voltage control logic units which output a basic voltage signal or a reinforcement voltage signal having a higher voltage level than the basic voltage signal according to whether or not word lines involve a cell having an access time failure; and word-line drivers which are one-to-one connected to output lines of the row decoder and supply the word lines with the basic voltage signal or the reinforcement voltage signal output from the word-line voltage control logic unit only if a signal output through the output line of the row decoder is an activation signal. | 08-19-2010 |
20100214864 | MEMORY DEVICE COMMAND DECODING SYSTEM AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME - Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode. | 08-26-2010 |
20100220543 | Circuitry and method for indicating a memory - Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 09-02-2010 |
20100226195 | INTEGRATED CIRCUIT SELF ALIGNED 3D MEMORY ARRAY AND MANUFACTURING METHOD - A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers. | 09-09-2010 |
20100232250 | Interface circuit and method for coupling between a memory device and processing circuitry - Interface circuitry is provided for coupling between a memory device and processing circuitry, the processing circuitry issuing a plurality of access signals relating to accesses to be performed in the memory device. The interface circuitry comprises write address latch circuitry for storing a write address signal, and write address decoder circuitry that is responsive to a set first enable signal to decode the write address signal provided from the write address latch circuitry. Further, read address latch circuitry is provided for storing a read address signal issued by the processing circuitry, and read address decoder circuitry is responsive to a set second enable signal for decoding the read address signal provided from the read address latch circuitry. Decoder select latch circuitry is responsive to an access type indication signal from the processing circuitry to generate the first and second enable signals in dependence on that access type indication signal. In the event of metastability occurring in the decoder select latch circuitry, the decoder select latch circuitry is arranged not to set at least the second enable signal, thereby disabling at least the read address decoder circuitry in the presence of such metastability. Such an approach prevents metastable signals being used in the arbitration of data accesses in a manner which could corrupt the state of the memory device. | 09-16-2010 |
20100238755 | SEMICONDUCTOR MEMORY DEVICE HAVING POWER SAVING MODE - A semiconductor memory device includes a memory cell array arranged in rows and columns, a row decoder and a control circuit. The row decoder drives word lines connected to the memory cell array by decoding a received row address and being synchronized with an internal clock signal. The control circuit receives a clock signal, a chip select signal and a mode signal, and generates the internal clock signal. The control circuit generates the internal clock signal so that the row decoder does not operate for a predetermined time in response to the chip select signal when the mode signal transitions from a power saving mode to a normal mode. | 09-23-2010 |
20100246309 | SEMICONDUCTOR MEMORY - An SRAM module includes bit cells arranged within an SRAM array of N×M, and a replica SRAM cell array of a replica bit cell used for bit cell performance measurement, and can control the number of replica bit cells used for performance measurement. When the clock generator circuit generates an internal pulse upon receiving a clock, the clock generator circuit generates a leading edge of a pulse by a clock (clk), and generates a trailing edge thereof by a delay circuit including the delay of the replica bit cells. The internal pulse is used for controlling the activation time of the word lines for selecting the memory cell, and the timing of a bit line control circuit (a bit line precharger circuit, an address logic circuit, and a sense amplifier circuit). | 09-30-2010 |
20100278003 | ADDRESS DECODER AND/OR ACCESS LINE DRIVER AND METHOD FOR MEMORY DEVICES - Address decoders and access line drivers are provided. One such row decoder and access line driver receives power supply voltages in a manner that prevents CHC damage and avoids GIDL currents in transistors in the decoder and driver. The row decoder and a latch in the driver are powered by a first supply voltage, and an output stage in the access line driver is powered by a second supply voltage. The first and second supply voltages are maintained at a relatively low level during standby before an address is decoded. Only after an address is decoded to set the latch are the supply voltages increased to levels needed to drive the access line. Further, before resetting the latch, the first and power supply voltages are decreased to their standby levels. By maintaining the first and second voltages relatively low until after the latch is set and reset, GIDL currents may be avoided and CHC damage may be prevented. | 11-04-2010 |
20100296357 | Semiconductor Memory Device - A semiconductor memory device is capable of scrambling input/output data according to row addresses. The semiconductor memory device includes a local line driving block configured to differentially drive a positive local line and a negative local line by selectively inverting data on a global line according to row addresses, a global line driving block configured to drive the global line by selectively inverting data on the positive local line and data on the negative local line according to the row addresses, a first cell region configured to allow a first internal data to be equalized with the data on the positive local line in response to the row addresses and column addresses, and a second cell region configured to allow a second internal data to be equalized with the data on the negative local line in response to the row addresses and the column addresses. | 11-25-2010 |
20100296358 | ACTIVE DRIVER CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - An active driver control circuit for a semiconductor memory apparatus includes an asynchronous decoding unit that can be activated in response to a bank selection signal, when an external command is a read or write command, can generate an enabled read/write enable signal, and when a precharge signal is enabled, disable the enabled read/write enable signal, a synchronous decoding unit that can be activated in response to the bank selection signal, can generate an enabled active enable signal when the external command is an active command, when the external command is a precharge command, can generate the precharge signal, and output the active enable signal and the precharge signal in synchronization with a clock, and an active driver control signal generating unit that can generate an active driver control signal in response to the active enable signal and the read/write enable signal. | 11-25-2010 |
20100302894 | WORD LINE SELECTION CIRCUIT AND ROW DECODER - A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals. | 12-02-2010 |
20100329067 | CHARGE PUMP AND SEMICONDUCTOR DEVICE HAVING THE SAME - A charge pump and method of operation are provided. The charge pump includes a first boosting unit configured to receive a pre-charge voltage and electrically charge a first MOS capacitor during a pre-charge period, and to boost a voltage of a connection node to a first output voltage during a boosting operation period, and a second boosting unit configured to receive the pre-charge voltage and electrically charge a second MOS capacitor during the pre-charge period, and to receive the first output voltage and boost a voltage of an output node to a second output voltage during the boosting operation period. Here, the pre-charge voltage is applied to electrically charge a parasitic capacitor during a parasitic capacitor charging period between the pre-charge period and the boosting operation period. | 12-30-2010 |
20100329068 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cells, a plurality of bit lines respectively connected to the memory cells, a plurality of first and second word lines respectively connected to the memory cells, a plurality of first drivers for driving the first word lines selected during a read operation, and a plurality of second drivers for driving the second word lines selected during a write operation, the second driver having a different drive capability from the first driver's. | 12-30-2010 |
20100329069 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cells that respectively stores data, a comparator that compares a row address in a previous cycle with a row address in a current cycle, and outputs a control signal to the row address decoder when the comparator detects a matching of a row address in a previous cycle and a row address in a current cycle, and a row address decoder that decodes the row address, and outputs a word line select signal to select one of word lines connected to a part of the plurality of memory cells based on the decoded row address, and prevents the output of the word line select signal when the control signal outputted from the comparator is inputted to the row address decoder. | 12-30-2010 |
20100329070 | Resistance Semiconductor Memory Device Having Three-Dimensional Stack and Word Line Decoding Method Thereof - A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved. | 12-30-2010 |
20110007597 | Semiconductor Control Line Address Decoding Circuit - Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2 | 01-13-2011 |
20110019495 | DECODER CIRCUITRY PROVIDING FORWARD AND REVERSE MODES OF MEMORY ARRAY OPERATION AND METHOD FOR BIASING SAME - Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks. | 01-27-2011 |
20110032784 | SEMICONDUCTOR MEMORY WITH MULTIPLE WORDLINE SELECTION - A semiconductor memory circuit, comprising: a memory array, the memory array including a plurality of wordlines each connected to a respective row of cells and a plurality of bitlines each connected to a respective column of cells. The semiconductor memory circuit also comprises at least one row decoder for selecting a group of wordlines within the plurality of wordlines; and a plurality of driver circuits for driving the plurality of bitlines respectively and setting the cells connected to the group of wordlines to a predetermined logic state. Also, a method for presetting at least part of a memory array, the memory array comprising a plurality of wordlines each connected to a respective row of cells. The method comprises selecting a group of wordlines within the plurality of wordlines; and simultaneously setting memory cells connected to the group of wordlines to a predetermined logic state. | 02-10-2011 |
20110032785 | WORDLINE DRIVER, MEMORY DEVICE INCLUDING THE SAME AND METHOD OF DRIVING A WORDLINE - A wordline driver includes a pre-driver, a sub-wordline driver and a transmission circuit. The pre-driver generates a wordline enable signal and a wordline disable signal based on one or more selection signals, a decoded address signal, and one or more timing control signals. The transmission circuit transmits the wordline enable signal and the wordline disable signal. The sub-wordline driver controls a voltage level of the sub-wordline based on the wordline enable signal and the wordline disable signal that are transmitted by the transmission circuit. Therefore, driving capacity may be improved. | 02-10-2011 |
20110032786 | SUB-WORD LINE DRIVER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A sub-word line driver includes a substrate, a plurality of gate lines and at least one gate tab. The substrate includes a plurality of isolation areas and a plurality of active areas, where the two active areas are separated by each isolation area, and the isolation areas and the active areas are extended in a first direction and are arranged in a second direction perpendicular to the first direction. The plurality of gate lines are formed on the substrate, where the gate lines are extended in a second direction and are arranged in the first direction. The at least one gate tab is formed on the substrate, where the at least one gate tab is extended in the first direction to cover the isolation area. Incorrect operation of the sub-word line driver may be prevented, and a power consumption of the sub-word line driver may be reduced. | 02-10-2011 |
20110044122 | WORD LINE DRIVING APPARATUS - A source potential of a pull-up transistor is increased after predetermined time from a rising timing of a word line selection command signal. To this end, a condenser is provided to couple the source potential and gate potential of the pull-up transistor. Preferably a gate potential control transistor that controls the gate potential of the pull-up transistor is a depletion type N-channel field effect transistor that maintains the gate potential at a low level. | 02-24-2011 |
20110058441 | DATA LINE DRIVING CIRCUIT - A data line driving circuit includes: an operation period signal generation unit configured to generate an operation period signal for determining a write period and a read period in response to a read command or a write command; and a read data line driving unit configured to fix a read data line to a first voltage level in response to the operation period signal, the read data line being dedicated to a read operation. | 03-10-2011 |
20110075505 | SEMICONDUCTOR MEMORY DEVICE AND LAYOUT STRUCTURE OF SUB-WORD LINE CONTROL SIGNAL GENERATOR - A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance. | 03-31-2011 |
20110110176 | ADDRESS CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - An address control circuit is presented for use in reducing a skew in a write operation mode. The address control circuit includes a read column address control circuit and a write column address control circuit. The read column address control circuit is configured to generate a read column address from an address during a first burst period for a read operation mode. The write column address control circuit is configured to generate a write column address from the address during a second burst period for a write operation mode. | 05-12-2011 |
20110116336 | Multi-layered memory devices - A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array. | 05-19-2011 |
20110122721 | Y-Decoder and Decoding Method Thereof - A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage. | 05-26-2011 |
20110128810 | MEMORY DEVICE AND MEMORY CONTROL FOR CONTROLLING THE SAME - A memory device includes: a memory cell array which stores two-dimensionally arranged data in a plurality of memory unit regions selected by an address; an internal address control unit which generates an internal address which selects a memory unit region according to an external address; and a decoder which decodes the internal address and selects a memory unit region. The plurality of memory unit regions store data arranged in a first direction from among two-dimensionally arranged data according to a least-significant bit group of the internal address and store data arranged in a second direction from among the two-dimensionally arranged data according to a most-significant bit group of the address. The internal address control unit successively generates an internal address corresponding to the scan direction according to a scan direction control signal which controls a plurality of scan directions including at least an oblique direction of the two-dimensionally arranged data. | 06-02-2011 |
20110141840 | NOR-OR DECODER - A decoder for decoding an address having a plurality of bits ranging from a first address bit a | 06-16-2011 |
20110149674 | Integrated circuit memory with word line driving helper circuits - An integrated circuit memory | 06-23-2011 |
20110149675 | Local Word Line Driver - A two transistor word line driver is disclosed. An example disclosed word line driver is simplified with common signals on the gates of the p-type and the n-type transistors. An example disclosed word line driver consumes less power by applying a negative voltage to a word line driver selected from multiple word line drivers. | 06-23-2011 |
20110158029 | WORD LINE DRIVING CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a word line driving circuit includes a driver and a booster circuit. The driver drives a word line based on an output of an inverter. The booster circuit connects a boosting capacitor to a source side of a P-channel field effect transistor of the inverter to boost the potential of the word line. | 06-30-2011 |
20110205829 | SEMICONDUCTOR MEMORY DEVICE - In order to latch and store a word line reset level voltage (negative voltage) which is set during reset operation, a word line driver includes PMOS transistors and NMOS transistors. The word line driver further includes a stress-reducing PMOS transistor and an NMOS transistor, and also a word line bias control circuit which controls and activates a supply bias during setting of a word line, start of resetting, and a reset period. | 08-25-2011 |
20110205830 | Semiconductor Control Line Address Decoding Circuit - Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2 | 08-25-2011 |
20110216620 | DECODER CIRCUIT - A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal. | 09-08-2011 |
20110228624 | SUB-WORD-LINE DRIVING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND METHOD OF CONTROLLING THE SAME - Provided is a semiconductor memory device including a sub-word-line driving circuit capable of reducing an amount of leakage current due to coupling. The semiconductor memory device includes a word-line enable signal generating circuit and a sub-word-line driving circuit. The sub-word-line driving circuit provides a pull-down current path between a selected word line and ground for a pulse type period of time in a precharge mode following an active mode for the selected word line, generates a word line driving signal on the basis of a main word line driving signal, a first sub-word-line control signal, and a second sub-word-line control signal, and provides the word line driving signal to a memory cell array. The semiconductor memory device may reduce an amount of leakage current flowing to a ground through the sub-word-line driving circuit. | 09-22-2011 |
20110242926 | PSEUDO-INVERTER CIRCUIT ON SeO1 - A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage. | 10-06-2011 |
20110242927 | Encoded Read-Only Memory (ROM) Decoder - Decoder circuits capable of decoding encoded ROM memory are provided. Embodiments provide several improvements over prior solutions which rely primarily on CMOS logic (e.g., inverters). For example, embodiments provide faster decoding by limiting the number of decoding stages to a single stage. Further, embodiments allow the use of partial swing (as opposed to full swing) on the bit lines, which results in significant power reduction. This, in turn, results in reduced amounts of capacitor discharges when reading the data. | 10-06-2011 |
20110267917 | ROW MASK ADDRESSING - Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed. | 11-03-2011 |
20110280097 | WORDLINE DRIVER FOR MEMORY - Subject matter disclosed herein relates to accessing memory, and more particularly to a wordline driver of same. | 11-17-2011 |
20110292754 | MEMORY WORD-LINE DRIVER HAVING REDUCED POWER CONSUMPTION - A word-line driving circuit for driving a word-line in a memory array includes a NAND circuit having a pair of address inputs and an output, an output inverter circuit having an inverter power supply node, an input coupled to the output of the NAND circuit and an output for providing a word line signal, a power gate coupled between a first power supply node and the inverter power supply node, and a control circuit coupled to the power gate. The control circuit controls the power gate to place the word line driver circuit in active or standby mode in response to the output of the NAND circuit. | 12-01-2011 |
20110299355 | WORD LINE DRIVER FOR MEMORY - A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line. | 12-08-2011 |
20110317508 | MEMORY WRITE OPERATION METHODS AND CIRCUITS - In some embodiments, write wordline boost may be obtained from wordline driver boost and/or from bit line access transistor boost. | 12-29-2011 |
20110317509 | MEMORY DEVICE WORD LINE DRIVERS AND METHODS - Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Each global word line driver includes at least one transistor of the first type. Other subsystems and methods are disclosed. | 12-29-2011 |
20120002500 | Multi-Voltage Level, Multi-Dynamic Circuit Structure Device - A multi-voltage level, multi-dynamic circuit structure device and method are disclosed. In a particular embodiment, the method includes discharging a first dynamic node at a first discharge circuit of a first dynamic circuit structure in response to receiving an asserted discharge signal. The first dynamic circuit structure includes the first dynamic node at a first voltage level and a first keeper circuit that is disabled when the asserted discharge signal is received. The asserted discharge signal has a second voltage level that is different from the first voltage level. A second keeper circuit of a second dynamic circuit structure is enabled responsive to discharging the first dynamic node to maintain a second dynamic node of the second dynamic circuit structure at the first voltage level. | 01-05-2012 |
20120014203 | SEMICONDUCTOR MEMORY APPARATUS - A reference voltage selecting unit selectively outputs a first external reference voltage and a second external reference voltage as a selection reference voltage in accordance with whether to perform a wafer test. An address buffer generates an internal address by buffering an external address in accordance with the selection reference voltage. A command buffer generates an internal command by buffering an external command in accordance with the selection reference voltage. A data buffer generates internal data by buffering to an external data in accordance with the second external reference voltage. | 01-19-2012 |
20120020179 | METHOD AND APPARATUS FOR WORD LINE DECODER LAYOUT - A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines. | 01-26-2012 |
20120033522 | VARIATION-TOLERANT WORD-LINE UNDER-DRIVE SCHEME FOR RANDOM ACCESS MEMORY - A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM. | 02-09-2012 |
20120063256 | MEMORY DEVICE WORD LINE DRIVERS AND METHODS - Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Other subsystems and methods are disclosed. | 03-15-2012 |
20120081988 | SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR SYSTEM - A semiconductor circuit includes a data driving circuit configured to change a slew rate in response to a control signal and drive data at a changed slew rate, a core/peripheral circuit block configured to provide the data to the data driving circuit, and a channel/memory module information setting unit configured to set the control signal according to channel/memory module information. | 04-05-2012 |
20120113740 | ROW DECODER CIRCUIT - A row decoder circuit includes a decoding unit and first and second wordline driving units. The decoding unit generates a first driving signal and a second driving signal based on a selection signal and wordline voltages. A voltage level of the first driving signal and a voltage level of the second driving signal depend on an operation mode. The first wordline driving unit is connected to a first wordline and outputs one of the first driving signal and the second driving signal as a first wordline driving signal based on first driving control signals. The second wordline driving unit is connected to a second wordline and outputs one of the first driving signal and the second driving signal as a second wordline driving signal based on second driving control signals. | 05-10-2012 |
20120120753 | Semiconductor device having point-shift type FIFO circuit - For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift register to generate an input pointer signal and a binary counter to generate an output pointer signal. The input selection circuit selects one of the latch circuits on the basis of a value of the input pointer signal. The output selection circuit selects one of the latch circuits on the basis of a value of the output pointer signal. Therefore, it is possible to prevent a hazard from occurring in the input selection circuit, as well as to reduce the number of signal lines that transmit the output pointer signal. | 05-17-2012 |
20120155210 | PHYSICAL ORGANIZATION OF MEMORY TO REDUCE POWER CONSUMPTION - Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream components may be activated while another wordline and downstream components may be deactivated. | 06-21-2012 |
20120155211 | SEMICONDUCTOR INTEGRATED CIRCUIT - A memory macro includes: a plurality of memory cells arranged in a matrix; a plurality of word lines corresponding to rows of the plurality of memory cells; and a plurality of word line drivers configured to drive the plurality of word lines. The voltage of the word lines in their activated state is set to vary with threshold voltage characteristics of a p-channel transistor and an n-channel transistor. | 06-21-2012 |
20120163114 | NAND logic word line selection - A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line. | 06-28-2012 |
20120163115 | Nor logic word line selection - A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line. | 06-28-2012 |
20120170398 | COLUMN ADDRESS COUNTER CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - The column address counter circuit of a semiconductor memory device includes at least one lower bit counter unit configured to generate a first bit of a column address by counting an internal clock, where the first bit is not a most significant bit of the column address, and a most significant counter unit configured to generate the most significant bit of the column address in response to a mask clock, where the mask clock is toggled when the internal clock is toggled by a set number of times. | 07-05-2012 |
20120170399 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 07-05-2012 |
20120188838 | MEMORY WITH WORD-LINE SEGMENT ACCESS - A memory comprises a row of bit cells, including a first plurality of bit cells and a second plurality of bit cells. A first word line segment driver is connected to the first plurality of bits cells. A second word line segment driver is connected to the second plurality of bits cells. The first and second word line segment drivers are selectively operable for activating one of the first and second pluralities of bit cells at a time to the exclusion of the other plurality of bit cells. A shared sense amplifier is coupled to at least one of the first plurality of bit cells and at least one of the second plurality of bit cells. The shared sense amplifier is configured to receive signals from whichever of the one first or second bit cell is activated by its respective word line segment driver at a given time. | 07-26-2012 |
20120188839 | BANK SELECTION CIRCUIT AND MEMORY DEVICE HAVING THE SAME - A bank selection circuit includes a command latch unit configured to latch an input command at a time earlier than a rising edge of a clock by a setup time, a command decoder configured to decode a latched command and generate a row operation signal, a bank address latch unit configured to latch an input bank address at a time earlier than the rising edge of the clock by the setup time, a bank address decoder configured to decode a latched bank address and generate a bank selection signal, and a bank selection unit configured to receive the row operation signal and the bank selection signal and transfer the row operation signal to a bank selected by the bank selection signal. | 07-26-2012 |
20120195152 | MEMORY ARCHITECTURE HAVING MULTIPLE PARTIAL WORDLINE DRIVERS AND CONTACTED AND FEED-THROUGH BITLINES - Various embodiments are disclosed relating to a memory circuit architecture. In an example embodiment, which may accommodate a change to a new memory size or cell aspect ratio, while migrating between different process nodes or the same process generation, while retaining at least a portion of the periphery circuitry, a memory circuit architecture may be employed in which the memory array is divided into an upper half and a lower half, thereby splitting the cache Ways among the two halves. The wordline may be split among the two array halves, with each half driven by a half wordline driver. Also, in another embodiment, two sets of bitlines may be provided for each column, including a contacted set of bitlines and a feed-through set of bitlines. | 08-02-2012 |
20120224448 | DELAY EFFICIENT GATER REPEATER - A gater repeater circuit is disclosed. In one embodiment, the circuit includes an activation circuit coupled to receive an input signal and a clock signal and configured to activate an output circuit. The output circuit is configured to drive an output signal. The output circuit includes first and second devices configured to drive the output signal to first and second states, respectively. A feedback circuit is configured to provide a delayed version of the output signal. A deactivation circuit is coupled to receive the clock signal and the delayed version of the output signal, and is configured to, when the clock signal is in the first state, cause the deactivation of an active one of the first and second devices. When the clock is in the second state, the circuit is configured to cause the second device to drive the output signal to the second state. | 09-06-2012 |
20120230143 | STATIC MEMORY WITH SEGMENTED CLEAR - Described embodiments provide a static memory system with multiple memory cell that, in response to a reset signal, simultaneously resets or clears a segment of the memory cells in the memory. Clearing the entire memory or a portion thereof is accomplished by sequencing though a subset of address bits while asserting the reset signal. | 09-13-2012 |
20120236675 | Methods and Apparatus for Memory Word Line Driver - A word line driver circuit and corresponding methods are disclosed. An apparatus, comprising a decoder circuit coupled to receive address inputs, and having a decoder output; and a word line clock gating circuit coupled to the decoder output and to a word line clock signal, configured to selectively output a word line signal responsive to an edge on the word line clock signal; wherein the address inputs have a set up time requirement relative to the edge of the word line clock signal, and the address inputs have a zero or less hold time requirement relative to the edge of the word line clock signal. Methods for providing a word line signal from a word line driver are disclosed. | 09-20-2012 |
20120236676 | SINGLE TRANSISTOR DRIVER FOR ADDRESS LINES IN A PHASE CHANGE MEMORY AND SWITCH (PCMS) ARRAY - The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line. | 09-20-2012 |
20120243365 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF SETTING OPERATION ENVIRONMENT THEREIN - A semiconductor memory device comprises: a memory cell array including a plurality of memory cells; an internal circuit having a function required in a storage operation of the memory cell array; a parameter storage unit configured to store a certain parameter and to have a storage place specified by a parameter address, the certain parameter designating an operation of the internal circuit; a command register configured to store a command instructing an operation of the internal circuit; and a converting circuit configured to adjust at least one of the parameter address and the command that differ between products or between standards to the internal circuit. | 09-27-2012 |
20120250444 | PSEUDO-INVERTER CIRCUIT ON SeOI - A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage. | 10-04-2012 |
20120281492 | Method and Apparatus for Decoding Memory - A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller. | 11-08-2012 |
20120314524 | SEMICONDUCTOR DEVICE - An object is to increase the retention characteristics of a memory device formed using a wide bandgap semiconductor. A bit line controlling transistor is inserted in a bit line in series. The minimum potential of a gate of the transistor is set to a sufficiently negative value. The gate of the transistor is connected to a bit line controlling circuit connected to a battery. The minimum potential of the bit line is set higher than that of a word line. When power from an external power supply is interrupted, the bit line is cut off by the transistor, ensuring prevention of outflow of charge in the bit line. The potential of a source or a drain (bit line) of a cell transistor is sufficiently higher than that of a gate of the cell transistor, resulting in an absolute off-state; thus, data can be retained. Other embodiments are disclosed. | 12-13-2012 |
20120314525 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level. | 12-13-2012 |
20130010564 | SEMICONDUCTOR MEMORY DEVICE - According to the embodiments, a semiconductor memory device includes serially-connected cell transistors includes respective gate electrodes coupled to respective word lines, a first driver and a second driver which drive the word lines, and a connection module. The connection module electrically couples the first driver commonly to a first subset of the word lines, and electrically couples the second driver commonly to a second subset of the word lines different from the first subset of the word lines. The first and second subsets of the word lines include the same number of word lines. | 01-10-2013 |
20130028041 | Memory Compression - Exemplary embodiments comprise memory for storing the look-up table values. One exemplary memory comprises a decoder, an encoder, and one or more patterns of crisscrossed interconnect lines that interconnect the encoder with the decoder. The patterns of crisscrossed interconnection lines may be implemented on one or more planar layers of conductor tracks vertically interleaved with isolating material. | 01-31-2013 |
20130070553 | SEMICONDUCTOR DEVICE HAVING CHARGE PUMP CIRCUIT AND INFORMATION PROCESSING APPARATUS INCLUDING THE SAME - Disclosed herein is a device that includes a capacitor, a pumping circuit supplying a pumping signal changed between first and second potential to a first electrode of the capacitor, and an output circuit precharging a second electrode of the capacitor to a third potential different from the first and second potentials. The second electrode of the capacitor is thereby changed from the third potential to a fourth potential higher than the third potential when the pumping signal is changed from the first potential to the second potential. | 03-21-2013 |
20130077427 | SEMICONDUCTOR DEVICE HAVING CAL LATENCY FUNCTION - Disclosed herein is a semiconductor device that includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal is activated. The latency control circuit activates a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles. The command receiver is activated based on a first control signal. The first control signal is activated in response to the first internal chip select signal. The first control signal is deactivated in response to the second control signal. | 03-28-2013 |
20130077428 | SEMICONDUCTOR DEVICE HAVING PDA FUNCTION - Disclosed herein is a semiconductor device that includes a command decoder activating a first mode register setting signal in response to a mode register setting command supplied from outside, a first latency shifter activating a second mode register setting signal after elapse of predetermined cycles of a clock signal since the first mode register setting signal is activated, and a mode register storing a mode signal supplied from outside in response to the second mode register setting signal. | 03-28-2013 |
20130077429 | SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE - Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command. | 03-28-2013 |
20130083618 | Apparatus and Method for Converting Static Memory Address to Memory Address Pulse - A tri-state NAND circuit includes a first input connected to receive a first input signal and a second input connected to receive a second input signal. The tri-state NAND circuit is connected to operate in accordance with a first clock signal and a second clock signal. A logic state of the second clock signal is opposite a logic state of the first clock signal. The tri-state NAND circuit is connected to transmit an output signal to a first node. A tri-state latch circuit is connected to hold a signal present at the first node in accordance with the first clock signal and the second clock signal. A pulse generating NAND circuit includes a first input connected to the first node and a second input connected to receive the first clock signal. The pulse generating NAND circuit is connected to transmit an output signal to a second node. | 04-04-2013 |
20130094320 | ADDRESS TRANSFORMING CIRCUITS INCLUDING A RANDOM CODE GENERATOR, AND RELATED SEMICONDUCTOR MEMORY DEVICES AND METHODS - Address transforming methods are provided. The methods may include generating a power-up signal when a semiconductor memory device is powered-up. The methods may further include generating a randomized output signal in response to the power-up signal. The methods may additionally include transforming bits of a first address in response to the randomized output signal to generate a second address. | 04-18-2013 |
20130094321 | SEMICONDUCTOR DEVICE HAVING LATENCY COUNTER TO CONTROL OUTPUT TIMING OF DATA AND DATA PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a device that includes a command decoder and a latency counter. The command decoder generates a first internal command in response to a first internal clock signal. The latency counter includes: a gate control signal generation unit generating output gate signals in response to a second internal clock signal; delay circuits each receiving an associated one of the output gate signals and generating an associated one of input gate signals; and a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command in response to one of the output gate signals. Each of the delay circuit includes a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage different from the first power supply voltage. | 04-18-2013 |
20130100758 | LOCAL WORD LINE DRIVER - A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver. | 04-25-2013 |
20130114366 | SEMICONDUCTOR DEVICE HAVING PLURAL SELECTION LINES SELECTED BASED ON ADDRESS SIGNAL - Disclosed herein is a device that includes: a set of address terminals supplied with a set of address signals, each of the address signals being changed in logic level; memory mats to which address ranges are allocated, respectively, the address ranges being different from each other, each of the memory mats including memory cells; and decoder units each provided correspondingly to corresponding memory mat. Each of the decoder units includes a set of first input nodes and a set of second input nodes, the set of first input nodes of each of the decoder units being coupled to the set of address terminals to receive the set of address signals, the set of second input nodes of each of the decoder units being coupled to receive an associated one of sets of control signals, each of the control signals being fixed in logic level. | 05-09-2013 |
20130148458 | BUFFER CIRCUIT AND WORD LINE DRIVER USING THE SAME - A buffer circuit includes a pull-up element configured to pull-up drive a first node through which an output signal is outputted, in response to an input signal; a first voltage control element configured to reduce a voltage of the first node and set a voltage of a second node in a standby mode; and a pull-down element configured to pull-down drive the second node in response to the input signal. | 06-13-2013 |
20130155801 | SUB WORD LINE DRIVER AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A sub word line driver and a semiconductor integrated circuit device having the same are provided. The semiconductor integrated circuit device includes adjacent four sub word line drivers configured to drive four sub word lines in response to signals of four main word lines, wherein first and second sub word line drivers of adjacent sub word line drivers share one keeper transistor with each other, and third and fourth sub word line drivers of the adjacent sub word line drivers share one keeper transistor with each other. | 06-20-2013 |
20130170313 | WORDLINE DRIVER - A circuit includes a first transistor and a second transistor of a first type. The circuit further includes a first transistor of a second type. A first first-type drain is coupled to a second first-type source. A first first-type source is configured to have a first voltage value. A first first-type gate is configured to have a first control signal. A second first-type drain is configured to serve as a wordline. A second first-type gate is configured to have a second voltage value. A first second-type source is configured to have a third voltage value. A first second-type gate is configured to have a second control signal. The first transistor and the second transistor of the first type are configured to provide the first voltage value for the wordline. The first transistor of the second-type is configured to provide the third voltage value the wordline. | 07-04-2013 |
20130176808 | WORD LINE BOOST CIRCUIT - A word line boost circuit including a first address transfer detector, a second address transfer detector and a boost operation unit is provided. The first address transfer detector generates a first detection pulse in response to variation of a row address signal. The second address transfer detector generates a second detection pulse in response to variation of a column address signal. Moreover, the boost operation unit generates a selection voltage by using a boost voltage according to the first detection pulse, and determines whether or not to use the boost voltage to generate the selection voltage according to a delay time between the first detection pulse and the second detection pulse. | 07-11-2013 |
20130208556 | Power-On-Reset (POR) Circuits for Resetting Memory Devices, and Related Circuits, Systems, and Methods - Power-on-reset (POR) circuits for resetting memory devices, and related circuits, systems, and methods are disclosed. In one embodiment, a POR circuit is provided. The POR circuit is configured to receive as input, a plurality of decoded address outputs from at least one memory decoding device. The POR circuit is further configured to generate a POR reset if any of the plurality of decoded address outputs are active. As a result, memory decoding device latches can be reset to a known, default condition to avoid causing an unintentional word line selection in the memory during power-on state before an external reset is available. Because the POR circuit can generate the POR reset without need of an external reset, the memory decoding devices can be reset quickly to allow for quicker availability of memory after a power-on condition. | 08-15-2013 |
20130223176 | MEMORY PRE-DECODER CIRCUITS EMPLOYING PULSE LATCH(ES) FOR REDUCING MEMORY ACCESS TIMES, AND RELATED SYSTEMS AND METHODS - Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods are disclosed. In one embodiment, the memory pre-decoder circuit includes a memory pre-decoder configured to pre-decode a memory address input within a memory pre-decode setup path to generate a pre-decoded memory address input. Additionally, a pulse latch is provided in the memory pre-decoder circuit outside of the memory pre-decode setup path. The pulse latch samples the pre-decoded memory address input based on a clock signal and generates a pre-decoded memory address output. As such, the memory pre-decode setup path sets up the pre-decoded memory address input prior to the clock signal for the pulse latch. In this manner, the pulse latch is configured to generate a pre-decoded memory address output without increasing setup times in the memory pre-decode setup path. | 08-29-2013 |
20130223177 | COMMAND DECODERS - Command decoders are provided. The command decoder includes an input buffer configured for buffering and receiving command address signals having address information and command information at first, second, third, and fourth edges of a clock pulse signal according to a reference voltage, a latch circuit configured for latching the command address signals output from the input buffer at the first and third edges of the clock pulse signal to generate and output latched signals, a first command generator configured for decoding the latched signals output from the latch circuit at the first edge of the clock pulse signal to generate and output a first internal command, and a second command generator configured for decoding the latched signals output from the latch circuit at the third edge of the clock pulse signal to generate and output a second internal command. | 08-29-2013 |
20130223178 | GLOBAL RESET WITH REPLICA FOR PULSE LATCH PRE-DECODERS - A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain. | 08-29-2013 |
20130242685 | SYSTEM AND METHOD FOR PROCESSING SIGNALS IN HIGH SPEED DRAM - The embodiments described herein provide memory devices. In one embodiment, a memory device includes bank control logic configured to generate a modified bank address signal and an active driver configured to provide a bank activate signal, receive an activate command signal, execute an activate command of the activate command signal at each one of a group of clock cycles, in which each one of the group of clock cycles is greater than one clock cycle, and receive the modified bank address signal, in which the modified bank address signal is high for at least a portion of each one of the group of clock cycles and the at least a portion of each one of the group of clock cycles is greater than one clock cycle. | 09-19-2013 |
20130242686 | SINGLE TRANSISTOR DRIVER FOR ADDRESS LINES IN A PHASE CHANGE MEMORY AND SWITCH (PCMS) ARRAY - The present disclosure relates to the fabrication of non-volatile memory devices. In at least one embodiment, a single transistor may be used to drive each address line, either a wordline or a bitline. Both an inhibit voltage and a selection voltage may be driven through these single transistor devices, which may be achieved with the introduction of odd and even designations for the address lines. In one operating embodiment, a selected address line may be driven to a selection voltage, and the address lines of the odd or even designation which is the same as the selected address line are allowed to float. The address lines of the odd or even designation with is different from the selected address lines are driven to an inhibit voltage, wherein adjacent floating address lines may act as shielding lines to the selected address line. | 09-19-2013 |
20130258797 | WORD LINE DRIVER - A first circuit is coupled to a second circuit, which is coupled to a third circuit. A high voltage value of a first input signal and of a first output signal of the first circuit are equal, and are less than a high voltage value of a second output signal of the second circuit. A low voltage value of the first input signal is higher than a low voltage value of the first output signal. A high voltage value of the second output signal and of a third output signal of the third circuit are equal. The low voltage value of the first output signal, the second output signal, and the third output signal are equal. | 10-03-2013 |
20130279285 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array region and a column decoder. The memory cell array region includes a plurality of memory cell arrays that are arranged in row and column directions. The column decoder includes a first column select line (CSL) driver and a second CSL driver that are disposed adjacent to a first edge of the memory cell array region extending in the row direction and that have different physical layouts. | 10-24-2013 |
20130286763 | PRE-DECODER FOR DUAL POWER MEMORY - A pre-decoder for providing a pulse signal to a dual power rail word line driver is provided. The pre-decoder includes a clock generator, an address latch and decoder, a level shifter and a processing unit. The clock generator generates a first signal according to a clock, wherein the first signal is powered by a first supply voltage. The address latch and decoder decodes an address to obtain a second signal according to the first signal. The level shifter generates a third signal according to the first signal, wherein the third signal is powered by a second supply voltage higher than the first supply voltage. The processing unit generates the pulse signal according to the second signal and the third signal, wherein the pulse signal is powered by the second supply voltage. | 10-31-2013 |
20130301374 | WORD LINE DRIVER HAVING A CONTROL SWITCH - A word line driver including a control switch configured to receive a control signal, where the control switch is between a first node configured to receive an operating voltage signal and a second node configured to determine an output of the word line driver. The word line driver further includes a cross-coupled amplifier electrically connected to the second node. The word line driver further includes at least one inverter electrically connected to the cross-coupled amplifier. A semiconductor device including the word line driver and a memory array including at least one electronic fuse. | 11-14-2013 |
20130308410 | HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY - Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example. | 11-21-2013 |
20130315023 | COLUMN SELECT SIGNAL GENERATION CIRCUIT - A column select signal generation circuit includes: a first current controller configured to control the level of a pre-column select signal in response to a bank active signal, a driver configured to generate an amplified column select signal in response to the pre-column select signal, and a second current controller configured to generate an output signal of the driver as a column select signal in response to the bank active signal. | 11-28-2013 |
20130322199 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR WORD LINE DECODING AND ROUTING - The invention discloses a semiconductor memory device and a method for word line decoding and routing. The present invention relates generally to semiconductor memory field, Problems solved by the invention is that, to improve the quality of word line signals results in routing congestion. Embodiments of the invention provide the program as follows: a semiconductor memory device and a method for word line decoding and routing, dividing memory array of the semiconductor memory device into a plurality of smaller memory arrays, on a first metal layer routing first decoded row address, on a second metal layer below the first metal layer routing second decoded row address, and the output word line after decoding drives the plurality of smaller memory allays, Embodiments of the invention are suitable for various semiconductor memory designs, including: on-chip cache, translation look-aside buffer, content addressable memory, ROM, EEPROM, and SRAM and so on. | 12-05-2013 |
20130329511 | CLOCKED MEMORY WITH LATCHING PREDECODER CIRCUITRY - A memory includes a memory array having a plurality of word lines, a plurality of latching predecoders, and word line driver logic. Each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results. | 12-12-2013 |
20130329512 | CLOCKED MEMORY WITH WORD LINE ACTIVATION DURING A FIRST PORTION OF THE CLOCK CYCLE - A memory includes a plurality of latching predecoders, each including a first transistor coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle. | 12-12-2013 |
20140010034 | SEMICONDUCTOR DEVICE, INFORMATION PROCESSING SYSTEM INCLUDING SAME, AND CONTROLLER FOR CONTROLLING SEMICONDUCTOR DEVICE - A system includes a control chip and a plurality of command terminals receiving a plurality of command signals, respectively; a command decoder coupled to the command terminals, the command decoder being configured to output an internal command in response to the command signals; and a layer address buffer configured to output a layer address each time the command decoder outputs a row command as the internal command and outputs a column command as the internal command; and a plurality of core chips stacked with one another, each of the core chips being configured to receive the, row command and the layer address output together with the row command, to receive the column command and the layer address output together with the column command, and to free from receiving the command signals. | 01-09-2014 |
20140036613 | SEMICONDUCTOR INTEGRATED CIRCUIT - There are included first and second dynamic circuits and first and second transistors. The first dynamic circuit keeps a first dynamic node at a first level when a plurality of input signals is in a first state, and switches the first dynamic node between the first level and a second level in accordance with a first clock signal when the plurality of input signals is in a second state. The second dynamic circuit includes a compensating circuit that is provided between the second dynamic node and a second power supply and connects the second dynamic node to the second power supply so as to compensate the level of the second dynamic node when the plurality of input signals is in the second state and the first dynamic node is at a level other than the first level. | 02-06-2014 |
20140056094 | WORD-LINE ACTIVATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a state where a signal (IN) is at “H” and an NMOS transistor ( | 02-27-2014 |
20140064013 | INTEGRATED CIRCUIT - An integrated circuit includes a plurality of mode register set (MRS) setting blocks configured to generate a plurality of additive latency (AL) codes in response to an MRS signal, and a decoding unit configured to decoding the plurality of AL codes in response to a stack information signal to generate a plurality of AL setting signals. | 03-06-2014 |
20140119150 | BIPOLAR LOGIC GATES ON MOS-BASED MEMORY CHIPS - A system for using selectable-delay bipolar logic circuitry within the address decoder of a MOS-based memory includes a MOS-based memory, which includes an array of a plurality of memory cells configured to store data; an address decoder including bipolar logic circuitry, where the address decoder is configured to accept a word including a plurality of bits and access the array of memory cells using the word; where the bipolar logic circuitry includes a plurality of bipolar transistor devices, where at least one bipolar transistor device has an adjustable gate bias and is configured to accept an input, wherein the gate bias is adjusted based on the input, where the gate bias determines a selectable gate delay. | 05-01-2014 |
20140126319 | SETTING INFORMATION STORAGE CIRCUIT AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME - A setting information storage circuit includes first decoders configured to generate first input enable signals, respectively, in response to selection codes and a first set signal, first register sets configured to correspond to the first decoders, respectively, and to receive setting data when first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and store the received setting data, a second decoders configured to generate a second input enable signals, respectively, in response to the selection codes and a second set signal, and a second register sets configured to correspond to the second decoders, respectively, and to receive the setting data when second input enable signals generated from the second decoders corresponding to the second register sets, respectively, are enabled, and store the received setting data. | 05-08-2014 |
20140160875 | ROW ADDRESS DECODING BLOCK FOR NON-VOLATILE MEMORIES AND METHODS FOR DECODING PRE-DECODED ADDRESS INFORMATION - Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage shift circuit configured to receive first pre-decoded address information at first voltage levels and further configured to latch the first pre-decoded address information and shift the voltage levels of the same to second voltage levels. An address decoder includes a second latch and voltage shift circuit configured to receive second pre-decoded address information at the first voltage levels and latch and shift the voltage levels of the same to the second voltage levels. The address decoder is further configured to select control gates of the memory cells of the memory based at least in part on the first and second pre-decoded address information. | 06-12-2014 |
20140169117 | DECODER CIRCUIT WITH REDUCED CURRENT LEAKAGE - A decoder circuit with reduced leakage configured to decode an address and drive one of a number of word lines may be implemented with two-high logic gates in a pre-decode stage, a decode stage, and a word line driver stage. Such decoder circuits may include, in the word line driver stage, a number of two-high NOR gates configured to drive one of a number of word lines. In some embodiments, the two-high logic gates that share common inputs are implemented with multi-output static logic. | 06-19-2014 |
20140169118 | ADDRESS INPUT CIRCUIT OF SEMICONDUCTOR APPARATUS - An address input circuit of a semiconductor device includes: an address latch unit configured to generate latch addresses, by latching addresses sequentially provided by an external, according to a command decoding signal, wherein latch timings of each of the addresses are adjusted differently from one another; and a command decoder configured to decode a command provided from the external and generate the command decoding signal. | 06-19-2014 |
20140219043 | APPARATUSES AND METHODS FOR TARGETED REFRESHING OF MEMORY - Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory. | 08-07-2014 |
20140233339 | APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS - A non-volatile memory device comprising a memory cell array including a plurality of non-volatile memory cells arranged in rows and columns, wherein memory cells arranged in a same row share a word line and memory cells arranged in a same column share a bit line; and at least an address decoder to provide a negative voltage to at least one non-accessed word line in said array when a programming or erasure voltage is provided along a shared bit line. | 08-21-2014 |
20140233340 | ROW DECODING CIRCUIT - A row decoding circuit including row decoding blocks is provided. Each of the row decoding blocks includes row decoders. Each of the row decoders receives a pre-charge signal, and includes an inverter, a selecting transistor and at least one switch transistors. The inverter receives the corresponding pre-charge signal, and outputs a first control signal. The first source/drain of the selecting transistor is coupled to a system high voltage, the gate receives the first control signal, and the second source/drain outputs a corresponding row selecting signal to a memory array of a memory device. The switch transistors are coupled between the second source/drain of the selecting transistor and a corresponding first reference signal in series. When the selecting transistor is controlled by the first control signal and turned on, the first reference signal is set to a high voltage level. | 08-21-2014 |
20140241101 | Word Line Driver and Related Method - A word line driver includes a first transistor electrically connected to a first voltage supply node and a word line, a second transistor electrically connected to a second voltage supply node and the word line, a first switch electrically connected to the first voltage supply node and a bulk electrode of the second transistor, and a second switch electrically connected to the second voltage supply node and the bulk electrode of the second transistor. | 08-28-2014 |
20140269140 | NON-VOLATILE MEMORY (NVM) WITH WORD LINE DRIVER/DECODER USING A CHARGE PUMP VOLTAGE - A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit. | 09-18-2014 |
20140269141 | WORDLINE DOUBLER - A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal. | 09-18-2014 |
20140313846 | DRIVER AND MEMORY CONTROLLER HAVING THE SAME - A memory controller includes a bus driver that allows the controller to support both a semiconductor memory device supporting a low power double data rate 3 (LPDDR3) transmission method and a semiconductor memory device supporting a low power double data rate 4 (LPDDR4) transmission method. | 10-23-2014 |
20140334241 | CIRCUITS, APPARATUSES, AND METHODS FOR OSCILLATORS - Circuits, apparatuses, and methods are disclosed for oscillators. In one such example oscillator circuit, a plurality of delay stages are coupled in series. A variable delay circuit stage is coupled to the plurality of delay stages and is configured to delay a signal through the variable delay circuit stage by a variable delay. The variable delay increases responsive to a rising magnitude of a supply voltage provided to the variable delay circuit stage. | 11-13-2014 |
20140347951 | SEMICONDUCTOR MEMORY DEVICE HAVING SUB WORD LINE DRIVER AND DRIVING METHOD THEREOF - A semiconductor memory device may include a memory cell array, a plurality of first sub word line drivers, and a plurality of second sub word line drivers. The memory cell array may comprise a plurality of sub cell arrays, a plurality of first word lines and a plurality of second word lines, wherein a loading of each of the first word lines is greater than a loading of each of the second word lines. Each of the plurality of first sub word line drivers may be connected to drive a corresponding one of the plurality of first word lines, wherein each of the first sub word line drivers has a first driving capability. Each of the plurality of second sub word line drivers may be connected to drive a corresponding one of the plurality of second word lines, wherein each of the second sub word line drivers has a second driving capability different from the first driving capability. | 11-27-2014 |
20140369149 | WORD LINE DRIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME - Word line drivers including a selection signal generator and a word line drive unit are provided. The selection signal generator generates a selection signal which is enabled according to a high-order address signal and a low-order address signal in an active mode. Further, the selection signal generator generates a complementary selection signal which is enabled when an equalization signal is inputted in a pre-charge mode after the active mode. The word line driver receives the main word line signal to drive a word line to have a first level when the selection signal is enabled, to drive the word line to have a second level when the selection signal is disabled, and to drive the word line to have a third level when the complementary selection signal is enabled. | 12-18-2014 |
20140369150 | COLUMN DECODERS - Column decoders are provided. The column decoder includes a power supplier and a column selection signal generator. The power supplier generates a supply voltage signal from a power voltage in response to a control signal enabled from a start point of time of a write mode or a read mode till an end point of time of a burst length. A level of the supply voltage signal is controlled according to the control signal. The column selection signal generator operates while the supply voltage signal is supplied. The column selection signal generator generates one of column selection signals, which is selectively enabled according to a logic combination of a high-order address signal, a mid-order address signal and a low-order address signal which are generated by decoding column address signals. | 12-18-2014 |
20140369151 | HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY - Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example. | 12-18-2014 |
20140369152 | N-WELL SWITCHING CIRCUIT - A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness. | 12-18-2014 |
20140376324 | TESTING THROUGH-SILICON-VIAS - Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TS V to at least one of a test input and a test evaluation circuit. | 12-25-2014 |
20150055431 | METHODS AND APPARATUSES INCLUDING TRANSMITTER CIRCUITS - Methods and apparatuses are disclosed for transmitter circuits. One example apparatus includes a pre-driver circuit configured to provide a transition control signal responsive to received data, and a main driver circuit configured to drive an output node responsive to the transition control signal. The apparatus also includes a feedback circuit configured to provide a feedback control signal responsive to a voltage of the output node reaching or exceeding a predefined threshold, and an equalizer driver circuit configured to assist the main driver circuit in driving the output node responsive to signals from at least one of the pre-driver circuit and the feedback circuit. | 02-26-2015 |
20150098294 | COUNTER CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A counter circuit includes a lower count signal generation unit suitable for generating a lower bit, an upper count signal generation unit suitable for generating an upper bit, and a control unit suitable for determining a counting route in response to a control signal and controlling the lower and upper count signal generation units based on a determined route, wherein in a first route, the upper bit is generated in response to the lower bit, and in a second route, the lower bit is generated in response to the upper bit. | 04-09-2015 |
20150103612 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections. | 04-16-2015 |
20150109875 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. The time determination signal generation circuit is configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined, and the timing circuit is configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged. | 04-23-2015 |
20150325276 | BIPOLAR LOGIC GATES ON MOS-BASED MEMORY CHIPS - A system for using selectable-delay bipolar logic circuitry within the address decoder of a MOS-based memory includes a MOS-based memory, which includes an array of a plurality of memory cells configured to store data; an address decoder including bipolar logic circuitry, where the address decoder is configured to accept a word including a plurality of bits and access the array of memory cells using the word; where the bipolar logic circuitry includes a plurality of bipolar transistor devices, where at least one bipolar transistor device has an adjustable gate bias and is configured to accept an input, wherein the gate bias is adjusted based on the input, where the gate bias determines a selectable gate delay. | 11-12-2015 |
20150380416 | SEMICONDUCTOR DEVICE - Disclosed embodiments relate to a semiconductor device having a plurality of unit transistors that include element isolation regions formed on a semiconductor substrate and a gate electrode formed in the shape of a frame and disposed on an active region sandwiched between the element isolation regions in such a way that the two ends of the outer periphery of the gate electrode extend onto the element isolation regions and the inner periphery thereof closes the active region. The active regions of unit transistors adjacent to one another in a first direction are electrically isolated from one another by means of the element isolation regions, and the active regions of unit transistors adjacent to one another in a second direction which intersects the first direction are linked to one another. | 12-31-2015 |
20160099041 | Semiconductor Device - Disclosed herein is a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes a driver configured to drive a selected one of the word lines from an inactive level to an active and to drive the selected one of the word lines from the active level to an intermediate level at a first rate and from the intermediated level to the inactive level at a second rate. The intermediate level is between the active and inactive levels, and the first rate is greater than the second rate. | 04-07-2016 |
20160118097 | BIPOLAR LOGIC GATES ON MOS-BASED MEMORY CHIPS - A system uses both MOS-based and bipolar-based decoding circuitry in an address decoder for MOS-based memory. The system includes a MOS-based memory, which includes an array of a plurality of memory cells configured to store data, and an address decoder including MOS-based circuitry and bipolar logic circuitry. The address decoder is configured to accept a word comprising a plurality of bits and access the array of memory cells using the word. | 04-28-2016 |
20180025762 | SEMICONDUCTOR DEVICE INCLUDING A COLUMN DECODER | 01-25-2018 |